Application Information STA7130MPR Series Driver ICs for 2-Phase Stepper Motor Unipolar Drives Introduction The STA7130MPR series are driver ICs for driving unipolar mode, 2-phase stepper motors. These drivers are designed for low-voltage (up to 44 V output) motor applications. The series provides a range of maximum output currents from 1 to 2 A, in pin-compatible proprietary (model STA) packages, allowing system optimization with reduced printed circuit board requirements. The logic section provides four modes of operation: forward and reverse normal drive rotation, outputs-off free spin (coast), and electronic braking. The innovative multi-chip internal structure separates the main logic IC (MIC) from the four output N-channel power MOSFETs. This results in lower thermal resistance and greater efficiency. PWM control allows constant-current control of output while reducing heat generation and power losses by synchronous rectification. The rich set of protection features helps to realize low component counts, and high performanceto-cost power management. Not to scale Figure 1. STA7130MPR series packages are 18-pin, fully molded ZIPs, with offset pins for through hole mounting. Features and Benefits • Power supply voltages, VBB : 46 V(max), 10 to 44 V normal operating range • Maximum output currents: 1 A, 1.5 A, 2 A • Clock-in drive between 2 phase and 2W1-2 step (full to eighth step modes) • Built-in Detection Resistance feature for motor current detection • All STA7130MPR series variants are pin-compatible • ZIP type 18-pin molded package (STA package) • Self-excitation PWM current control with fixed off-time: automatic 3-level PWM off-time shifting, based on the current setting ratio • Built-in synchronous rectification circuit reduces losses at PWM switching • Synchronous PWM chopping function prevents motor noise in Hold mode • Sleep mode for reducing the IC input current in stand-by state • Built-in protection circuitry against opens/shorts in motor coil The product lineup for the STA7130MPR series provides the following: Maximum Output Current (A) Detection Resistance Protection (OCP, TSD, Open/Short Load) STA7130MPR 1 ○ ○ STA7131MPR 1.5 ○ ○ STA7132MPR 2 ○ ○ Part Number STA7130MPR-AN SANKEN ELECTRIC CO., LTD. http://www.sanken-ele.co.jp/en/ December 24, 2013 Table of Contents Introduction 1 Features and Benefits 1 Specifications 3 Functional Block Diagram Pin Description Package Outline Drawing Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Typical Application Drawing 3 3 4 5 5 6 9 Truth Tables 10 Input Logic Timing 11 Excitation Sequence Diagrams 12 Excitation Change Sequencing 16 Individual Circuit Descriptions 17 Functional Description 18 Application Information 23 Characteristic Performance 28 Logic Input Pins Excitation Mode Input Pins Monitor Output Pins Logic Input Pin Structure Clock Signal CW/CCW, M1 and M2 Signals Awakening from Sleep2 Mode Reset Signal Rotation Direction and Mode Change 2 Phase Excitation (Full Step) 1-2 Phase Excitation (Half Step) W1-2 Phase Excitation (Quarter Step) 2W1-2 Phase Excitation (Eighth Step) Monolithic Control IC (MIC) Output MOSFET Chip Sense Resistor PWM Control PWM Off-Time Protection Functions Motor Current Ratio Setting Lower Limit of Control Current Avalanche Energy Motor Current Ratio Setting (R1, R2, RS) Clock Input Chopping Synchronous Circuit Output Disable (Sleep1 and Sleep2) Circuits Ref/Sleep1 Pin Logic Input Pins Logic Output Pins Thermal Design Output MOSFET On-Voltage, VDS(on) , Characteristics Output MOSFET Body Diode Forward Voltage, VF , Characteristics STA7130MPR-AN 10 10 10 11 11 11 11 11 11 12 13 14 15 17 17 17 18 20 20 23 23 23 23 25 25 25 26 26 26 26 28 29 December 24, 2013 SANKEN ELECTRIC CO., LTD. 2 Functional Block Diagrams 7 13 8 12 9 17 OutB 6 OutB 5 VBB 4 Reset M2 Clock CW/CC W Sleep2 15 M1 11 Mo Flag OutA 2 Ref/Sleep1 OutA 1 18 Reg. MIC ÷3 PreDriver PreDriver Sequencer & Standby Circuit Protect Protect DAC SenseA TSD +Com p - 3 Rs DAC Synchro Control PWM Control Com + p - PWM Control OSC OSC 14 1 Pin Number. Symbol 1 OutA 4 3 6 5 10 9 12 11 14 13 16 15 18 17 Function Output of phase A 2 ¯ Ō¯ū¯¯¯tĀ 3 SenseA 4 Mo 5 M1 6 M2 7 Sleep2 8 Clock Step clock input 9 VBB Power supply (motor power supply) 10 Gnd 11 Ref/Sleep1 12 Reset 13 CW/CCW 14 Sync Rs Gnd 8 7 SenseB 10 Sync 2 16 Output of phase Ā Phase A current sensing Monitor output in 2-phase-excitation state Motor current excitation control input Sleep2 setup input Product ground Control current and Sleep1 setup input Reset for internal logic Forward/reverse switch input Synchronous PWM control switch input 15 Flag 16 SenseB Protection circuits monitor output 17 ¯¯¯tB̄ ¯ Ō¯ū Output of phase B̄ 18 OutB Output of phase B Phase B current sensing STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 3 Package Outline Drawing 25.25 ±0.3 Gate protrusion 4 ±0.2 (b) Gate protrusion (2X) 9.0 ±0.2 (a) (1) (3.3 ±0.5) (6.9) (3.6) +0.2 0.45 – 0.1 0.55 +0.2 – 0.1 2.54 ±0.5 Dimension between tips of pins 17XP1.27 ±0.5 = 21.59 ±1 Dimension between tips of pins C1.5 ±0.5 1 3 2 5 4 7 6 9 8 11 10 13 12 R-end 1.3 ±0.1 Dimension at root of pins (4XR1) 15 14 17 16 18 25.55 Pin core material: Cu Pin plating: Ni, with solder dip Dimensions in millimeters Branding codes: (a) Type: 713xMPR Where: x is the current rating (0 = 1 A, 1 = 1.5 A, or 2 = 2 A ) (b) Lot Number: YMDD Where: Y is the last digit of the year of manufacture M is the month (1 to 9, O, N, D) DD is the date Leadframe plating Pb-free. Device composition includes high-temperature solder (Pb >85%), which is exempted from the RoHS directive. STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 4 Absolute Maximum Ratings, valid at TA = 25°C Characteristic Symbol Motor Power Supply Voltage VM Main Power Supply Voltage VBB Notes Rating Unit 46 V STA7130MPR Output Current IO STA7131MPR Control current value STA7132MPR 46 V 1.0 A 1.5 A 2.0 A Logic Input Voltage VLI –0.3 to 6 V Logic Output Voltage VLO –0.3 to 6 V REF Input Voltage VREF –0.3 to 6 V Sense Voltage VRS Allowable Power Dissipation PD No heatsink ±1 V 3.5 W Junction Temperature TJ 150 °C Operating Ambient Temperature TA –20 to 80 °C TSTG –30 to 150 °C Storage Temperature Recommended Operating Conditions Characteristic Symbol Motor Power Supply Voltage VM Main Power Supply Voltage VBB Case Temperature TC Conditions Measured at the root of pin 10; no heatsink STA7130MPR-AN Min. Max. Unit – 44 V 10 44 V – 85 °C December 24, 2013 SANKEN ELECTRIC CO., LTD. 5 ELECTRICAL CHARACTERISTICS1 valid at TA = 25°C, VBB = 24 V; unless otherwise specified Characteristics Main Power Supply Current MOSFET Breakdown Voltage Output MOSFET On Resistance Output MOSFET Body Diode Forward Voltage Maximum Input Frequency Logic Input Voltage Logic Input Current Symbol Test Conditions IBB Operating IBBS In Sleep1 or Sleep2 mode VDSS VBB = 44 V, ID = 1 mA RDS(on) VF fclk Min. Typ. Max. Unit – – 10 mA – – 3 mA 100 – – V STA7130MPR – 0.1 0.13 Ω STA7131MPR – 0.7 0.85 Ω STA7132MPR – 0.25 0.4 Ω STA7130MPR – 0.18 0.24 V STA7131MPR – 0.85 1.1 V STA7132MPR – 0.95 1.2 V 250 – – kHz VIL Input clock duty cycle = 50% 0 – 0.7 V VIH 2.3 – 5.5 V IIL – ±1 – μA IIH – ±1 – μA Logic Output Voltage VLO ILO = 5 mA – – 0.8 V Logic Output Current ILO VLO = 0.8 V – – 5 mA 0.1 – 0.9 V 2.0 – 5.5 V VREF Ref/Sleep1 Pin Input Voltage Ref/Sleep1 Pin Input Current Reference Voltage Ratio2 Sense Voltage Sense Resistor3 In Sleep1 mode; output off, IBBS in specification, sequencer enabled VREFS IREF – ±10 – μA Mode F – 100 – % Mode E – 98.1 – % Mode C – 92.4 – % – 83.1 – % – 70.7 – % Mode 6 – 55.5 – % Mode 4 – 38.2 – % Mode 2 – 19.5 – % VSENSE VREF / 3 – 0.03 VREF / 3 VREF / 3 + 0.03 V STA7130MPR 0.296 0.305 0.314 Ω STA7131MPR 0.199 0.205 0.211 Ω STA7132MPR 0.150 0.155 0.160 Ω – 1.5 – μs Mode A Mode 8 RS VREF / 3 ≈ VSENSE = 100% Reference Voltage Ratio = 100% PWM Minimum On-Time (Blanking Time) ton(min) tPOFF1 Mode 8, A, C, E, or F – 11.5 – μs PWM Off-Time tPOFF2 Mode 4 or 6 – 8.5 – μs tPOFF3 Mode 2 – 7 – μs Continued on the next page… STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 6 ELECTRICAL CHARACTERISTICS1 (continued) valid at TA = 25°C, VBB = 24 V; unless otherwise specified Characteristics Sleep-to-Enable Recovery Time Switching Time Overcurrent Detection Voltage4 Overcurrent Detection Current Load Disconnection Detect Time Thermal Shutdown Temperature Symbol Test Conditions Min. Typ. Max. Unit μs tSE From Sleep1 or Sleep2 mode 100 – – tcon From input clock edge to output on – 1.4 – μs tcoff From input clock edge to output off – 0.7 – μs VOCP 0.65 0.7 0.75 V STA7130MPR – 2.3 – A STA7131MPR Measured as VOCP / RS – 3.5 – A STA7132MPR – 4.6 – A tOPP Starting from PWM-off edge – 2 – μs TTSD Measurement point on the unbranded side of the device case (at a saturation temperature) – 125 – ºC IOCP Motor coil short-circuited 1The polarity value for current specifies a sink as "+ ," and a source as “−,” referencing the IC. Reference Voltage Ratio proportions are the same as the SLA7070M series for corresponding modes. 3Includes the inherent bulk resistance (approximately 5 mΩ) of the resistor itself. 4V SENSE ≥ VOCP always. 2The STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 7 VREFS(max) = 5.5 V Sleep 1 Set Range VREFS(min) = 2.0 V Prohibition Zone VREF(max) = 0.9 V Motor Current Setup Range* *Motor Current Set Range is determined by the value of the resistor built into the device. VREF(min) = 0.1 V 0V Allowable Power Dissipation, PD (W) Figure 1. Reference Voltage Setting (VREF, Ref/Sleep1 Pin). Please pay extra attention to the change-over between the Motor Current Setup range , and the Sleep1 Set range. VOCP = 0.7 V is equivalent to VREF = 2.1 V, but will be as a state of Sleep1. 4.0 3.5 RθJA = 35.7 °C/W 3.0 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 90 Figure 2. Allowable Power Dissipation STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 8 Typical Application Drawing Vs =10 to 44 V VCC =3.0 to 5.5 V Sleep R1 Q1 R11 R10 C1 OutA OutA Reset Clock CW/CCW M1 M2 Sleep2 Sync Mo Flag Ref/Sleep1 SenseA Microcontroller CB VBB OutB OutB STA7130MPR STA7131MPR STA7132MPR Gnd CA SenseB C2 R4 R5 R6 R7 R8 R9 R2 R3 Pin10 Gnd Power Gnd Logic Gnd Figure 3. Typical Application Circuit External Component Typical Values (for reference use only): Component Value Component Value R1 10 kΩ CA 100 μF / 50 V R2 1 kΩ (varistor) CB 10 μF / 10 V R3 10 kΩ C1, C2 0.1 μF R4 to R9* 1 to 10 kΩ R10 to R11 5.1 to 10 kΩ *Not required if corresponding device input pin open. • Take precautions to avoid noise on the VDD line and the Logic Gnd line; noise levels greater than 0.5 V on the VDD line may cause device malfunction, so be careful when laying out Gnd traces. Noise can be reduced by separating the Logic Gnd and the Power Gnd on the PCB from the device Gnd pin (pin 10). • If unused, the logic input pins CW / CCW, M1, M2, Sleep2, Reset, and Sync must be pulled up to VDD or pulled down to Gnd. If those unused pins are left open, the device malfunctions. • If unused, the logic output pins Mo and Flag must be kept open. STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 9 Truth Tables Logic Input Pins Table 1 shows the truth table for the logic input pins of the STA7130MPR series. Excitation Mode Input Pins Table 2 shows the logic of the pins (M1 and M2) that set the commutation mode. • The Reset function is asynchronous. If the input on the Reset pin is set high, the internal logic circuits are reset. At this point, if the Ref/Sleep1 pin is kept low, then the motor outputs turn on at the starting point of excitation. Note that the output disable function is not available when the Reset pin is high. • Voltage at the Ref/Sleep1 pin controls the PWM current and the Sleep1 function. ▫ For normal operation, VREF should be less than 1.5 V ( low level ). ▫ For Sleep1 mode, VREF should be greater than 2.0 V ( high level ). This turns off (disables) the outputs, stops the internal linear circuits, and reduces the main power supply current, IBB. The logic control circuits remain active, and will respond to a signal on the Clock input. Monitor Output Pins The STA7130MPR series provides two device status monitor outputs: • Mo pin – motor output sequencing • Flag pin – protection function operation Table 3 shows the logic for the monitor pins. The monitor outputs are open drain, so an external pull-up resistor rated at 5.1 to 10 kΩ must be connected (see Typical Application Drawing section). Table 2. Motor Phase Excitation Mode Truth Table Pin Name M1 Excitation Mode M2 L L 2 phase excitation (mode F, full step) H L 1-2 phase excitation (mode F, half step) L H W1-2 phase (quarter step) • Voltage at the Sleep2 pin controls the Sleep2 function. When the Sleep2 pin is pulled high, the outputs are turned off (disabled), H H 2W1-2 phase (eighth step) the internal linear circuits are stopped, and the main power supply current, IBB , is reduced, similar to the Sleep1 state. In addition, however, the logic control circuits are disabled (Hold mode), and the device will not respond to a signal on the Clock input. When Table 3. Monitor Output Truth Table awaking from the Sleep2 state, delay at least 100 μs before sendPin Name Low Level ing a Clock pulse (see figure 4). Setting the Sleep2 pin high releases any protection states in effect. Alternatively, cycle the VDD power supply. High Level Mo Other than 2-phase excitation timing 2-phase excitation timing Flag Normal operation Protection circuit operation Table 1. Logic Input Truth Table Pin Name Low Level High Level Reset Normal operation Logic reset CW/CCW Forward rotation (CW) Reverse rotation (CCW) M1, M2 Commutation control Sleep2 Normal operation Sleep2 function (Reset protection functions) Ref / Sleep1 Normal operation Sleep1 function Sync Asynchronous PWM control Synchronous PWM control STA7130MPR-AN Clock Default (Positive edge) December 24, 2013 SANKEN ELECTRIC CO., LTD. 10 Logic Input Pin Structure The low pass filter incorporated with the logic input pins (Reset, Clock, CW/CCW, M1, M2, Sleep2, and Sync) improves noise rejection. These are MOS inputs and are high impedance. Apply a fixed input level, either low or high. Input Logic Timing The timing considerations described in the following sections are illustrated in figure 4. Clock Signal The internal sequencer logic switches on a positive (rising) edge of a Clock input signal. The Clock pulse width should be longer than 2 μs in both the positive and negative phases, which corresponds to a clock response frequency of 250 kHz. Note: Although in standard configuration only the positive edge is used for output switch timing, it is necessary to control the pulse widths both before and after each Clock signal edge, in order to maintain proper stepping operation. CW/CCW, M1, and M2 Signals The CW/CCW, M1, and M2 signals are also timed relative to the Clock input signal edges, and setup and hold time intervals are required. Switching of these inputs should occur at least 1 μs before or after the Clock signal switching pulse edge (positive edge for standard configuration, and positive or negative edge for W option). If either interval is shorter than 1 μs, the sequencer logic circuitry can malfunction. Awakening from Sleep1 and Sleep2 Mode When awaking from the Sleep1 and Sleep2 state, after setting the corresponding Sleep1 or Sleep2 input low, a delay, tSE , of at least 100 μs is required before sending a Clock pulse. Reset Signal The Reset pulse width, that is, the time the high voltage level is maintained on the Reset pin, must greater than 2 μs. If a Reset release (falling edge) and Clock edge occur simultaneously, the internal logic might cause an unexpected operation. Therefore, a greater than 5 μs delay is required between the falling edge of the Reset input and the next edge of the Clock input. Rotation Direction and Mode Change When a change is made to the rotation direction or excitation mode using the CW/CCW, M1, and M2 inputs, the changes are implemented at the next switching edge of the Clock input. Depending on the state of the motor when the Clock switching edge is received, the motor might be unable to respond and an out-of-step operation could occur. Therefore, please perform sufficient evaluation of the switching sequence with the motor in the application. Sleep2 100 μs(min) Reset 2 μs(min) 5 μs(min) Clock 4 μs(min) Output switching 2 μs(min) 1 μs(min) 2 μs(min) 1 μs(min) Output switching 2 μs(min) 1 μs(min) 1 μs(min) CW/CCW, M1, M2 Figure 4. Clock timing diagrams STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 11 Stepping Sequence Diagrams 2 Phase Excitation (Full Step) Reset Clock (Standard) 0 1 2 … B CW A A 0 CCW 0 100 100 B Excitation Mode Selection M1 M2 Low Low Shows the state to which the stepping sequence progresses at each switching edge of the Clock input STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 12 1-2 Phase Excitation (Half Step) Reset Clock (Standard) 0 1 2 3 4 … B CW A A 0 CCW 0 100 100 B Excitation Mode Selection M1 M2 High Low Shows the state to which the stepping sequence progresses at each switching edge of the Clock input STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 13 W1-2 Phase Excitation (Quarter Step) Reset Clock (Standard) 0 1 2 3 4 5 6 7 8 … B CW A A 0 38.2 70.7 CCW 0 38.2 70.7 100 100 92.4 92.4 B Excitation Mode Selection M1 M2 Low High Shows the state to which the stepping sequence progresses at each switching edge of the Clock input STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 14 2W1-2 Phase Excitation (Eighth Step) Reset Clock (Standard) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 … B CW A A 0 19.5 38.2 55.5 70.7 83.1 0 19.5 38.2 55.5 70.7 83.1 98.1 92.4 CCW 100 92.4 100 98.1 B Excitation Mode Selection M1 M2 High High Shows the state to which the stepping sequence progresses at each switching edge of the Clock input STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 15 Excitation Change Sequencing The excitation state of the STA7130MPR outputs represent the relative position of the motor, according to the Excitation Mode Sequence shown in table 4. When the Clock signal is received, the position changes to the next step in the sequence (set by the M1 and M2 pins). The direction of position change is set by the CW/CCW pin. Table 4. Excitation Mode States Internal Sequence Statea Phase A Direction PWM Counter Clockwise (CCW) Clockwise (CW) aThe Excitation Mode Sequence Phase B Mode PWM Mode 2 Phase (Full Step) 1-2 Phase (Half Step) √ √ A 8 B 8 A 6 B A A 4 B C A 2 B E – – B F Ā 2 B E Ā 4 B C Ā 6 B A Ā 8(F)b B 8(F)b Ā A B 6 Ā C B 4 Ā E B 2 Ā F – – Ā E B̄ 2 Ā C B̄ 4 Ā A B̄ 6 Ā 8(F)b B̄ 8(F)b Ā 6 B̄ A Ā 4 B̄ C Ā 2 B̄ E – – B̄ F A 2 B̄ E A 4 B̄ C A 6 B̄ A A 8(F)b B̄ 8(F)b A A B̄ 6 A C B̄ 4 A E B̄ 2 A F – – A E B 2 A C B 4 A A B 6 W1-2 Phase 2W1-2 Phase (Quarter Step) (Eighth Step) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Reference Voltage Ratio proportions are the same as the SLA7070M series for corresponding modes. Sequence State is Mode 8 for W1-2 Phase and 2W1-2 Phase sequencing, and is Mode F for 2 Phase and 1-2 Phase sequencing. bInternal STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 16 Individual Circuit Descriptions • Regulator Circuit The integrated regulator circuit is used in powering the pre-driver for the output MOSFET gates and for other internal linear circuits. Monolithic Control IC (MIC) • Sequencer Logic The single Clock input is used for step tim- ing. Direction is controlled by the CW/CCW input. Excitation mode is controlled by the combination of the M1 and M2 input logic levels. For details, refer to the individual truth table and logic timing descriptions. • PWM Control Each pair of outputs is controlled by a fixed offtime PWM current-control circuit. The internal oscillator (OSC) sets the off-time. Its operation mechanism is identical to that of the SLA7070M series. • Synchronous Control This function prevents abnormal motor noise when the STA7130MPR series is in Hold state. It synchronizes PWM chopping timing between the A and B output phases. Setting the Sync input to logic high sends a timing signal that synchronizes the chopping off-time of both phases A and B. This function is only recommended for synchronizing 2-Phase (full/half step sequence) excitation in Hold state. Use in non2-phase operations may result in no synchronization or greatly reduced phase control currents, caused by the mismatch of timing signal values and PWM off-cycles. • Protection Circuit A built-in protection circuit against motor coil opens or shorts is provided. Protection is activated by sensing voltage on the internal RS resistors; therefore, an overcurrent condition which results from the the Outx pins or Sensex pins, or both, shorting to Gnd cannot be detected by this means. Protection against motor coil opens is available only during PWM operation; therefore, it does not work at constant voltage driving, when the motor is rotating at high speed. Operation of the protection circuit disables all of the outputs. To come out of protection mode, set the Sleep2 pin high, or cycle the VDD power supply . • TSD circuit This circuit protects the device by shifting the outputs to Disable mode when the temperature of the device control IC (MIC) rises and becomes higher than threshold value, TTSD. To come out of protection mode, set the Sleep2 pin high, or cycle the VDD power supply . Output MOSFET Chips The value of the built-in output MOSFET chips varies according to the current rating of the STA7130MPR variant. Sense Detection Resistance We do not recommend using this function while the motor is in rotation, because it may interfere with motor current control, reduce motor torque, and raise motor vibrations. • DAC (D-to-A Converter) The sequencer logic controls the generation of an internal reference standard through the individual output phase DACs. The standard voltage amounts to: The sense resistance varies according to the current rating of the STA7130MPR variant, as follows: Output Current (A) RS Resistance (Ω typ) 1 0.305 1.5 0.205 2 0.155 VREF /3 × Mode Ratio Where internal VSENSE is a factor. The Reference Voltage Ratio for the various modes are given in the Electrical Characteristics table. Each resistance shown above includes the inherent resistance (approximately 5 mΩ) in the resistor itself. STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 17 Functional Description 20 μs/div ITRIP PWM Control Blanking Time An operating waveform on a Sensex pin, when driving a motor, is shown in figure 5. After PWM switching from off to on, ringing noise (spiked waveforms) can be observed for several microseconds on the Sensex pins. Ringing noise can be generated by various causes, such as capacitance between motor coils and inappropriate placement of motor wiring. PWM current control of each output phase is performed using a comparator with inputs from the voltage detection circuit, VRS, and the DAC output voltage to switch the PWM pulse from on to off. If the ringing noise on the sense resistor pin exceeds VTRIP , the comparator would turn off PWM repeatedly (referred to as seeking) as shown in figure 6. To prevent this phenomenon, the device is set to disregard signals from the current-sense comparator for a certain period, the blanking time, immediately after PWM turns on (figure 7). • Blanking time and seeking phenomenon When a motor is driven by the device, the seeking phenomenon may occur, generating noise from a torque reduction or the motor may become audibly louder. Although current control can be improved by shortening blanking time, the degree of margin for suppressing ringing noise decreases commensurately. The STA7130MPR series offers two blanking times: the standard variant duration is 1.5 μs, and the B option offers a duration of 3.0 μs. Using the variant with the longer, B option may solve the ringing problem. 5 μs/div 0 Figure 6. Example of a Sensex terminal waveform during seeking phenomenon PWM Pulse Width Phase A tOFF(Fixed) tON ITRIP 0 Phase A Phase A is on. Blanking Time Figure 7. Sensex pin waveform during PWM control 500 ns/div ITRIP ITRIP Figure 5. Operating waveforms on the Sensex pins during PWM chopping (circled area of left panel is shown in expanded scale in right panel) STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 18 • Blanking time tradeoffs The tradeoffs from different blanking times are shown in table 5. This comparison is based on the case where drive conditions, such as a motor, motor power supply voltage, Ref input voltage, and a circuit constant, were kept the same; in other words, while only the blanking time was changed. ▫ Minimize PWM on-time . Even if the on-time is shortened in order to reduce the current level, the minimum on-time could not be less than the blanking time. The minimum PWM on-time refers to the time the output MOSFET actually is turned on. In other words, the blanking time would set a minimum on-time, so short is selected in table 5). ▫ Minimize Coil current. This corresponds to the coil current during PWM minimum on-time, such as when the coil current is reduced when the power is reduced. In that case the shorter blanking time will allow a greater reduction in current. Table 5. Characteristic Comparison by the Difference in Blanking Time Parameter Better Performance Internal Blanking Time Setting Short Minimum PWM on-time Short Ringing noise suppression Minimum coil current Long ←← →→ Low Coil current waveform distortion at a high rotation rate (especially with microstepping) Large ←← →→ Large Standard blanking time (1.7 μs (typ)) ▫ Coil current waveform distortion during high rotation rate. During microstepping, the ITrip value (the internal reference voltage splitting ratio) changes with each Clock input, to predetermined values approximating a sine wave. Because PWM control of the motor coil current is set according to the Itrip value, the coil current is also in sine wave form. Due to the inductance characteristics of the coils, some amount of time is required for the device to settle the coil current at the targeted values. In general, if the relationship between this convergence time, tconv , and the period, tclk , of the input Clock is tconv < tclk, the range of the coil current level will follow the the Itrip value in any mode. The limiting value of tconv on the low side is determined by: the power supply voltage, the circuit time constant, and the minimum on-time. The limiting value of tconv on the high side is determined by: the power supply voltage and the coil circuit time constant. When the frequency of the Clock input is raised, because tclk becomes correspondingly small, the case can be expected in which the coil current cannot be raised to the Itrip value within a single clock period. In this case, the waveform amplitude of the coil current degenerates from the sine wave form, a condition referred to as waveform distortion. Figure 8 shows the waveform distortion at two different blanking times (both samples have the same power supply voltage, current preset value, motor, and so forth). As the circled sections show, the Sensex pin waveforms at 1.7 μs blanking time closely follow Option B blanking time (3.2 μs (typ)) Clock SenseA SenseB 500 μs/div 500 μs/div Figure 8. Operating waveforms on the Sensex pins during high rotation rate STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 19 a sinusoidal waveform envelope, but with a blanking time of 3.0 μs, the waveforms have begun to degenerate. In table 5 the preference for long blanking time means that the wave distortion will be less where the blanking time is longer, assuming the same drive conditions, while the wave distortion will be larger where the blanking time is shorter, if the Clock frequency is the same. In addition, despite such waveform distortion being confirmed, it is uncertain that the motor characteristic will be affected. Therefore, please make a final judgment after evaluating very thoroughly. PWM Off-Time The PWM off-time is controlled at a fixed time by an internal oscillator (similar to the SLA7070MPRT series). It is switched to one of three levels (see the Electrical Characteristics table) according to the switching sequence selected. In addition, the series provides a function that decreases losses occurring when the PWM turns off. This function dissipates back EMF stored in the motor coil at MOSFET turn-on, as well as at PWM turn-on (referred to as synchronous rectification). Figure 9 shows the difference in back EMF generation between the SLA7060M series and STA7130MPR series. The SLA7060M series performs on–off operations using only the MOSFETs on the PWM-on side, but the SLA7130MPR series also performs on–off operations using the MOSFETs on the PWM-off side. To prevent simultaneous switching of the MOSFETs at synchronous rectification operation, the IC has a dead time of approximately 0.5 μs. During dead time, the back EMF regeneration currentflows through the body diode of the MOSFET. Protection Functions The STA7130MPR series includes a motor coil short-circuit protection circuit, a motor coil open protection circuit, and an overheating protection circuit. An explanation of each protection circuit is provided below. • Motor Coil Short-Circuit Protection (Load Short) Circuit. This protection circuit, built into the STA7130MPR series, begins to operate when the device detects an increase in the sense resistor voltage level, VRS. The voltage at which motor coil short-circuit protection starts its operation, VOCP , is set at approximately 0.7 V. +V VCC Ion Ioff Vg Stepper Motor PWM On Dead Time PWM Off PWM On Dead Time FET Gate 0 Signal t Vg Vg Vg VREF Back EMF at Dead Time VRS VRS RS 0 t Figure 9. Synchronous rectification operation; Back EMF flows into body diode during Dead Time. STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 20 The outputs are disabled at the time the protection circuit starts, where VRS exceeds VOCP . (See figure 10.) • Motor Coil Open Protection Driver destruction can occur when one output pin (motor coil) is disconnected in a unipolar drive during operation. This is because a MOSFET reconnected after disconnection will be in the avalanche breakdown state, where very high energy is added with back EMF when PWM is off. With an avalanche state, an output cancels the energy stored in the motor coil where the resistance between the drain and source of the MOSFET is reached (the condition which caused the breakdown). Although MOSFETs with a certain amount of avalanche energy tolerance rating are used in the STA7130MPR series, avalanche energy tolerance falls as temperature increases. Because high energy is added repeatedly whenever PWM operation disconnects the MOSFET, the temperature of the MOSFET rises, and when the applied energy exceeds the tolerance, the driver will be destroyed. Therefore, a circuit which detects this avalanche state and protects the driver is provided in the STA7130MPR series. The operation is shown in figure 11. As explained above, when the motor coil is disconnected, the accumulated voltage in the MOSFET causes a reverse current to flow during the PWM off-time. For this reason, VRS that is negative during the PWM off-time in a normal operation becomes positive when the motor coil is disconnected. Thus, a disconnected motor is detectable by sensing that VRS in the PWM offtime is positive. In the STA7130MPR series, in order to avoid detection malfunctions, when a state of motor disconnection is detected 3 times continuously, the protection functions are enabled (figure 12). Note: When the breakdown of an output is confirmed by the occurrence of surge noise after PWM turn-off, the protection feature may operate and continue after the breakdown condition lasts beyond the overload disconnection undetected time (topp), even if the load is not actually disconnected. In that case, please review the placement of the motor, wiring, and so forth to improve and to settle the breakdown time within the load disconnection undetected time (topp) (application variations also must be taken into consideration). If the breakdown is not confirmed, operation continues normally. Moreover, the device may be made to operate normally by inserting a capacitor for surge noise suppression between the Outx and Gnd pins as one possible corrective strategy. • Overheating Protection When the product temperature rises and exceeds TTSD , the protection circuit starts operating and all the outputs are set to Disable mode. Note: This product has multichip composition (one IC for control, four MOSFETs, and two chip resistors). Although the location which actually detects temperature is the control IC (MIC), because the main heat sources are the MOSFET chips and the chip resistors, which are separated by a distance from the control IC, some delay will occur while the heat propagates to the control IC. For this reason, because a rapid temperature change cannot be detected, please perform worst-case thermal evaluations in the application design phase. VM Coil Short Circuit +V Coil Short Circuit Stepper Motor VRS RSInt Output Disable VOCP VREF Vg Normal Operation VRS 0 t Figure 10. Motor coil short circuit protection circuit operation. Overcurrent that flows without passing the sense resistor is undetectable. STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 21 PWM Operation at Normal Device Operation VM PWM Operation at Motor Disconnection VM Stepper Motor Stepper Motor Ion Ioff Disconnection Vg Vg VOUT VOUT RS VRS VRS RS Motor Disconnection FET Gate Signal Vg 0 FET Gate Signal Vg 0 VDSS Vout 2 VM VM Vout 0 Breakdown (Avalanche state) 0 VREF VREF VRS VRS 0 0 Motor Disconnection Sense Figure 11. Load open circuit protection circuit operation. Overcurrent that flows without passing the sense resistor is undetectable. Surge does not reach VDSS level Breakdown period shorter than tOPP tOPP Breakdown period longer than tOPP tOPP tOPP VDSS VOUT tCONFIRM tCONFIRM No problem No problem tCONFIRM Improvement required Figure 12. Coil Open Protection STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 22 Application Information Motor Current Ratio Setting (R1, R2, RS) The setting calculation of motor current, IO , for the STA7130MPR series is determined by the ratios of the external components R1 and R2, and current sense resistors, RS . The following is a formula for calculating IO: 1 1 R2 IO = VDD (1) 3 RS R1 + R2 control current varies with conditions of the motor or other factors, but can be estimated from the following formula: IO(min) = VM R 1 –1 –t exp OFF tc (4) Given: VREF = R2 R1 + R2 where VDD (2) if VREF is set less than 0.1 V, normal product variations, impedances of the wiring pattern, and similar factors may influence the IC and the possibility of less accurate current sensing becomes high. The standard voltage for current ITrip that the STA7130MPR series controls is partially divided by the internal DAC: VREF 1 Mode Ratio ITrip = 3 RS (3) Lower Limit of Control Current The STA7130MPR series uses a self-oscillating PWM current control topology in which the off-time is fixed. As energy stored in motor coil is eliminated within the fixed PWM off-time, coil current flows intermittently, as shown in figure 13. Thus, average current decreases and motor torque also decreases. The point at which current starts flowing into the coil intermittently is considered as the lower limit of the control current, IO(min) , where IO is the target current level. The lower limit of A VM is the motor supply voltage, RDS(on) is the MOSFET on-resistance, Rm is the motor winding resistance, Lm is the motor winding reactance, tOFF is the PWM off-time, and tC is calculated as: tc = Lm / R , where R (5) = Rm + RDS(on) + RS (6) Even if the control current value is set at less than the lower limit of the control current, there is no setting at which the IC fails to operate. However, control current will worsen against setting current. Avalanche Energy In the unipolar topology of the STA7130MPR series, a surge voltage (ringing noise) that exceeds the MOSFET capacity to withstand might be applied to the IC. To prevent damage, the ITRIP(Big) ITRIP(Small) 0 Interval where coil current becomes zero A Figure 13. Control current lower limit model waveform STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 23 STA7130MPR series is designed with a built-in MOSFET having sufficient avalanche resistance to withstand this surge voltage. Therefore, even if surge voltages occur, users will be able to use the IC without any problems. However, in cases in which the motor harness is long or the IC is used above its rated current or voltage, there is a possibility that an avalanche energy could be applied that exceeds Sanken design expectations. Thus, users must test the avalanche energy applied to the IC under actual application conditions. The following procedure can be used to check the avalanche energy in an application. Refer to figure 14, to determine the test point. For the purposes of this example, use the following values: VDS(AV) = 140 V, ID = 1 A, and t = 0.5 μs. EAV = VDS(AV) 1/ 2 = 140 (V) 1/ 2 ID (7) t 1 (A) 0.5 10-6 (μs) = 0.035 (mJ) By comparing the EAV calculated with the graph shown in figure 15, the application can be evaluated if it is safe for the IC, by being within the avalanche energy-tolerated does range of the MOSFET. Motor Supply Voltage (VM) and Main Power Supply Voltage (VBB) Because the STA7130MPR series has a structure that separates the control IC (MIC) and the power MOSFETs, the motor supply and main power supply are separated electrically. Therefore, it is possible to drive the IC using different power supplies and different voltages for motor supply and main power supply. However, extra caution is required because the supply voltage ranges differ between the two purposes. Internal Logic Circuits Resetting the Internal Sequencer When power is applied to the main power supply (VBB) the internal reset function operates and the sequencer circuit initializes. The motor driver outputs are set to the excitation Home state. VDS(av) ID To reset the internal sequencer after the motor has been in operation, a reset signal must be input on the Reset pin. In a case in which external reset control is not necessary, and the Reset pin is not used, the Reset pin must be pulled to logic low on the application circuit board. t Figure 14. Test point definition Avalanche Energy, EAV (mJ) The avalanche energy, EAV can be calculated as follows: 12 STA7132MPR STA7131MPR 8 STA7130MPR 4 0 0 25 50 75 100 Case Temperature, TC (°C) 125 150 Figure 15. STA7130MPR iterated avalanche energy tolerated level, EAV(max) STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 24 Clock Input If the Clock input signal stops, excitation changes to the motor Hold state. At this time, there is no difference to the IC if the Clock input signal is at the low level or the high level. The STA7130MPR series is designed to move one sequence increment at a time, according to the current stepping mode, when a positive Clock pulse edge is detected. Chopping Synchronous Circuit The STA7130MPR series has a chopping synchronous function to protect from abnormal noise that may occasionally occur during the motor Hold state. This function can be operated by setting the Sync pin at high level. However, if this function is used during motor rotation, control current does not stabilize, and therefore this may cause reduction of motor torque or increased vibration. So, Sanken does not recommend using this function while the motor is rotating. In addition, the synchronous circuit should be disabled in order to control motor current properly in case it is used other than in dual excitation state (Modes 8 and F) or single excitation Hold state. In normal operation, generally the input signal for switching can be sent from an external microcomputer. However, in applications where the input signal cannot be transmitted adequately such as due to the limitations of a port, the methods described below can be used. The schematic diagram in figure 16 shows how the IC is designed so that the Sync signal can be generated by using the Clock input signal. When a logic high signal is received on the Clock pin, the internal capacitor, C, is charged, and the Sync signal is set to logic low level. However, if the Clock signal cannot rise above logic low level (such as when the circuit between the microcomputer and the IC is not adequate), the capacitor is discharged by the internal resistor, R, and the Sync signal is set to logic high, causing the IC to shift to synchronous mode. The RC time constant in the circuit should be determined by the minimum clock frequency used. In the case of a sequence that keeps the Clock input signal at logic high, an inverter circuit must be added. In a case where the Clock signal is set at an undetermined level the edge detection circuit shown in figure 17 can be used to prepare the signal for the Clock input, allowing correct processing by the circuit shown in figure 16. Output Disable (Sleep1 and Sleep2) Circuits There are two methods to set this IC at motor free-state (coast, with outputs disabled). One is to set the Ref/Sleep1 pin to more than 2 V (Sleep1), and the other is to use the Sleep2 pin. In either way, the IC will change to Sleep mode, decreasing circuit current. The difference between the two methods is that, in Sleep1 mode, the internal sequencer remains enabled. In Sleep2 mode, the internal sequencer is in the Hold state, meaning that if a Clock signal pulse is received, the sequencer remains in the Hold state. Further, the Sleep2 state is used to clear any protection states in effect. When awaking to normal operating mode (motor rotation) from Disable (Sleep1 or Sleep2) mode, set an appropriate delay time from cancellation of the Disable mode to the initial Clock input edge (positive or negative for W option). In doing so, consider not only the rise time for the IC, but also the rise time for the motor excitation current. A delay of at least 100 μs is required (see figure 18). VCC 74HC14 Clock R Sync C Figure 16. Clock signal shutoff detection circuit Clock Step Clock Figure 17. Clock signal edge detection circuit Ref/Sleep1 or Sleep2 100 μs (minimum) Clock t Figure 18. Timing delay between Disable mode cancellation and the next Clock input STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 25 Ref/Sleep1 Pin The Ref/Sleep1 pin provides access to the following functions: following is a simplified formula for calculation of power dissipation: PD = I 2O • Standard voltage setting for output current level setting (RDS(on)+ RS) 2 (8) • Output Enable-Disable control input • The output control current value changes with changes in the VREF setting. Caution is required to avoid inducing losses. • The output enable-disable function control voltage affects the control current values, and caution is required to avoid inducing losses. In addition an output may fail to settle and repeatedly swtich between enabled and disabled states. Logic Input Pins If a logic input pin (Clock, Reset, CW/CCW, M1, M2, or Sync) is not used (fixed logic level), the pin must be tied to VDD or Gnd. Please do not leave them floating, because there is possibility of undefined effects on IC performance when they are left open. Logic Output Pins The MO and Flag output pins are designed as monitor outputs, and inside of the IC both are configured as open drain outputs. If used, both must be pulled up to VDD using a 5.1 to 10 kΩ external resistor (see figure 19). If either or both pins are unused, let the unused pins float. Thermal Design It is not practical to calculate the power dissipation of the STA7130MPR series accurately, because that would require factors that are variable during operation, such as time periods and excitation modes during motor rotation, input frequencies and sequences, and so forth. Given this situation, it is preferable to perform an approximate calculation at worst conditions. The STA7130MPR ESD Protection 5.1 to 10 kΩ Mo or Flag where PD is the power dissipation in the IC, IO is the operating output current, RDS(on) is the resistance of the output MOSFET, and RS is the output current sense resistance. Based on the PD calculated using the above formula, junction temperature, ΔTJ , of the device can be estimated using figure 20. At this time, if junction temperature does not exceed 150°C in the worst condition (the maximum of ambient air temperature of operation), there will be no problem. However, as a last judgment, product heat generation in actual operation should be measured, to confirm a loss and junction temperature from figure 20. When the device is used with a heatsink attached, device package thermal resistance, RθJA , changes the variable used in calculating ΔTj-a. The value of RθFIN is calculated from the following formula: RQJA≈RQJC+RQFin=RQJA–RQCA+RQFin (9) where Rθj-a is the thermal resistance of the heatsink. ΔTj-a can be calculated with using the value of RθJA. The following procedure should be used to measure product temperature and to estimate junction temperature in actual operation: First, measure the temperature rise at the center of the back surface of the device case (ΔTc-a). Increase in Junction Temperature, ∆TJ (°C) These functions are further described in the Truth Table section, and in the discussion of output disabling, above. In addition, please observe the following: 150 125 100 ∆Tj-a = 35.7 × PD 75 50 ∆Tc-a = 22.9 × PD 25 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Maximum Allowable Power Dissipation, PD(max) (W) Figure 19. Mo pin and Flag pin equivalent circuit Figure 20. Temperature increase STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 26 Second, estimate the loss (PD) and junction temperature (Tj) from the temperature rise with reference to figure 20, the temperature increase graph. At this point, the device temperature rise (ΔTc-a) and the junction temperature rise (ΔTj) can be estimated under the following equation: ΔTJ ≈ ΔTc-a+PD Rθj-c (10) Notes The STA7130MPR series is designed as a multichip package, with separate power elements (MOSFET), control IC (MIC), and sense resistance. Consequently, because the control IC cannot accurately detect the temperature of the power elements (which are the primary sources of heat), the device does not provide a protection function against overheating. For thermal protection, users must conduct sufficient thermal evaluations to be able to ensure that the junction temperature does not exceed the warranty level (150°C). This thermal design information is provided for preliminary design estimations only. The thermal performance of the device will be significantly determined by the conditions of the application, in particular the state of the mounting PCB, heatsink, and the ambient air. Before operating the device in an application, the user must experimentally determine the actual thermal performance. The maximum recommended case temperatures (at the center back surface) for the devices are: • With no external heatsink connection: 85°C • With external heatsink connection: 75°C STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 27 Characteristic Performance Output MOSFET On-Voltage, VDS(on) , Characteristics STA7130MP 1.4 Io=1.5A Io=1A 1.2 1.2 1.0 0.8 Io=0.5A 0.6 V DS(on) (V) 1.0 V DS(on) (V) STA7131MP 1.4 0.8 0.4 0.4 0.2 0.2 0.0 0.0 -25 Io=1A 0.6 -25 0 25 50 75 100 125 Case Temperature, TC (°C) 0 25 50 75 100 125 Case Temperature, TC (°C) STA7132MP 1.2 Io=2A 1.0 V DS(on) (V) 0.8 0.6 Io=1A 0.4 0.2 0.0 -25 0 25 50 75 100 125 Case Temperature, TC (°C) STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 28 Output MOSFET Body Diode Forward Voltage, VF , Characteristics STA7130MPR STA7131MPR 1.1 1.0 1.0 0.9 0.9 V F (V) V F (V) 1.1 0.8 Io=1A 0.8 0.7 Io=0.5A 0.7 Io=1.5A Io=1A 0.6 -25 0.6 0 25 50 75 100 125 Case Temperature, TC (°C) -25 0 25 50 75 100 125 Case Temperature, TC (°C) STA7132MPR 1.1 1.0 V F (V) 0.9 Io=2A 0.8 Io=1A 0.7 0.6 -25 0 25 50 75 100 125 Case Temperature, TC (°C) STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 29 Sanken reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Therefore, the user is cautioned to verify that the information in this publication is current before placing any order. When using the products described herein, the applicability and suitability of such products for the intended purpose shall be reviewed at the users responsibility. Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to society due to device failure or malfunction. Sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Their use in any application requiring radiation hardness assurance (e.g., aerospace equipment) is not supported. When considering the use of Sanken products in applications where higher reliability is required (transportation equipment and its control systems or equipment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written confirmation of your specifications. The use of Sanken products without the written consent of Sanken in applications where extremely high reliability is required (aerospace equipment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited. The information included herein is believed to be accurate and reliable. Application and operation examples described in this publication are given for reference only and Sanken assumes no responsibility for any infringement of industrial property rights, intellectual property rights, or any other rights of Sanken or any third party that may result from its use. The contents in this document must not be transcribed or copied without Sanken’s written consent. STA7130MPR-AN December 24, 2013 SANKEN ELECTRIC CO., LTD. 30