Data Sheet

74HC4040-Q100;
74HCT4040-Q100
12-stage binary ripple counter
Rev. 1 — 24 March 2014
Product data sheet
1. General description
The 74HC4040-Q100; 74HCT4040-Q100 is a 12-stage binary ripple counter with a clock
input (CP), an overriding asynchronous master reset input (MR) and twelve parallel
outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A
HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Complies with JEDEC standard no. 7A
 Input levels:
 For 74HC4040-Q100: CMOS level
 For 74HCT4040-Q100: TTL level
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Multiple package options
3. Applications
 Frequency dividing circuits
 Time delay circuits
 Control counters
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
12-stage binary ripple counter
4. Ordering information
Table 1.
Ordering information
Type number
Package
74HC4040D-Q100
Temperature range
Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
40 C to +125 C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16
leads; body width 4.4 mm
SOT403-1
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5  3.5  0.85 mm
74HCT4040D-Q100
74HC4040DB-Q100
74HCT4040DB-Q100
74HC4040PW-Q100
74HCT4040PW-Q100
74HC4040BQ-Q100
74HCT4040BQ-Q100
SOT763-1
5. Functional diagram
CP
MR
10
11
T
12-STAGE COUNTER
CD
9
7
6
5
3
2
4
13
12
14
15
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad589
Fig 1.
Functional diagram
CTR12
10
11
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
9
7
6
5
3
2
4
13
12
14
15
1
10
11
CT
11
001aad585
Fig 2.
Logic symbol
74HC_HCT4040_Q100
Product data sheet
0
+
CT = 0
9
7
6
5
3
2
4
13
12
14
15
1
001aad586
Fig 3.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 19
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
12-stage binary ripple counter
CP
FF
T 1
Q
FF
T 2
Q
Q
FF
T 3
Q
RD
Q
FF
T 4
Q
RD
Q
FF
T 5
Q
RD
Q
FF
T 6
Q
Q
RD
Q
RD
RD
MR
Q0
FF
T 7
Q
Q1
FF
T 8
Q
Q
Q2
FF
T 9
Q
RD
FF
T 10
Q
RD
Q6
Q
Q3
FF
T 11
Q
RD
Q7
Q
Q
FF
T 12
Q
RD
Q8
Q5
Q4
Q
RD
Q9
Q
RD
Q10
Q11
001aad588
Fig 4.
Logic diagram
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 19
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
12-stage binary ripple counter
6. Pinning information
6.1 Pinning
4
WHUPLQDO
LQGH[DUHD
+&4
+&74
9&&
+&4
+&74
4
4
4
4
9&&
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
05
4
4
&3
*1'
4
4
05
&3
*1'
*1'
DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO16, SSOP16 and
TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q11
1
output 11
Q5
2
output 5
Q4
3
output 4
Q6
4
output 6
Q3
5
output 3
Q2
6
output 2
Q1
7
output 1
GND
8
ground (0 V)
Q0
9
output 0
CP
10
clock input (HIGH-to-LOW, edge-triggered)
MR
11
master reset input (active HIGH)
Q8
12
output 8
Q7
13
output 7
Q9
14
output 9
Q10
15
output 10
VCC
16
positive supply voltage
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 19
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
12-stage binary ripple counter
7. Functional description
7.1 Function table
Table 3.
Function table
Input
Output
CP
MR

L
no change

L
count
X
H
L
[1]
Q0 to Q11
H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition.
7.2 Timing diagram
1
2
4
8
16
32
64
128
256
512 1024 2048 4096
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
001aad587
Fig 7.
Timing diagram
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
Min
Max
Unit
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IOK
output clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IO
output current
0.5 V < VO < VCC + 0.5 V
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
-
50
mA
Tstg
storage temperature
65
+150
C
-
500
mW
[1]
Tamb = 40 C to +125 C
total power dissipation
Ptot
[1]
For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70 C, Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC4040-Q100
74HCT4040-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
t/V
input transition rise and fall rate
40
+25
+125
40
+25
+125
C
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
Typ
VCC = 2.0 V
1.5
VCC = 4.5 V
VCC = 6.0 V
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
1.2
-
1.5
-
1.5
-
3.15
2.4
-
3.15
-
3.15
-
V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
74HC4040-Q100
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
V
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH
VOL
HIGH-level
output voltage
LOW-level
output voltage
25 C
Conditions
Min
Typ
IO = 20 A; VCC = 2.0 V
1.9
IO = 20 A; VCC = 4.5 V
4.4
IO = 20 A; VCC = 6.0 V
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
2.0
-
1.9
-
1.9
-
V
4.5
-
4.4
-
4.4
-
V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
CI
input
capacitance
-
3.5
-
pF
74HCT4040-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4 mA
3.98
4.32
-
3.84
-
3.7
-
V
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA
-
0.15
0.26
-
0.33
-
0.4
V
VOL
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
-
0.1
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
A
ICC
additional
supply current
per input pin;
VI = VCC  2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
capacitance
74HC_HCT4040_Q100
Product data sheet
pin CP
-
85
306
-
383
-
417
A
pin MR
-
110
396
-
495
-
539
A
-
3.5
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
-
-
-
-
pF
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC4040-Q100
tpd
propagation
delay
[1]
CP to Q0; see Figure 8
VCC = 2.0 V
-
47
150
-
190
-
225
ns
VCC = 4.5 V
-
17
30
-
38
-
45
ns
VCC = 5.0 V; CL = 15 pF
-
14
-
-
-
-
-
ns
VCC = 6.0 V
-
14
26
-
33
-
38
ns
VCC = 2.0 V
-
28
100
-
125
-
150
ns
VCC = 4.5 V
-
10
20
-
25
-
30
ns
VCC = 5.0 V; CL = 15 pF
-
8
-
-
-
-
ns
VCC = 6.0 V
-
8
17
-
21
-
26
ns
-
61
185
-
230
-
280
ns
-
22
37
-
46
-
56
ns
-
18
31
-
39
-
48
ns
Qn to Qn+1; see Figure 8
tPHL
HIGH to LOW MR to Qn; see Figure 8
propagation
VCC = 2.0 V
delay
VCC = 4.5 V
VCC = 6.0 V
tt
tW
[2]
transition time Qn; see Figure 8
pulse width
-
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC = 4.5 V
-
7
15
-
19
-
22
ns
VCC = 6.0 V
-
6
13
-
16
-
19
ns
VCC = 2.0 V
80
14
-
100
-
120
-
ns
VCC = 4.5 V
16
5
-
20
-
24
-
ns
VCC = 6.0 V
14
4
-
17
-
20
-
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
VCC = 2.0 V
50
8
-
65
-
75
-
ns
VCC = 4.5 V
10
3
-
13
-
15
-
ns
VCC = 6.0 V
9
2
-
11
-
13
-
ns
VCC = 2.0 V
6
27
-
4.8
-
4
-
MHz
VCC = 4.5 V
30
82
-
24
-
20
-
MHz
-
MHz
-
MHz
CP input, HIGH or LOW;
see Figure 8
MR input, HIGH;
see Figure 8
trec
fmax
recovery time
maximum
frequency
MR to CP; see Figure 8
CP input; see Figure 8
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
74HC_HCT4040_Q100
Product data sheet
35
90
98
-
28
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
-
24
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
CPD
power
dissipation
capacitance
VI = GND to VCC
[3]
CP to Q0; see Figure 8
[1]
-
20
Min
Max
Min
Max
-
-
-
-
pF
-
-
-
ns
-
30
ns
-
-
ns
-
74HCT4040-Q100
tpd
propagation
delay
VCC = 4.5 V
-
19
40
-
VCC = 5.0 V; CL = 15 pF
-
16
-
-
50
-
60
ns
VCC = 4.5 V
-
10
20
-
VCC = 5.0 V; CL = 15 pF
-
8
-
-
-
23
45
-
56
-
68
ns
-
7
15
-
19
-
22
ns
16
7
-
20
-
24
-
ns
16
6
-
20
-
24
-
ns
10
2
-
13
-
15
-
ns
30
72
-
24
-
20
-
MHz
-
79
-
Qn to Qn+1; see Figure 8
tPHL
tt
HIGH to LOW MR to Qn; see Figure 8
propagation
VCC = 4.5 V
delay
pulse width
-
[2]
transition time Qn; see Figure 8
VCC = 4.5 V
tW
25
CP input, HIGH or LOW;
see Figure 8
VCC = 4.5 V
MR input, HIGH;
see Figure 8
VCC = 4.5 V
trec
recovery time
MR to CP; see Figure 8
VCC = 4.5 V
fmax
maximum
frequency
CP input; see Figure 8
power
dissipation
capacitance
VI = GND to VCC
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
CPD
[1]
tpd is the same as tPHL, tPLH.
[2]
tt is the same as tTHL, tTLH.
[3]
[3]
-
20
-
-
-
-
-
MHz
-
-
-
-
pF
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 19
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
12-stage binary ripple counter
12. Waveform and test circuit
9,
90
05LQSXW
W:
WUHF
9,
IPD[
90
&3LQSXW
W3+/
W3/+
W:
4RU4Q
RXWSXW
W3+/
90
W7/+
W7+/
DDG
74HC4040-Q100: VM = 50 %; VI = GND to VCC.
74HCT4040-Q100: VM = 1.3 V; VI = GND to 3 V.
Fig 8.
Clock propagation delays, pulse width, transition times, maximum pulse frequency and master resets
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
9,
QHJDWLYH
SXOVH
W:
90
90
*1'
WI
9,
WI
SRVLWLYH
SXOVH
*1'
WU
WU
90
90
W:
9&&
*
9,
92
'87
57
&/
DDK
Test data is given in Table 8.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 9.
Table 8.
Test circuit for measuring switching times
Test data
Type
Input
Load
Test
VI
tr, tf
CL
74HC4040-Q100
VCC
6.0 ns
15 pF, 50 pF
tPLH, tPHL
74HCT4040-Q100
3.0 V
6.0 ns
15 pF, 50 pF
tPLH, tPHL
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 19
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
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74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 19
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NXP Semiconductors
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74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 19
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
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74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 19
74HC4040-Q100; 74HCT4040-Q100
NXP Semiconductors
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74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
14. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
TTL
Transistor-Transistor Logic
15. Revision history
Table 10.
Revision history
Document ID
Release date
74HC_HCT4040_Q100 v.1 20140324
74HC_HCT4040_Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT4040_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT4040_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 19
NXP Semiconductors
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
18. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveform and test circuit . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 March 2014
Document identifier: 74HC_HCT4040_Q100