Data Sheet

HEF4040B-Q100
12-stage binary ripple counter
Rev. 1 — 4 April 2013
Product data sheet
1. General description
The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input (CP), an
overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of CP. Each counter stage is
a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to
its Schmitt trigger action.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Tolerant of slow clock rise and fall time
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
3. Applications
 Frequency dividing circuits
 Time delay circuits
 Control counters
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
HEF4040BT-Q100 SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
5. Functional diagram
CP
MR
10
11
T
12-STAGE COUNTER
CD
9
7
6
5
3
2
4
13
12
14
15
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad589
Fig 1.
Functional diagram
FF 1
Q
CP
FF 2
Q
T
FF 12
Q
T
Q
CD
T
Q
Q
CD
CD
MR
Q0
Q1
Q11
001aae615
Fig 2.
Logic diagram
HEF4040B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
2 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
1
2
4
8
16
32
64
128
256
512 1024 2048 4096
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
001aad587
Fig 3.
Timing diagram
6. Pinning information
6.1 Pinning
+()%4
4
9''
4
4
4
4
4
4
4
4
4
05
4
&3
966
4
DDD
Fig 4.
Pin configuration
HEF4040B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
3 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VSS
8
ground supply voltage
Q0 to Q11
9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1
parallel output
CP
10
clock input (HIGH-to-LOW edge-triggered)
MR
11
master reset input (active HIGH)
VDD
16
supply voltage
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
0.5
+18
V
-
10
mA
0.5
VDD + 0.5
V
-
10
mA
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
-
10
mA
IDD
supply current
-
50
mA
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+85
C
-
500
mW
-
100
mW
Ptot
total power dissipation
P
power dissipation
[1]
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
[1]
per output
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol
Parameter
VDD
VI
Conditions
Min
Typ
Max
Unit
supply voltage
3
-
15
V
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
ms/V
VDD = 10 V
-
-
0.5
ms/V
VDD = 15 V
-
-
0.08
ms/V
HEF4040B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
4 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
9. Static characteristics
Table 5.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
VDD
IO < 1 A
LOW-level output voltage
HIGH-level output current
LOW-level output current
input leakage current
IDD
supply current
input capacitance
HEF4040B_Q100
Product data sheet
Tamb = 40 C
Tamb = 25 C
Tamb = 85 C
Min
Max
Min
Max
Min
Max
Unit
5V
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
mA
VO = 4.6 V
5V
-
0.52
-
0.44
-
0.36
mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
IO < 1 A
HIGH-level output voltage IO < 1 A
ILI
CI
Conditions
IO < 1 A
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
VO = 1.5 V
15 V
3.6
-
3.0
-
2.4
-
mA
15 V
-
0.3
-
0.3
-
1.0
A
5V
-
20
-
20
-
150
A
10 V
-
40
-
40
-
300
A
15 V
-
80
-
80
-
600
A
-
-
-
-
7.5
-
-
IO = 0 A
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
pF
© NXP B.V. 2013. All rights reserved.
5 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
10. Dynamic characteristics
Table 6.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure 6.
Symbol
Parameter
Conditions
tPHL
HIGH to LOW
propagation delay
CP  Q0
see Figure 5
Qn  Qn + 1
MR  Qn
see Figure 5
LOW to HIGH
propagation delay
tPLH
CP  Q0
see Figure 5
Extrapolation formula[1]
Min
Typ
Max
Unit
5V
78 ns + (0.55 ns/pF)CL
-
105
210
ns
10 V
34 ns + (0.23 ns/pF)CL
-
45
90
ns
15 V
27 ns + (0.16 ns/pF)CL
-
35
70
ns
5V
[2]
(0.55 ns/pF)CL
-
35
70
ns
10 V
[2]
(0.23 ns/pF)CL
-
15
30
ns
15 V
[2]
VDD
(0.16 ns/pF)CL
-
10
20
ns
5V
63 ns + (0.55 ns/pF)CL
-
90
180
ns
10 V
29 ns + (0.23 ns/pF)CL
-
40
80
ns
15 V
22 ns + (0.16 ns/pF)CL
-
30
60
ns
5V
58 ns + (0.55 ns/pF)CL
-
85
170
ns
10 V
29 ns + (0.23 ns/pF)CL
-
40
80
ns
22 ns + (0.16 ns/pF)CL
-
30
60
ns
5V
[2]
(0.55 ns/pF)CL
-
35
70
ns
10 V
[2]
(0.23 ns/pF)CL
-
15
30
ns
15 V
[2]
(0.16 ns/pF)CL
-
10
20
ns
5V
[3]
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
15 V
Qn  Qn + 1
transition time
tt
pulse width
tW
recovery time
trec
maximum
frequency
fmax
see Figure 5
-
20
40
ns
CP input HIGH;
minimum width;
see Figure 5
5V
50
25
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
MR input HIGH;
minimum width;
see Figure 5
5V
40
20
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
40
20
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
10
20
-
MHz
10 V
15
30
-
MHz
15 V
25
50
-
MHz
MR input;
see Figure 5
CP input;
see Figure 5
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
For loads other than 50 pF at the nth output, use the slope given.
[3]
tt is the same as tTHL and tTLH.
HEF4040B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
6 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
Table 7.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol
Parameter
dynamic power
dissipation
PD
VDD
Typical formula for PD (W)
where:
PD = 400  fi + (fo  CL)  VDD
5V
2
fi = input frequency in MHz,
10 V
PD = 2000  fi + (fo  CL)  VDD2
fo = output frequency in MHz,
15 V
PD = 5200  fi + (fo  CL)  VDD
CL = output load capacitance in pF,
2
VDD = supply voltage in V,
(fo  CL) = sum of the outputs.
11. Waveforms
VI
VM
MR input
VSS
1/fmax
tW
trec
VI
VM
CP input
VSS
tPHL
tPLH
VOH
Q0 or Qn
output
VOL
tW
tPHL
VM
tTLH
tPLH
tPHL
tTHL
VOH
VM
Qn + 1 output
VOL
001aaj763
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.
Measurement points are given in Table 8, test circuit in Figure 6 and test data in Table 9
Fig 5.
Waveforms showing propagation delays for MR to Qn and CP to Q0, minimum MR and CP pulse widths
Table 8.
Measurement points
Supply voltage
Input
VDD
VI
VM
VM
5 V to 15 V
VDD or VSS
0.5VDD
0.5VDD
HEF4040B_Q100
Product data sheet
Output
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
7 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
tW
VI
90 %
90 %
negative
pulse
VM
VM
10 %
0V
VI
10 %
tf
tr
tr
tf
90 %
positive
pulse
90 %
VM
VM
10 %
0V
10 %
tW
001aaj781
a. Input waveforms
VDD
VI
VO
G
DUT
CL
RT
001aag182
b. Test circuit
Test data is given in Table 9.
Definitions test circuit:
DUT = Device Under Test;
CL = load capacitance, including the jig and probe capacitance;
RL = load resistance, which should be equal to the output impedance of the pulse generator.
Fig 6.
Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
 20 ns
50 pF
HEF4040B_Q100
Product data sheet
Load
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
8 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 7.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4040B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
9 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4040B_Q100 v.1
20130404
Product data sheet
-
-
HEF4040B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
10 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4040B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
11 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4040B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
12 of 13
HEF4040B-Q100
NXP Semiconductors
12-stage binary ripple counter
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 April 2013
Document identifier: HEF4040B_Q100