Data Sheet

74LV393-Q100
Dual 4-bit binary ripple counter
Rev. 2 — 17 September 2014
Product data sheet
1. General description
The 74LV393-Q100 is a low–voltage Si-gate CMOS device and is pin and function
compatible with 74HC393-Q100 and 74HCT393-Q100.
The 74LV393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock
input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel
outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A
HIGH on nMR clears the counter stages and forces the outputs LOW, independent of the
state of nCP.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Optimized for low voltage applications: 1.0 V to 3.6 V
 Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
 Typical VOLP (output ground bounce) 0.8 V at VCC = 3.3 V, Tamb = 25 C
 Typical VOHV (output VOH undershoot) 2 V at VCC = 3.3 V, Tamb = 25 C
 Two 4-bit binary counters with individual clocks
 Divide-by any binary module up to 28 in one package
 Two master resets to clear each 4-bit counter individually
 Complies with JEDEC standard no. 7A
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LV393D-Q100
40 C to +125 C
SO14
plastic small outline package; 14 leads; body
width 3.9 mm
SOT108-1
74LV393PW-Q100
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14
leads; body width 4.4 mm
SOT402-1
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
4. Functional diagram
4
&75
&3
4
4
4
4
05
&75
&3
4
4
4
05
Fig 2.
&3
05
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5,33/(
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4
4
4
4
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4
4
4
74LV393_Q100
Product data sheet
DDG
DDG
Functional diagram
IEC logic symbol
Fig 3.
4
DDG
Logic symbol
&7
DDG
Fig 1.
&7 &7
&7 Fig 4.
State diagram
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
4
&3
7
4
))
7
5'
4
))
7
5'
4
))
7
5'
))
5'
05
4
4
4
4
DDG
Fig 5.
Logic diagram (one counter)
5. Pinning information
5.1 Pinning
/94
&3
9&&
05
&3
4
05
4
4
4
4
4
*1'
/94
&3
05
9&&
&3
4
05
4
4
4
4
4
4
*1'
4
4
4
DDD
Fig 6.
Pin configuration SO14
74LV393_Q100
Product data sheet
DDD
Fig 7.
Pin configuration TSSOP14
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1CP
1
clock input (HIGH-to-LOW, edge-triggered)
1MR
2
asynchronous master reset input (active HIGH)
1Q0
3
flip-flop output
1Q1
4
flip-flop output
1Q2
5
flip-flop output
1Q3
6
flip-flop output
GND
7
ground (0 V)
2Q3
8
flip-flop output
2Q2
9
flip-flop output
2Q1
10
flip-flop output
2Q0
11
flip-flop output
2MR
12
asynchronous master reset input (active HIGH)
2CP
13
clock input (HIGH-to-LOW, edge-triggered)
VCC
14
supply voltage
6. Functional description
Table 3.
Count sequence for one counter [1]
Count
Output
nQ0
nQ1
nQ2
nQ3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
10
L
H
L
H
11
H
H
L
H
12
L
L
H
H
13
H
L
H
H
14
L
H
H
H
15
H
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level.
74LV393_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+4.6
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
-
50
mA
IO
output current
VO = 0.5 V to VCC + 0.5 V
-
25
mA
ICC
supply current
-
+50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
SO14 package
[1]
-
500
mW
TSSOP14 packages
[2]
-
400
mW
Min
Typ
Max
Unit
1.0
3.3
3.6
V
total power dissipation
Ptot
[1]
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
[2]
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
VCC
supply voltage
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
-
+125
C
t/V
input transition rise and fall rate
-
-
500
ns/V
74LV393_Q100
Product data sheet
Conditions
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
-
-
200
ns/V
VCC = 2.7 V to 3.6 V
-
-
100
ns/V
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Rev. 2 — 17 September 2014
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74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
VOH
Conditions
40 C to +85 C
40 C to +125 C
Min
Typ[1]
Max
Min
Max
Unit
VCC = 1.2 V
0.9
-
-
0.9
-
V
VCC = 2.0 V
1.4
-
-
1.4
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 1.2 V
-
-
0.3
-
0.3
V
VCC = 2.0 V
-
-
0.6
-
0.6
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
-
1.2
-
-
-
V
HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
1.8
2.0
-
1.8
-
V
IO = 100 A; VCC = 2.7 V
2.5
2.7
-
2.5
-
V
IO = 100 A; VCC = 3.0 V
2.80
3.0
-
2.8
-
V
IO = 6 mA; VCC = 3.0 V
2.40
2.82
-
2.20
-
V
IO = 100 A; VCC = 1.2 V
-
0
-
-
-
V
IO = 100 A; VCC = 2.0 V
-
0
0.2
-
0.2
V
IO = 100 A; VCC = 2.7 V
-
0
0.2
-
0.2
V
LOW-level output voltage VI = VIH or VIL
VOL
IO = 100 A; VCC = 3.0 V
-
0
0.2
-
0.2
V
IO = 6 mA; VCC = 3.0 V
-
0.25
0.40
-
0.50
V
II
input leakage current
VI = VCC or GND; VCC = 3.6 V
-
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
-
-
20.0
-
160
A
ICC
additional supply current
quiescent per input
VI = VCC  0.6 V;
VCC = 2.7 V to 3.6 V
-
-
500
-
850
A
CI
input capacitance
-
3.5
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 C.
74LV393_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10.
Symbol
tpd
Parameter
propagation delay
40 C to +85 C
Conditions
Min
Max
Min
Max
VCC = 1.2 V
-
75
-
-
-
ns
VCC = 2.0 V
-
26
49
-
60
ns
VCC = 2.7 V
-
19
36
-
44
ns
VCC = 3.3 V, CL = 15 pF
-
12
-
-
-
ns
VCC = 3.0 V to 3.6 V
-
14
29
-
35
ns
VCC = 1.2 V
-
25
-
-
-
ns
VCC = 2.0 V
-
9
17
-
20
ns
VCC = 2.7 V
-
6
13
-
15
ns
VCC = 3.3 V, CL = 15 pF
-
4
-
-
-
ns
-
5[2]
10
-
12
ns
VCC = 1.2 V
-
70
-
-
-
ns
VCC = 2.0 V
-
24
44
-
54
ns
VCC = 2.7 V
-
18
33
-
40
ns
VCC = 3.3 V, CL = 15 pF
-
11
-
-
-
ns
VCC = 3.0 V to 3.6 V
-
13[2]
26
-
32
ns
VCC = 2.0 V
-
-
-
-
-
ns
VCC = 2.7 V
-
-
-
-
-
ns
VCC = 3.0 V to 3.6 V
-
-
-
-
-
ns
VCC = 2.0 V
34
10
-
41
-
ns
VCC = 2.7 V
25
8
-
30
-
ns
VCC = 3.0 V to 3.6 V
20
6[2]
-
24
-
ns
VCC = 2.0 V
34
12
-
41
-
ns
VCC = 2.7 V
25
9
-
30
-
ns
VCC = 3.0 V to 3.6 V
20
7[2]
-
24
-
ns
VCC = 1.2 V
-
5
-
-
-
ns
VCC = 2.0 V
5
2
-
5
-
ns
VCC = 2.7 V
5
2
-
5
-
ns
5
1[2]
-
5
-
ns
nCP to nQ0; see Figure 8
nQ to nQn1; see Figure 8
[3]
[3]
VCC = 3.0 V to 3.6 V
tPHL
tt
tW
HIGH to LOW
propagation delay
transition time
pulse width
40 C to +125 C Unit
Typ[1]
nMR to nQx; see Figure 9
nQx; see Figure 8
[4]
nCP HIGH or LOW; see Figure 8
nMR HIGH; see Figure 9
trec
recovery time
nMR to nCP; see Figure 9
VCC = 3.0 V to 3.6 V
74LV393_Q100
Product data sheet
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Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10.
Symbol
fmax
Parameter
maximum
frequency
40 C to +85 C
Conditions
Min
Max
Min
Max
VCC = 2.0 V
14
53
-
12
-
MHz
VCC = 2.7 V
19
72
-
16
-
MHz
-
99
-
-
-
MHz
24
90[2]
-
20
-
MHz
-
23[2]
-
-
-
pF
see Figure 8
VCC = 3.3 V, CL = 15 pF
VCC = 3.0 V to 3.6 V
power dissipation
capacitance
CPD
40 C to +125 C Unit
Typ[1]
VI = GND to VCC
[1]
All typical values are measured at Tamb = 25 C.
[2]
Typical values are measured at VCC = 3.3 V.
[3]
tpd is the same as tPLH and tPHL.
[4]
tt is the same as tTHL and tTLH.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
[5]
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
74LV393_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
10.1 Waveforms
I PD[
9,
LQSXWQ&3
90
*1'
W 3+/
W 3/+
92+
RXWSXWQ4[
90
92/
W 7+/
W 7/+
DDG
tTLH = 10 % and tTHL = 90 %,
Measurement points are given in Table 8.
Fig 8.
Table 8.
Propagation delays clock (nCP) to output (nQx), output transition times and maximum clock frequency
Measurement points
Supply voltage VCC
Input
Output
VM
VM
VX
VY
< 2.7 V
0.5VCC
0.5VCC
VOL + 0.1VCC
VOH  0.1VCC
2.7 V to 3.6 V
1.5VCC
1.5VCC
VOL + 0.3VCC
VOH  0.3VCC
9,
LQSXWQ05
90
*1'
W:
W UHF
9,
LQSXWQ&3
90
*1'
W 3+/
92+
RXWSXWQ4[
90
92/
DDG
Measurement points are given in Table 8.
Fig 9.
Propagation delays clock (nCP) to output (nQx), pulse width master reset (nMR), and recovery time
master reset (nMR) to clock (nCP)
74LV393_Q100
Product data sheet
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Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
9,
W:
QHJDWLYH
SXOVH
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
9
90
90
90
W:
9(;7
9&&
9,
*
5/
92
'87
57
5/
&/
DDH
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 10. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPHL, tPLH
< 2.7 V
VCC
 2.5 ns
50 pF
1 k
open
2.7 V to 3.6 V
2.7 V
 2.5 ns
15 pF, 50 pF
1 k
open
74LV393_Q100
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
11. Package outline
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Fig 11. Package outline SOT108-1 (SO14)
74LV393_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
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Fig 12. Package outline SOT402-1 (TSSOP14)
74LV393_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
12. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
13. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LV393_Q100 v.2
20140917
Product data sheet
-
74LV393_Q100 v.1
Modifications:
74LV393_Q100 v.1
74LV393_Q100
Product data sheet
•
Figure 10 and Table 9 updated because of a missing load resistance in the test circuit.
20140526
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
-
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 16
74LV393-Q100
NXP Semiconductors
Dual 4-bit binary ripple counter
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LV393_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 16
74LV393-Q100
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LV393_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 16
NXP Semiconductors
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16. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
10.1
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 17 September 2014
Document identifier: 74LV393_Q100