74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs Rev. 1 — 24 March 2014 Product data sheet 1. General description The 74HC4017-Q100; 74HCT4017-Q100 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9). It has an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). Either a LOW-to-HIGH transition at CP0 while CP1 is LOW, or a HIGH-to-LOW transition at CP1 while CP0 is HIGH, advances the counter. The Q5-9 output is LOW while the counter is in states 5, 6, 7, 8 and 9. When cascading counters, it can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). An internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses provides automatic code correction of the counter. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC4017-Q100: CMOS level For 74HCT4017-Q100: TTL level Complies with JEDEC standard no. 7 A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4017D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC4017PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC4017BQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal-enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm 40 C to +125 C SO16 74HC4017-Q100 74HCT4017-Q100 74HCT4017D-Q100 74HCT4017BQ-Q100 40 C to +125 C plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 DHVQFN16 plastic dual in-line compatible thermal-enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm 4. Functional diagram 13 14 15 CP1 CP0 5-STAGE JOHNSON COUNTER MR Q5-9 DECODING AND OUTPUT CIRCUITRY 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 3 Fig 1. 2 4 7 10 1 5 6 9 11 001aah242 Functional diagram 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs CTRDIV10/DEC 14 13 14 15 0 Q0 3 Q1 2 Q2 4 Q3 7 3 Q4 10 4 Q5 1 5 Q6 5 6 Q7 6 7 Q8 9 8 Q9 11 9 Q5-9 12 CT≥5 CP1 CP0 MR & 13 15 1 001aah239 Fig 2. Fig 3. Q FF 1 CP Q RD Q FF 2 CP Q RD D CP0 2 4 7 10 1 5 6 9 11 12 001aah240 Logic symbol CP1 2 CT = 0 3 IEC logic symbol Q FF 3 CP Q RD D Q FF 4 CP Q RD D Q FF 5 CP Q RD D D MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q5-9 001aah243 Fig 4. Logic diagram 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs CP0 INPUT CP1 INPUT MR INPUT Q0 OUTPUT Q1 OUTPUT Q2 OUTPUT Q3 OUTPUT Q4 OUTPUT Q5 OUTPUT Q6 OUTPUT Q7 OUTPUT Q8 OUTPUT Q9 OUTPUT Q5-9 OUTPUT Fig 5. 001aah244 Timing diagram 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs 5. Pinning information 5.1 Pinning 4 WHUPLQDO LQGH[DUHD +&4 +&74 05 4 &3 4 &3 4 4 4 4 4 4 *1' 05 4 &3 4 &3 4 4 4 4 4 *1' 4 4 4 4 9&& 4 *1' 4 9&& +&4 +&74 DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 6. Pin configuration SO16 and TSSOP16 Fig 7. Pin configuration DHVQFN16 5.2 Pin description Table 2. Pin description Symbol Pin Q[0:9] 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output Description GND 8 ground (0 V) Q5-9 12 carry output (active LOW) CP1 13 clock input (HIGH-to-LOW edge-triggered) CP0 14 clock input (LOW-to-HIGH edge-triggered) MR 15 master reset input (active HIGH) VCC 16 supply voltage 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs 6. Functional description Table 3. Function table[1] MR CP0 CP1 Operation H X X Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW L H counter advances L L counter advances L L X no change L X H no change L H no change L L no change [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition; 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C SO16 package [2] - 500 mW TSSOP16 package [3] - 500 mW DHVQFN16 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. [4] Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC4017-Q100 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V ambient temperature Tamb - - 83 ns/V 40 - +125 C 74HCT4017-Q100 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V t/V input transition rise and fall rate VCC = 4.5 V - 1.67 139 ns/V Tamb ambient temperature 40 - +125 C 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V 74HC4017-Q100 VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - 0.1 - 1.0 - 1.0 A supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A input capacitance - 3.5 - - - - - pF II input leakage current ICC CI VI = VCC or GND; VCC = 6.0 V 74HCT4017-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V IO = 4 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A - - 8.0 - 80 - 160 A CP0 input - 25 90 - 113 - 123 A CP1 input - 40 144 - 180 - 196 A MR input - 50 180 - 225 - 245 A - 3.5 - - - - - pF II input leakage current ICC supply current VI = VCC or GND; VCC = 5.5 V; IO = 0 A ICC additional per input pin; supply current VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A CI input capacitance 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 63 230 - 290 - 345 ns 74HC4017-Q100 tpd propagation delay CP0 to Qn; CP0 to Q5-9; see Figure 10 [1] VCC = 2.0 V VCC = 4.5 V - 23 46 - 58 - 69 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns VCC = 6.0 V - 18 39 - 49 - 59 ns VCC = 2.0 V - 61 250 - 315 - 375 ns VCC = 4.5 V - 22 50 - 63 - 75 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns VCC = 6.0 V - 18 43 - 54 - 64 ns VCC = 2.0 V - 52 230 - 290 - 345 ns VCC = 4.5 V - 19 46 - 58 - 69 ns VCC = 6.0 V - 15 39 - 49 - 59 ns VCC = 2.0 V - 55 230 - 290 - 345 ns VCC = 4.5 V - 20 46 - 58 - 69 ns - 16 39 - 49 - 59 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns CP1 to Qn; CP1 to Q5-9; see Figure 10 tPHL tPLH HIGH to LOW propagation delay LOW to HIGH propagation delay MR to Q[1:9]; see Figure 10 MR to Q5-9, Q0; see Figure 10 VCC = 6.0 V tt tW transition time pulse width [2] see Figure 10 CP0 and CP1 (HIGH or LOW); see Figure 9 MR (HIGH); see Figure 9 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11. Symbol Parameter tsu th trec fmax set-up time hold time recovery time maximum frequency 25 C Conditions Min Typ Max Min Max Min Max VCC = 2.0 V 50 8 - 65 - 75 - ns VCC = 4.5 V 10 3 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns VCC = 2.0 V 50 17 - 65 - 75 - ns VCC = 4.5 V 10 6 - 13 - 15 - ns VCC = 6.0 V 9 5 - 11 - 13 - ns VCC = 2.0 V 5 17 - 5 - 5 - ns VCC = 4.5 V 5 6 - 5 - 5 - ns VCC = 6.0 V 5 5 - 5 - 5 - ns VCC = 2.0 V 6.0 23 - 4.8 - 4.0 - MHz VCC = 4.5 V 30 70 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 77 - - - - - MHz 25 83 - 28 - 24 - MHz - 35 - - - - - pF VCC = 4.5 V - 25 46 - 58 - 69 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 4.5 V - 25 50 - 63 - 75 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns - 22 46 - 58 - 69 ns - 20 46 - 58 - 69 ns CP1 to CP0; CP0 to CP1; see Figure 8 CP1 to CP0; CP0 to CP1; see Figure 8 MR to CP0 and MR to CP1; see Figure 9 CP0 or CP1; see Figure 9 VCC = 6.0 V CPD power dissipation capacitance 40 C to +85 C 40 C to +125 C Unit VI = GND to VCC; VCC = 5 V; fi = 1 MHz [3] CP0 to Qn; CP0 to Q5-9; see Figure 10 [1] 74HCT4017-Q100 tpd propagation delay CP1 to Qn; CP1 to Q5-9; see Figure 10 tPHL HIGH to LOW propagation delay MR to Q[1:9]; see Figure 10 tPLH LOW to HIGH propagation delay MR to Q5-9, Q0; see Figure 10 74HC_HCT4017_Q100 Product data sheet VCC = 4.5 V VCC = 4.5 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 7 15 - 19 - 22 ns 16 7 - 20 - 24 - ns 16 4 - 20 - 24 - ns 10 3 - 13 - 15 - ns 10 6 - 13 - 15 - ns 5 5 - 5 - 5 - ns VCC = 4.5 V 30 61 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 67 - - - - - MHz - 36 - - - - - pF [2] tt transition time see Figure 10 tW pulse width CP0 and CP1 (HIGH or LOW); see Figure 9 VCC = 4.5 V VCC = 4.5 V MR (HIGH); see Figure 9 VCC = 4.5 V tsu set-up time CP1 to CP0; CP0 to CP1; see Figure 8 th hold time CP1 to CP0; CP0 to CP1; see Figure 8 VCC = 4.5 V VCC = 4.5 V trec recovery time MR to CP0 and MR to CP1; see Figure 9 VCC = 4.5 V fmax CPD [1] maximum frequency power dissipation capacitance CP0 or CP1; see Figure 9 VI = GND to VCC 1.5 V; VCC = 5 V; fi = 1 MHz [3] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs 11. Waveforms VI CP0 input VM GND tsu th tsu th VI CP1 input VM GND 001aah245 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Waveforms showing the set-up and hold times for CP0 to CP1 and CP1 to CP0 1/f max tW VI CP0 input VM GND 1/f max VI CP1 input VM GND tW trec VI MR input VM GND tW VOH Q1 - Q9 output VM VOL tPHL VOH Q0, Q5 - Q9 output VOL VM tPLH 001aah246 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Waveforms showing minimum pulse widths, maximum CP input frequencies, recovery times and output propagation delays 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs VI CP0 input VM GND VI CP1 input VM GND tPHL tPLH VOH Q1 - Q9 output VM VOL tPLH tPHL VOH Q0, Q5 - Q9 output VOL VM tTLH tTHL 001aah247 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW transition. Fig 10. Waveforms showing propagation delays for CP to Qn outputs and output transition times Table 8. Measurement points Type Input Output VM VM 74HC4017-Q100 0.5 VCC 0.5 VCC 74HCT4017-Q100 1.3 V 1.3 V 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 11. Load circuitry for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC4017-Q100 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT4017-Q100 3 V 6 ns 15 pF, 50 pF 1 k open GND VCC 12. Application information Some examples of applications for the 74HC4017-Q100; 74HCT4017-Q100 are: • • • • Decade counter with decimal decoding 1 out of n decoding counter (when cascaded) Sequential controller Timer Figure 12 shows a technique for extending the number of decoded output states for the 74HC4017-Q100; 74HCT4017-Q100. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs &3 FORFN 05 &3 05 &3 05 +&4 +&74 +&4 +&74 +&4 +&74 &3 4 4 4 4 &3 4 4 4 4 &3 4 4 4 GHFRGHG RXWSXWV GHFRGHG RXWSXWV GHFRGHG RXWSXWV ILUVWVWDJH LQWHUPHGLDWHVWDJHV ODVWVWDJH DDD Fig 12. Counter expansion Remark: Do not enable the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW. It causes an extra count. Figure 13 shows an example of a divide-by 2 through divide-by 10 circuit using one 74HC4017-Q100; 74HCT4017-Q100. Since the 74HC4017-Q100; 74HCT4017-Q100 has an asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths can be enlarged by inserting an RC network at the MR input. +&4 +&74 GLYLGHE\ 4 9&& 9&& 4 05 4 &3 GLYLGHE\ 4 &3 GLYLGHE\ 4 4 GLYLGHE\ 4 4 GLYLGHE\ GLYLGHE\ 4 4 GLYLGHE\ *1' 4 GLYLGHE\ ILQ GLYLGHE\ IRXW DDD Fig 13. Divide-by 2 through divide-by 10 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 15. Package outline SOT403-1 (TSSOP16) 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 16. Package outline SOT763-1 (DHVQFN16) 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 18 of 22 74HC4017-Q100; 74HCT4017-Q100 NXP Semiconductors Johnson decade counter with 10 decoded outputs 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4017_Q100 v.1 20140324 Product data sheet - 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 - © NXP Semiconductors N.V. 2014. All rights reserved. 19 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT4017_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 20 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT4017_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 21 of 22 NXP Semiconductors 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 March 2014 Document identifier: 74HC_HCT4017_Q100