Application Information SSC2100 Series Power Factor Correction Continuous Conduction Mode Controller Introduction The SSC2100 series devices are controller ICs intended to implement a Discontinuous Conduction Mode (DCM) interleaved Power Factor Correction (PFC) circuit. Using the two-phase interleaved control incorporated in this IC, it is possible to achieve a low cost, high performance PFC system with low input / output ripple currents, low noise, and few external components. Features and benefits include the following: ▪ Interleaved Discontinuous Conduction Mode (DCM) operation: low peak current, low ripple current, and low noise; for medium- to high-power applications ▪ Constant Voltage Mode control: no auxiliary windings required on inductors because of the built-in arithmetic circuit; achieves a simple PFC system • Maximum on-time: 15 μs (typ) ▪ Built-in Soft Start function: reduces stress on power devices at startup ▪ Built-in High Speed Response (HSR): suppression of output voltage changes during dynamic load transients ▪ Error Amplifier reference voltage: 3.5 V (typ) ▪ Protection Functions ▫ Soft Overvoltage Protection (SOVP): output voltage reduction ▫ Output Overvoltage Protection (OVP): gate drive on/off on a pulse-by-pulse basis, with auto-restart ▫ Overcurrent Protection (OCP): dual-level OCP, with auto-restart ▫ Output Open Loop Detection (OLD): switching operation stop and transition to standby mode ▫ Open Terminal Protection (OTP): switching operation stop or output voltage reduction, during open condition on VFB, VIN, or IS terminals ▫ Thermal Shutdown (TSD): auto-restart with hysteresis SSC2100-AN Figure 1. The SSC2100 series devices are provided in a compact, standard package, a surface mount SOP8. Contents Introduction Electrical Characteristics Functional Description Parameters Design Design Notes SANKEN ELECTRIC CO., LTD. http://www.sanken-ele.co.jp/en/ 1 4 7 14 16 Functional Block Diagram – Peak Current Limitation COMP 1 VCC Gain Control – VFB 3 3.5 V + 8 IS + gm – + R Q S Q 7 OUT1 6 GND – 3.72 V OVP + – + R Q S Q 5 OUT2 – 0.7 V or 0.5 V + Phase Management VIN 2 VCC OVP UVLO VCC 4 TSD VREG5V Pin-out Diagram COMP 1 8 IS VIN 2 7 OUT1 VFB 3 6 GND VCC 4 5 OUT2 Terminal List Table Name 1 SSC2100-AN Number COMP Function Error Amplifier output and phase compensation terminal 2 VIN AC mains rectified voltage monitoring input terminal 3 VFB Feedback control terminal, input for: Constant Voltage Mode control signal, Overvoltage Protection signal, and Open Loop Detection signal 4 VCC IC power supply input terminal 5 OUT2 Gate drive 2 output terminal 6 GND IC ground terminal 7 OUT1 Gate drive 1 output terminal 8 IS Peak current detection signal input terminal SANKEN ELECTRIC CO., LTD. 2 Typical Application Diagram D1 85 to 264 VAC RC1 L1 D2 L2 D3 EMI Filter VOUT C1 R7 R1 7 4 OUT1 External power supply R3 VCC SSC2100 5 3 OUT2 VFB Q1 R8 Q2 2 VIN COMP C2 1 R4 IS 8 R2 R5 R6 GND 6 C4 GND C3 Package Outline Drawing 10º 0º 5.2 ±0.3 8 0.15 +0.1 –0.05 A B 4.4 ±0.2 Branding: 6.2 ±0.3 A. Type number (abbreviation): SC21xx C 0.4 ±0.2 B. Lot number 1st letter: Last digit of year 1 0.695 TYP 0.10 1.27 ±0.05 SSC2100-AN 2nd letter: Month 2 1 to 9 for January to September O for October N for November D for December 0.4 ±0.1 0.12 M 3rd letter: Week 1 for dates 1 through 10 2 for dates 11 through 20 3 for dates 21 through 31 1.5 ±0.1 0.05 ±0.05 Dimensions in mm SANKEN ELECTRIC CO., LTD. C. Sanken tracking number 3 Electrical Characteristics Absolute Maximum Ratings* TA = 25°C unless otherwise specified Characteristics VCC Terminal Voltage Symbol Notes Terminals Rating Unit A VCC 4–6 −0.3 to 30 VCOMP 1–6 −0.3 to 5.5 A VFB 3–6 −0.3 to 5.5 V VFB Terminal Current IFB 3–6 −1 to 1 mA VIN Terminal Voltage VIN 2–6 −0.3 to 5.5 V VIN Terminal Current IIN 2–6 −1 to 1 mA IS Terminal Voltage VIS 8–6 −16.0 to 5.5 V COMP Terminal Voltage VFB Terminal Voltage IIS 8–6 −1.75 to 1 mA OUT2 Terminal Voltage IS Terminal Current VOUT2 5–6 −0.3 to 30 V OUT1 Terminal Voltage VOUT1 7–6 −0.3 to 30 V Operating Frame Temperature TFOP – −40 to 85 °C Storage Temperature Tstg – −40 to 125 °C Junction Temperature Tj – −40 to 125 °C *Current polarity is defined relative to the IC: sink as positive, source as negative. ELECTRICAL CHARACTERISTICS Valid at TA = 25°C, unless otherwise specified Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit Power Supply Start-up Operation VCC Operation Start Voltage VCC(ON) 4–6 10.8 11.6 12.4 V VCC Operation Stop Voltage VCC(OFF) 4–6 9.8 10.6 11.4 V VCC Undervoltage Lockout Hysteresis VCC(HYS) 4–6 0.8 1.0 1.2 V VCC Circuit Current in Pre-operation ICC(OFF) 4–6 – 40 100 μA VCC Circuit Current in Operation ICC(ON) 4–6 – 11.0 15.0 mA VCC Circuit Current During OVP ICC(OVP) 4–6 – 8.0 10.0 mA ICC(Standby) 4–6 – 100 200 μA Maximum On-Time tONMAX 7–6 14 15 16 μs OUT1 to OUT2 On-Time Matching tRATIO 5–6 7–6 −5 0 5 % OUT1 to OUT2 Phase Difference ∆PHASE 5–6 7–6 170 180 190 deg. VCC Circuit Current During Standby Oscillator Operation Continued on the next page… SSC2100-AN SANKEN ELECTRIC CO., LTD. 4 ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, unless otherwise specified Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit Protection Operation VFB Output Open Loop Stop Voltage VFB(OLDL) 3–6 0.46 0.50 0.54 V VFB Output Open Loop Start Voltage VFB(OLDH) 3–6 0.64 0.70 0.76 V VFB Output Overvoltage Protection Voltage VFB(OVP) 3–6 3.64 3.72 3.80 V VFB Output Soft Overvoltage Protection Voltage VFB(SOVP) 3–6 3.60 3.68 3.76 V IS Lower Overcurrent Protection Voltage VIS(OCPL) 8–6 −0.48 −0.42 −0.36 V IS Upper Overcurrent Protection Voltage VIS(OCPH) 8–6 −0.62 −0.55 −0.48 V COMP Sink Current During Protection Mode ICOMP(SK) 1–6 80 100 120 μA Upper Thermal Shutdown Protection Threshold Temperature TJTSDH Not tested, guaranteed by design – 150 – – °C Lower Thermal Shutdown Protection Threshold Temperature TJTSDL Not tested, guaranteed by design – 140 – – °C TJTSDHYS Not tested, guaranteed by design – – 10 – °C VFB(REF) 3–6 3.4 3.5 3.6 V gmEA – 80 100 120 μS COMP Error Amplifier Maximum Source Current ICOMP(SO) 1–6 –36 –30 –24 μA COMP Error Amplifier Maximum Output Voltage VCOMP(MAX) 1–6 4.00 4.12 4.25 V VFB High Speed Response Enable Voltage VFB(HSR)enable Not tested, guaranteed by design 3–6 3.3 3.4 3.5 V VFB High Speed Response Active Voltage VFB(HSR)active 3–6 3.1 3.2 3.3 V COMP High Speed Response Source Current ICOMP(SOHSR) 1–6 –120 –100 –80 μA IFB(bias) 3–6 – – 1.5 μA VCOMP(OLD) 1–6 0.7 0.9 1.1 V Thermal Shutdown Protection Hysteresis Error Amplifier Operation VFB Error Amplifier Reference Voltage VFB Error Amplifier Transconductance Gain VFB Input Bias Current COMP Voltage During Output Open Loop Detection Continued on the next page… SSC2100-AN SANKEN ELECTRIC CO., LTD. 5 ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, unless otherwise specified Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit Drive Circuit OUTx Gate Voltage (Low) VOUT(L) 5–6 7–6 – – 0.3 V OUTx Gate Voltage (High) VOUT(H) 5–6 7–6 – 10.2 – V OUTx Rise Time tr 5–6 7–6 – 70 – ns OUTx Fall Time tf 5–6 7–6 – 35 – ns OUTx Peak Source Current IOUT(SO) Not tested, guaranteed by design 5–6 7–6 – –0.5 – A OUTx Peak Sink Current IOUT(SK) Not tested, guaranteed by design 5–6 7–6 – 0.5 – A Terminals Min. Typ. Max. Unit – – 65 85 ºC/W *Current polarity is defined relative to the IC: sink as positive, source as negative. Thermal Characteristics Valid at TA = 25°C Characteristics Symbol Package Thermal Resistance (Junction to Internal Leadframe) RθJF SSC2100-AN Test Conditions Internal leadframe temperature (TF) is measured at the root of pin 6, the GND terminal. SANKEN ELECTRIC CO., LTD. 6 Functional Description Interleaved Discontinuous Conduction Mode (DCM) The well-known single-phase Discontinuous Conduction Mode (DCM) technique achieves low switching noise because the drain current increase starts at zero when a power MOSFET turns on, and the rate of drain current increase is not steep, as shown by the waveforms in Figure 1. However, the usable power level of single-phase DCM is limited by the very high input / output ripple currents that are generated. The SSC2100 series provides two-phase interleaved DCM (see Figure 2). This advanced technique incorporates two boost converters working together to cancel input ripple currents and to reduce output ripple currents. This result is based on a phase difference of 180° between the two converters. Interleaved DCM also achieves a PFC system with lower switching noise and smaller input filter footprint in comparison to single-phase DCM. This is because reducing input / output ripple currents increases the filtering effectiveness of the EMI filter and also reduces switching noise. ID L1 VOUT MOSFET Drain Current IL IL Q1 ID 0 Inductor Current 0 Figure 1. External circuit and current waveforms for single-phase DCM L1 IL(Q1) ID(Q1) VOUT L2 ID MOSFET Drain Current ID(Q2) I D(Q1 0 Q1 IL(Q2) ) ) I D(Q2 Q2 IL IL CM P Inductor Current 0 ) I L(Q2 ) I L(Q1 ILCMP = Composite Inductor Current Figure 2. External circuit and current waveforms for two-phase interleaved DCM SSC2100-AN SANKEN ELECTRIC CO., LTD. 7 Startup Operation Soft Start Function VCC is the external power supply input to the SSC2100 IC. The external circuit for the VCC terminal is shown in Figure 3. Soft start is adjusted by the external circuits on the VFB and COMP terminals, as shown in Figure 5. At startup, when the input voltage increases to approximately 20% of the rated output voltage, VOUT , and the VCC terminal voltage increases to VCC(ON) = 11.6 V (typ), soft start operation begins. When AC mains and VCC external voltage are applied, after the VFB terminal voltage increases to VFB(OLDH) = 0.7 V (typ) or more and the VCC terminal voltage increases to VCC(ON) = 11.6 V (typ) or more, the control circuit starts switching operation. Note: One of the startup conditions is that the input voltage must reach 20% or more of the rated value for VOUT . This value of VOUT is equivalent to approximately VFB(OLDH) = 0.7 V (typ). As shown in Figure 6, during the soft start period, the COMP terminal is charged by ICOMP(SO) = −30 μA. In this way, the output power increases gradually, reducing stress on the power devices. 8176 When the VCC terminal voltage subsequently decreases to VCC(OFF) = 10.6 V (typ) or less, the control circuit stops switching operation. It does so by enabling the UVLO (undervoltage lockout) circuit, and then reverting to the standby mode that is the state of the IC before startup. When the VFB terminal voltage subsequently decreases to VFB(OLDL) = 0.5 V (typ) or less, the control circuit stops switching operation and reverts to pre-startup standby mode, even if VCC terminal voltage has increased to VCC(ON) or more. Because the regulation range of the VCC internal circuit is very wide, between VCC(OFF) = 11.4 V (max) and the VCC absolute maximum rating of 30 V (max), a wide input voltage range from the external power supply can be applied. The behaviors of ICC during startup and when switching is stopped are shown in Figure 4. % 4 55% %1/2 Ǵ# 4 % % % 4 +5 8+0 176 8($ )0& 8%% 176 Figure 5. External circuits of VFB and COMP terminals IDS(Q1,Q2) SSC2100 IS 8 1 COMP power supply 2 VIN OUT1 7 3 VFB GND 6 4 VCC C6 VFB VFB(REF) OUT2 5 Cf Time Soft start period Constant voltage operation 3.5 V ≈ 3.2 V VOUT=100% ≈ 90% of VOUT 0.7 V 0 Figure 3. External circuit of VCC terminal Time ICOMP ICC ICC(ON) 11 mA(typ ) 0 Stop Startup ICOMP(SO) Time VCC ICC(OFF) 40 μA(typ) VCC(ON) 11.6 V(typ) External power supply for VCC 10.6 V(typ) VCC(OFF) 11.6V(typ) VCC VCC(ON) Figure 4. Relationship of VCC and ICC at startup and stopping SSC2100-AN 㧙30ǴA 0 Time Figure 6. Soft Start operation SANKEN ELECTRIC CO., LTD. 8 using the voltage-mode control method. Thus, a PFC system used with this IC has no requirement for an auxiliary winding to detect zero crossings of the inductor current. This allows simple circuits with few external components. Voltage Control Operation A generic PFC circuit for implementing single-phase DCM is shown in Figure 7. The circuit is composed of a boost inductor (L1), a switching device (Q1), a rectifier diode (D2), and an output capacitor (C2). A control circuit would monitor the C2 voltage and generate an error amplifier output signal to operate Q1. When the control circuit detects an off-time at the L1 Zero Current Detection (ZCD) winding, it turns on Q1 for a period of time. When Q1 is later turned off, the energy stored in L1 is transferred through D2 to C2. After all of the energy stored in L1 is transferred to C2, the control circuit would again turn on Q1, repeating the process. In the boost PFC converter, tON is a function of load power and tOFF is a function of both the input voltage, EIN , and the rated output voltage, VOUT . The relationship between tON and tOFF is given by the following: EIN (1) tOFF > × tON VOUT – EIN The VIN terminal voltage is monitored internally and used to calculate the internal tOFF . The typical relationship between tON and the VIN terminal voltage, VIN , is shown in Figure 8. The maximum tON occurs at VIN = 0 V. The values shown assume VCOMP = 4 V , where VCOMP is the COMP terminal voltage. The SSC2100 series two-phase interleaved DCM uses the VIN terminal to monitor the AC mains rectified input voltage, the VFB terminal to monitor output voltage, and the COMP terminal to monitor phase compensation. This IC internally generates the on-time, tON , and off-time, tOFF , and it controls output voltage '+0 & . As shown in Figure 9, the rectified input voltage is divided by R1 and R2, and input to the VIN terminal. The output voltage is divided by R3 and R4, and input to the VFB terminal. Because of the way in which the VIN terminal voltage and the VFB terminal voltage are used for internal calculations, the two dividers should be well matched. Thus, the R1, R2, and C7 values of the input portion should be equal to the R3, R4, and C8 values of the output portion. 8176 <%& % % 3 R1 is recommended to be a high-value resistor, in the range from several hundred kΩ to several MΩ, ±1% tolerance, and of an anti-electromigration type, such as metal oxide film. C8, if necessary to reduce high frequency noise, is recommended to have a capacitance of in the range of 0.1 to 10 nF. Figure 7. PFC circuit with generic single-phase DCM 16 On-Time, t ON (μs) 15 14 13 12 11 10 9 8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VIN terminal voltage, VIN (V) Figure 8. Typical relationship between VIN and tON SSC2100-AN SANKEN ELECTRIC CO., LTD. 9 nal voltage increases to VFB(HSR)enable = 3.4 V (typ) or more, the control circuit enables the HSR operation. If the VFB terminal voltage subsequently decreases to VFB(HSR)active = 3.2 V (typ) or less, whether due to dynamic load change or other conditions, the control circuit activates the HSR operation. High Speed Response Function (HSR) The boost PFC converter is supplied by an AC sinusoidal waveform at the local commercial mains input voltage and frequency. However, the IC voltage control circuit, described above, characteristically responds at a relatively slow rate. As a result, the dynamic load response of the IC would be slow, and could cause the output voltage to drop too quickly. When HSR is in active operation, the COMP terminal charges by ICOMP(SOHSR) = −100 μA (typ) and the output power increases until the COMP terminal voltage increases to 3.2 V (typ). VFB(HSR)active = 3.2 V (typ) is equivalent to approximately 91.4% of the rated output voltage, VOUT . The innovative built-in High Speed Response (HSR) function reduces variation of the output voltage under dynamic load change conditions. As shown in Figure 10, when the VFB termi4% ' +0 8#% L1 & L2 & 81 76 4 % 4 4 % 3 4 3 4 55% +5 %1/2 4 % 4 % 8+0 176 8($ )0& 8%% 176 Figure 9. External circuits for VIN and VFB terminals OUT1,OUT2 Low HSR OFF HSR enable VFB COMP Sink 3.72 V 3.68 V HSR active 3.5 V 3.4 V ≈ 3.2 V 3.2 V SS : Soft start period CV : Constant voltage operation period LC : Dynamic load change period HSR: High speed response operation period OV : Overvoltage operation period HSR 0 ICOMP ICOMP(SK) 0 ICOMP(SO) Time SS CV LC CV OV CV 100ǴA 㧙30ǴA Time ICOMP(SOHSR) 㧙100ǴA Figure 10. VFB terminal voltage waveforms SSC2100-AN SANKEN ELECTRIC CO., LTD. 10 Gate Drive The OUT1 and OUT2 terminals each directly drive an external power MOSFET. Currents and voltages are set as follows: Peak Current Gate Voltage Source Sink Low High –0.5 A (typ) 0.5 A (typ) 0.3 V (max) 10.2 V (typ) Resistors R7, R8, R9, and R10 in Figure 11 should be selected for performance in the actual application, because these values relate to the individual board layout patterns and power MOSFET capacities. The gate resistors, R7 and R8, are recommended to be in the range of several ohms to several tens of ohms, and should be selected to reduce gate voltage ringing and EMI noise. R9 and R10 help to prevent malfunctions caused by steep dV/dt during power MOSFET turn-off. The recommended values are in the 10 to 100 kΩ range. These components should be placed close to the gate and source terminals of the corresponding power MOSFET. Error Amplifier Phase Compensation The phase compensation circuit is connected between the COMP and GND terminals, as shown in Figure 12. The COMP terminal is the output of the internal Error Amplifier. The Error Amplifier circuit, which implements the enhanced response functions, consists of a transconductance amplifier and switched current sources. The Error Amplifier response is set below 20 Hz to maintain power factor correction at standard commercial power frequencies of 50 or 60 Hz. The phase compensation components, C4, C5, and R11 (see Figure 12), have typical recommended values shown below, but should be selected for performance in the application: to reduce ripple, or to enhance transient load response at the rated output voltage. • C4: 0.047 to 0.47 μF • C5: 0.47 to 10 μF • R11: 10 to 100 kΩ Thermal Shutdown Protection (TSD) When the temperature of the IC increases to TJTSDH = 150°C (min) or more, the control circuit stops switching operation. Conversely, when temperature decreases to TJTSDL = 140°C or less, the control circuit restarts switching operation. The hysteresis of the detection temperature, TJTSDHYS, is 10°C (typ). 8176 55% %1/2 +5 8+0 176 8($ )0& 8%% 176 L1 & L2 & % 55% +5 %1/2 4 3 % 4 4 3 4 Figure 11. External circuits for OUTx terminals SSC2100-AN 4 8176 4 % % 4 % 8+0 176 8($ )0& 8%% 176 Figure 12. Phase compensation circuit (external COMP terminal circuit) SANKEN ELECTRIC CO., LTD. 11 Overcurrent Protection (OCP) The inductor current of both inductors is monitored by the detection resistor, R5, and is input to the IS terminal, as shown in Figure 13. The overcurrent protection function has two stages, IS Lower OCP, and IS Upper OCP, described below. IS Lower Overcurrent Protection, VIS(OCPL) When the inductor current is increasing and if the IS terminal voltage decreases to VIS(OCPL) = −0.42 V (typ), the control circuit limits the output power by turning off either one or both power MOSFETs, according to the output states of both OUT1 and OUT2, as follows: • If either one of OUT1 or OUT2 is high when the fault occurs, that output is now set low (so both outputs are off). Figure 14 is RC1 EIN L1 D2 L2 D3 • If both OUT1 and OUT2 are high when the fault occurs, the output that went high earlier than the other output (considering the current pulses only) is now set low (the other output remains high). Figure 15 is an example where both OUT1 and OUT2 are high (Q1 and Q2 are on), and the IS terminal detects VIS(OCPL) or lower. Under this condition, because OUT1 was set high before OUT2 was, OUT1 is now set low (and OUT2 remains high). R5 (see Figure 13) should be selected for performance in the actual application, such that IS terminal voltage reaches VIS(OCPL) or lower under the conditions of minimum input voltage and peak load. VOUT MOSFET(Q1) Drain current % Q1 Q1:OFF C2 Q2 MOSFET(Q2) Drain current R10 Inductor current IL an example. Where the IS terminal voltage falls to VIS(OCPL) or lower while OUT1 is high (Q1 is ON) and OUT2 is low, under this condition, OUT1 is set to low. R9 OUT1 terminal R5 R8 R7 R6 SSC2100 %1/2 +5 8+0 176 8($ )0& 8%% 176 OUT2 terminal IS terminal When both OUT1and OUT2 are set to high, OUT1 which is set to high ahead is set to low C3 VIS(OCPL) 㧙0.42V(TYP) Figure 15. VIS(OCPL) operation waveform after both OUT1 and OUT2 are set to high Figure 13. External circuits for IS and OUTx terminals MOSFET(Q1) Drain current Q1= OFF MOSFET(Q2) Drain current OUT1 terminal MOSFET(Q1) Drain current MOSFET(Q2) Drain current OUT1 is set to low after detecting VIS(OCPL) OUT1 terminal OUT2 terminal OUT2 terminal IS terminal IS terminal VIS(OCPL) 㧙0.42V(TYP) Figure 14. VIS(OCPL) operation waveform after OUT1 is set to high and OUT2 is set to low SSC2100-AN Abnormal state, such as inductor is shorted or is saturated Both OUT1 and OUT2 are set to low after detecting V IS(OCPH) VIS(OCPH) 㧙0.55V(TYP) Figure 16. Phase compensation circuit (external COMP terminal circuit) SANKEN ELECTRIC CO., LTD. 12 R6 is a damping resistor, which buffers IS terminal current against surge currents, such as inrush currents. It is recommended to have a value of 100 Ω. C3, if necessary to reduce high frequency noise, is recommended to have a capacitance of in the range of 0.1 to 10 nF. IS Upper Overcurrent Protection, VIS(OCPH) If the IS terminal voltage decreases to VIS(OCPH) = −0.55 V (typ) or lower, the control circuit limits the output power on a pulse-by-pulse basis by setting both OUT1 and OUT2 low, which turns off both power MOSFETs. This is shown in Figure 16. This protection function operates under abnormal conditions such as when an inductor is shorted or is saturated. Overvoltage Protection (OVP) The overvoltage protection function has two stages, Soft OVP, and OVP, illustrated in Figure 17 and described below. VFB Output Soft Overvoltage Protection, VFB(SOVP) When VFB terminal voltage increases to VFB(SOVP) = 3.68 V (typ), Soft Overvoltage Protection is activated. This discharges the COMP terminal by ICOMP(SK) = 100 μA (typ) and the output voltage is decreased. VFB(SOVP) = 3.68 V (typ) is equivalent to about 105% of the rated output voltage, VOUT . The output voltage threshold that initiates Soft Overvoltage Protection, is calculated approximately as follows: VOUT(norm) (2) VOUT(SOVP) ≈ × VFB(SOVP) VFB(REF) where VOUT(norm) is VOUT under normal operating conditions, and VFB(REF) is the Error Amplifier reference voltage, 3.5V (typ). VFB terminal voltage 3.72 V(typ) VFB Output Overvoltage Protection, VFB(OVP) When the VFB terminal voltage increases to VFB(OVP) = 3.72 V (typ), both OUT1 and OUT2 are set low on a pulse-by-pulse basis, which stops the output supply by turning off the power MOSFETS. When VFB terminal voltage decreases to VFB(SOVP) , the control circuit stops discharging from the COMP terminal and restores switching operation. The output voltage threshold that initiates Overvoltage Protection, is calculated approximately as follows: VOUT(norm) (3) VOUT(OVP) ≈ × VFB(OVP) VFB(REF) where VOUT(norm) is VOUT under normal operating conditions, and VFB(REF) is the Error Amplifier reference voltage, 3.5V (typ). R3 is recommended to be a high-value resistor, in the range from several hundred kΩ to several MΩ, ±1% tolerance, and of an anti-electromigration type, such as metal oxide film. C8 is recommended if necessary to reduce high frequency noise, and should have a rating of 0.1 to 10 nF. Open Loop Detection (OLD) In the event that the output voltage detection resistor, R3 (see Figure 18), opens and VFB terminal voltage decreases to VFB(OLDL) = 0.5 V (typ) or less, the control circuit stops the switching operation and enters standby mode. VFB(OLDL) = 0.5 V (typ) is equivalent to about 14.3% of the rated output voltage, VOUT . When the VFB terminal voltage subsequently increases to VFB(OLDH) = 0.7 V (typ) or more, the control circuit restores switching operation. VFB(OLDH) = 0.7 V (typ) is equivalent to about 20% of the rated output voltage, VOUT . OUT1,OUT2 is set to low ≈ 106% of V OUT 3.68 V(typ) 8176 VFB(OVP) ≈ 105% of V OUT VFB(SOVP) 3.50 V(typ) % VFB(REF) 4 VOUT =100% 0 CV OV 55% %1/2 +5 Time CV Ǵ# 4 COMP terminal current 100ǴA(typ ) ICOMP(SK) % % 4 % 8+0 176 8($ )0& 8%% 176 Time CV : Constant voltage operation period OV : Overvoltage operation period Figure 17. Overvoltage operation waveform and external circuit SSC2100-AN SANKEN ELECTRIC CO., LTD. 13 Open Terminal Protection (OTP) The specifications of this design example are: The VFB, IS, and VIN terminals each have dedicated internal Open Terminal Protection functions. • AC input voltage: 85 to 264 VAC • Total output power of two-phase interleaved PFC: 400 W (PO = 200 W for each phase) VFB Open Protection The VFB terminal is internally connected with a pull-up current source. In the event that the VFB terminal is open, VFB terminal voltage is pulled-up to the internal supply voltage, the IC overvoltage protection is activated, and both OUT1 and OUT2 are set low, decreasing the output voltage. Output Voltage, VOUT Selection The DC input voltage must always be lower than output voltage in a boost converter. Hence, the rated output voltage, VOUT , is set to be at least 10 V higher than the peak voltage of the commercial AC mains input voltage: IS Open Protection The IS terminal is internally connected with a pull-up current source. In the event that the IS terminal is open, the IS terminal voltage is pulled-up to the internal supply voltage, the IC overcurrent protection is activated, and both OUT1 and OUT2 are set low, decreasing the output voltage. VOUT ≥ √2 × VINRMS + 10 (V) (4) For example: VIN Open Protection The VIN terminal is internally connected with a pull-up current source. In the event that the VIN terminal is open, the VIN terminal voltage is pulled-up to the internal supply voltage, and the control circuit limits IC operation or stops it. VOUT ≥ √2 × 264 (VAC) + 10 (V) ≈ 383 (V) Hence, VOUT is set to 390 VDC. Inductor Current Parameters Design The waveform of the inductor current is triangular. The maximum peak current, ILPEAK (MAX), running through each inductor is calculated in two stages. Symbols in this section are defined as follows: • PO: PFC output power per phase (W) First, calculate the maximum input power, PIN(MAX). Defining the output power margin as KOM and the inductor saturation margin as KLM, PIN(MAX) can be calculated as follows: • η: PFC efficiency (%) • tON: On-time (sec.) • VINRMS: Input rms voltage (V) KOM × KLM × PO (5) (W) η where η is the efficiency, which depends on the on-resistance, PIN(MAX) = • VOUT: PFC output voltage (V) • IINRMS: Input rms current (A) 4% '+0 L1 & L2 & 8176 % 4 4 4 3 % 4 3 4 55% +5 %1/2 8+0 4 % 4 % 176 8($ )0& 8%% 176 Figure 18. External VFB terminal circuit SSC2100-AN SANKEN ELECTRIC CO., LTD. 14 RDS(on) , of the power MOSFET and the forward voltage, Vf , of the rectifier diode. η is generally in the range of 0.90 to 0.97. KOM and KLM depend on the design margins. Generally, as reference, KOM and KLM are in the range of 1.2 to 1.3. For example: 1.2 × 1.2 × 200 (W) PIN(MAX) = ≈ 313 (W) 0.92 Finally, calculate the single-phase maximum inductor peak current, ILPEAK(MAX) . Defining the minimum input rms voltage as VINRMS(MIN) , ILPEAK(MAX) is calculated as follows: ILPEAK(MAX) = For example: ILPEAK(MAX) = 2√2 × PIN(MAX) (6) VINRMS(MIN) Inductance Value The inductance for a single phase, L, is calculated as follows: (H) (7) where tON(MAX) can be determined from the VIN terminal voltage, using the chart in Figure 8. To calculate the VIN terminal voltage, VIN , recall that the values of R1 and R2 (see Figure 18) for VIN terminal voltage detection should be equal to the values of R3 and R4 for VOUT detection. Defining the rectified AC input voltage as EIN , the VIN terminal voltage, VIN , is calculated as follows: R V Given: 1 + 3 = V OUT , then R4 FB(REF) EIN VIN = VOUT ⁄ VFB(REF) where VFB(REF) is as defined for Equation 3. (8) For example, to calculate the inductance value, L, given an input of 85 VAC, first determine VIN by applying Equation 8: VIN √2 × 85 (VAC) ≈ 390 (V) ⁄ 3.5 (V) ≈ 1.08 (V) Substituting into Equation 7: N= √2 × 85 (VAC) × 12.4 (μs) 102 (mm2) × 250 (mT) (9) × 10 9 ≈ 58 (turns) Overcurrent Detection Resistance First, the maximum duty cycle, DON(MAX) , can be calculated as follows: DON(MAX) = VOUT – √2 × VINRMS(MIN) (%) VOUT (10) For example: DON(MAX) ≈ 390 (V) – √2 × 85 (VAC) ≈ 69% 390 (V) KR is calculated differently for DON(MAX) greater than or equal to 50%, than for DON(MAX) less than 50%, as follows: Given: DON(MAX) ≥ 50% , then KR = 1 + DON(MAX) – 0.5 DON(MAX) DON(MAX) < 50% , then 0.5 – DON(MAX) KR = 1 + 1 – DON(MAX) or, (11) For example, with a duty cycle of 69% : 0.69 – 0.5 ≈ 1.28 0.69 The composite inductor current, ILCMP(MAX) , is calculated as follows: ILCMP(MAX) = KR × I 'LCMP(MAX) √2 × 85 (VAC) × 12.4 (μs) ≈ 143 (μH) 10.4 (A) SSC2100-AN √2 × VINRMS(MIN) × tON(MAX) × 10 9 (turns) Ae × ∆BMAX For example: N= KR ≈ 1 + Then determine tON(MAX) from Figure 8. Given a VIN of 1.08 V, tON(MAX) is approximately 12.4 μs. L≈ Defining the turns number of the inductor as N, the effective area of inductor core as Ae (mm2), and the maximum magnetic flux density as ∆BMAX (mT), N is calculated as follows: The overcurrent detection resistor, R5 (Figure 18), sets the level for monitoring the composite inductor current of both boost converters, ILCMP . Because the composite inductor current (see Figure 2) varies according to the duty cycle, DON , a coefficient KR is calculated from DON , and used in the calculation of R5 by determining ILCMP(MAX) . 2√2 × 313 (W) ≈ 10.4 (A) 85 (VAC) √2 × VINRMS(MIN) × tON(MAX) L≥ ILPEAK(MAX) Inductor Turns (12) where I ′LPEAK(MAX) is calculated as follows: SANKEN ELECTRIC CO., LTD. 15 I 'PEAK(MAX) ≈ 2√2 × KOM × PO η × VINRMS(MIN) (A) (13) Design Notes External Components For example: Take care to use properly rated, including derated as necessary, and proper types of components. The part identifier codes in the following refer to Figure 19. I 'PEAK(MAX) ≈ 2√2 × 1.2 × 200 (W) ≈ 8.7 (A) 0.92 × 85 (VAC) Substituting into Equation 12: ILCMP(MAX) ≈ 1.28 × 8.7 (A) ≈ 11.1 (A) Finally, R5 is calculated from the peak current of the composite inductor current and the threshold voltage, as follows: R5 ≤ |VIS(OCPL)| (Ω) ILCMP(MAX) (14) For example: R5 ≈ |–0.42 (V, typ)| ≈ 0.038 (Ω) 11.1 (A) RC1 VAC • Electrolytic capacitor C2. Apply proper derating for ripple current, voltage, and temperature rise. Use of high ripple current and low impedance types, designed for switch mode power supplies (SMPS), is recommended. • Inductors L1 and L2. Apply proper derating against temperature rise due to core and copper losses. • Current detection resistor R5. A high frequency switching current flows through R5, and may cause poor operation if a high inductance resistor is used. Choose a low inductance and surgeproof type. • Higher-rated resistors for high applied voltage. Choose a resistor type, such as metal oxide film, that is not susceptible to EIN L1 D2 L2 D3 VOUT Q1 Q2 C1 C2 R10 R1 R9 R3 R5 R6 R8 SSC2100 1 COMP IS 8 2 VIN R11 External power supply C6 R2 R4 C5 C4 C7 R7 Main circuit Signal ground OUT1 7 3 VFB GND 8 4 VCC OUT2 5 C8 Cf C3 Figure 19. External circuits for SSC2100 connection SSC2100-AN SANKEN ELECTRIC CO., LTD. 16 degradation by electromigration, or by electrolytic corrosion or oxidation of the resistive material. frequency and high voltage, and the PCB trace design and component layouts should comply with all safety guidelines. • Bypass diode D1. Choose a surge-current–proof type diode for D1, which is a bypass diode to protect D2 and D3 against excessive currents, such as inrush current. Furthermore, in the case where MOSFETs are being used as the switching devices, take into account the positive thermal coefficient of RDS(on) when preparing a thermal design. • Rectifiers D2 and D3. Choose an ultra–high-speed type diode with short trr (reverse recovery time) to reduce noise and power loss. Figure 19 shows an example of external circuit connections. The following should be taken into consideration when designing the circuit layouts: • Bypass diodes and rectifier diodes for power factor correction (PFC). Sanken Electric has many product line-ups for bypass diodes and rectifiers for PFC applications. Please contact the Sanken Electric Sales Department to inquire about them. • Avoid placing traces parallel and adjacent to control system or main circuit traces, to avoid interference due to crosstalk noise. • Connect the GND terminal directly to R5 with a short, dedicated trace. The goal is to reduce common mode impedance by separating the IC control system ground from the main circuit ground. Also, connect R6 directly to R5 with a dedicated trace. Circuit Layout Design PCB circuit trace design and component layout affect proper functioning during operation, EMI noise, and power dissipation. Therefore, where high frequency current traces form a loop, as in Figure 20, wide, short traces and small circuit loops are important to reduce line impedance. In addition, local ground and earth ground traces affect radiated EMI noise, and the same measures should be taken into account. • Connect external components to the IC with the shortest traces practicable. Switch mode power supplies consist of current traces with high • Place R10 between the gate and source terminals of Q2. • If the distance between C6 and the IC is lengthy, place Cf (a film capacitor in the 0.1 to 1 μF /50 V range) between the VCC and GND terminals. • Place R9 between the gate and source terminals of Q1. D1 RC1 L1 D2 L2 D3 VAC C1 Q1 VOUT C2 Q2 GND R5 Figure 20. High frequency current loop SSC2100-AN SANKEN ELECTRIC CO., LTD. 17 All performance characteristics given are typical values for circuit or system baseline design only and are at the nominal operating voltage and an ambient temperature of 25°C, unless otherwise stated. • The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the latest revision of the document before use. • Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights or any other rights of Sanken or any third party which may result from its use. • Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device failure or malfunction. • Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales representative to discuss, prior to the use of the products herein. The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required (aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited. • In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses, instantaneous values, maximum values and minimum values must be taken into consideration. In addition, it should be noted that since power devices or IC's including power devices have large self-heating value, the degree of derating of junction temperature affects the reliability significantly. • When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance and proceed therewith at your own responsibility. • Anti radioactive ray design is not considered for the products listed herein. • Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken's distribution network. • The contents in this document must not be transcribed or copied without Sanken's written consent. SSC2100-AN SANKEN ELECTRIC CO., LTD. 18