HI-539 Data Sheet July 1999 Precision, 4-Channel, Low-Level, Differential Multiplexer Performance is guaranteed for each channel over the voltage range ±10V, but is optimized for low level differential signals. Leakage current, for example, which varies slightly with input voltage, has its distribution centered at zero input volts. • Differential Performance, Typical: - Low ∆rON , 125oC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5Ω - Low ∆ID(ON) , 125oC . . . . . . . . . . . . . . . . . . . . . . . 0.6nA - Low ∆ Charge Injection . . . . . . . . . . . . . . . . . . . . 0.1pC - Low Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . -124dB • Settling Time, ±0.01% . . . . . . . . . . . . . . . . . . . . . . . 900ns • Wide Supply Range . . . . . . . . . . . . . . . . . . . ±5V to ±18V • Break-Before-Make Switching In most monolithic multiplexers, the net differential offset due to thermal effects becomes significant for low level signals. This problem is minimized in the HI-539 by symmetrical placement of critical circuitry with respect to the few heat producing devices. • No Latch-Up Supply voltages are ±15V and power consumption is only 2.5mW. • Precision Instrumentation Applications • Low Level Data Acquisition • Test Systems Ordering Information PART NUMBER 3149.2 Features The Intersil HI-539 is a monolithic, 4-Channel, differential multiplexer. Two digital inputs are provided for channel selection, plus an Enable input to disconnect all channels. TEMP. RANGE (oC) File Number TRUTH TABLE PACKAGE PKG. NO. HI1-0539-5 0 to 75 16 Ld CERDIP F16.3 HI1-0539-8 -55 to 125 16 Ld CERDIP F16.3 HI3-0539-5 0 to 75 16 Ld PDIP E16.3 HI4P0539-5 0 to 75 20 Ld PLCC N20.35 ON CHANNEL TO EN A1 A0 OUT A OUT B L X X None None H L L 1A 1B H L H 2A 2B H H L 3A 3B H H H 4A 4B Pinouts A1 15 GND GND 16 A1 NC A0 1 EN 2 A0 HI-539 (PLCC) TOP VIEW EN HI-539 (CERDIP, PDIP) TOP VIEW 3 2 1 20 19 14 V+ V- 3 V- 4 18 V+ 13 IN 1B IN 4A 7 10 IN 4B 9 OUT B OUT A 8 1 NC 6 16 NC IN 2A 7 15 IN 2B IN 3A 8 14 IN 3B 9 10 11 12 13 IN 4B 11 IN 3B NC IN 3A 6 17 IN 1B OUT B 12 IN 2B OUT A IN 2A 5 IN 1A 5 IN 4A IN 1A 4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HI-539 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V V+ or V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . . . V- to V+ Analog Current (IN or OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 85 32 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A PLCC Package. . . . . . . . . . . . . . . . . . . 80 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (PLCC - Lead Tips Only) Operating Conditions Temperature Range HI-539-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-539-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Supplies = ±15V, VEN = 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified Electrical Specifications TEST CONDITIONS -8 -5 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 250 750 - 250 750 ns Full - - 1,000 - - 1,000 ns 25 30 85 - 30 85 - ns Full 30 - - 30 - - ns 25 - 250 750 - 250 750 ns Full - - 1,000 - - 1,000 ns 25 - 160 650 - 160 650 ns Full - - 900 - - 900 ns 25 - 0.9 - - 0.9 - µs Charge Injection (Output) Full - 3 - - 3 - pC ∆ Charge Injection (Output) Full - 0.1 - - 0.1 - pC PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN) Enable Delay (OFF), tOFF(EN) Settling Time To 0.01% Charge Injection (Input) Full - 10 - - 10 - pC Differential Crosstalk Note 4 25 - -124 - - -124 - dB Single Ended Crosstalk Note 4 25 - -100 - - -100 - dB Channel Input Capacitance, CS(OFF) Full - 5 - - 5 - pF Channel Output Capacitance, CD(OFF) Full - 7 - - 7 - pF Channel On Output Capacitance, CD(ON) Full - 17 - - 17 - pF Full - 0.08 - - 0.08 - pF Full - 3 - - 3 - pF Input Low Threshold, VAL Full - - 0.8 - - 0.8 V Input High Threshold, VAH Full 4.0 - - 4.0 - - V Input Leakage Current (High), IAH Full - - 1 - - 1 µA Input Leakage Current (Low), IAL Full - - 1 - - 1 µA Input to Output Capacitance, CDS(OFF) Note 5 Digital Input Capacitance, CA DIGITAL INPUT CHARACTERISTICS 2 HI-539 Supplies = ±15V, VEN = 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified (Continued) Electrical Specifications TEST CONDITIONS PARAMETER -8 -5 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Full -10 - +10 -10 - +10 V ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON VIN = 0V VlN = ±10V ∆rON, (Side A-Side B) VIN = 0V VlN = ±10V Off Input Leakage Current, IS(OFF) Condition 0V (Note 2) Condition ±10V (Note 2) ∆IS(OFF), (Side A-Side B) Condition 0V Condition ±10V Off Output Leakage Current, ID(OFF) Condition 0V (Note 2) Condition ±10V (Note 2) ∆ID(OFF), (Side A-Side B) Condition 0V Condition ±10V On Channel Leakage Current, ID(ON) Condition 0V (Note 2) Condition ±10V (Note 2) ∆ID(ON), (Side A-Side B) Condition 0V Condition ±10V Differential Offset Voltage, ∆VOS Note 3 25 - 650 850 - 650 850 Ω Full - 950 1.3K - 800 1K Ω 25 - 700 900 - 700 900 Ω Full - 1.1K 1.4K - 900 1.1K Ω 25 - 4.0 24 - 4.0 24 Ω Full - 4.75 28 - 4.0 24 Ω 25 - 4.5 27 - 4.5 27 Ω Full - 5.5 33 - 4.5 27 Ω 25 - 30 - - 30 - pA Full - 2 10 - 0.2 1 nA 25 - 100 - - 100 - pA Full - 5 25 - 0.5 2.5 nA 25 - 3 - - 3 - pA Full - 0.2 2 - 0.02 0.2 nA 25 - 10 - - 10 - pA Full - 0.5 5 - 0.05 0.5 nA 25 - 30 - - 30 - pA Full - 2 10 - 0.2 1 nA 25 - 100 - - 100 - pA Full - 5 25 - 0.5 2.5 nA 25 - 3 - - 3 - pA Full - 0.2 2 - 0.02 0.2 nA 25 - 10 - - 10 - pA Full - 0.5 5 - 0.05 0.5 nA 25 - 50 - - 50 - pA Full - 5 25 - 0.5 2.5 nA 25 - 150 - - 150 - pA Full - 6 40 - 0.8 4.0 nA 25 - 10 - - 10 - pA Full - 0.5 5 - 0.05 0.5 nA 25 - 30 - - 30 - pA Full - 0.6 6 - 0.08 0.8 nA 25 - 0.02 - - 0.02 - µV Full - 0.70 - - 0.08 - µV 25 - 2.3 - - 2.3 - mW Full - - 45 - - 45 mW 25 - 0.150 - - 0.150 - mA Full - - 2.0 - - 2.0 mA POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Current, l+ 3 HI-539 Supplies = ±15V, VEN = 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified (Continued) Electrical Specifications TEST CONDITIONS PARAMETER Current, l- Supply Voltage Range -8 -5 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 0.001 - - 0.001 - mA Full - - 1.0 - - 1.0 mA Full ±5 ±15 ±18 ±5 ±15 ±18 V NOTES: 2. See Figures 2B, 2C, 2D. The condition ±10V means: lS(OFF) and ID(OFF): (VS = +10V, VD = -10V), then (VS = -10V, VD = +10V) ID(ON): (+10V, then -10V) 3. ∆VOS (Exclusive of thermocouple effects) = rON ∆ID(ON) + ID(ON) ∆rON . See Applications section for discussion of additional VOS error. 4. VlN = 1kHz, 15VP-P on all but the selected channel. See Figure 7. 5. Calculated from typical Single-Ended Crosstalk performance. Test Circuits and Waveforms Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V 100µA ON RESISTANCE (Ω) V2 IN OUT HI-539 VIN VIN = 0V 800 V2 rON = 700 600 100µA 500 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 1A. TEST CIRCUIT FIGURE 1B. ON RESISTANCE vs TEMPERATURE 900 125oC 700 ON RESISTANCE (kΩ) ON RESISTANCE (Ω) 800 25oC 600 -55oC 500 400 -12 -10 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 12 FIGURE 1C. ON RESISTANCE vs ANALOG INPUT VOLTAGE 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 VIN = 0V 5 9 11 13 SUPPLY VOLTAGE (±V) 15 FIGURE 1D. ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 4 7 17 HI-539 Test Circuits and Waveforms Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) 10 LEAKAGE CURRENT (nA) HI-539† 0.8V EN ID(ON) OUT A 1 A ±10V ± ID(OFF) = IS(OFF) A0 25 50 75 TEMPERATURE (oC) 100 125 A1 FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 6) HI-539† HI-539† OUT A OUT A IS(OFF) A 0.8V A0 EN ± ±10V 10V † Similar Connection For Side “B” FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE A ID(OFF) ID(ON) EN A1 ±10V 10V 10V ± A0 A1 4V † Similar Connection For Side “B” †Similar Connection For Side “B” FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 6) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 6) NOTE: 6. Three measurements = ±10V, 10V, and 0V. ± FIGURE 2. LEAKAGE CURRENT 14 A +15V/+10V +ISUPPLY I+ SUPPLY CURRENT (mA) FUNCTIONAL LIMIT 12 A1 10 VSUPPLY = ±15V 8 V+ IN 1A A0 VSUPPLY = ±10V VA IN 2A 50Ω IN 3A 6 IN 4A 5V 4 EN GND 2 0 100Hz VA 1kHz 10kHz 100kHz HIGH = 4.0V LOW = 0V 50% DUTY CYCLE 1MHz 3MHz 10MHz TOGGLE FREQUENCY FIGURE 3. DYNAMIC SUPPLY CURRENT -10V/-5V OUT A V10MΩ A -ISUPPLY -15V/-10V †Similar Connection For Side “B” FIGURE 3A. SUPPLY CURRENT vs TOGGLE FREQUENCY 5 +10V/+5V HI-539 † FIGURE 3B. TEST CIRCUIT 14pF HI-539 Test Circuits and Waveforms Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) +15V 320 V+ IN 1A 300 280 IN 2A, IN 3A A0 VA 260 50Ω ±10V HI-539 IN 4A 240 EN 5V GND ± ACCESS TIME (ns) A1 10V OUT A V- 10 kΩ 220 200 50 pF -15V 3 4 5 6 7 8 9 10 11 12 13 14 15 LOGIC LEVEL (HIGH) (V) FIGURE 4A. ACCESS TIME vs LOGIC LEVEL (HIGH) VAH = 4V FIGURE 4B. TEST CIRCUIT ADDRESS DRIVE (VA) VA INPUT 2V/DIV. 50% 0V S1 ON +10V OUTPUT OUTPUT 5V/DIV. 10% -10V tA S4 ON 200ns/DIV. FIGURE 4C. MEASUREMENT POINTS FIGURE 4D. WAVEFORMS FIGURE 4. ACCESS TIME +15V VAH = 4V V+ HI-539 † ADDRESS DRIVE (VA) 0V IN 2, IN 3A A1 IN 4A A0 OUTPUT 50% +5V IN 1A VOUT EN 50% VA 50Ω 5V GND OUT A V- 700 Ω tOPEN -15V † Similar connection for side “B” FIGURE 5A. MEASUREMENT POINTS 6 FIGURE 5B. TEST CIRCUIT 12.5pF HI-539 Test Circuits and Waveforms Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) VA INPUT 2V/DIV. S1 ON S4 ON OUTPUT 1V/DIV. 100ns/DIV. FIGURE 5C. WAVEFORMS FIGURE 5. BREAK-BEFORE-MAKE DELAY +15V V+ HI-539 † VAH = 4V IN 1A 50% ENABLE DRIVE (VA) 50% A1 0V 90% +10V IN 2A THRU IN 4A A0 VOUT EN OUTPUT 10% VA 50 Ω GND OUT A V- 700 Ω 0V tON(EN) -15V tOFF(EN) † Similar connection for side “B” FIGURE 6A. MEASUREMENT POINTS FIGURE 6B. TEST CIRCUIT ENABLE DRIVE 2V/DIV. ENABLED DISABLED (S1 ON) OUTPUT 2V/DIV. 100ns/DIV. FIGURE 6C. WAVEFORMS FIGURE 6. ENABLE DELAYS 7 12.5pF HI-539 Test Circuits and Waveforms Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) HI-539 HI-539 INSTRUMENTATION AMPLIFIER† INSTRUMENTATION AMPLIFIER † G = 1000 + G = 1000 + - 350Ω - 350Ω 1kHz, 15VP-P 350Ω 1kHz, 15VP-P † AD606 or BB3630, for Example † AD606 or BB3630, for example FIGURE 7A. SINGLE-ENDED CROSSTALK TEST CIRCUIT FIGURE 7B. DIFFERENTIAL CROSSTALK TEST CIRCUIT FIGURE 7. CROSSTALK Application Information General The Hl-539 accepts inputs in the range -15V to +15V, with performance guaranteed over the ±10V range. At these higher levels of analog input voltage it is comparable to the Hl509, and is plug-in compatible with that device (as well as the Hl-509A). However, as mentioned earlier, the Hl-539 was designed to introduce minimum error when switching low level inputs. Special care is required in working with these low level signals. The main concern with signals below 100mV is that noise, offset voltage, and other aberrations can represent a large percentage error. A shielded differential signal path is essential to maintain a noise level below 50µVRMS . Low Level Signal Transmission The transmission cable carrying the transducer signal is critical in a low level system. It should be as short as practical and rigidly supported. Signal conductors should be tightly twisted for minimum enclosed area to guard against pickup of electromagnetic interference, and the twisted pair should be shielded against capacitively coupled (electrostatic) interference. A braided wire shield may be satisfactory, but a lapped foil shield is better since it allows only 1/10 as much leakage capacitance to ground per foot. A key requirement for the transmission cable is that it presents a balanced line to sources of noise interference. This means an equal series impedance in each conductor plus an equally distributed impedance from each conductor to ground. The result should be signals equal in magnitude but opposite in phase at any transverse plane. Noise will be coupled in phase to both conductors, and may be rejected as common-mode voltage by a differential amplifier connected to the multiplexer output. 8 Coaxial cable is not suitable for low level signals because the two conductors (center and shield) are unbalanced. Also, ground loops are produced if the shield is grounded at both ends by standard BNC connectors. If coax must be used, carry the signal on the center conductors of two equal-length cables whose shields are terminated only at the transducer end. As a general rule, terminate (ground) the shield at one end only, preferably at the end with greatest noise interference. This is usually the transducer end for both high and low level signals. Watch Small ∆V Errors Printed circuit traces and short lengths of wire can add substantial error to a signal even after it has traveled hundreds of feet and arrived on a circuit board. Here, the small voltage drops due to current flow through connections of a few milliohms must be considered, especially to meet an accuracy requirement of 12 bits or more. Table 1 is a useful collection of data for calculating the effect of these short connections. (Proximity to a ground plane will lower the values of inductance.) As an example, suppose the Hl-539 is feeding a 12-bit converter system with an allowable error of ±1/2 LSB (±1.22mV). lf the interface logic draws 100mA from the 5V supply, this current will produce 1.28mV across 6 inches of #24 wire; more than the error budget. Obviously, this digital current must not be routed through any portion of the analog ground return network. HI-539 TABLE 1. WIRE GAGE EQUIVALENT WIDTH OF P.C. CONDUCTOR (2 oz. Cu) DC RESISTANCE PER FOOT INDUCTANCE PER FOOT IMPEDANCE PER FOOT 60Hz 10kHz 18 0.47” 0.0064Ω 0.36µH 0.0064Ω 0.0235Ω 20 0.30” 0.0102Ω 0.37µH 0.0102Ω 0.0254Ω 22 0.19” 0.0161Ω 0.37µH 0.0161Ω 0.0288Ω 24 0.12” 0.0257Ω 0.40µH 0.0257Ω 0.0345Ω 26 0.075” 0.041Ω 0.42µH 0.041Ω 0.0488Ω 28 0.047” 0.066Ω 0.45µH 0.066Ω 0.0718Ω 30 0.029” 0.105Ω 0.49µH 0.105Ω 0.110Ω 32 0.018” 0.168Ω 0.53µH 0.168Ω 0.171Ω Provide Path For IBIAS Differential Offset, ∆VOS The input bias current for any DC-coupled amplifier must have an external path back to the amplifier’s power supply. No such path exists in Figure 8A, and consequently the amplifier output will remain in saturation. There are two major sources of ∆VOS . That part due to the expression (rON ∆lD(ON) + lD(ON) ∆rON) becomes significant with increasing temperature, as shown in the Electrical Specifications tables. The other source of offset is the thermocouple effects due to dissimilar materials in the signal path. These include silicon, aluminum, tin, nickel-iron and (often) gold, just to exit the package. A single large resistor (1MΩ to 10MΩ) from either signal line to power supply common will provide the required path, but a resistor on each line is necessary to preserve accuracy. A single pair of these bias current resistors on the HI-539 output may be used if their loading effect can be tolerated (each forms a voltage divider with rON). Otherwise, a resistor pair on each input channel of the multiplexer is required. The use of bias current resistors is acceptable only if one is confident that the sum of signal plus common-mode voltage will remain within the input range of the multiplexer/amplifier combination. Another solution is to simply run a third wire from the low side of the signal source, as in Figure 8B. This wire assures a low common-mode voltage as well as providing the path for bias currents. Making the connection near the multiplexer will save wire, but it will also unbalance the line and reduce the amplifier's common-mode rejection. 9 For the thermocouple effects in the package alone, the constraint on ∆VOS may be stated in terms of a limit on the difference in temperature for package pins leading to any channel of the Hl-539. For example, a difference of 0.13oC produces a 5µV offset. Obviously, this ∆T effect can dominate the ∆VOS parameter at any temperature unless care is taken in mounting the Hl-539 package. Temperature gradients across the Hl-539 package should be held to a minimum in critical applications. Locate the Hl-539 far from heat producing components, with any air currents flowing lengthwise across the package. HI-539 HI-539 “FLOATING” SOURCE V+ rON + rON V- FIGURE 8A. HI-539 V+ rON + rON V- 1M TO 10M POWER SUPPLY COMMON POWER SUPPLY COMMON NOTE: The amplifier in Figure 8A is unusable because its bias currents cannot return to the power supply. Figure 8B shows two alternative paths for these bias currents: either a pair of resistors, or (better) a third wire from the low side of the signal source. FIGURE 8B. 10 HI-539 Die Characteristics DIE DIMENSIONS: PASSIVATION: 92 mils x 100 mils Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2.0kÅ METALLIZATION: Type: AlCu Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 2.54 x 105 A/cm2 at 20mA SUBSTRATE POTENTIAL (NOTE): TRANSISTOR COUNT: -VSUPPLY 236 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-539 V- EN A0 A1 GND V+ IN1A IN1B IN2A IN2B IN3A IN4A OUTA OUTB IN4B IN3B All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 11