HA-2420, HA-2425 ® Data Sheet November 19, 2004 FN2856.6 3.2µs Sample and Hold Amplifiers Features The HA-2420 and HA-2425 is a monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultra-low leakage analog switch and JFET input unity gain amplifier. • Maximum Acquisition Time - 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . 4µs (Max) - 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . 6µs (Max) With an external hold capacitor connected to the switch output, a versatile, high performance sample-and-hold or track-and-hold circuit is formed. When the switch is closed, the device behaves as an operational amplifier, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened the output will remain at its last level. Performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. Accuracy to better than 0.01% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than 1 frequently eliminates the need for external scaling amplifiers. The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc. For more information, please see Application Note AN517.. Ordering Information PART NUMBER TEMP. RANGE (oC) HA1-2420-2 -55 to 125 HA3-2425-5 0 to 75 1 PACKAGE PKG. DWG. # 14 Ld CERDIP F14.3 14 Ld PDIP E14.3 • Low Droop Rate (CH = 1000pF). . . . . . . . . . 5µV/ms (Typ) • Gain Bandwidth Product . . . . . . . . . . . . . . . 2.5MHz (Typ) • Low Effective Aperture Delay Time . . . . . . . . . 30ns (Typ) • TTL Compatible Control Input • ±12V to ±15V Operation Applications • 12-Bit Data Acquisition • Digital to Analog Deglitcher • Auto Zero Systems • Peak Detector • Gated Operational Amplifier Pinout HA-2420 (CERDIP) HA-2425 (PDIP) TOP VIEW -IN 1 14 S/H CONTROL +IN 2 13 GND OFFSET ADJ. 3 12 NC OFFSET ADJ. 4 11 HOLD CAP. V- 5 10 NC NC 6 9 V+ OUTPUT 7 8 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-2420, HA-2425 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V Digital Input Voltage (Sample and Hold Pin) . . . . . . . . . . +8V, -15V Output Current . . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 95 N/A Maximum Junction Temperature (Ceramic Packages). . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Range HA-2420-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-2425-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . ±12V to ±15V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Test Conditions (Unless Otherwise Specified) VSUPPLY = ±15.0V; CH = 1000pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) Electrical Specifications TEST CONDITIONS HA-2420-2 HA-2425-5 TEMP. (oC) MIN TYP MAX MIN TYP MAX UNITS Input Voltage Range Full ±10 - - ±10 - - V Offset Voltage 25 - 2 4 - 3 6 mV Full - 3 6 - 4 8 mV 25 - 40 200 - 40 200 nA Full - - 400 - - 400 nA 25 - 10 50 - 10 50 nA Full - - 100 - - 100 nA Input Resistance 25 5 10 - 5 10 - MΩ Common Mode Range Full ±10 - - ±10 - - V PARAMETER INPUT CHARACTERISTICS Bias Current Offset Current TRANSFER CHARACTERISTICS Large Signal Voltage Gain RL = 2kΩ, VO = 20VP-P Full 25 50 - 25 50 - kV/V Common Mode Rejection VCM = ±10V Full 80 90 - 74 90 - dB Hold Mode Feedthrough Attenuation (Note 2) fIN ≤ 100kHz Full - -76 - - -76 - dB 25 - 2.5 - - 2.5 - MHz Full ±10 - - ±10 - - V 25 ±15 - - ±15 - - mA Gain Bandwidth Product (Note 2) OUTPUT CHARACTERISTICS Output Voltage Swing RL = 2kΩ Output Current Full Power Bandwidth (Note 2) VO = 20VP-P 25 - 100 - - 100 - kHz Output Resistance DC 25 - 0.15 - - 0.15 - Ω Rise Time (Note 2) VO = 200mVP-P 25 - 75 100 - 75 100 ns Overshoot (Note 2) VO = 200mVP-P 25 - 25 40 - 25 40 % Slew Rate (Note 2) VO = 10VP-P 25 3.5 5 - 3.5 5 - V/µs TRANSIENT RESPONSE 2 FN2856.6 November 19, 2004 HA-2420, HA-2425 Test Conditions (Unless Otherwise Specified) VSUPPLY = ±15.0V; CH = 1000pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) (Continued) Electrical Specifications TEST CONDITIONS HA-2420-2 HA-2425-5 TEMP. (oC) MIN TYP MAX MIN TYP MAX UNITS VIN = 0V Full - - -0.8 - - -0.8 mA VIN = 5V Full - - 20 - - 20 µA Low Full - - 0.8 - - 0.8 V High Full 2.0 - - 2.0 - - V PARAMETER DIGITAL INPUT CHARACTERISTICS Digital Input Current Digital Input Voltage SAMPLE AND HOLD CHARACTERISTICS Acquisition Time (Note 2) To 0.1% 10V Step 25 - 2.3 4 - 2.3 4 µs Acquisition Time (Note 2) To 0.01% 10V Step 25 - 3.2 6 - 3.2 6 µs Hold Step Error VIN = 0V 25 - 10 20 - 10 20 mV Hold Mode Settling Time To ±1mV 25 - 860 - - 860 - ns Aperture Time (Note 3) 25 - 30 - - 30 - ns Effective Aperture Delay Time 25 - 30 - - 30 - ns Aperture Uncertainty 25 - 5 - - 5 - ns 25 - 5 - - 5 - pA HA1-2420 Full - 1.8 10 - - - nA HA1-2425 Full - - - - 0.1 1.0 nA HA3-2425, HA4P2425, HA9P2425 Full - - - - 7.5 10.0 nA Supply Current (+) 25 - 3.5 5.5 - 3.5 5.5 mA Supply Current (-) 25 - 2.5 3.5 - 2.5 3.5 mA Power Supply Rejection Full 80 90 - 74 90 - dB Drift Current (Note 2) VIN = 0V POWER SUPPLY CHARACTERISTICS NOTES: 2. AV = ±1, RL = 2kΩ, CL = 50pF. 3. Derived from computer simulation only; not tested. Functional Diagram OFFSET ADJUST V+ 3 -INPUT +INPUT S/H CONTROL 1 2 9 4 - - + + OUT HA-2420/2425 14 13 GND 3 7 5 V- 11 HOLD CAPACITOR FN2856.6 November 19, 2004 HA-2420, HA-2425 Test Circuits and Waveforms -IN OUTPUT INPUT +IN S/H CONTROL HOLD CAP HOLD SAMPLE S/H CONTROL GND OUTPUT CH VSTEP S/H CONTROL INPUT NOTE: Set rise/fall times of S/H Control to approximately 20ns. FIGURE 1. HOLD STEP ERROR AND DRIFT CURRENT FIGURE 2. HOLD STEP ERROR TEST +5V SINE WAVE INPUT HOLD SAMPLE S/H CONTROL OUTPUT ∆V ∆t IN2 IN1 IN3 IN4 IN5 IN6 IN7 IN8 A2 A1 EN HI-508A MUX -IN HA-2420/2425 VO OUT OUT +IN S/H HOLD CONTROL CAP GND VINP-P CH A0 S/H CONTROL INPUT NOTE: Compute hold mode feedthrough attenuation from the formula: V OUT HOLD Feedthrough Attenuation = 20 log --------------------------------V IN HOLD NOTE: Measure the slope of the output during hold, ∆V/∆t, and compute drift current from: ID = CH ∆V/∆t. Where VOUTHOLD = Peak-to-Peak value of output sinewave during the hold mode. FIGURE 3. DRIFT CURRENT TEST FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION 4 FN2856.6 November 19, 2004 HA-2420, HA-2425 Schematic Diagram OFFSET ADJ. R1 R2 Q29 Q30 Q89 Q5 Q17 Q23 Q106 V+ Q58 Q64 J63 Q65 Q90 Q66 Q2 Q82 Q72 Q4 Q45 Q46 Q59 Q7 Q9 Q74 J61 RP Q73 Q91 Q105 Q87 Q51 Q15 Q6 Q11 Q47 Q52 R7 Q48 CH Q53 Q54 Q49 Q50 Q27 D1 Q Q8 19 Q21 Q75 Q20 Q31 C3 15pF Q32 Q100 Q3 S/H CONTROL Q24 Q18 Q10 R10 Q56 Q38 Q77 Q35 GND Q76 Q55 Q22 Q83 R9 OUT Q101 Q33 Q34 Q25 Q13 R8 Q26 C4 Q67 Q69 J60 Q12 Q68 R121 Q14 R11 Q103 Q39 Q40 Q42 Q43 Q83 Q41 Q44 GND J86 Q78 Q70 J57 Q102 Q62 Q16 Q79 Q71 Q80 R14 R13 Q81 +IN 5 -IN V- FN2856.6 November 19, 2004 HA-2420, HA-2425 Application Information RF INPUT HOLD STEP VOLTAGE (mV) RI OUTPUT -IN +10 +IN 5 -10 0.002RF -5 +5 +10 OUT S/H CONTROL 0 DC INPUT VOLTAGE (V) -5 S/H CONTROL INPUT CH = 0.1µF –RF NOTE: GAIN ∼ ----------RI FIGURE 6. INVERTING CONFIGURATION -10 CH = 10,000pF CH = 1000pF -15 INPUT -20 OUTPUT +IN -25 -IN OUT S/H CONTROL CH = 100pF -30 -35 RF RI FIGURE 5. HOLD STEP vs INPUT VOLTAGE S/H CONTROL INPUT RF NOTE: GAIN ~ 1 + -------RI 0.002RI Offset Adjustment The offset voltage of the HA-2420 and HA-2425 may be adjusted using a 100kΩ trim pot, as shown in Figure 8. The recommended adjustment procedure is: Apply 0V to the sample-and-hold input, and a square wave to the S/H control. Adjust the trim pot for 0V output in the hold mode. Gain Adjustment The linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. The two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. FIGURE 7. NON-INVERTING CONFIGURATION Figure 8 shows a typical unity gain circuit, with Offset Zeroing. All of the other normal op amp feedback configurations may be used with the HA-2420, HA-2425. The input amplifier may be used as a gated amplifier by utilizing Pin 11 as the output. This amplifier has excellent drive capabilities along with exceptionally low switch leakage. CONTROL V+ CH - + + - The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input voltage that should produce a +10V output. 3. Adjust the trim pot for +10V output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. 5. Measure the output hold voltage (V-10NOMINAL). Adjust the trim pot for an output hold voltage of ( V – 10 NOMINAL ) + ( -10V ) ----------------------------------------------------------------2 IN V- OUT 100kΩ OFFSET TRIM (±25mV RANGE) FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW) The method used to reduce leakage paths on the PC board and the device package is shown in Figure 9. This guard ring is recommended to minimize the drift during hold mode. The hold capacitor should have extremely high insulation resistance and low dielectric absorption. Polystyrene (below 85oC), Teflon, or Parlene types are recommended. For more applications, consult Intersil Application Note AN517, or the factory applications group. 6 FN2856.6 November 19, 2004 HA-2420, HA-2425 Effective Aperture Delay Time (EADT) CONTROL GND -IN HOLD CAPACITOR +IN V- OUT The difference between the digital delay time from the Hold command to the opening of the S/H switch, and the propagation time from the analog input to the switch. EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to VIN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of VIN that occurred before the Hold command. Aperture Uncertainty V+ FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW) Glossary of Terms The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. Drift Current Acquisition Time The time required following a “sample” command, for the output to reach its final value within ±0.1% or ±0.01%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. The net leakage current from the hold capacitor during the hold mode. Drift current can be calculated from the droop rate using the formula: ∆V I D (pA) = C H (pF) × -------- (V ⁄ s ) ∆t Aperture Time The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is that interval between the conditions of 10% open and 90% open. 7 FN2856.6 November 19, 2004 HA-2420, HA-2425 Typical Performance Curves 1000 1000 MIN. SAMPLE TIME DRIFT DURING HOLD FOR 0.1% ACCURACY AT 25oC (mV/s) 10V SWINGS (µs) 100 UNITY GAIN PHASE MARGIN (DEGREES) 10 1.0 NOISE (µVRMS) HOLD STEP OFFSET ERROR (mV) UNITY GAIN BANDWIDTH (MHz) 0.1 OUTPUT NOISE “HOLD” MODE 100 10 EQUIV. INPUT NOISE “SAMPLE” MODE - 0Ω SOURCE RESISTANCE SLEW RATE (V/µs) 0.01 10pF 0.01µF 1000pF CH VALUE 100pF 0.1µF 1 10 1.0µF FIGURE 10. TYPICAL SAMPLE AND HOLD PERFORMANCE AS A FUNCTION OF HOLDING CAPACITOR OPEN LOOP VOLTAGE GAIN (dB) ID (pA) 100 10 1 -50 -25 0 25 50 75 TEMPERATURE (oC) 100 100 1K 10K 100K BANDWIDTH (LOWER 3dB FREQUENCY = 10Hz) 1M FIGURE 11. BROADBAND NOISE CHARACTERISTICS 1000 125 100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 10 CH = 100pF CH = 1000pF CH = 0.01µF CH = 1.0µF CH = 0.1µF 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 12. DRIFT CURRENT vs TEMPERATURE FIGURE 13. OPEN LOOP FREQUENCY RESPONSE OPEN LOOP PHASE ANGLE (DEGREES) -30 CH = 1000pF -40 ATTENUATION (dB) EQUIV. INPUT NOISE “SAMPLE” MODE - 100kΩ SOURCE RESISTANCE -50 -60 -70 -80 -90 0 CH = 0.01µF 20 CH = 1000pF 40 CH ≤ 100pF CH = 1.0µF 60 80 100 CH = 0.1µF 120 140 160 180 200 220 240 100 1K 10K 100K 1M 10M 10 100 ±10V SINUSOIDAL INPUT FREQUENCY (Hz) 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 14. HOLD MODE FEED THROUGH ATTENUATION FIGURE 15. OPEN LOOP PHASE RESPONSE 4V S/H CONTROL 8 SAMPLE HOLD 0V FN2856.6 November 19, 2004 HA-2420, HA-2425 Typical Performance Curves (Continued) S/H (5V/DIV.) S/H (5V/DIV.) 0V +10V VOUT VOUT (2V/DIV.) (2V/DIV.) 0V -10V TIME (1µs/DIV) TIME (1µs/DIV) FIGURE 16. ACQUISITION TIME (CH = 1000pF) FIGURE 17. ACQUISITION TIME (CH = 1000pF) S/H (5V/DIV.) S/H (5V/DIV.) 0V +1V VOUT (0.5V/DIV.) VOUT (0.5V/DIV.) 0V -1V TIME (1µs/DIV) FIGURE 18. ACQUISITION TIME (CH = 1000pF) TIME (1µs/DIV) FIGURE 19. ACQUISITION TIME (CH = 1000pF) S/H (5V/DIV.) S/H (5V/DIV.) 0.1V 0V 0V VOUT VOUT (50mV/DIV.) -0.1V (50mV/DIV.) TIME (500ns/DIV) FIGURE 20. ACQUISITION TIME (CH = 1000pF) 9 TIME (500ns/DIV) FIGURE 21. ACQUISITION TIME (CH = 1000pF) FN2856.6 November 19, 2004 HA-2420, HA-2425 Die Characteristics PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ DIE DIMENSIONS: 102 mils x 61 mils x 19 mils 2590µm x 1550µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ TRANSISTOR COUNT: 78 SUBSTRATE POTENTIAL: V- PROCESS: Bipolar Dielectric Isolation BACKSIDE FINISH: Gold, Nickel, Silicon, etc. Metallization Mask Layout +IN IN HA-2420, HA-2425 GND VOS ADJ VOS ADJ HOLD CAP V- V+ OUTPUT 10 FN2856.6 November 19, 2004 HA-2420, HA-2425 Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D) N 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 C D 0.735 0.775 18.66 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.355 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 0.204 14 2.54 BSC - 7.62 BSC 0.430 - 0.150 2.93 6 10.92 3.81 14 7 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). 11 FN2856.6 November 19, 2004 HA-2420, HA-2425 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 eA e ccc M C A-B S eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 14 14 5. This dimension allows for off-center lid, meniscus, and glass overrun. 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN2856.6 November 19, 2004