AN1258 Op Amp Precision Design: PCB Layout Techniques Kumen Blake Microchip Technology Inc. INTRODUCTION This application note covers Printed Circuit Board (PCB) effects encountered in high (DC) precision op amp circuits. It provides techniques for improving the performance, giving more flexibility in solving a given design problem. It demonstrates one important factor necessary to convert a good schematic into a working precision design. This material is for engineers who design slow precision circuits, including those with op amps. It is aimed at those engineers with little experience in this kind of design, but can also help experienced engineers that are looking for alternate solutions to a design problem. The information in this application note can be applied to all precision (DC) analog designs, with some thought and diligence. The focus is on common op amp circuits so that the reader can quickly convert this material into improvements in their own op amp designs. Additional material at the end of the application note includes references to the literature and the schematic of a PCB used in the design example. THERMOCOUPLE JUNCTION BEHAVIOR While thermocouples are a common temperature sensor , it is not commonly known that every PCB design includes many unintended thermocouple junctions that modify the signal voltages. This section covers the physics behind this effect and gives practical illustrations. Seebeck Effect When two dissimilar conductors (or semiconductors) are joined together, and their junction is heated, a voltage results between them (Seebeck or thermoelectric voltage); this is known as the Seebeck effect. This voltage is roughly proportional to absolute temperature. There are many references that discuss this effect in detail, including the “Temperature Products” section of reference ; see especially pages Z-13, Z-14 and Z-23 through Z-32. Figure 1 shows the Seebeck voltage as a function of temperature for the standard type K thermocouple. Notice that the response is not strictly linear, but can be linearized over small temperature ranges (e.g., ±10°C). ocouple Voltage (mV) Thermo Author: • • • • • • • • Op Amp Temperature Thermal Gradient Thermocouple Junction Thermoelectric Voltage IC Sockets Contact Potential PCB Surface Contamination Related Application Notes The following application notes, together with this one, form a series about precision op amp design topics. They cover both theory and practical methods to improve a design’s performance. • AN1177 on DC Errors  • AN1228 on Random Noise  2009-2012 Microchip Technology Inc. ITS-90 Type K Thermocouple -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 Key Words and Phrases 60 55 50 45 40 35 30 25 20 15 10 5 0 -5 -10 Thermocouple Temperature (°C) FIGURE 1: Response. Type K Thermocouple’s Most thermocouple junctions behave in a similar manner. The following are examples of thermocouple junctions on a PCB: • • • • • Components soldered to a copper pad Wires mechanically attached to the PCB Jumpers Solder joints PCB vias DS01258B-page 1 AN1258 The linearized relationship between temperature and thermoelectric voltage, for small temperature ranges, is given in Equation 1. The Seebeck coefficients for the junctions found on PCBs are typically, but not always, below ±100 µV/°C. EQUATION 1: TABLE 1: Junction No. VREF (mV) kJ (µV/°C) 1 10 40 2 -4 -10 3 4 10 -10 -40 SEEBECK VOLTAGE VTH k J T J – T REF VTH = V REF + V TH 4 Where: Note 1: VTH = Change in Seebeck voltage (V) kJ = Seebeck coefficient (V/°C) In this illustration, temperature is constant across the PCB. This means that the junctions are at the same temperature. Let’s also assume that this temperature is +125°C and that the voltage on the left trace is 0V. The results are shown in Figure 3. Notice that VTH is the voltage change from one conductor to the next. TREF = Reference Temperature (°C) VTH = Seebeck voltage (V) VREF = Seebeck voltage at TREF (V) Illustrations Using a Resistor Three different temperature profiles will be shown that illustrate how thermocouple junctions behave on PCB designs. Obviously, many other components will also produce thermoelectric voltages (e.g., PCB edge connectors). Figure 2 shows a surface mount resistor with two metal (copper) traces on a PCB. The resistor is built with end caps for soldering to the PCB and a very thin conducting film that produces the desired resistance. Thus, there are three conductor types shown in this figure, with four junctions. Copper Traces 2: VREF and kJ have polarities that assume a leftto-right horizontal direction. TREF = 25 °C. CONSTANT TEMPERATURE TJ = Junction Temperature (°C) Resistor Film ASSUMED THERMOCOUPLE JUNCTION PARAMETERS 14 mV 0 mV +125.00°C +125.00°C FIGURE 2: on PCB. Resistor and Metal Traces For illustrative purposes, we’ll use the arbitrary values shown in Table 1. Notice that junctions 1 and 4 are the same, but the values are shown with opposite polarities; this is one way to account for the direction current flows through these junctions (the same applies to junctions 2 and 3). DS01258B-page 2 +125.00°C +125.00°C Location Resistor End Caps Junction #4 Junction #3 14 mV 0 mV VREF VTH VTH (mV) (mV) (mV) Junction #1 10 4 14 Junction #2 -4 -1 -5 Junction #3 4 1 5 Junction #4 -10 -4 -14 FIGURE 3: Results. Junction #1 Junction #2 9 mV Constant Temperature TEMPERATURE CHANGE IN THE NORMAL DIRECTION In this illustration, temperature changes vertically in Figure 2 (normal to the resistor’s axial direction), but does not change in the axial direction (horizontally). The metal areas maintain almost constant voltages in the normal direction, so this case is basically the same as the previous one. Note: When temperature is constant along the direction of current flow, the net change in thermoelectric voltage between two conductors of the same material is zero. 2009-2012 Microchip Technology Inc. AN1258 TEMPERATURE CHANGE IN THE AXIAL DIRECTION In this illustration, temperature changes horizontally in Figure 2 (along the resistor’s axial direction), but does not change in the normal direction (vertically). Let’s assume 0V on the left copper trace, +125°C at Junction #1, a temperature gradient of 10°C/in (0.394°C/mm) from left to right (0 in the vertical direction) and a 1206 SMD resistor. The resistor is 0.12 inches long (3.05 mm) and 0.06 inches wide (1.52 mm). Assume the end caps are about 0.01 inches long (0.25 mm) and the metal film is about 0.10 inches long (2.54 mm). The results are shown in Figure 4. 8.999 mV 14.000 mV 14.010 mV 0 mV -0.038 mV PREVENTING LARGE THERMOELECTRIC VOLTAGES This section includes several general techniques that prevent the appearance of large temperature gradients at critical components. Reduced Heat Generation When a PCB’s thermal gradient is mainly caused by components attached to it, then find components that dissipate less power. This can be easy to do (e.g., change resistors) or hard (change a PICmicro® microcontroller). Increasing the load resistance, and other resistor values, also reduces the dissipated power. Choose lower power supply voltages, where possible, to further reduce the dissipated power. Redirect the Heat Flow Changing the direction that heat flows on a PCB, or in its immediate environment, can significantly reduce temperature gradients. The goal is to create nearly constant temperatures in critical areas. +125.0°C +125.1°C Location +126.1°C +126.2°C VREF (mV) VTH (mV) VTH (mV) Junction #1 10 4.000 14.000 Junction #2 -4 -1.001 -5.001 Junction #3 Junction #4 FIGURE 4: 1.011 5.011 -10 -4.048 4 -14.048 Axial Gradient Results. Thus, the temperature gradient of 10°C/in (1.2°C increase from left to right) caused a total of -38 µV to appear across this resistor. Notice that adding the same temperature change to all junction temperatures will not change this result. Note: Shifting all of the junction temperatures by the same amount does not change the temperature gradient. This means that the voltage drop between any two points in the circuit using the same conductive material is the same (assuming we’re within the linear region of response). 2009-2012 Microchip Technology Inc. ALTERNATE HEAT PATHS Adding heat sinks to parts that dissipate a lot of power will redirect the heat to the surrounding air. One form of heat sink that is often overlooked is either ground planes or power planes in the PCB; they have the advantage of making temperature gradients on a PCB lower because of their large (horizontal) thermal conductivity. Adding a fan to a design will also redirect heat to the surrounding air, which reduces the temperature drop on the PCB. This approach, however, is usually avoided to minimize other design issues (random temperature fluctuations, acoustic noise, power, cost, etc.). It is important to minimize air (convection) currents near critical components. Enclose either the parts with significant temperature rise, or the critical parts. Conformal coating may also help. ISOLATION FROM HEAT GENERATORS It is possible to thermally isolate critical areas on the PCB. Regions with little or no metal act like a good thermal insulator. Signals that need to cross these regions can be sent through series resistors, which will also act as poorly conducting thermal elements. Place heat sources as far away from critical points as possible. Since many heat sources are in the external environment, it can be important to place these critical points far away from the edges of the PCB. Components that dissipate a lot of power should be kept far away from critical areas of the PCB. DS01258B-page 3 AN1258 Low profile components will have reduced exposure to the external environment. They may have the additional advantage of reduced electrical crosstalk. CURING THERMOELECTRIC VOLTAGE EFFECTS Thermal barriers, such and conformal coating and PCB enclosures, can be helpful too. They usually do not have to be added unless there are other compelling reasons to do so. This section focuses on methods that minimize the effects of a given temperature gradient. They can be powerful aids in improving a design because they tend to be low cost. Slow Temperature Changes Metallurgy In some applications, sudden changes thermoelectric voltages can also be a concern. in Avoid power-up and power-down thermal transient problems by minimizing the currents drawn during these times. Also, reducing the times can help. Quick changes in voltages at heavy loads can be another source of concern. If the load cannot be made lighter, then isolation is usually the best approach to solving this problem. Critical points, that need to have the same total thermoelectric voltage, should use the same conductive material. For example, the inputs to an op amp should connect to the same materials. The PCB traces will match well, but components with different constructions may be a source of trouble. It is possible to find combinations of metals and solders that have low Seebeck coefficients. While this obviously reduces voltage errors, this can be complicated and expensive to implement in manufacturing. Following Contour Lines Place critical components so that their current flow follows constant temperature contour lines; this minimizes their thermoelectric voltages. Figure 5 shows an inverting amplifier that will be used to illustrate this concept; RN, RG and RF are the critical components in this circuit. RG RF VIN VOUT VDD RN U1 FIGURE 5: C1 Inverting Amplifier. Figure 6 shows one implementation of this concept. Constant temperature contour lines become reasonably straight when they are far from the heat source. Placing the resistors in parallel with these lines minimizes the temperature drop across them. Constant Temperature Contour Lines Heat Source VIN RF RG RN U1 VDD C1 VOUT FIGURE 6: Contour Lines. DS01258B-page 4 Resistors Aligned with 2009-2012 Microchip Technology Inc. AN1258 The main drawback to this technique is that the contour lines change when the external thermal environment changes. For instance, picking up a PCB with your hands adds heat to the PCB, usually at locations not accounted for in the design. Cancellation of Thermoelectric Voltages It is possible to cancel thermoelectric voltages when the temperature gradient is constant. Several examples will be given to make this technique easy to understand. TRADITIONAL OP AMP LAYOUT APPROACH Figure 7 shows a non-inverting amplifier that needs to have the resistors’ thermoelectric voltage effect minimized. The traditional approach is to lay out the input resistors (RN and RG) close together, at equal distances from the op amp input pins and in parallel. VIN U1 C1 VOUT RG FIGURE 7: RF Non-inverting Amplifier. Figure 8 shows one layout that follows the traditional approach, together with a circuit diagram that includes the resulting thermoelectric voltages (VTHx and VTHy). VTHx is positive on the right side of a horizontally oriented component (e.g., RN). VTHy is positive on the top side of a vertically oriented component (e.g., RF). RF RG RN VIN G N = 1 + RF R G VOUT = V IN + V THx G N – V THx G N – 1 + V THy = V IN G N + V THx + VTHy When the gain (GN) is high, the thermoelectric voltage contributes little to the output error. This layout may be good enough in that case. Notice that the cancellation between RN and RG is critical to good performance. When the gain is low, or the very best performance is desired, this layout needs improvement. The following sections give guidance that helps achieve this goal. SINGLE RESISTOR SUBSTITUTIONS VDD Figure 9 shows the original resistor and its model on the top, and a two series resistor substitution and its model on the bottom. The original resistor has a thermally induced voltage VTHx that is based on the temperature gradient in the x-direction (horizontal). The two resistors on the bottom have thermally induced voltages VTHy that are based on the temperature gradient in the y-direction (vertical); they are equal because the temperature gradient is constant and the resistor lengths are equal. Due to their parallel alignment, these voltages cancel; the net thermally induced voltage for this combination (as laid out) is zero. C1 VTHx C1 U1 R1A R1B RN VTHx RF V THy FIGURE 8: One Possible Layout (not recommended) and its Thermoelectric Voltage Model. VTHy R1B Where: R1A = R1B = R1/2 FIGURE 9: Note: 2009-2012 Microchip Technology Inc. VTHy R1A VOUT RG V THx R1 R1 VOUT VDD VIN U1 EQUATION 2: A single resistor on a PCB will produce a thermoelectric voltage, as discussed before. Replacing that resistor with two resistors that are properly aligned will cancel the two resulting thermoelectric voltages. VDD RN The output has a simple relationship to the inputs (VIN and the three VTHx and VTHy sources): Series Resistor Substitution. The orientation of these two resistors (R1A and R1B) is critical to canceling the thermoelectric voltages. DS01258B-page 5 AN1258 Figure 10 shows the original resistor and its model on the top, and a two parallel resistor substitution and its model on the bottom. RG RN VIN The original resistor has a thermally induced voltage VTHx that is based on the temperature gradient in the x-direction (horizontal). The two resistors on the bottom have thermally induced voltages VTHy that are based on the temperature gradient in the y-direction (vertical); they are equal because the temperature gradient is constant and the resistor lengths are equal. Due to their orientation, and because R1A = R1B, these voltages produce currents that cancel. The net thermally induced voltage for this combination (as laid out) is zero. R1 R1 R1A VTHx C1 VDD VIN U1 RN VTHx VOUT RG V THx RF V THx FIGURE 12: First Layout (not recommended) and its Thermoelectric Voltage Model. The output has a simple relationship to the inputs (VIN and the three VTHx sources): R1B R1A VTHy G N = 1 + RF R G VOUT = V IN + V THx G N – V THx G N – 1 + V THx = V IN G N + 2V THx Where: R1A = R1B = 2R1 FIGURE 10: Substitution. Parallel Resistor NON-INVERTING AMPLIFIER Figure 11 shows a non-inverting amplifier. We will start with the layout in Figure 12 (previously shown in Figure 6). The resistor RF is horizontal so that all of the thermoelectric voltages may be (hopefully) cancelled. The model shows how the thermoelectric voltages modify the circuit. VIN C1 VOUT EQUATION 3: VTHy R1B U1 VDD RF U1 When the gain (GN) is high, the thermoelectric voltage’s contribution to the output error is relatively small. This layout may be good enough in that case. Notice that the cancellation between RN and RG is critical. We have a better layout shown in Figure 13. Recognizing that subtracting the last term in the VOUT equation (middle equation in Equation 3) completely cancels the thermoelectric voltages, the resistor RF was oriented in the reverse direction. RF RG RN VIN VDD C1 RN VOUT RG FIGURE 11: RF Non-inverting Amplifier. U1 C1 VOUT VDD VIN VDD C1 U1 RN VTHx VOUT RG V THx RF V THx FIGURE 13: Second Layout and its Thermoelectric Voltage Model. DS01258B-page 6 2009-2012 Microchip Technology Inc. AN1258 With the reversed direction for RF, the output voltage is now: VDD RF U1 – RG VIN RG C1 + RF VREF VOUT EQUATION 4: GN = 1 + RF RG V OUT = VIN + VTHx G N – VTHx G N – 1 – VTHx The cancellation between RN and RG is critical to this layout; the change to RF’s position is not as important. INVERTING AMPLIFIER VTHx VREF C1 VDD U1 VOUT RG V THx RF V THx FIGURE 16: Difference Amplifier Layout and its Thermoelectric Voltage Model. VDD U1 The output has a simple relationship to the inputs (VIN, VREF and the four VTHx sources): C1 VOUT RG + VIN RF – Inverting amplifiers use the same components as noninverting amplifiers, so the resistor layout is the same; see Figure 14. RF VIN RG RN VTHx RG = VIN G N EQUATION 5: RF VIN VOUT VDD RN U1 C1 G = RF R G VOUT = V IN + V THx – V THx G + V REF + V THx – VTHx = V IN G + V REF FIGURE 14: Inverting Amplifier. DIFFERENCE AMPLIFIER Figure 15 shows a difference amplifier. This topology has an inherent symmetry between the non-inverting and inverting signal paths, which lends itself to cancelling the thermoelectric voltages. Figure 16 shows the layout and its model. RG RF VREF U1 + VIN – VDD INSTRUMENTATION AMPLIFIER INPUT STAGE Figure 17 shows an instrumentation amplifier input stage, which is sometimes used to drive the input of a differential ADC. While this is a symmetrical circuit, achieving good thermoelectric voltage cancellation on the PCB presents difficulties. It is best to use a dual op amp, so the RF resistors have to be on both sides of the op amp, while RG connects both sides; the distances between resistors are too large to be practical (thermal gradient is not constant). C1 U1A VOUT RG FIGURE 15: RN RF Difference Amplifier. + VIN RG – VDD C1 RF RF + VOUT – RN U1B FIGURE 17: Instrumentation Amplifier Input Stage (not recommended). 2009-2012 Microchip Technology Inc. DS01258B-page 7 AN1258 The solution to this problem is very simple; split RG into two equal series resistors so that we can use the non-inverting layout (see Figure 13) on both sides of the dual op amp. Each side of this amplifier will cancel its thermoelectric voltages independently; this is shown in Figure 18 and Figure 19. The VTHx sources cancel, for the reasons already given, so the differential output voltage is simply: EQUATION 6: G = 1 + 2R F R G VOUT = V IN G U1A VDD + VIN – MODIFICATIONS FOR NON-CONSTANT TEMPERATURE GRADIENTS C1 RN RG/2 RF RG/2 RF Temperature gradients are never exactly constant. One cause is the wide range of thermal conductivities (e.g., traces vs. FR4) on a PCB, which causes complex temperature profiles. Another cause is that many heat sources act like point sources, and the heat is mainly conducted by a two dimensional object (the PCB); the temperature changes rapidly near the source and slower far away. + VOUT – RN U1B FIGURE 18: Input Stage. Instrumentation Amplifier C1 U1 VDD RF RG/2 RN One method is to minimize the size of critical components (e.g., resistors). If we assume that temperature has a quadratic shape, then using components that are half as long should reduce the non-linearity error to about one quarter the size. VIN+ VOUT+ VDD VOUT– VIN– RF RG/2 RN Another method is to keep all heat sources and sinks far away from the critical components. This makes the contour lines straighter. C1 U1A RN VTHx + VIN – RG/2 V THx RF V THx RG/2 VTHx RF VTHx + VOUT – RN VTHx U1B FIGURE 19: Instrumentation Amplifier Input Stage Layout and its Thermoelectric Voltage Model. DS01258B-page 8 Non-constant temperature gradients will cause the temperature profile to have significant curvature, which causes all of the previous techniques to have less than perfect success. Usually, the curvature is small enough so that those techniques are still worth using. Sometimes, additional measures are needed to overcome the problems caused by the curvature. The contour lines can be deliberately changed in shape. Using a ground plane (also power planes) to conduct heat away from the sources helps equalize the temperatures, which reduces the non-linear errors. Adding guard traces or thermal heat sinks that surround the critical components also help equalize the temperatures. We can modify the sizes of the critical components so that the cancellation becomes closer to exact. In order to match resistors, for instance, we need to make sure that the temperature change across each of the matched resistors is equal; see Figure 20 for an illustration. 2009-2012 Microchip Technology Inc. AN1258 (T = +1.0°C) +25.0°C +26.0°C MEASUREMENT OF TEMPERATURE RELATED QUANTITIES While the techniques previously shown are a great help in producing an initial PCB layout, it is important to verify that your design functions as specified. This section includes methods for measuring the response of individual components and of a PCB. With this information, it is possible to make intelligent design tweaks. TEMPERATURE There are many ways to measure temperature [4, 5, 6]. We could use thermocouples, RTDs, thermistors, diodes, ICs or thermal imagers (infrared cameras) to measure the temperature. +25.1°C +26.1°C +26.3°C (T = +1.0°C) FIGURE 20: Example of Mismatching the Component Sizes. Figure 21 shows a circuit based on the MCP9700 IC temperature sensor. Because all of the components draw very little current, their effect on PCB temperature will be minimal. There is enough filtering and gain to make VOUT easy to interpret. This circuit can be built on a very small board of its own, which can be easily placed on top of the PCB of interest. VDD = 5.0V U1 MCP9700 C1 1.0 µF 100 nF Temp. Sensor R1 100 kΩ VDD TPCB C4 100 nF VDD U2 R2 MCP6041 113 kΩ R3 12.4 kΩ R4 100 kΩ C2 1.0 µF FIGURE 21: Circuit. R5 1.00 MΩ R6 1.00 kΩ VOUT C3 22 nF IC Temperature Sensor The MCP9700 outputs a voltage of about 500 mV plus 10.0 mV/°C times the board temperature (TPCB, in °C). The amplifier provides a gain of 10 V/V centered on 500 mV (when VDD = 5.0V), giving: EQUATION 7: VOUT = 500 mV + T PCB 100 mV/C 2009-2012 Microchip Technology Inc. DS01258B-page 9 AN1258 Since the MCP9700 outputs a voltage proportional to temperature, VOUT needs to be sampled by an ADC that uses an absolute voltage reference. The absolute accuracy of this circuit does not support our application, so it is important to calibrate the errors. Leave the PCB in a powered-off state (except for the temperature sensor) for several minutes. Measure VOUT at each point, with adequate averaging. The changes in VOUT from the calibration value represents the change in TPCB from the no power condition. VDD RF VDD/2 VREF RG PACKAGE THERMAL RESISTANCE The way to estimate the temperature (T in °C) of a component is to multiply its dissipated power (P in W) by the package thermal resistance (JA in °C/W). This helps establish temperature maximum points. To measure JA, when it is not given in a data sheet, place the temperature sensor at the IC (usually, a thermocouple between the package and the PCB). Insert a small resistor in the supply to measure the supply current when on (IDD in A). Measure the change in temperature (T in °C) between the off and on conditions, supply voltage (VDD in V) and IDD. Then, RF RG VTHx VDD/2 VREF C1 U1 VOUT RG V THx RF V THx FIGURE 22: Difference Amplifier with Deliberately Unbalanced Thermoelectric Voltages and Heat Generating Resistor. We can also place a short across one component, of a matched pair, with a copper trace on the PCB. Figure 23 shows a non-inverting amplifier layout that shorts RN (with a copper trace) to unbalance the thermoelectric voltages. It also connects the two inputs together, and uses larger resistors, to simplify measurements (VOUT = VDD/2, ideally). The short is easily removed from the PCB. VDD/2 VDD 10 Ohm U1 RG (RN) + VX – C1 VOUT THERMOELECTRIC VOLTAGES The large resistor on the right of the layout can be used to generate heat, causing a horizontal temperature gradient at the resistors RG and RF. The gain (G) is set high to make the measurements more accurate. The thermoelectric voltage (VTHx) across one resistor is: VTHx RF VDD EQUATION 8: The easiest way to measure thermoelectric voltages is to thermally imbalance a difference amplifier circuit. The thermoelectric voltages have a polarity that adds (instead of cancelling) in Figure 22 (compare to Figure 16). The differential input voltage is zero, and the resistors are larger to emphasize the thermoelectric voltages. 1W VOUT RF T JA = -------------------V DD I DD + VX – C1 RG THERMAL GRADIENTS To measure thermal gradients, simply measure the temperature at several points on the PCB. The gradient is then the change in temperature divided by the distance between points. More points give better resolution on the gradient, but reduce the accuracy of the numerical derivative. 10 Ohm U1 RN VTHx VDD 1W C1 U1 VDD/2 VOUT RG V THx RF V THx FIGURE 23: Shorted Resistor (RN) that Unbalances Thermoelectric Voltages. With the unbalance, we now have the thermoelectric voltage: EQUATION 10: G N = 1 + RF R G EQUATION 9: G = RF RG VOUT – VREF V THx = --------------------------------2G + 2 DS01258B-page 10 VOUT – VDD 2 V THx = ------------------------------------–GN 2009-2012 Microchip Technology Inc. AN1258 TROUBLESHOOTING TIPS AND TRICKS LEAKAGE CURRENTS Using a strip chart to track the change in critical DC voltages over time helps locate the physical source of the errors. Not only can it show how large the change is between two different thermal conditions (e.g., on and off), but it shows the time constants of these shifts. They can be roughly divided into the following three categories: Leakage currents cause voltage drops when they flow through either resistors or parasitic resistances. This section focuses on parasitic resistances presented by the PCB: surface resistance and bulk (through the dielectric) resistance. • Time constant << 1 s, within component (e.g., thermal crosstalk within an op amp) • Time constant 1 s, single component (e.g., in an eight lead SOIC package) • Time constant >> 1 s, PCB and its environment To quickly and easily change the temperature at one location on a PCB, do the following. Use a clean drinking straw to blow air at the location (component) of interest. Use a piece of paper to re-direct the airflow away from other nearby components. When troubleshooting, the paper can be used to divide a PCB area in half to help locate the problem component. This approach does not give exact numbers, but can be used to quickly find problem components on a PCB. You can use a heat sink (with electrically insulating heat sink compound) to reduce the temperature difference between two critical points on your PCB. The greater the area covered at both ends of the heat sink, the quicker and better this thermal “short” will work. Leakage currents cause voltage ramps when they flow into a capacitor. Common examples are the gain capacitor of a transimpedance amplifier (see Figure 32) and the non-inverting input of an op amp with no DC path to ground (not recommended). Op amp leakage (bias) currents are discussed in . High Impedance Sources High impedance signal sources are susceptible to errors caused by leakage currents. These sources are usually modeled as a current source with a high parallel resistance (a Norton model): VIN IS FIGURE 24: RS Norton Source Model. One sensor that is modeled as a Norton current source is the photodiode . A common op amp circuit used for photocurrent measurements is the transimpedance amplifier (see Figure 32). Sometimes, high impedance sources are modeled as a voltage source with a high series resistance (a Thevenin model): VIN VS FIGURE 25: RS Thevenin Source Model. The pH electrode  is one example with a Thevenin source. A common op amp implementation is a noninverting amplifier. PCB Surface Leakage PARASITIC SURFACE RESISTANCES Surface contamination on a PCB creates resistive paths for leakage currents. These leakage currents can cause appreciable voltage shifts, even in well-designed circuits. The contamination can be humidity (moisture), dust, chemical residue, etc. 2009-2012 Microchip Technology Inc. DS01258B-page 11 AN1258 On a PCB, leakage currents flow on the surface, to a sensitive node (high resistance), from nearby bare metal objects (including traces) at a different voltage. To model sensitivity to surface contamination in your circuit, add resistors between the high impedance node and other nearby nodes. For example, Figure 26 shows an amplifier circuit with a Thevenin source (VS and RS). Since RS is high and the amplifier’s input is high impedance, VIN is a high impedance node. Parasitic resistances (RP1 to RP4) are connected to all other (nearby) voltage nodes (traces on a PCB), including ground. RP1 to RP4 are open-circuited for most design work. For leakage current design calculations, they take on high resistance values (usually one at a time). RP1 RS VS VIN RP4 CLEANING A standard PCB clean step helps minimize surface contamination, but may not eliminate the problem. An additional cleaning step, using isopropyl alcohol, is needed to clean the residue left by some PCB cleaning solvents. This can then be blown dry using compressed air (with an in-line moisture trap). COATING In order to maintain the PCB cleanliness after the initial clean, you may coat the PCB surface. The coating needs to be a barrier to moisture and other contaminants; solder mask, epoxy and silicone rubber are examples. The coating will have internal (bulk) leakage currents; this effect needs to be evaluated for your design. VDD RP2 GUARD RINGS VOUT RP3 FIGURE 26: Thevenin Source and Parasitic Leakage Resistances. Figure 27 shows an amplifier circuit with a Norton source. Guard rings surrounding critical signal traces, when properly applied, can significantly reduce PCB surface leakage currents into critical (high resistance) nodes. These guard rings have no solder mask so that the leakage currents flow into them, instead of into the sensitive trace. The guard ring is biased at the same voltage as the sensitive node; it needs to be driven by a low impedance source. Guard rings increase the capacitance at critical nodes. Since they are driven by low impedance sources, these capacitances have little effect on performance. Unity Gain Buffer RP1 VIN IS RS RP2 VDD VOUT RP3 Figure 28 shows a unity gain buffer with a guard ring. This guard ring is biased by VOUT and protects (surrounds) the op amp’s non-inverting input (and all top metal connected to it) on the PCB surface. The diagram is for surface mount components only. RN is an 0805 SMD to give sufficient clearance for the guard ring trace between its pads. The parasitic resistor values (RP) depend on your PCB layout. For a typical layout, with today’s geometries (traces are close and short) and materials, we have: VIN C1 RN VOUT • RP ~ 1000 GΩ, low humidity and contamination • RP ~ 1 GΩ, high humidity and contamination These RP values need to be modified for atypical geometries; see Appendix B: “PCB Parasitic Resistance”. These RP values also need to be modified for the worst case conditions for your application. Measurements in your conditions, and with your PCB layout, will give better estimates of RP. DS01258B-page 12 VDD U1 FIGURE 27: Norton Source and Parasitic Leakage Resistances. VDD VIN RN C1 U1 VOUT FIGURE 28: Ring. Unity Gain Buffer with Guard 2009-2012 Microchip Technology Inc. AN1258 The parasitic resistances are connected as shown in Figure 29. RP2 injects current into U1’s non-inverting input (the high impedance node). The other parasitic resistors inject current into the guard ring, which is driven by VOUT; they do not affect the performance. The voltage across RP2 is U1’s offset voltage (VOS), so the leakage current is greatly reduced. For instance, if VOS ±2 mV and the voltage without the guard ring is 2V, the leakage current would be reduced by a factor of about 1000. The parasitic resistances are connected as shown in Figure 31. Similar to the Unity Gain Buffer in the last section, U1’s offset voltage (VOS) is across RP2, which greatly reduces its leakage current. The other parasitic resistances are driven by VOUT, RF and RG; they do not affect the performance. The leakage current is typically reduced by a factor of about 1000. RP1 RP3 RP2 RP1 RP3 VIN C1 U1 RP4 C1 U1 RN RP2 RN VIN VDD VDD RG VOUT VOUT RF RP4 RP5 FIGURE 29: Equivalent Circuit for Unity Gain Buffer with Guard Ring. FIGURE 31: Equivalent Circuit for Noninverting Amplifier with Guard Ring. One example of an application that sometimes uses unity gain op amps are pH meters. In that case, however, both VIN and RN are located off the PCB; the guard ring only needs to surround U1’s non-inverting input. Transimpedance Amplifier Non-inverting Gain Amplifier Figure 30 shows a non-inverting gain amplifier with a guard ring. This guard ring is biased by VOUT, RF and RG; it protects (surrounds) the op amp’s non-inverting input (and all top metal connected to it) on the PCB surface. RF and RG are low impedance, to drive the guard ring properly. RN is a low valued resistor that cancels thermojunction voltage effects, but has little effect on bias current errors (e.g., IBRN << ±1 mV). Figure 32 shows a photo-diode at the input of a transimpedance amplifier, with a guard ring. This guard ring is biased at ground; it protects (surrounds) the op amp’s inverting input (and all top metal connected to it) on the PCB surface. RF is high valued for the DC gain (VOUT/ID1). VDD RF U1 CF C1 D1 VOUT RF CF VDD U1 RG RF VIN C1 RN VDD VIN C1 U1 FIGURE 30: with Guard Ring. RF VOUT Non-inverting Gain Amplifier 2009-2012 Microchip Technology Inc. VDD C1 FIGURE 32: Photo-diode and Transimpedance Amplifier, with Guard Ring. RN RG U1 D1 VOUT VOUT ID1 The parasitic resistances are connected as shown in Figure 33. Similar to the Non-inverting Gain Amplifier in the last section, U1’s offset voltage (VOS) is across RP1, which greatly reduces its leakage current. The other parasitic resistances are connected to ground; they do not affect the performance. The leakage current is typically reduced by a factor of about 1000. DS01258B-page 13 AN1258 CF RP1 Top Trace RP2 RP1 RF VOUT ID1 U1 D1 C1 RP3 FIGURE 33: Equivalent Circuit for Photodiode and Transimpedance Amplifier, with Guard Ring. Guard Rings on Both PCB Surfaces For op amps in through-hole packages (e.g., PDIP), guard rings are needed on both top and bottom surfaces. The same design principles apply to both surfaces. Any jumper traces (via to other surface, trace and via back to the original surface), connected to traces with guard rings, also need guard rings around the jumper traces. It is better, when possible, to avoid jumper traces for critical nodes. PCB Bulk Leakage The dielectric material used in a PCB (e.g., FR4) is an insulator. Its resistance to leakage currents through the bulk (the dielectric) is described by its volume resistivity (ρV). ρV values vary considerably, depending on the dielectric and on ambient conditions. Usually, bulk leakage currents are much smaller than surface leakage currents; they can be neglected in many designs. Designs that minimize surface leakage currents, however, may be affected by bulk currents. Example 1 shows one example of how bulk leakage currents occur. Two traces run in parallel and are separated by the dielectric. The leakage current between the traces, flowing through the dielectric, is modelled by a parasitic resistor (see RP1 in Figure 34). EXAMPLE 1: Bottom Trace VDD PARALLEL TRACES, OPPOSITE SURFACES FIGURE 34: Equivalent Circuit for Parallel Traces, Opposite Surfaces. Any two metal areas on the PCB (on a surface or buried in an inner layer), at different potentials, will have a leakage current between them. The value of the parasitic (bulk) resistance depends on: • The geometry of the areas - The distance between - The cross sectional area seen by the current • Nearby metal objects (e.g., a guard ring) that modify the current flow path • The volume resistivity (ρV) - Dielectric material - Exposure to chemicals (e.g., water) The following discussion shows simple techniques to minimize these leakage currents. See Appendix B: “PCB Parasitic Resistance” for ways to estimate bulk leakage currents. SEPARATION Moving traces to the surfaces, from inner layers, increases the distance between them (e.g., Example 1). Example 2 shows two parallel traces, with a distance separating them. This extra distance increases the parasitic resistance. EXAMPLE 2: TWO PARALLEL TRACES, WITH OFFSET Top View End View Side View Top View End View DS01258B-page 14 Side View 2009-2012 Microchip Technology Inc. AN1258 CROSSED TRACES GUARD PLANE When two traces must cross, place them on opposite surfaces and in normal directions to minimize the parasitic resistance; see Example 3. Example 5 shows a trace on the left (node 1), a guard plane (node 2) and a sensitive trace (node 3). The guard plane behaves similar to a guard ring, except that it forms a distributed attenuator to the input voltage (see Figure 36); this attenuation can be much greater. EXAMPLE 3: TWO NORMAL TRACES Top View EXAMPLE 5: TWO PARALLEL TRACES, WITH GUARD PLANE Top View End View Side View End View Side View GUARD RINGS Example 4 shows a trace on the left (node 1), a guard ring (node 2) and a sensitive trace (node 3). The guard ring provides a low resistance path that redirects some of the current between node 1 and node 3 to itself. RPB2 in Figure 35 acts as an attenuator to the input voltage (V1). When V2 ≈ V3, the parasitic current (into V3) is significantly reduced. EXAMPLE 4: TWO PARALLEL TRACES, WITH GUARD RING Top View RPB1 RPB3 RPB5 RPB7 V1 V3 RPB2 RPB4 RPB6 RPB8 V2 (guard plane) FIGURE 36: (Lumped) Equivalent Circuit for Two Parallel Traces, With Guard Plane. DIELECTRIC MATERIAL Changing the dielectric material changes its bulk resistivity (ρV) and susceptibility to humidity. For designs that need exceptional performance, this is an option worth exploring. MOISTURE CONTROL End View Side View When a dielectric is exposed to moisture for an extended period of time, it can become wet. This reduces its bulk resistivity (ρV). Measures to control exposure to moisture reduce this effect. One possibility is the use of coatings. RPB1 ISOLATING SENSITIVE NODES RPB3 V1 V3 RPB2 V2 (guard ring) FIGURE 35: Equivalent Circuit for Two Parallel Traces, With Guard Ring. 2009-2012 Microchip Technology Inc. Another way to minimize PCB leakage currents is to isolate sensitive nodes (wires, package pins, etc.) from the board (i.e., not touching). One approach is to use teflon stand-offs. This has technical advantages, but can be costly to implement. Another approach is to keep sensitive nodes in the air. Bending package leads and routing holes in the PCB are possible techniques to accomplish this. DS01258B-page 15 AN1258 OTHER TIPS DESIGN EXAMPLE This section discusses other effects and design tips. This section goes over the thermal design of a thermocouple PCB available from Microchip. This PCB has the following descriptors: Packages IC packages contribute to leakage currents. Pins that are close together (fine pitch) will see greater leakage currents, due to dust and shorter leakage paths. The package itself will have bulk leakage, which depends on its chemistry. • MCP6V01 Thermocouple Auto-Zeroed Reference Design • 104-00169-R2 • MCP6V01RD-TCPL The application of this PCB is discussed in detail in reference . Piezoelectric Effect Some capacitors accumulate extra charge from mechanical stress (a variable capacitor), creating a DC shift. Some ceramic capacitors (not all) suffer from this effect. Minimize stresses with acoustic noise reduction techniques, and by making the PCB assembly more rigid. Circuit Description Figure 37 shows the general functionality of this design (the schematic is shown in Figure A-1). PC (Thermal Management Software) Triboelectric Effect Mechanical friction can cause charges to accumulate (a variable capacitor), causing a DC shift. Air flow over a PCB is one source of mechanical friction. Flexing wires and coax cables excessively can also cause this to happen. Shield against air flow, and make bends in wiring with a large radius. For remote sensors, use low noise coax or triax cable. Contact Potential Sometimes, for convenience on the bench, a PCB has sockets for critical components (e.g., an op amp). While these sockets make it easy to change components, they cause significant DC errors in high precision designs. The problem is that the socket and the IC pins are made of different metals, and are mechanically forced into contact. In this situation, there is a (contact) voltage potential developed between the metals (the Volta effect). Physicists explain this phenomenon through the difference between their work functions. In our bench tests of our auto-zeroed op amps, we saw voltage potentials of ±1 µV to ±2 µV due to the IC socket. The solution is very simple; do not use sockets for critical components. Instead, solder all critical components to the PCB. MCP1541 4.1V Reference USB PIC18F2250 (USB) Microcontroller I2C™ Port SDA, SCLK, ALERT 3 CVREF (cold junction compensation) VOUT2 ×1 nd 2 Order, Low-pass Filter VSHIFT MCP9800 Temp. Sensor VREF 10-bit ADC Module VOUT1 TCJ Type K Thermocouple (welded bead) MCP6V01 Difference Amp. VP VM TTC Connector (cold junction) FIGURE 37: Block Diagram. Thermocouple Circuit’s The (type K) thermocouple senses temperature at its hot junction (TTC) and produces a voltage at the cold junction (at temperature TCJ). The conversion constant for type K thermocouples is roughly 40 µV/°C. This voltage (VP – VM) is input to the Difference Amplifier (MCP6V01). The MCP9800 senses temperature at the Type K Thermocouple’s cold junction (TCJ). The result is sent to the PICmicro microcontroller via an I2C™ bus. The firmware corrects the measured temperature for TCJ. The difference amplifier uses the MCP6V01 auto-zeroed op amp to amplify the thermocouple’s output voltage. The VREF input shifts the output voltage down so that the temperature range includes -100°C. The VSHIFT input shifts the output voltage, using a DS01258B-page 16 2009-2012 Microchip Technology Inc. AN1258 digital POT internal to the microcontroller (CVREF), so that the temperature range is segmented into 16 smaller ranges; this gives a greater range (-100°C to +1000°C) with reasonable accuracy. The MCP1541 provides an absolute reference voltage because the thermocouple’s voltage depends only on temperature (not on VDD). It sets the nominal VOUT and serves as the reference for the ADC internal to the microcontroller. 1. 2. 3. nd The 2 Order, Low-pass Filter reduces noise and aliasing at the ADC input. A double R-C filter was chosen to minimize DC errors and complexity. CVREF is a digital POT with low accuracy and highly variable output resistance. The buffer (×1 amplifier) eliminates the output impedance problem, producing the voltage VSHIFT. Since CVREF has 16 levels, we can shift VOUT1 by 16 different amounts, creating 16 smaller ranges; this adds 4 bits resolution to the measured results (the most significant bits). The 10 bits produced by the ADC are the least significant bits; they describe the measured values within one of the 16 different smaller ranges. VSHIFT is brought back into the PICmicro microcontroller so that it can be sampled by the ADC. This gives VSHIFT values the same accuracy as the ADC (“10 bits”), which is significantly better than CVREF’s accuracy. The measured value of VOUT2 is adjusted by this measured VSHIFT value. The Difference Amplifier is as close to the sensor as possible, and is on the opposite PCB surface from the PICmicro microcontroller. This minimizes electrical and thermal crosstalk between the two active devices. Small resistors (0805 SMD) reduce the thermoelectric voltages, for a given temperature gradient. The resistors that are a part of the Difference Amplifier play a critical role in this design’s accuracy. a) R6 and R7 are at the input from the thermocouple, and give a gain of 1000 V/V to VOUT1. They are arranged so that their thermoelectric voltages cancel. b) R9 and R10 are at the input from the range selection circuitry (VSHIFT), and give a gain of 17.9 V/V to VOUT1. Changing their location and orientation on the PCB might improve the performance. c) R8 and R11 convert the inputs to the output voltage (VOUT1). Changing their location and orientation may not improve the performance enough to be worth the trouble. Figure 39 shows the top metal layer of the PCB. The sensitive analog and sensor circuitry is connected to this layer. The overall accuracy of this mixed signal solution is set by the 10-bit ADC. The resolution is 14 bits, but the accuracy cannot be better than the ADC, since it calibrates the measurements. 4 6 PCB Layout 5 In the figures in this section (Figure 38 through Figure 43), the red numbers (inside the circles) point to key design choices, which are described by a list after each figure. Figure 38 shows the top silk screen layer of the PCB designed for the MCP6V01 Thermocouple Auto-Zeroed Reference Design. 7 6 4 FIGURE 39: 4. 5. 3 2 6. 1 7. FIGURE 38: 1st Layer – Top Silk. 2009-2012 Microchip Technology Inc. 1st Layer – Top Metal. Metal fill, connected to the ground plane, minimizes thermal gradients at the cold junction connector. The MCP9800 Temperature Sensor (cold junction compensation) is centered at the cold junction connector to give the most accurate reading possible. Sensor traces are separated from power (top layer) and digital (bottom layer) traces to reduce crosstalk. The MCP9800’s power traces are kept short, straight and above ground plane for minimal crosstalk. DS01258B-page 17 AN1258 Figure 40 shows the power plane. It minimizes noise conducted through the power supplies and isolates the analog and digital signals. 8 10 9 14. This ground plane extension provides better isolation between digital signals and the MCP9800’s power supply. It also helps protect the thermocouple signal lines. However, it increases the thermal conduction between the left and right sides of the PCB. Figure 42 shows the bottom silk layer. 15 16 17 FIGURE 40: 2nd Layer – Power Plane. 8. The power plane on the left helps keep the temperature relatively constant near the auto-zeroed op amp. It also provides isolation from the microcontroller’s electrical and thermal outputs. 9. The power plane on the right helps keep the temperature relatively constant near the thermocouple’s cold junction and MCP9800 cold junction temperature sensor. 10. The FR4 gap provides attenuation to heat flow (a relatively high temperature drop) between the active components on the left (MCP6V01 and PIC18F2550) and the sensors on the right (thermocouple and MCP9800). Figure 41 shows the ground plane. It also minimizes noise conducted through the power supplies and isolates the analog and digital signals. FIGURE 42: 4th Layer – Bottom Silk. 15. The USB connector and its components are isolated from the rest of the circuit. 16. The crystal (XTAL) oscillator is as far from everything else as possible, except from the clock input pins of the microcontroller. 17. The microcontroller produces both thermal and electrical crosstalk, so it is isolated from the analog components. Figure 43 shows the bottom metal layer of the PCB. The digital circuitry is connected to this layer. 18 11 13 12 19 14 FIGURE 43: FIGURE 41: 3rd Layer – Ground Plane. 11. Same function as #8. 12. Same function as #9. 13. Same function as #10. DS01258B-page 18 4th Layer – Bottom Metal. 18. Metal fill, connected to the ground plane, minimizes thermal gradients at the cold junction. 19. The digital traces that run under the ground plane extension have series resistors inserted inside the FR4 gap. This reduces the thermal conduction between the sides that solid traces would produce; otherwise this would become the worst case thermal conductor between the microcontroller and the temperature sensors. 2009-2012 Microchip Technology Inc. AN1258 SUMMARY This application note covers thermal effects on Printed Circuit Boards (PCB) encountered in high (DC) precision op amp circuits. Causes, effects and fixes have been covered. Thermocouple junctions are everywhere on a PCB. The Seebeck effect tells us that these junctions create a thermoelectric voltage. This was shown to produce a voltage across resistors (and other components) in the presence of a temperature gradient. Preventing large thermoelectric voltages from occurring is usually the most efficient way to deal with thermocouple junctions. The amount of heat generated on the PCB can be reduced, and the heat flow redirected away from critical circuit areas. It also pays to keep any temperature changes from occurring too quickly. Any remaining thermoelectric voltage effects need to be reduced. Choosing the metals, in critical areas, to have approximately the same work function will minimize the thermoelectric coefficients of the metal junctions. Critical components can be oriented so that they follow constant temperature contour lines. It is possible to cancel most of the thermoelectric voltage effects at the input of op amps by correctly orienting them. Smaller components, spaced closer together, will also help. Once a design has been implemented on a PCB, it pays to measure its thermal response. Information on where to focus design effort can greatly speed up the design process. Information has been given on measuring temperature, thermal gradients, package JA‘s and troubleshooting tips and tricks. REFERENCES Related Application Notes  AN990, “Analog Sensor Conditioning Circuits – An Overview,” Kumen Blake; Microchip Technology Inc., DS00990, 2005.  AN1177, “Op Amp Precision Design: DC Errors,” Kumen Blake; Microchip Technology Inc., DS01177, 2008.  AN1228, “Op Amp Precision Design: Random Noise,” Kumen Blake; Microchip Technology Inc., DS01228, 2008. Other Application Notes  AN990, “Analog Sensor Conditioning Circuits – An Overview,” Kumen Blake; Microchip Technology Inc., 2005.  AN684, “Single Supply Temperature Sensing with Thermocouples,” Bonnie C. Baker; Microchip Technology Inc., DS00684, 1998.  AN679, “Temperature Sensing Technologies,” Bonnie Baker,” Microchip Technology Inc., DS00679, 1998. Other References  User’s Guide, “MCP6V01 Thermocouple Auto-Zeroed Reference Design,” Microchip Technology Inc., DS51738, 2008.  “The OMEGA® Made in the USA Handbook™,” Vol. 1, OMEGA Engineering, Inc., 2002. Leakage current effects also need to be minimized. Methods to accomplish this for surface and bulk leakage currents have been shown. Other effects were also discussed. A design example using the MCP6V01 Thermocouple Auto-zeroed Reference Design PCB illustrates the theory and recommendations given in this application note. The circuit operation is described, then the PCB layout choices are covered in detail. At the end of this application note, references to the literature and an appendix with the design example’s schematic are provided. 2009-2012 Microchip Technology Inc. DS01258B-page 19 FIGURE A-1: DS01258B-page 20 ALERT 1.0K R16 1 VDD SDA 5 2 VSS 3ALERT SCLK4 U3 R14 1.0K THERMO_CONN J1 CVREF R15 MCP9800_SOT23-5 1.0K C11 0.1UF VDD U4 VIN– VDD 4 MCP6001_SOT23-5 2 VSS 3 VIN+ 1 VOUT SCL SDA VSHIFT VDD R7 100 R6 100 VSHIFT R9 5.6K C14 0.1UF R10 5.6K VIN VOUT VSS 2 1 MCP1541 3 U2 NC NC 8 7 VDD 6 VOUT 5 U5 R11 100K VREF C9 22pF VREF CVREF VSHIFT VOUT1 VDD C8 0.47uF C10 22pF Y1 20 MHz C5 1uF MCP6V01_SOIC VSS 1 NC 2 VIN– 3 VIN+ 4 R8 100K C12 0.1uF VDD VREF VOUT RA0/AN0 MCLR/VPP/RE3 RA5/AN4/SS/HLVDIN/C2 RA4/TOCKI/C1OUT/RCV RA3/AN3/VREF+ R3 1 OHM C3 10uF TP1 RB7/KBI3/PGD RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC SDA TP3 TP4 RC4/D–/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT/SDO TP5 ALERT R4 100K 21 22 23 24 25 26 27 28 C1 0.1UF USB CONN 7 11 8 6 SDA 10 J3 1 2 3 4 5 VDD ALERT R2 10K SCL VDD R5 10K VDD R1 10K VDD N/C 9 15 16 17 18 VDD 20 VSS 19 RB0/AN12/SDI/SDA RB1/AN10/SCK/SCL RB2/AN8/INT2/VMO RB3/AN9/CCP2/VPO C4 10uF SCL VOUT VOUT2 L1 10uH TP2 C7 0.1uF R13 499 R12 499 C6 0.1uF VDD U1 PIC18F2550–SOIC28 2nd Order RC Low-Pass Filter C2 1uF VUSB RC2/CCP1 RC1/T1OSI/CCP2/UOE RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSCI/CLKI VDD C13 0.1UF 14 13 12 11 10 9 8 VSS 7 6 5 RA1/AN1 4 RA2/AN2/VREF–/CVREF 3 2 1 VDD J2 APPENDIX A: N/C HDR1X6 AN1258 PCB SCHEMATIC (MCP6V01 THERMOCOUPLE AUTO-ZEROED REFERENCE DESIGN) THERMOCOUPLE CIRCUIT’S SCHEMATIC. 2009-2012 Microchip Technology Inc. AN1258 APPENDIX B: PCB PARASITIC RESISTANCE The body of this application note emphasized better PCB designs. For this reason, detailed analyses of leakage currents were not included. This appendix shows you how to estimate parasitic resistances on a PCB. This will help adjust designs sensitive to leakage currents. Example B-2 shows two parallel planes on opposite PCB surfaces. This geometry is useful for measuring ρV on a given PCB process. Make the planes as large as possible, to maximize the bulk leakage current. For instance, a 6 in × 6 in PCB (60 mil thick) could have two planes 5 in long and 5 in wide. With ρS = 1 × 105 MΩ and ρV = 1 × 106 MΩ cm, we can estimate RPS ≈ ∞ and RPB ≈ 0.9 GΩ. EXAMPLE B-2: B.1 PCB Resistivities PARALLEL PLANES Top View Surface resistivity (ρS, in units of MΩ, or equivalent) describes the local, physical behavior of a PCB surface under a voltage gradient field. The aggregate behavior over all such points creates an equivalent, parasitic surface resistance (RPS) between any two points. Bulk resistivity (ρV, in units of MΩ cm, or equivalent) describes the local, physical behavior inside a PCB’s dielectric under a voltage gradient field. The aggregate behavior over all such points creates an equivalent, parasitic bulk resistance (RPB) between any two points. Typical resistivities for FR4, based on several manufacturer’s data, are: • ρS ≈ 1 × 105 MΩ • ρV ≈ 1 × 106 MΩ cm Different operating conditions and manufacturing flows will produce different values; sometimes by two or three orders of magnitude in either direction. B.2 Measuring Resistivities Example B-1 shows two parallel, serpentine traces on the same PCB surface. This geometry is useful for measuring ρS on a given PCB process. Make the traces as long as possible, and as close together as possible, to maximize the surface leakage current. For example, a 6 in × 6 in PCB (60 mil thick) could have two serpentine traces 10 mil wide and 10 mil apart. If the overlap area is 5 in × 5 in, the equivalent length would be 1250 in. With ρS = 1 × 105 MΩ and ρV ≈ 1 × 106 MΩ cm, we estimate RPS ≈ 0.8 MΩ and RPB ≈ 2 GΩ. EXAMPLE B-1: PARALLEL TRACES Top View End View Side View Be sure to measure ρS and ρV under various conditions seen by your circuit. These values will also change between different manufacturers and processes. B.3 B.3.1 Numerical Solutions COMMERCIAL SOFTWARE When optimizing a complicated PCB geometry, it may pay to use a PDE (partial differential equation) solver. Searching the internet for “partial differential equation software,” or the equivalent, should bring up several commercially available software packages. B.3.2 USING SPICE It is possible to use SPICE to implement a network of resistors representing heat flow between adjacent points. Select an array of equally spaced points. Resistors connect adjacent points and represent the local resistance to current flow, in that direction. To simulate a particular parasitic resistance, force a voltage at its input and measure the current at its output. The voltage-to-current ratio is that resistance. Figure B-1 shows a typical array point, in a two dimensional (2D) array. The central point is at voltage V0. The four adjacent points are connected by the four resistors R1, R2, R3 and R4. 2009-2012 Microchip Technology Inc. DS01258B-page 21 AN1258 V2 R2 V0 V3 R3 R1 V1 R4 V4 FIGURE B-1: TYPICAL 2D ARRAY. The resistors represent the local resistivity between adjacent points. Use very low valued resistors for points connected by metal. For instance, R1 is: EQUATION B-1: R1 = ρS ∆x / ∆y, for surface calculations = ρV ∆x / (∆y ∆z), for bulk calculations Where: ρS = Local Surface Resistivity (MΩ) ρV = Local Bulk Resistivity (MΩ cm) ∆x = grid spacing in the x-direction ∆y = grid spacing in the y-direction ∆z = z-dimension (common to all objects) This approach is easily extended to three dimensions (3D). B.3.3 USING A SPREADSHEET It is possible to simulate in a spreadsheet by using an iterative approach. Set up the resistive array like the last section. The iteration equation at V0 is: EQUATION B-2: V0 = (V1/R1 + V2/R2 + V3/R3 + V4/R4) / (1/R1 + 1/R2 + 1/R3 + 1/R4) = (V1 + V2 + V3 + V4) / 4, all Rs equal The convergence can be slow, so this approach should be used for simple problems. Once the voltages are determined, it is a simple matter to calculate the sum of currents into (or out of) a node of interest. This approach is easily extended to three dimensions (3D). DS01258B-page 22 2009-2012 Microchip Technology Inc. AN1258 APPENDIX C: REVISION HISTORY Revision B (July 2012) The following is the list of modifications: 1. 2. 3. 4. 5. 6. Added power supply components to circuit diagrams. Re-wrote Section “Leakage Currents”, starting on page 11. a) Added information on high impedance sources and parasitic leakage resistances. b) Corrected guard ring connections so they are driven by a low impedance source. c) Added current source examples. d) Added discussion of bulk leakage currents. e) Expanded discussion on isolating sensitive connections from a PCB. Added Section “Other Tips”, on page 16. Added AN990 to Section “References”, on page 19. Added Appendix B: “PCB Parasitic Resistance”, starting on page 21. Added Appendix C: “Revision History”, on page 23. Revision A (March 2009) • Original Release of this Document. 2009-2012 Microchip Technology Inc. DS01258B-page 23 AN1258 NOTES: DS01258B-page 24 2009-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-404-6 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2009-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS01258B-page 25 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS01258B-page 26 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 11/29/11 2009-2012 Microchip Technology Inc.