AN1859

AN1859
PCB Layout Guide for MEC140x/MEC141x
Author:
Tom Tse
Microchip Technology Inc.
INTRODUCTION
This application note provides information on design considerations for a printed circuit board (PCB) for the Microchip
MEC140x / MEC141x family devices including the following:
- MEC1404, MEC1406, MEC1408
- MEC1414, MEC1416, MEC1418
The design of the PCB requires care to provide good supply and ground paths; in addition, other design issues are
addressed in this document.
The functional blocks in the MEC140x / MEC141x have different requirements for routing and external connections,
which are also outlined in this application note.
Please see References for device-level information such as VCC1 power planes, and mechanical package information
for the 128-Pin VTQFP and 144-Pin WFBGA.
This document includes the following topics:
•
•
•
•
•
Section 1.0, "General Layout Considerations," on page 2
Section 2.0, "Miscellaneous Considerations," on page 8
Section 3.0, "2-Wire Debug Interface (ICSP)," on page 16
Section 4.0, "Programmable Comparators," on page 18
Section 5.0, "How to setup ADC voltage states to distinguish PC model and pcb types," on page 21
Audience
This document is written for a reader that is familiar with hardware design. The goal of this application note is to provide
information about sensitive areas of the MEC140x / MEC141x PCB layout.
References
The following documents should be referenced when using this application note. Please contact your Microchip representative for availability.
•
•
•
•
•
Microchip MEC140x / MEC141x Data Sheet / eSPI Addendum
Microchip MEC140x / MEC141x EVBs, TBD
Microchip MPLAB ICD3 In-Circuity Debugger User’s Guide (Doc#: DS51766B)
PCI Local Bus Specification (see www.pcisig.com)
I2C-bus specification and user manual, Rev. 6 - 4 April, 2014 or later (see www.nxp.com/documents/user_manual/
UM10204.pdf)
• Intel, Enhanced Serial Peripheral Interface (eSPI) Specification (for Client Platform)
• Microchip “eSPI Controller” Specification, DS00000A
Package Information
The MEC140x / MEC141x device is currently available in the following package:
• MEC140x / MEC141x for 128-pin, VTQFP
• MEC140x / MEC141x for 144-pin, WFBGA
 2014 - 2015 Microchip Technology Inc.
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1.0
GENERAL LAYOUT CONSIDERATIONS
This section describes layout considerations for the MEC140x / MEC141x device. This includes the following topics:
•
•
•
•
Section 1.1, "Decoupling Capacitors," on page 2
Section 1.2, "32.768kHz Crystal Oscillator," on page 4
Section 1.3, "CAP Pins, AVSS/GND Connection," on page 6
Section 1.4, "BGA Package PCB Layout Considerations," on page 6
1.1
Decoupling Capacitors
This section includes the following topics:
• Section 1.1.1, "MEC140x / MEC141x VTQFP Capacitors," on page 2
• Section 1.1.2, "MEC140x / MEC141x WFBGA Capacitors," on page 3
Decoupling capacitors should be placed as close to the chip as possible to keep series inductance low. When the capacitors are mounted on the bottom side of the PCB, the capacitors are connected to the ground plane from the bottom
layer directly using the shortest path to the device. Each VCC pin should have a 0.1 μF capacitor located as close to
the pin as possible. Bypass capacitors should be placed close to the supply pins of the MEC140x / MEC141x with short
and wide traces.
The MEC140x / MEC141x has an integrated voltage regulator to supply the core circuitry. Decoupling this regulator
requires a critical capacitor of 1μF on the CAP pin. ESR of this 1μF capacitor, including the routing resistance, must be
less than 100 mOhm.
Capacitors may carry large currents that generate magnetic fields, inducing noise on nearby traces. Sensitive traces
such as the 32kHz crystal should be separated by at least five times the trace width from decoupling capacitors when
possible.
Connecting decoupling caps to power and ground planes using two vias per pad will reduce series inductance.
• FIGURE 1-1: on page 3 shows decoupling for the MEC140x / MEC141x 128-pin VTQFP.
• FIGURE 1-2: on page 4 shows decoupling for the MEC140x / MEC141x 144-pin WFBGA.
The VCC pin decoupling capacitors can use any typical 16V 10% Ceramic. See also the MEC140x / MEC141x EVB
Schematics and Bill of Materials.
1.1.1
MEC140X / MEC141X VTQFP CAPACITORS
• Figure 1-1 shows decoupling for the MEC140x / MEC141x 128-pin VTQFP package.
Note:
The capacitors can use any typical 16V 10% ceramic.
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MEC140X / MEC141X DECOUPLING IN 128-PIN VTQFP PACKAGE
2 Vias to VCC1
C2
VTR[5]
XTAL2[125]
VSS_VBAT1[124]
XTAL1[123]
VBAT[122]
C1
C10
C8
VTR[103]
C12
C13
ADC_VREF[115]
Y1
FIGURE 1-1:
2 Vias to GND
C7
1uF
Low
ESR
C3
VR_CAP[18]
VTR[19]
C9
DAC_VREF[22]
MEC140x
VTR [43]
C61
VTR[82]
VTR_33_18 [54]
C11
C4
C6
VTR[65]
C5
Note: (For Part Numbers see MEC140x EVB Schematic)
C1= 0.1uF on VBAT
C2 – C8 = 0.1uF on VTR
C9 = 0.1uF on DAC_VREF
C10 = 0.1uF on ADC_VREF
C11 = 1uF Low ESR +/-20% <100 mOhm on CAP (X5R or X7R)
Y1 = 9pF load crystal, C12 & C13 are 10pF
C61 = 10uF on VTR- place between MEC140x and VTR source
1.1.2
MEC140X / MEC141X WFBGA CAPACITORS
• Figure 1-2 shows decoupling for the MEC140x / MEC141x 144-pin WFBGA package.
Note:
The capacitors can use any typical 16V 10% ceramic.
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FIGURE 1-2:
1.2
MEC140X / MEC141X DECOUPLING IN 144-PIN WFBGA PACKAGE
32.768kHz Crystal Oscillator
This section describes specific layout and design considerations for the 32.768kHz crystal oscillator; this can be used
to source the internal 32kHz clock domain, in lieu of the silicon oscillator or an external pin. The crystal implementation
is required to support the RTC function within the MEC140x / MEC141x.
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1.2.1
32.768KHZ CRYSTAL OSCILLATOR LAYOUT
The MEC140x / MEC141x 32kHz crystal oscillator is designed to generate an synchronous on-chip clock signal with an
appropriate external oscillator crystal. The design has been optimized for low power (1.5 μW typical), stability and minimum jitter using a general purpose parallel resonant 32kHz crystal. For a suggested part number, please see the
MEC140x / MEC141x EVB schematic (see References).
This unique low power crystal oscillator drive circuit means that a standard inverter crystal layout should not be used.
The design has been characterized to allow a variation of 4pF to 18pF on each pin. Based on the following load capacitance calculation, Microchip recommends 10pf load capacitors with a crystal that has a 9pf Cl rating. Other than these
capacitors, no additional external components are required for normal operation of the clock circuit.
Where:
•
•
•
•
•
C12 is the cap from pin XTAL1 to ground.
C13 is the cap from pin XTAL2 to ground.
Cpin_xtal2 is the pin capacitance of pin XTAL2. This is estimated to be 5pf (Note 1-1).
Cpin_xtal1 is the pin capacitance of pin XTAL1. This is estimated to be 3pf (Note 1-1).
Cbrd is estimated at 1.5pF.
Note 1-1
1.2.2
At the time of publication, the MEC140x / MEC141x silicon has not been characterized. Please check
with your Microchip FAE for final pin capacitance values after silicon validation is complete. Any
variation from the estimates provided here could change the crystal Cl value requirement.
CRYSTAL ACCURACY
The accuracy of the 32kHz input translates directly into accuracy of the internal clock and the functions in the MEC140x
/ MEC141x using the 32kHz: 32KHZ_OUT, week timer, hibernation timers, and so forth.
The accuracy, with regard to actual error in time can be illustrated as such: +/-1ppm of error in frequency corresponds
to 32.768 kHz x 1ppm x 10-6 = +/-0.032768 Hz. This translates into ~1 µsec/sec or ~+/-0.086 sec/day.
Based on customer RTC accuracy timer requirements, Microchip recommends using a +/-20ppm crystal. This would
equal approximately +/-2 sec/day, other factors discounted.
For arguments sake, it is safe to say that stray capacitance is difficult to calculate exactly. So, as an exercise in completeness, this calculation describes the effect of each picofarad of additional capacitance over/under the crystal Cload
value:
where C0 is the shunt capacitance, C1 is the motional capacitance and CL is the load capacitance of the chosen crystal
(these numbers can be found in the crystal data sheet). For example, using a crystal with C0 = 0.8pF, C1 = 0.0019pF,
CL = 12.5pF, we get a shift of 5.37ppm/pF. So, in terms of time, each pF of added/subtracted capacitance is approximately 5.37 x 0.086 = +/-462 msec/day for this particular crystal.
This example is meant to illustrate the magnitude of the potential error. In practice, slight capacitance mismatch does
not equate to many seconds a day.
1.2.3
SINGLE ENDED CLOCKING
An external clock source (maximum voltage of 3.3V) may be applied to the XTAL2 pin if the XOSEL bit in Clock Enable
Register configures as a single-ended 32.768 kHz clock input (SUSCLK). The XTAL1 pin should be left floating. If an
external clock source is used, the designer must ensure that the source is available in all desired power states in which
the EC will be active.
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1.3
CAP Pins, AVSS/GND Connection
The recommended filtering for the CAP pin on the MEC140x / MEC141x is shown in Figure 1-3, for VTQFP connections.
The filtering components shown should be placed close to the device and away from noise sources.
FIGURE 1-3:
1.4
VTQFP CAP PIN REFERENCE AND AVSS DIRECTLY CONNECTED TO GND
BGA Package PCB Layout Considerations
The MEC140x / MEC141x devices have BGA lead-free RoHS-Compliant package as follows:
• 144-pin WFBGA: 9mm x 9mm, 0.65mm ball pitch (see Figure 1-4)
Note:
Please refer to the latest data sheet for most up-to-date PCB LAND pattern information.
The following list summarizes BGA routing guidelines, but it is understood that final layout is process- dependent and
your design should reflect your needs:
• Through-hole vias technology is not recommended for pitches less than 0.8mm (unless the ball matrix is depopulated in the center)
• NSMD ball pads for pitches 0.8mm – 0.4mm
• Solder Mask to be 1:1 scale of the land size, when routing 0.5mm pitch ball pads
• μVias – next generation PCB technology for tighter pitches
• Eliminate through-hole vias
• Increase routing density & enhance electrical performance
• Decrease routing layers
• Provide fan-out solutions for multiple layers (stacked Vias)
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FIGURE 1-4:
LAND PATTERN DIMENSIONS, 144-WFBGA, 0.65MM BALL PITCH
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2.0
MISCELLANEOUS CONSIDERATIONS
This section covers a variety of layout topics:
•
•
•
•
•
•
•
•
•
•
Section 2.1, "Battery Circuit," on page 8
Section 2.2, "LPC Interface," on page 8
Section 2.3, "eSPI Interface," on page 9
Section 2.4, "PS/2 Interface," on page 9
Section 2.5, "EOS Considerations," on page 10
Section 2.6, "ADC Input Layout Requirements," on page 10
Section 2.7, "SPI Flash Interface," on page 11
Section 2.8, "1MHz Pullup Resistor Requirement," on page 15
Section 2.9, "5V Tolerant Pins," on page 15
Section 2.10, "1.8V Capability," on page 15
2.1
Battery Circuit
Please see the Power Sources section of the MEC140x / MEC141x PCS.
For the battery circuity requirement, VCC0 must always be present if VCC1 is present. The following circuit is recommended to fulfill this requirement.
FIGURE 2-1:
2.2
RECOMMENDED BATTERY CIRCUIT
LPC Interface
The firmware must configure the GPIO Pin Control Registers for the LPC alternate function, configure the LPC Base
Address Register, and activate the LPC block.
2.2.1
VTR_33_18 POWER PIN
The LPC Interface Signals require the VTR_33_18 power pin to be connected to the 3.3V VTR rail. Please also configure the VTR_LPC_ESPI_SEL18 bit 3 at Power Regions Voltage Control Register (0xFC48) accordingly.
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2.2.2
HOST RESET SELECT
The platform reset signal that will be used to assert nSIO_RSET is determined by the POWER RESET CONTROL Register (80148h) Bit 1 = 0 - LRESET# pin.
2.2.3
LAD[3:0] /LFRAME#/ LDRQ#/SERIRQ
The AC and DC specifications for these signals are set the same as defined for AD[31:0] in Section 4.2.2 of the “PCI
Local Bus Specification, Rev 2.1”. That section contains the specifications for the 3.3V signaling environment. LAD[3:0]
must go high during the TAR phase. The last device driving the LAD[3:0] is responsible to drive the signals high during
the first clock of the TAR phase. During the 2nd clock, LAD[3:0] is floated and maintained high by weak pullup resistors
(approximately 100 k Ω). These pullups are not included in the MEC140x / MEC141x, but may be included in the chipset.
2.2.4
OTHER SIGNALS
All the other LPC I/F signals are connected to other PCI signals that are already present in the system. The MEC140x
/ MEC141x use 3.3V signaling for all LPC signals, including the PCI Reset and Clock, therefore the system must drive
these signals at 3.3V signaling levels.
2.3
eSPI Interface
The firmware must configure the GPIO Pin Control Registers for the eSPI alternate function, configure the eSPI I/O
Component Base Address Register, and activate the eSPI block.
2.3.1
VTR_33_18 POWER PIN
The eSPI Interface signals require the VTR_33_18 power pin to be connected to the 1.8V rail. Please also configure
the VTR_LPC_ESPI_SEL18 bit 3 at Power Regions Voltage Control Register (0xFC48) accordingly.
2.3.2
HOST RESET SELECT
The platform reset signal that will be used to assert nSIO_RSET is determined by the POWER RESET CONTROL Register (80148h) Bit 1 = 1 - eSPI_PLTRST# pin.
2.3.3
OTHER SIGNALS
All the eSPI I/F signals are connected to other eSPI signals that are already present in the system. The MEC140x /
MEC141x use 1.8V signaling for all eSPI signals. Please refer to the Intel Skylake Ultrabook Platform U-Series RVP
Customer Reference Board Schematic, Microchip MEC140x / MEC141x Evaluation Board Schematic, and reworks
instruction for detailed information.
Few design notes as below:
• LPC_AD0_ESPI_IO0, LPC_AD1_ESPI_IO1, LPC_AD2_ESPI_IO2, LPC_AD3_ESPI_IO3, LPC_FRAME_ESPI_CS#, and LPC_CLK_0_ESPI_CLK signals have 15 ohm series resistor close to each chipset pin
and another 15 ohm series resistor close to the MEC141x for eSPI mode.
• GPP_C5/SML0ALERT# (Intel Skylake chipset pin W1) is used as strapping pin to determine either LPC mode
(Low) or eSPI mode (High).
2.4
PS/2 Interface
The routing of the PS/2 interface is also not critical, except that it should not be routed next to rapidly switching signals.
The Clock and Data pins are Open Drain and require pullup resistors. A small 10 - 100pF (typ) capacitor to ground and
4.7kΩ (typ) pullups are recommended. The power pin of the PS/2 pin should be decoupled with a capacitor that is large
enough to adequately filter the supply to PS/2 devices. Unused PS/2 clock and data pins should be pulled up to VCC
with a 10kΩ (typ) resistor.
Note:
The PS/2 Interface is not 5V tolerant.
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2.5
EOS Considerations
For SMBus signals that terminate external to the main system board (for example, Smart Battery) the designer should
take care in protecting these signals from EOS (Note 2-1) and ESD (Note 2-2). Please refer to the SMBus 2.0 specification, section 3.1.2.2 for appropriate guidelines. The specification recommends a series protection resistor and an
optional ESD transorb on these nets. In addition to the SMBus specification recommendation, past experience shows
that using 2 high speed diodes on each SMBus trace (instead of the transorb in the SMBus spec) is an effective way to
improve immunity to EOS and ESD events. A Schottky diode pair is a good example. Figure 2-2 shows the suggested
circuit implementation for each net that goes to a connector.
.
FIGURE 2-2:
SCHOTTKY DIODE PAIR EXAMPLE
It should also be noted that any other signal that goes to an external connector should also be considered for EOS/ESD
susceptibility. For instance, an ID pin (tied to a GPIO) that might seem benign, but is routed near high voltage sources
could suffer transient EOS events. A similar protection scheme should be considered for these nets.
Note 2-1
EOS is defined as damage to the part caused by the application of voltages (to any pin) beyond the
power supply rails, usually forward biasing internal protection diodes and resulting in high levels of
current flow. This typically induces open failures by damaging the metal inside the part. EOS is
typically a low voltage, high current situation.
Note 2-2
ESD is the applied reverse bias to the PN junction -- heat due to power dissipation melts the silicon
in the part. ESD is typically a high transient voltage spike with low current situation.
2.6
ADC Input Layout Requirements
• It is suggested that the Analog-Digital Converter (ADC) Source AVSS reference connects to the MEC140x /
MEC141x AVSS via a low noise AVSS island, which is shown in Figure 1-3.
• It is suggested that a low pass filter, see Figure 2-3, be used on each ADC input of MEC140x / MEC141x. Filter
components below are a good starting point, the R should has value between 100 ohm to 1.1 kohm and the C
should has value between 100pF to 2500pF. The RC values are based on high frequency cut off desired for the
application, F = 1 / ( 2π * RC ).
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.
FIGURE 2-3:
ADC INPUT LOW PASS FILTER
Source
Analog
Voltage
R = 100 ohmto 1.1 kohm
ADC_IN
C = 100 pF to 2500 pF
AVSS
It is recommended that the ADC nets are spaced at least 20 mils from any high speed switching signals to prevent cross
talk that could add noise.
2.7
SPI Flash Interface
The MEC140x / MEC141x SPI flash interface enables the host and embedded controller (EC) access to an external SPI
flash device. The MEC140x / MEC141x PCS documentation has more details on signal implementation (see References on page 1). This section describes specific PCB layout design considerations to setup this feature.
Note:
The SPI Flash Interface of MEC140x / MEC141x supports 3.3V ONLY. Any lower voltage SPI flashes are
not supported and should not be used with the MEC140x / MEC141x.
The standard set of SPI flash signals are designated with “SHD_” for shared connections, for example, SHD_SCLK; for
details, see Section 2.7.3, "Shared SPI Flash Interface". MEC140x / MEC141x has an added set of signals for connection to another SPI flash device as private, protected data; these signals are designated with “PVT_,” for example,
PVT_SCLK; for details, see Section 2.7.4, "Private SPI Flash Interface". The Private SPI can be used as a crisis recovery interface as it shares pins with the keyboard interface. MEC140x / MEC141x has a third SPI interface as a general
SPI interface labeled as “SPI_,” for example, SPI_CLK.
TABLE 2-1:
SPI INTERFACE SIGNALS
Generic Pin Signal
Name
SPICLK
IO0
IO1
IO2
MEC140x /
MEC141x Pin
Number
Pin Signal
Function name
SHD_SCLK
Pin Function Signal Description
32
Shared SPI Clock
PVT_SCLK
15
Private SPI Clock
SHD_IO0
28
Shared SPI Data I/O 0
PVT_IO0
16
Private SPI Data I/O 0
SHD_IO1
29
Shared SPI Data I/O 1
PVT_IO1
2
Private SPI Data I/O 1
SHD_IO2
30
Shared SPI Data I/O 2
PVT_IO2
50
Private SPI Data I/O 2
IO3
SHD_IO3
31
Shared SPI Data I/O 3
PVT_IO3
46
Private SPI Data I/O 3
SPI_CS#
SHD_CS#
27
Shared SPI Chip Select
PVT_CS#
14
Private SPI Chip Select
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2.7.1
BOOT ROM STRAP OPTION
The Boot ROM will only load code from either the shared flash interface or the private SPI interface.
The Boot ROM will sample the CR_STRAP pin 68; no hardware is required.
.
2.7.2
CR_STRAP
Source
1
Use 3.3V Shared SPI
0
Use 3.3V Private SPI
PRIVATE VS. SHARED SPI_CS# IMPLEMENTATION
Section 2.7.3, "Shared SPI Flash Interface" describes implementing the SPI Flash Interface using the shared signals
(for example, SHD_SCLK); Section 2.7.4, "Private SPI Flash Interface" describes implementing the SPI Flash Interface
using private signals (for example, PVT_SCLK).
See Section 2.7.4, "Private SPI Flash Interface," on page 13 for further details of this setup. Only the Private SPI Flash
Interface supports Crisis recovery.
2.7.3
2.7.3.1
SHARED SPI FLASH INTERFACE
Shared SPI Flash Implementation
Figure 2-4 is a topology for implementing a single MEC140x / MEC141x SPI flash for shared SPI flash devices. See
Table 2-2 for specifications on PCB trace recommendations represented by “L1,” “L2,” and so forth.
FIGURE 2-4:
MEC140X / MEC141X TOPOLOGY FOR SHARED SPI FLASH DEVICE
H o s t In te rfa c e (In te l® P C H )
R2
R2
R2
R2
L1
L2
L0 L0 L0
SPI_SIO0
S H D _ S IO 1 L 0
S H D _ S IO 2 L 0
S H D _ S IO 3 L 0
SHD _SC LK L0
L1
L1
L1
L1
SPI_SIO1
R2
SPI_SIO2
L0
SPI_SIO3
R1
RSM RST#
S H D _ S IO 0
SPI_SCLK
SPI_CS0
RSMRST#
L0
M EC 1404
L0
SPI
F la s h
R1 R1 R1 R1
L2 L2
L2
L2
L3
L3
L3
L3
R3
L0
R3
R3
R3
L0
L0
L0
L3
R3
S IO 0
S IO 1
S IO 2
S IO 3
L0
CLK
+ 3 .3 V
+ 3 .3 V
R4
SH D _C S#
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L4
CS
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TABLE 2-2:
MEC140X / MEC141X SHARED SPI FLASH DEVICE SPECIFICATIONS
Description
Spec
L0
Connection between MEC140x / MEC141x, Host/PCH, or SPI flash 0.1-inch to 0.5-inch
device and termination resistors.
L1
PCB trace from the MEC140x / MEC141x termination resistor to the L1 = L2 = L3
PCB trace connection from the SPI flash and Host/PCH.
These trace connections can
PCB trace from the Host/PCH termination resistor to the PCB trace equal 1-inch up to 5-inches. See
Note 2-5
connection from the SPI flash and MEC140x / MEC141x.
L2
L3
PCB trace from the SPI flash termination resistor to the PCB trace
connection from the MEC140x / MEC141x or Host/PCH.
L4
PCB trace from Host/PCH or MEC140x / MEC141x to SPI flash for
chip select.
L4 = L1 + L3 + (2 x L0) or
L4 = L2 + L3 + (2 x L0)
+/- 0.100 inches.
R1
These resistors are between the PCB trace and the Host/PCH.
25 ohm, see Note 2-3, Note 2-4
R2
These resistors are between the PCB trace and the MEC140x /
MEC141x.
15 ohm, see Note 2-3, Note 2-4
R3
These resistors are between the PCB trace and the SPI flash.
15 ohm, see Note 2-3, Note 2-4
R4
Pull-high resistor to +3.3V for SPI CS connections; between the
MEC140x / MEC141x or Host/PCH and the SPI flash device. This
pull-high must connect to the same power rail of the SPI flash.
4.7K ohm
Note 2-3
The final value of the series resistors should be chosen based on performing electrical analysis to
ensure the electrical timings and min/max voltage specifications are met for each device (SPI, EC,
PCH or other Host SPI controller) including the undershoot/ overshoot specifications for the MEC140x
/ MEC141x (-0.3V min. to VCC1+0.3V max).
Note 2-4
Resistor recommendations are based on testing with 180nm PCH and SPI flash drivers. Any change
to a driver would require a change to the related termination resistors, see also Note 2-3.
Note 2-5
L1, L2, L3 must be equal to each other. For example, if L1 = 2-inches, then L3 must be 2-inches.
2.7.4
Note:
PRIVATE SPI FLASH INTERFACE
Either Shared SPI or Private SPI interface can support a dedicated SPI chip. The Private SPI is targeted
for use as a crisis recovery option since it is muxed with keyscan pins.
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2.7.4.1
Private SPI Flash Implementation
Figure 2-5 is a topology for implementing the MEC140x / MEC141x SPI flash for a single private SPI flash device. See
Table 2-3 for specifications on PCB trace recommendations represented by “L1,” “L2,” and so forth.
FIGURE 2-5:
MEC140X / MEC141X TOPOLOGY FOR PRIVATE SPI FLASH DEVICE
MEC1404
SPI
Flash
L0 R1
L0 R1
L1
L0 R1
PVT_SIO2
R1
PVT_SIO3 L0
L0 R1
L1
PVT_SIO0
PVT_SIO1
PVT_SCLK
R2 L0
SIO0
R2 L0
SIO1
R2 L0
SIO2
R2 L0
SIO3
L1
L1
L2
CLK
+3.3V
+3.3V
SHD_CS#
TABLE 2-3:
L3
R3
CS
MEC140X / MEC141X PRIVATE SPI FLASH DEVICE SPECIFICATIONS
Description
Spec
L0
Connection between MEC140x / MEC141x or SPI flash device and termination resistors.
0.1-inch to 0.5-inch
L1
The PCB trace between terminating resistors on the IO lines.
1-inch to 10-inch
L2
The PCB trace from MEC140x / MEC141x or R1 resistor to SPI flash.
1-inch to 10-inch
L3
PCB trace from MEC140x / MEC141x to SPI flash for chip select.
L3 = L0 + L1
R1
These resistors are between the trace and the MEC140x / MEC141x.
25 ohm, see also Note 2-6
R2
This resistor is on the IO lines between the SPI flash and trace.
45 ohm, see Note 2-6.
R3
This is a Pull-High resistor (to +3.3V) for SPI CS connections. This pullhigh must connect to the same power rail of the SPI flash.
4.7K ohm
Note 2-6
2.7.5
The final value of the series resistors should be chosen based on performing electrical analysis to
ensure the electrical timings and min/max voltage specifications are met for each device (SPI, EC,
PCH or other Host SPI controller) including the undershoot/ overshoot specifications for the MEC140x
/ MEC141x (-0.3V min. to VCC1 +0.3V max).
SPI FLASH IMPLEMENTATION RECOMMENDATIONS
The following recommendations are for both Shared and Private SPI Flash Implementations.
• The MEC140x / MEC141x SPI memory interface has serial flash device compatibility requirements that are
defined in the MEC140x / MEC141x PCS. Please make sure the selected SPI flash meets these requirements.
• SPI_CLK must be 20mils spacing from any other high frequency (>1GHz) signal.
• The SPI flash parts should support operating at 8.5MHz for the ROM code loader, and up to 33MHz clock speed in
RAM code loading.
• The designer should follow the SPI interface host design guidelines.
DS00001859B-page 14
 2014 - 2015 Microchip Technology Inc.
AN1859
• IBIS models are available to aid in simulating the SPI system topology.
• The chip select CS# signals should have weak pullup resistors to the same power rail as the SPI flash. The pullup
resistor value should meet the rise time requirements of the SPI flash.
• EC firmware must configure the MEC140x / MEC141x SPI memory interface to disable mode, which will tri-state
the SPI memory interface from MEC140x / MEC141x to the SPI flash, before releasing the RSMRST# signal.
• This configuration requires that the PCH tri-states its SPI flash pins when RSMRST# is asserted.
• The characteristic impedance of the PCB trace should be 50 ohms +/-15% at 50MHz operating frequency.
• Within the SPI flash device, Schmitt trigger inputs are assumed on both the clock line and IO data lines.
• Within the Intel PCH, a Schmitt trigger input is assumed on the IO data lines.
• The output drivers for the SPI flash chip select pins should be programmed as open-drain using the GPIO Pin
Control registers.
• The SPI Data IO traces should be length-matched to the CLK lines within 0.100-inch.
• Signal Integrity should be checked for each SPI part on your BOM.
2.7.6
SPI FLASH EXTERNAL PROGRAMMER
The SPI Flash on either Shared or Private SPI Flash interface must be programmed externally using a suitable programmer, such as Dediprog’s SF100 (http://www.dediprog.com/pd/spi-flash-solution/sf100).
Provisions for a programming header on each SPI flash are recommended if the SPI is not socketed.
2.8
1MHz Pullup Resistor Requirement
Please refer to the I2C-bus specification and user manual as indicated in the section References on page 1 for more
information.
2.9
5V Tolerant Pins
There are no 5V tolerant pins on the MEC140x / MEC141x.
2.10
1.8V Capability
Please refer to the MEC140x / MEC141x Data Sheet section 2.6 for more information.
Note:
The LPC Interface Signals require the VTR_33_18 power pin to be connected to the 3.3V VTR rail. The
eSPI Interface signals require the VTR_33_18 power pin to be connected to the 1.8V rail. The GPIO signals
on these pins may operate at either 1.8V or 3.3V. Please also configure the VTR_LPC_ESPI_SEL18 bit 3
at Power Regions Voltage Control Register (0xFC48) accordingly.
Note:
The SMB00 to SMB04 Ports have the option to be configured for either 3.3V or 1.8V signaling. This selection is determined by the GPIO alternate function mux.
 2014 - 2015 Microchip Technology Inc.
DS00001859B-page 15
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3.0
2-WIRE DEBUG INTERFACE (ICSP)
Please refer to the Microchip ICD User Manual as indicated in the section References on page 1 for more information.
• The Figure 3-1 shows the standard recommended target circuitry.
• The Figure 3-2 shows the circuits that will prevent the debugger from functioning.
TABLE 3-1:
ICSP INTERFACE SIGNALS
Pin Signal
Function name
MEC140x /
MEC141x Pin
Number
Pin Function Signal Description
ICSP_MCLR
87
ICSP Master Clear
ICSP_CLOCK
101
ICSP Clock (shown as PGC in Figure 3-1)
ICSP_DATA
102
ICSP Data (shown as PGD in Figure 3-1)
FIGURE 3-1:
DS00001859B-page 16
STANDARD CONNECTION TARGET CIRCUITRY
 2014 - 2015 Microchip Technology Inc.
AN1859
FIGURE 3-2:
IMPROPER CIRCUIT COMPONENTS
 2014 - 2015 Microchip Technology Inc.
DS00001859B-page 17
AN1859
4.0
PROGRAMMABLE COMPARATORS
MEC140x / MEC141x has two programmable comparators.
Figure 4-1 shows the comparators signals information.
Figure 4-1 show the comparators alternate circuitry in single supply operation.
See the additional information that can be used as reference.
• Hysteresis is implemented externally by implementing feedback resistor circuit on VOUT to VIN pin.
• Input voltage range (VIN) from 0 to 3.63V.
• Input threshold range may come from VREF pin or from internal DAC that is configurable from 0 to 3.63V.
TABLE 4-1:
COMPARATORS SIGNALS
MEC140x /
MEC141x Pin
Number
Pin Signal
Function name
Pin Function Signal Description
GPIO165/CMP_VREF0
25
Comparator 0 Voltage Reference
GPIO020/CMP_VIN0
20
Comparator 0 Voltage Input
GPIO124/CMP_VOUT0
85
Comparator 0 Voltage Output
GPIO166/CMP_VREF1
26
Comparator 1 Voltage Reference
GPIO021/CMP_VIN1
21
Comparator 1 Voltage Input
GPIO120/CMP_VOUT1
83
Comparator 1 Voltage Output
FIGURE 4-1:
DS00001859B-page 18
COMPARATORS IN SINGLE-SUPPLY OPERATION
 2014 - 2015 Microchip Technology Inc.
AN1859
4.1
Thermistor Application
This section shows the calculation of the nominal hysteresis for the circuitry shown in the Figure 4-2, "Thermistor Application example".
FIGURE 4-2:
4.1.1
THERMISTOR APPLICATION EXAMPLE
COMPARATOR VOLTAGE OUTPUT CALCULATION
Use Kirchhoff’s Voltage Law with assumption I2 = 0, ideal condition with some small leakage in uAmps region.
EQUATION 1:
AT ROOM TEMP
- 3.3V + I1 (100K) + I1 (100K) + I1 (1K) + 2.69V = 0
I1 (201K) = 0.66V
I1 = 3.3uAmps
100K x 3.3uAmps = 0.3V
3.3V - 0.3V = 3V at Room Temperature
EQUATION 2:
JUST BEFORE TRIP POINT
- 3.3V + I1 (100K) + I1 (100K) + I1 (1K) + 1.1V = 0
I1 (201K) = 2.2V
I1 = 11uAmps
100K x 11uAmps = 1.1V
3.3V - 1.1V = 2.2V at Just Before Trip Point
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DS00001859B-page 19
AN1859
4.1.2
HYSTERESIS CALCULATION
EQUATION 3:
JUST BEFORE TRIP POINT
- 2.2V + I1(100K) + I1(1K) + 1.1V = 0
I1 (101K) = 1.1V
I1 = 11uAmps
VIN = 11uAmps (1K) +1.1V = 1.111V
EQUATION 4:
AFTER TRIP POINT
1.1V = 100K / 101K (VIN)
VIN = 1.089
As a result, the hysteresis is +/- 11mV, total 22mV between 1.111V to 1.089V.
4.1.3
CONCLUSION
• Based on the 100K and 1K external feedback resistor values chosen, the nominal is +/- 11m and the total of 22mV
hysteresis.
• The output of the comparator is ~3V at room temperature.
• The output of the open drain comparator at just before trip point is 2.2V, which is still high enough based on fact of
the circuitry.
• Trip point at ~ 82C, based on a typical 100K NTC Thermistor resistance numbers from the thermistor data sheet.
DS00001859B-page 20
 2014 - 2015 Microchip Technology Inc.
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5.0
HOW TO SETUP ADC VOLTAGE STATES TO DISTINGUISH PC MODEL AND
PCB TYPES
This section provides general guidelines regarding how to use the ADC input to distinguish the PC models and PCB
types in the design as follows:
1.
2.
3.
4.
Choose resistor values by taking into account the effects of the ADC input impedance (refer to MEC140x /
MEC141x data sheet for more information).
Make sure the tolerance of the large resistors are taken into account.
Final calculated voltages, taking into account the ADC input impedance and Resistor tolerance, should give the
designer a range of voltages for each resistor set, then make sure there is enough voltage separation to distinguish (accounting for anticipated system noise and accuracy of ADC input resolution), recommend a minimum
of 250mV between ADC steps for a robust design.
Adjust resistor (such as lower value of resistors used, or use a better tolerance if needed) if step 3 is not satisfactory.
5.1
Reference Example
This section shows the calculation and suggestion based on the above guideline.
5.1.1
IDEALIZED CASE
Pull Down
Pull Up
Ideal Voltage Divider
Gap
1
100K
10K
3V
0.199V
2
100K
17.8K
2.801V
0.203V
3
100K
27K
2.598V
0.197V
4
100K
37.4K
2.402V
0.2V
5
100K
49.9K
2.201V
0.2V
6
100K
64.9K
2.001V
0.193V
7
100K
82.5K
1.808V
0.214V
8
100K
107K
1.594V
0.295V
9
100K
154K
1.299V
0.199V
10
100K
200K
1.100V
5.1.2
IDEALIZED CASE WITH 3 MOHM INPUT IMPEDANCE
Pull Down
Pull Up
Ideal Voltage Divider
Gap
1
96.774K
10K
2.991V
0.204V
2
96.774K
17.8K
2.787V
0.207V
3
96.774K
27K
2.58V
0.2V
4
96.774K
37.4K
2.38V
0.203V
5
96.774K
49.9K
2.177V
0.202V
6
96.774K
64.9K
1.975V
0.194V
7
96.774K
82.5K
1.781V
0.214V
8
96.774K
107K
1.567V
0.294V
9
96.774K
154K
1.273V
0.197V
10
96.774K
200K
1.076V
 2014 - 2015 Microchip Technology Inc.
DS00001859B-page 21
AN1859
5.1.3
WITH 1% RESISTORS TOLERANCE - WORST CASE ANALYSIS
Actual Pull Down with 3 Mohm Input
99%
95.83736689K
100%
96.77419355K
101%
97.71041599K
Low Side
High Side
101% Pull Down w/
3 Mohm
Low side Pull
Up (99%)
High Side
Voltage
99% Pull Down w/
3 Mohm
High Side Pull
Up (101%)
Low Side
Voltage
97.71K
9.9K
2.996V
95.837K
10.1K
97.71K
17.622K
2.796V
95.837K
17.978K
2.779V
0.188V
97.71K
26.73K
2.591V
95.837K
27.27K
2.569V
0.176V
97.71K
37.026K
2.393V
95.837K
37.774K
2.367V
0.175V
97.71K
49.401K
2.192V
95.837K
50.399K
2.163V
0.172V
97.71K
64.251K
1.991V
95.837K
65.549K
1.96V
0.162V
97.71K
81.675K
1.797V
95.837K
83.325K
1.765V
0.182V
97.71K
105.93K
1.583V
95.837K
108.07K
1.551V
0.262V
97.71K
152.46K
1.289V
95.837K
155.54K
1.258V
0.168V
97.71K
198K
1.09V
95.837K
202K
1.062V
DS00001859B-page 22
2.985V
GAP
0.19V
 2014 - 2015 Microchip Technology Inc.
AN1859
APPENDIX A:
TABLE A-1:
APPLICATION NOTE REVISION HISTORY
REVISION HISTORY
Revision Level & Date
Section/Figure/Entry
DS00001859B (07-08-15)
All
Section 1.1
Section 2.2
Section 2.3
Section 2.10
DS00001859A (11-26-14)
Correction
Added MEC141x family devices
Added144-pin WFBGA package info
Update LPC Section
Added eSPI Interface Section
Added 1.8V Capability Section
Document Release
 2014 - 2015 Microchip Technology Inc.
DS00001859B-page 23
AN1859
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck,
MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and
UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK,
MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial
Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2014 - 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781632775672
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS00001859B-page 24
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
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and manufacture of development systems is ISO 9001:2000 certified.
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DS00001859B-page 25