Data Sheet

74AVC16374-Q100
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Rev. 2 — 16 March 2015
Product data sheet
1. General description
The 74AVC16374-Q100 is a 16-bit edge triggered flip-flop featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus-oriented applications. The
74AVC16374-Q100 consist of 2 sections of 8 edge-triggered flip-flops. A clock input (CP)
and an output enable (OE) are provided per 8-bit section.
The 74AVC16374-Q100 is designed to have an extremely fast propagation delay and a
minimum amount of power consumption.
To ensure the high-impedance output state during power-up or power-down, nOE should
be tied to VCC through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line
drive during transient (see Figure 5 and Figure 6).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Wide supply voltage range from 1.2 V to 3.6 V
 Complies with JEDEC standards:
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-1A (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 exceeds 1000 V
 HBM JESD22-A114F exceeds 1000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 CMOS low power consumption
 Input/output tolerant up to 3.6 V
 Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,
resulting in noise reduction without speed degradation
 Low inductance multiple VCC and GND pins to minimize noise and ground bounce
 Supports Live Insertion
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
74AVC16374DGG-Q100
Temperature range Name
Description
Version
40 C to +85 C
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
TSSOP48
4. Functional diagram
2(
&3
2(
&3
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(1
(1
'
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IEC logic symbol
74AVC16374_Q100
Product data sheet
2(
2(
'
4
'
4
4
'
4
4
'
4
4
'
4
4
'
4
4
'
4
4
'
4
4
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4
4
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4
4
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4
4
'
4
4
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4
4
'
4
'
4
'
4
4
4
4
&3
&3
4
PQD
Fig 1.
&
&
Fig 2.
PQD
Logic symbol
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Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
'
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4
4
&3
))
&3
2(
WRRWKHUFKDQQHOV
'
'
4
4
&3
&3
))
2(
WRRWKHUFKDQQHOV
Fig 3.
PQD
Logic diagram
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
5. Pinning information
5.1 Pinning
$9&4
2(
&3
4
'
4
'
*1'
*1'
4
'
4
'
9&&
9&&
4
'
4
'
*1' *1'
4 '
4 '
4 '
4 '
*1' *1'
4 '
4 '
9&& 9&&
4 '
4 '
*1' *1'
4 '
4 '
2( &3
DDD
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE
1
output enable input (active LOW)
1Q0 to 1Q7
2, 3, 5, 6, 8, 9, 11, 12
3-state flip-flop outputs
GND
4, 10, 15, 21, 28, 34, 39, 45
ground (0 V)
VCC
7, 18, 31, 42
supply voltage
2Q0 to 2Q7
13, 14, 16, 17, 19, 20, 22, 23
3-state flip-flop outputs
2OE
24
output enable input (active LOW)
2CP
25
clock input
2D0 to 2D7
36, 35, 33, 32, 30, 29, 27, 26
data input/output
1D0 to 1D7
47, 46, 44, 43, 41, 40, 38, 37
data input/output
1CP
48
clock input
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
6. Functional description
Table 3.
Function table[1]
Operating modes
Inputs
Internal flip-flops
Outputs
nOE
nCp
nDn
Load and read register
L

I
L

h
H
H
Load register and disable outputs
H

I
L
Z
H

h
H
Z
[1]
nQn
L
L
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
 = LOW-to-HIGH CP transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
Conditions
VI < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
-
50
mA
0.5
+4.6
V
mA
50
-
output HIGH or LOW
[1]
0.5
VCC + 0.5
V
output 3-state
[1]
0.5
+4.6
V
-
50
mA
VO < 0 V
IO
output current
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
VO = 0 V to VCC
Tamb = 40 C to +85 C
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
VCC
supply voltage
Conditions
Min
Typ
Max
Unit
according to JEDEC Low Voltage Standards
1.4
-
1.6
V
1.65
-
1.95
V
2.3
-
2.7
V
3.0
-
3.6
V
1.2
-
3.6
V
0
-
3.6
V
for low-voltage applications
VI
input voltage
VO
output voltage
output HIGH or LOW
0
-
VCC
V
output 3-state
0
-
3.6
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall
rate
VCC = 1.4 V to 1.6 V
0
-
40
ns/V
VCC = 1.65 V to 2.3 V
0
-
30
ns/V
VCC = 2.3 V to 3.0 V
0
-
20
ns/V
VCC = 3.0 V to 3.6 V
0
-
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
VCC = 1.2 V
VCC
-
-
V
VCC = 1.4 V to 1.6 V
0.65  VCC
0.9
-
V
VCC = 1.65 V to 1.95 V
0.65  VCC
0.9
-
V
VCC = 2.3 V to 2.7 V
1.7
1.2
-
V
VCC = 3.0 V to 3.6 V
2.0
1.5
-
V
VCC = 1.2 V
-
-
GND
V
VCC = 1.4 V to 1.6 V
-
0.9
0.35  VCC V
VCC = 1.65 V to 1.95 V
-
0.9
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
1.2
0.7
V
VCC = 3.0 V to 3.6 V
-
1.5
0.8
V
Unit
Tamb = 40 C to +85 C
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
74AVC16374_Q100
Product data sheet
VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 3.6 V
VCC  0.20
VCC
-
V
IO = 3 mA; VCC = 1.4 V
VCC  0.35
VCC  0.23
-
V
IO = 4 mA; VCC = 1.65 V
VCC  0.45
VCC  0.25
-
V
IO = 8 mA; VCC = 2.3 V
VCC  0.55
VCC  0.38
-
V
IO = 12 mA; VCC = 3.0 V
VCC  0.70
VCC  0.48
-
V
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Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Min
Typ[1]
Max
Unit
IO = 100 A; VCC = 1.65 V to 3.6 V
-
GND
0.20
V
IO = 3 mA; VCC = 1.4 V
-
0.10
0.35
V
IO = 4 mA; VCC = 1.65 V
-
0.10
0.45
V
IO = 8 mA; VCC = 2.3 V
-
0.26
0.55
V
IO = 12 mA; VCC = 3.0 V
-
0.36
0.70
V
Symbol Parameter
Conditions
VOL
VI = VIH or VIL
LOW-level output voltage
II
input leakage current
per pin; VI = VCC or GND;
VCC = 1.4 V to 3.6 V
-
0.1
2.5
A
IOFF
power-off leakage current
VI or VO = 3.6 V; VCC = 0.0 V
-
0.1
10
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND
VCC = 1.4 V to 2.7 V
-
0.1
5
A
VCC = 3.0 V to 3.6 V
-
0.1
10
A
-
0.1
20
A
-
0.2
40
A
-
5
-
supply current
ICC
VI = VCC or GND; IO = 0 A
VCC = 1.4 V to 2.7 V
VCC = 3.0 V to 3.6 V
input capacitance
CI
[1]
pF
All typical values are measured at Tamb = 25 C.
9.1 Graphs
PQD
,2+
P$
PQD
,2/
P$
9
9
9
9
9
9
92+9
Fig 5.
Product data sheet
92/9
Output voltage as a function of the HIGH-level
output current.
74AVC16374_Q100
Fig 6.
Output voltage as a function of the LOW-level
output current.
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Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). tr = tf  2 ns. For test circuit, see Figure 10.
Symbol
tpd
Parameter
propagation delay
40 C to +85 C
Conditions
Min
Max
-
3.1
-
ns
VCC = 1.4 V to 1.6 V
1.2
2.4
8.4
ns
VCC = 1.65 V to 1.95 V
1.0
2.0
6.7
ns
VCC = 2.3 V to 2.7 V
0.8
1.5
4.1
ns
VCC = 3.0 V to 3.6 V
0.7
1.3
3.3
ns
-
5.4
-
ns
nCP to nQn; see Figure 7
[1]
VCC = 1.2 V
ten
enable time
nOE to nQn, nBn; see Figure 8
[1]
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
1.6
3.9
8.5
ns
VCC = 1.65 V to 1.95 V
2.3
3.3
6.7
ns
VCC = 2.3 V to 2.7 V
0.9
2.3
4.3
ns
0.7
2.0
3.4
ns
-
5.6
-
ns
VCC = 1.4 V to 1.6 V
2.5
4.5
9.4
ns
VCC = 1.65 V to 1.95 V
1.8
3.3
7.8
ns
VCC = 2.3 V to 2.7 V
1.0
1.8
4.2
ns
VCC = 3.0 V to 3.6 V
1.2
2.0
3.9
ns
-
0.8
-
ns
VCC = 3.0 V to 3.6 V
tdis
disable time
nOE to nQn; see Figure 8
VCC = 1.2 V
tW
pulse width
VCC = 1.4 V to 1.6 V
set-up time
-
0.5
-
ns
VCC = 1.65 V to 1.95 V
3.1
0.3
-
ns
VCC = 2.3 V to 2.7 V
2.5
0.2
-
ns
VCC = 3.0 V to 3.6 V
2.5
0.2
-
ns
-
0.6
-
ns
VCC = 1.4 V to 1.6 V
2.7
0.3
-
ns
VCC = 1.65 V to 1.95 V
1.9
0.3
-
ns
VCC = 2.3 V to 2.7 V
1.4
0.2
-
ns
VCC = 3.0 V to 3.6 V
1.4
0.1
-
ns
-
0.8
-
ns
VCC = 1.4 V to 1.6 V
1.3
0.7
-
ns
VCC = 1.65 V to 1.95 V
1.2
0.6
-
ns
VCC = 2.3 V to 2.7 V
1.1
0.5
-
ns
VCC = 3.0 V to 3.6 V
1.1
0.4
-
ns
nDn to nCP; see Figure 8
VCC = 1.2 V
th
hold time
nDn to nCP; see Figure 8
VCC = 1.2 V
74AVC16374_Q100
Product data sheet
[1]
HIGH; nCP; see Figure 7
VCC = 1.2 V
tsu
Unit
Typ[2]
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Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). tr = tf  2 ns. For test circuit, see Figure 10.
Symbol
Parameter
fmax
40 C to +85 C
Conditions
maximum frequency
Min
Max
VCC = 1.2 V
-
250
-
MHz
VCC = 1.4 V to 1.6 V
-
300
-
MHz
VCC = 1.65 V to 1.95 V
160
320
-
MHz
VCC = 2.3 V to 2.7 V
200
350
-
MHz
200
350
-
MHz
outputs enabled
-
66
-
pF
outputs disabled
-
1
-
pF
see Figure 8
VCC = 3.0 V to 3.6 V
power dissipation
capacitance
CPD
[1]
Unit
Typ[2]
[3]
per input; VI = GND to VCC
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2]
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V respectively.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL  VCC2  fo) = sum of the outputs.
11. Waveforms
IPD[
9,
Q&3LQSXW
90
90
*1'
W:
W3+/
W3/+
92+
Q4QRXWSXW
90
92/
PQD
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Clock input (nCP) to output (nQn) propagation delays
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
9,
Q2(LQSXW
90
*1'
W 3=/
W 3/=
9&&
RXWSXW
/2:WR2))
2))WR/2:
90
9;
92/
W 3=+
W 3+=
92+
9<
RXWSXW
+,*+WR2))
2))WR+,*+
90
*1'
RXWSXWV
HQDEOHG
RXWSXWV
GLVDEOHG
RXWSXWV
HQDEOHG
PQD
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
3-state enable and disable times
9,
90
Q&3LQSXW
*1'
WVX
WVX
WK
WK
9,
90
Q'QLQSXW
*1'
92+
90
Q4QRXWSXW
92/
PQD
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Data set-up and hold times for nDn input to nCP input
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Table 8.
Measurement points
Supply voltage
VM
Input
VCC
VI
tr = tf
VX
VY
1.2 V
0.5  VCC
VCC
 2 ns
VOL + 0.15 V
VOH  0.15 V
1.4 V to 1.6 V
0.5  VCC
VCC
 2 ns
VOL + 0.15 V
VOH  0.15 V
1.65 V to 1.95 V
0.5  VCC
VCC
 2 ns
VOL + 0.15 V
VOH  0.15 V
2.3 V to 2.7 V
0.5  VCC
VCC
 2 ns
VOL + 0.15 V
VOH  0.15 V
3.0 V to 3.6 V
0.5  VCC
VCC
 2 ns
VOL + 0.3 V
VOH  0.3 V
W:
9,
QHJDWLYH
SXOVH
90
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
90
90
9
W:
9(;7
9&&
*
9,
5/
92
'87
57
5/
&/
DDH
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
 2 ns
15 pF
2 k
open
2  VCC
GND
1.4 V to 1.6 V
VCC
 2 ns
15 pF
2 k
open
2  VCC
GND
1.65 V to 1.95 V
VCC
 2 ns
30 pF
1 k
open
2  VCC
GND
2.3 V to 2.7 V
VCC
 2 ns
30 pF
500 
open
2  VCC
GND
3.0 V to 3.6 V
VCC
 2 ns
30 pF
500 
open
2  VCC
GND
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
12. Package outline
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Fig 11. Package outline SOT362-1 (TSSOP48)
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
MIL
Military
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AVC16374_Q100 v.2
20150316
Product data sheet
-
74AVC16374_Q100 v.1
Modifications:
74AVC16374_Q100 v.1
74AVC16374_Q100
Product data sheet
•
Section 2: ESD protection; for MIL-STD-883 (method 3015) and HBM JESD22-A114F
the value is changed from 2000 V to 1000 V.
20130916
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
-
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AVC16374_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AVC16374_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 16
74AVC16374-Q100
NXP Semiconductors
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
9.1
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 March 2015
Document identifier: 74AVC16374_Q100