74LVC74A-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 2 — 5 April 2013 Product data sheet 1. General description The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVC74APW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC74ABQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 74LVC74AD-Q100 SOT762-1 4. Functional diagram 4 2 3 1SD 1D 1CP SD Q D Q 4 10 3 1SD 2SD 2 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 1 5 9 10 6 8 11 12 13 1RD 2RD 1 13 Fig 1. Logic symbol 74LVC74A_Q100 Product data sheet Fig 2. 1Q 6 RD S 5 1 C1 1D 6 10 1RD 2SD R 12 S 9 11 C1 2D 2CP SD Q D 2Q 9 CP FF 1D Q 8 2Q 8 RD R 13 mna419 mna418 5 CP FF 4 1Q IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 Fig 3. 2RD mna420 Functional diagram © NXP B.V. 2013. All rights reserved. 2 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Q C C C C C C D Q C C RD SD mna421 C CP C Fig 4. Logic diagram for one flip-flop 5. Pinning information 5.1 Pinning 9&& ' 5' &3 ' 6' &3 5' WHUPLQDO LQGH[DUHD 5' 4 *1' 4 &3 ' 6' 4 4 &3 *1' 6' 4 5' 4 6' ' *1' 4 9&& /9&$4 /9&$4 4 DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration for SO14 and TSSOP14 74LVC74A_Q100 Product data sheet Fig 6. Pin configuration for DHVQFN14 All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 3 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 5.2 Pin description Table 2. Pin description Symbol Pin Description 1RD, 2RD 1, 13 asynchronous reset-direct input (active LOW) 1D, 2D 2, 12 data input 1CP, 2CP 3, 11 clock input (LOW-to-HIGH, edge-triggered) 1SD, 2SD 4, 10 asynchronous set-direct input (active LOW) 1Q, 2Q 5, 9 true output 1Q, 2Q 6, 8 complement output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care Table 4. Function table[1] Input Output nSD nRD nCP nD nQn+1 nQn+1 H H L L H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition; X = don’t care 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 4 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA 0.5 VCC + 0.5 V VO output voltage IO output current - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For TSSOP14 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 8. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage for maximum speed performance 1.65 - 3.6 V for low-voltage applications 1.2 - 3.6 V 0 - 5.5 V VI input voltage VO output voltage 0 - VCC V Tamb ambient temperature 40 - +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 5 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 9. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL Typ[1] 40 C to +125 C Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - 0.12 V VCC = 1.2 V - - 0.12 VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = 100 A; VCC = 1.65 V to 3.6 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V 0.1 5 - 20 A II input leakage VCC = 3.6 V; VI = 5.5 V or GND current ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 4.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 6 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max - 15 - - - ns VCC = 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns VCC = 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns VCC = 2.7 V 1.0 2.7 6.0 1.0 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.6 5.2 1.0 6.5 ns - 15 - - - ns nCP to nQ, nQ; see Figure 7 [2] VCC = 1.2 V nSD to nQ, nQ; see Figure 8 VCC = 1.2 V VCC = 1.65 V to 1.95 V 0.5 4.0 10.6 0.5 12.2 ns VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns VCC = 2.7 V 1.0 2.9 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns - 15 - - - ns VCC = 1.65 V to 1.95 V 0.5 4.1 10.7 0.5 12.4 ns VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns VCC = 2.7 V 1.0 3.0 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns nRD to nQ, nQ; see Figure 8 VCC = 1.2 V tW pulse width clock HIGH or LOW; see Figure 7 set or reset LOW; see Figure 8 trec recovery time 74LVC74A_Q100 Product data sheet VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 1.5 - - 1.5 - ns VCC = 2.7 V 1.5 - - 1.0 - ns VCC = 3.0 V to 3.6 V +1.0 3.0 - 1.0 - ns set or reset; see Figure 8 All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 7 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter 40 C to +85 C Conditions Min tsu set-up time hold time th maximum frequency fmax tsk(o) CPD [1] Typ[1] Max 40 C to +125 C Unit Min Max nD to nCP; see Figure 7 VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 2.2 - - 2.2 - ns VCC = 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns VCC = 1.65 V to 1.95 V 2.0 - - 2.0 - ns VCC = 2.3 V to 2.7 V 1.5 - - 1.5 - ns VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V +1.0 0.2 - 1.0 - ns VCC = 1.65 V to 1.95 V 100 - - 80 - MHz VCC = 2.3 V to 2.7 V 125 - - 100 - MHz VCC = 2.7 V 150 - - 120 - MHz VCC = 3.0 V to 3.6 V 150 250 - 120 - MHz - - 1.0 - 1.5 ns nD to nCP; see Figure 7 nCP; see Figure 7 output skew time VCC = 3.0 V to 3.6 V [3] power dissipation capacitance [4] per flip-flop; VI = GND to VCC VCC = 1.65 V to 1.95 V - 12.4 - - - pF VCC = 2.3 V to 2.7 V - 16.0 - - - pF VCC = 3.0 V to 3.6 V - 19.1 - - - pF Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 8 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 11. AC waveforms VI VM nD input GND th th t su t su 1/fmax VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH t PHL mna422 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Clock propagation delays, pulse widths, set-up, hold times and maximum frequency 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 9 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9. Set and reset propagation delays, pulse widths and recovery time Measurement points Supply voltage Input VCC VI VM VM 1.2 V VCC 0.5 VCC 0.5 VCC 1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC 2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V 74LVC74A_Q100 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 10 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Table 10. Load circuitry for switching times Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC 2 ns 30 pF 1 k open 2 VCC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 VCC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 74LVC74A_Q100 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 11 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 12 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 13 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 14 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC74A_Q100 v.2 20130405 Product data sheet - 74LVC74A_Q100 v.1 Modifications: 74LVC74A_Q100 v.1 74LVC74A_Q100 Product data sheet • Section 2 “Features and benefits” removed redundant temperature range 20130326 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 - © NXP B.V. 2013. All rights reserved. 15 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC74A_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 16 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 17 of 18 74LVC74A-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 5 April 2013 Document identifier: 74LVC74A_Q100