Data Sheet

HEF4060B-Q100
14-stage ripple-carry binary counter/divider and oscillator
Rev. 2 — 9 September 2014
Product data sheet
1. General description
The HEF4060B-Q100 is a 14-stage ripple-carry binary counter/divider and oscillator. It
has three oscillator terminals (RS, REXT and CEXT) and ten buffered outputs (Q3 to Q9
and Q11 to Q13). It also has an overriding asynchronous master reset input (MR).
The oscillator configuration allows the design of either RC or crystal oscillator circuits. An
external clock signal at input RS can replace the oscillator. The Schmitt trigger action of
the clock makes it highly tolerant to slower clock rise and fall times. The counter advances
on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to
Q9 and Q11 to Q13 = LOW), independent of other input conditions.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Tolerant of slow clock rise and fall times
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 Inputs and outputs are protected against electrostatic effects
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
HEF4060BT-Q100
Package
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
4. Functional diagram
10
9
REXT
11
12
CEXT
RS
14-STAGE BINARY COUNTER
CP
CD
MR
Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q11 Q12 Q13
7
5
4
6
14
13
15
1
2
3
001aae652
Fig 1.
Functional diagram
CEXT
REXT
FF1
FF4
FF10
FF12
FF14
CP
CP
CP
RS
CP
CP
Q
CD
Q
Q
CD
MR
Q
CD
Q3
Q
CD
Q9
CD
Q11
Q13
001aae654
Fig 2.
Logic diagram
5. Pinning information
5.1 Pinning
+()%4
4
9''
4
4
4
4
4
4
4
05
4
56
4
5(;7
966
&(;7
DDD
Fig 3.
Pin configuration
HEF4060B_Q100
Product data sheet
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Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q11 to Q13
1, 2, 3
counter output
Q3 to Q9
7, 5, 4, 6, 14, 13, 15
counter output
VSS
8
ground supply voltage
CEXT
9
external capacitor connection
REXT
10
oscillator pin
RS
11
clock input/oscillator pin
MR
12
master reset
VDD
16
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
Output
RS
MR
Q3 to Q9 and Q11 to Q13

L
no change

L
count
X
H
L
[1]
H = HIGH voltage level; L = LOW voltage level;  = LOW-to-HIGH clock transition;  HIGH-to-LOW clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
Conditions
Min
0.5
VI < 0.5 V or VI > VDD + 0.5 V
0.5
VO < 0.5 V or VO > VDD + 0.5 V
Max
Unit
+18
V
10
mA
VDD + 0.5
V
-
10
mA
input/output current
-
10
mA
IDD
supply current
-
50
mA
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+85
C
Ptot
total power dissipation
Tamb 40 C to +85 C
P
power dissipation
per output
[1]
[1]
-
500
mW
-
100
mW
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
HEF4060B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD
VI
Conditions
Min
Typ
Max
Unit
supply voltage
3
-
15
V
input voltage
0
-
VDD
V
40
-
+85
C
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
Tamb
ambient temperature
in free air
t/V
input transition rise and fall
rate
input MR
9. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level
input voltage
IO < 1 A
LOW-level
input voltage
IO < 1 A
HIGH-level
output voltage
IO < 1 A
LOW-level
output voltage
HIGH-level
output current
LOW-level
output current
II
input leakage current
IDD
supply current
CI
Conditions
input capacitance
HEF4060B_Q100
Product data sheet
IO < 1 A
VDD
5V
Tamb = 40 C
Tamb = 25 C
Tamb = 85 C
Min
Max
Min
Max
Min
Max
3.5
-
3.5
-
3.5
-
Unit
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
mA
VO = 4.6 V
5V
-
0.52
-
0.44
-
0.36
mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
VO = 1.5 V
15 V
3.6
-
3.0
-
2.4
-
mA
15 V
-
0.3
-
0.3
-
1.0
A
5V
-
20
-
20
-
150
A
IO = 0 A
10 V
-
40
-
40
-
300
A
15 V
-
80
-
80
-
600
A
-
-
-
-
7.5
-
-
pF
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Rev. 2 — 9 September 2014
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4 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V; CL = 50 pF; tr = tf  20 ns; unless otherwise specified.
Symbol
Parameter
propagation delay
tpd
transition time
tt
pulse width
tW
recovery time
trec
Conditions
Typ
Max
Unit
183 ns + (0.55 ns/pF) CL
-
210
420
ns
5V
see Figure 4
10 V
69 ns + (0.23 ns/pF) CL
-
80
160
ns
15 V
42 ns + (0.16 ns/pF) CL
-
50
100
ns
Qn Qn + 1;
5V
-
-
25
50
ns
see Figure 4
10 V
-
-
10
20
ns
15 V
-
-
6
12
ns
MR Qn;
5V
73 ns + (0.55 ns/pF) CL
-
100
200
ns
HIGH to LOW
10 V
29 ns + (0.23 ns/pF) CL
-
40
80
ns
see Figure 4
15 V
22 ns + (0.16 ns/pF) CL
-
30
60
ns
see Figure 4
5V
[3]
10 ns + (1.00 ns/pF) CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF) CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF) CL
-
20
40
ns
120
60
-
ns
minimum width; 5 V
RS HIGH;
10 V
50
25
-
ns
see Figure 4
15 V
30
15
-
ns
minimum width; 5 V
50
25
-
ns
MR HIGH;
10 V
30
15
-
ns
see Figure 4
15 V
20
10
-
ns
input MR;
5V
160
80
-
ns
see Figure 4
10 V
80
40
-
ns
15 V
60
30
-
ns
see Figure 4
[1]
[2]
Extrapolation formula[1] Min
RS Q3;
maximum frequency input RS;
fmax
VDD
5V
4
8
-
MHz
10 V
10
20
-
MHz
15 V
15
30
-
MHz
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
tpd is the same as tPHL and tPLH.
[3]
tt is the same as tTHL and tTLH.
HEF4060B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
Table 8.
Power dissipation
Dynamic power dissipation PD and total power dissipation Ptot can be calculated from the formulas shown. Tamb = 25 C.
Symbol Parameter
Conditions
VDD
Typical formula for PD and Ptot (W)[1]
PD
per device
5V
PD = 700  fi + (fo  CL)  VDD2
dynamic power
dissipation
10 V PD = 3300  fi + (fo  CL)  VDD2
15 V PD = 8900  fi + (fo  CL)  VDD2
Ptot
[1]
total power
dissipation
when using
the on-chip
oscillator
5V
Ptot = 700  fosc + (fo  CL)  VDD2 + 2  Ct  VDD2  fosc + 690  VDD
10 V Ptot = 3300  fosc + (fo  CL)  VDD2 + 2  Ct  VDD2  fosc + 6900  VDD
15 V Ptot = 8900  fosc + (fo  CL)  VDD2 + 2  Ct  VDD2  fosc + 22000  VDD
Where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo  CL) = sum of the outputs;
Ct = timing capacitance (pF);
fosc = oscillator frequency (MHz).
11. Waveforms
tr
tf
90 %
VM
MR input
10 %
tW
1/fmax
trec
VM
RS input
tPHL
tPLH
tW
tPHL
90 %
Qn output
VM
10 %
tt
tt
001aaj472
Measurement points are given in Table 9.
Fig 4.
Waveforms showing propagation delays for MR to Qn and CP to Q0, minimum MR, and CP pulse widths
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4060B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
9''
9,
*
92
'87
&/
57
DDJ
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test;
CL = load capacitance including jig and probe capacitance;
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 5.
Test circuit for measuring switching times
Table 10.
Measurement point and test data
Supply voltage
Input
Load
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
 20 ns
50 pF
12. RC oscillator
+()%4
05IURPORJLF
56
&
5
5(;7
&(;7
5W
&W
DDD
1
Typical formula for oscillator frequency: f osc = -----------------------------2.3  R t  C t
Fig 6.
External component connection for RC oscillator
12.1 Timing component limitations
The oscillator frequency is mainly determined by Rt  Ct, provided Rt << R2 and
R2  C2 << Rt  Ct. R2 minimizes the influence of the forward voltage across the input
protection diodes on the frequency. The stray capacitance C2 should be kept as small as
possible. In consideration of accuracy, Ct must be larger than the inherent stray
capacitance. Rt must be larger than the LOCMOS (Local Oxidation Complementary
Metal-Oxide Semiconductor) ‘ON’ resistance in series with it. This resistance is typically
500  at VDD = 5 V, 300  at VDD = 10 V and 200  at VDD = 15 V.
HEF4060B_Q100
Product data sheet
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Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
The recommended values for these components to maintain agreement with the typical
oscillation formula are:
Ct  100 pF, up to any practical value,
10 k  Rt  1 M.
12.2 Typical crystal oscillator circuit
In Figure 7, R2 is the power limiting resistor. For starting and maintaining oscillation, a
minimum transconductance is necessary.
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Rbias
5(;7
NȍWR
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S)WR
S)
560 kΩ
5ELDV
VDD
5
Nȍ
&
S)
0.47 μF
Vi
(f = 1 kHz)
100 μF
input
output
A
io
VSS
DDD
001aae657
gfs = dio/dvi at vo is constant (see also Figure 9);
MR = LOW.
Fig 7.
External component connection for
crystal oscillator
HEF4060B_Q100
Product data sheet
Fig 8.
Test setup for measuring forward
transconductance (gfs)
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Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
001aae658
12.5
001aae659
105
gfs
(mA/V)
fosc
(Hz)
Rt
10
104
(1)
Ct
7.5
(2)
103
(3)
5
102
2.5
0
0
5
10
10 3
10
10−4
15
VDD (V)
Tamb = 25 C.
104
10−3
105
10−2
Rt (Ω)
Ct (μF)
106
10−1
Ct curve at Rt = 100 k; R2 = 470 k.
(1) Average + 2 .
Rt curve at Ct = 1 nF; R2 = 5 Rt.
(2) Average.
VDD = 5 V to 15 V; Tamb = 25 C.
(3) Average  2 .
Where ‘’ is the observed standard deviation.
Fig 9.
Typical forward transconductance gfs as a
function of the supply voltage
Fig 10. RC oscillator frequency as a function of
Rt and Ct
001aae660
(1)
8
Δfosc
(%)
4
(2)
(3)
(4)
0
(5)
−4
(6)
−8
−12
−50
0
50
100
150
Tamb (°C)
Lines (1) and (2): VDD = 15 V.
Lines (3) and (4): VDD = 10 V.
Lines (5) and (6): VDD = 5 V.
Lines (1), (3), (6): Rt = 100 k; Ct = 1 nF; R2 = 0 W.
Lines (2), (4), (5): Rt = 100 k; Ct = 1 nF; R2 = 300 k.
Referenced at: fosc at Tamb = 25 C and VDD = 10 V.
Fig 11. Oscillator frequency deviation (fosc) as a function of ambient temperature
HEF4060B_Q100
Product data sheet
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Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
13. Package outline
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Fig 12. Package outline SOT109-1 (SO16)
HEF4060B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4060B_Q100 v.2
20140909
Product data sheet
-
HEF4060B_Q100 v.1
Modifications:
HEF4060B_Q100 v.1
HEF4060B_Q100
Product data sheet
•
Section 2: ESD protection: MIL-STD-833 changed to MIL-STD883
20130228
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 September 2014
-
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4060B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4060B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 14
HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
18. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
12.1
12.2
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing component limitations . . . . . . . . . . . . . . 7
Typical crystal oscillator circuit . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 September 2014
Document identifier: HEF4060B_Q100