INTERSIL HCTS75D

HCTS75MS
Radiation Hardened
Dual 2-Bit Bistable Transparent Latch
September 1995
Features
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
Q0 1
1
16 1 Q0
D0 1
2
15 1 Q1
D1 1
3
14 1 Q1
E 2
4
13 1 E
5
12
D0 2
6
11
D1 2
7
10 2 Q0
Q1 2
8
VCC
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
9
GND
2 Q0
2 Q1
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS75MS is a Radiation Hardened dual 2-bit
bistable transparent latch. Each of the two latches are controlled
by a separate enable input (E) which are active low. E low latches
the output state.
The HCTS75MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS75MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Q0 1
1
16
1 Q0
D0 1
2
15
1 Q1
D1 1
3
14
1 Q1
1 E
E 2
4
13
VCC
5
12
GND
D0 2
6
11
2 Q0
D1 2
7
10
2 Q0
Q1 2
8
9
2 Q1
Functional Diagram
LATCH 0
2(6)
D0
16(10
13(4)
E
D
Q
LE
LE
1(11
Ordering Information
14(8
PART
NUMBER
TEMPERATURE
RANGE
SCREENING
LEVEL
PACKAGE
HCTS75DMSR
-55oC to +125oC
Intersil Class
S Equivalent
16 Lead SBDIP
HCTS75KMSR
-55oC to +125oC
Intersil Class
S Equivalent
16 Lead Ceramic
Flatpack
HCTS75D/
Sample
+25oC
Sample
16 Lead SBDIP
HCTS75K/
Sample
+25oC
Sample
16 Lead Ceramic
Flatpack
HCTS75HMSR
+25oC
Die
Die
3(7)
D1
5
12
LE
D
Q
15(9
LATCH 1
VCC
GND
TRUTH TABLE
INPUTS
OUTPUTS
D
E
Q
Q
L
H
L
H
H
H
H
L
X
L
Q0
Q0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
470
LE
Spec Number
File Number
518625
3189.1
Specifications HCTS75MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W
29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Noise Immunity
Functional Test
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
FN
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
20
µA
2, 3
+125oC, -55oC
-
400
µA
1
+25oC
4.8
-
mA
2, 3
+125oC, -55oC
4.0
-
mA
1
+25oC
-4.8
-
mA
2, 3
+125oC, -55oC
-4.0
-
mA
VCC = 5.5V, VIH = 2.75V,
VIL = 0.8V, IOL = 50µA
1, 2, 3
+25oC, +125oC,
-55oC
-
0.1
V
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, IOL = 50µA
1, 2, 3
+25oC, +125oC,
-55oC
-
0.1
V
VCC = 5.5V, VIH = 2.75V,
VIL = 0.8V, IOH = -50µA
1, 2, 3
+25oC, +125oC,
-55oC
VCC -0.1
-
V
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, IOH = -50µA
1, 2, 3
+25oC, +125oC,
-55oC
VCC -0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-0.5
+0.5
µA
2, 3
+125oC, -55oC
-5.0
+5.0
µA
7, 8A, 8B
+25oC, +125oC,
-55oC
-
-
V
(NOTE 1)
CONDITIONS
VCC = 5.5V,
VIN = VCC or GND
VCC = VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
VCC = VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
471
518625
Specifications HCTS75MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
D to Q
SYMBOL
TPLH
TPHL
Propagation Delay
D to Q
TPLH
TPHL
Propagation Delay
E to Q
TPLH
TPHL
Propagation Delay
E to Q
(NOTES 1, 2)
CONDITIONS
TPLH
TPHL
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
GROUP
A SUBGROUPS
LIMITS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
19
ns
10, 11
+125oC, -55oC
2
24
ns
9
+25oC
2
27
ns
10, 11
+125oC, -55oC
2
35
ns
9
+25oC
2
23
ns
10, 11
+125oC, -55oC
2
29
ns
9
+25oC
2
19
ns
10, 11
+125oC, -55oC
2
22
ns
9
+25oC
2
21
ns
10, 11
+125oC, -55oC
2
25
ns
9
+25oC
2
20
ns
10, 11
+125oC, -55oC
2
23
ns
9
+25oC
2
24
ns
10, 11
+125oC, -55oC
2
29
ns
9
+25oC
2
28
ns
10, 11
+125oC, -55oC
2
34
ns
NOTES:
1. All voltages referenced to device GND.
2. Measurements made with RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Capacitance Power
Dissipation
CPD
Input Capacitance
CIN
Pulse Width Time
Setup Time
Hold Time
Output Transition
Time
TW
TSU
TH
TTHL,
TTLH
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
36
pF
1
+125oC, -55oC
-
51
pF
1
+25oC
-
10
pF
1
+125oC, -55oC
-
10
pF
1
+25oC
-
16
ns
1
+125oC, -55oC
-
24
ns
1
+25oC
-
12
ns
1
+125oC, -55oC
-
18
ns
1
+25oC
-
12
ns
1
+125oC, -55oC
-
18
ns
1
+25oC
15
ns
1
+125oC, -55oC
22
ns
VCC = 5.0V, f = 1MHz
VCC = 5.0V, f = 1MHz
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
472
518625
Specifications HCTS75MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
PARAMETERS
(NOTE 1)
CONDITIONS
SYMBOL
TEMPERATURE
MIN
MAX
UNITS
Supply Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.4
mA
Output Current
(Sink)
IOL
VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0V
+25oC
4.0
-
mA
Output Current
(Source)
IOH
VCC = VIH = 4.5V, VOUT = VCC - 0.4V,
VIL = 0V
+25oC
-4.0
-
mA
Output Voltage Low
VOL
VCC = 5.5V, VIH = 2.75V, VIL = 0.8V,
IOL = 50µA
+25oC
-
0.1
V
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
IOL = 50µA
+25oC
-
0.1
V
VCC = 5.5V, VIH = 2.75V, VIL = 0.8V,
IOH = -50µA
+25oC
VCC
-0.1
-
V
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
IOH = -50µA
+25oC
VCC
-0.1
-
V
µA
Output Voltage High
VOH
Input Leakage
Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25oC
-5
+5
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
(Note 3)
+25oC
-
-
TPHL
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
35
ns
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
24
ns
TPHL
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
22
ns
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
29
ns
TPHL
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
23
ns
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
25
ns
TPHL
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
34
ns
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
29
ns
Propagation Delay
D to Q
Propagation Delay
D to Q
Propagation Delay
E to Q
Propagation Delay
E to Q
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
±6µA
IOL/IOH
5
-15% of 0 Hour
PARAMETER
Spec Number
473
518625
Specifications HCTS75MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Sample/5005
1, 7, 9
Group A (Note 1)
Group B
Group D
READ AND RECORD
ICC, IOL/H
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
NOTES:
1. Alternate group A inspection in accordance with method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE
GROUPS
Group E Subgroup 2
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
-
5
-
-
-
2, 3, 4, 5, 6, 7, 13
-
-
1, 8, 9, 10, 11, 14, 15, 16
5
4, 13
2, 3, 6, 7
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
1, 8, 9, 10, 11, 14, 15, 16
2, 3, 4, 6, 7, 12, 13
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
1, 8, 9, 10, 11, 14, 15, 16
12
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
12
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
1, 8, 9, 14, 15, 16
12
2, 3, 4, 5, 6, 7, 10, 11, 13
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group
E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
474
518625
HCTS75MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
475
518625
HCTS75MS
Propagation Delay Timing Diagram and Load Circuit
VIH
DUT
INPUT
VS
VSS
TEST
50pF
TPLH
500Ω
TPHL
VOH
VS
OUTPUT
VOL
Transition Timing Diagram
VOLTAGE LEVELS
TTLH
VOH
TTHL
80%
20%
VOL
PARAMETER
80%
OUTPUT
20%
HCTS
UNITS
VCC
4.50
V
VIH
3.00
V
VS
1.30
V
VIL
0
V
GND
0
V
Pulse Width, Setup, Hold Timing Diagram and Load Circuit
DUT
D INPUT
VIH
VS
TEST
50pF
500Ω
VIL
TH
TSU
E INPUT
VIH
TW
VOLTAGE LEVELS
PARAMETER
VS
VIL
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
HCTS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
Pulse Width, Setup, Hold Timing Diagram Negative Edge Trigger and Load Circuit
DUT
TW
INPUT
VIH
VS
TEST
50pF
500Ω
VIL
TH
TSU
INPUT CP
VIH
TW
VOLTAGE LEVELS
PARAMETER
VS
VIL
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
HCTS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
Spec Number
476
518625
HCTS75MS
Die Characteristics
DIE DIMENSIONS:
89 x 88 mils
2.25 x 2.24mm
METALLIZATION:
Type: SiAl
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCTS75MS
D0 1
(2)
Q0 1
(1)
Q0 1
(16)
(15) 1 Q1
D1 1 (3)
(14) 1 Q1
E 2 (4)
VCC (5)
(13) 1 E
(12) GND
D0 2 (6)
(11) 2 Q0
D1 2 (7)
(8)
Q1 2
(9)
Q1 2
(10)
Q0 2
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCTS75 is TA14442A.
Spec Number
477
518625
HCTS75MS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number
478