Data Sheet

74AUP1G74-Q100
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 1 — 27 May 2015
Product data sheet
1. General description
The 74AUP1G74-Q100 provides a low-power, low-voltage single positive-edge triggered
D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-12 (0.8 V to 1.3 V)
 JESD8-11 (0.9 V to 1.65 V)
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-B (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
 HBM JESD22-A114F Class 3A. Exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Low static power consumption; ICC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial power-down mode operation
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
74AUP1G74DC-Q100 40 C to +125 C
Description
Version
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74AUP1G74DC-Q100
p74
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
6'
'
&3
6'
4
'
4
6
&3
))
4
&
4
'
5'
5'
Fig 1.
Logic symbol
74AUP1G74_Q100
Product data sheet
5
DDK
DDK
Fig 2.
IEC logic symbol
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74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
4
&
&
&
&
'
4
&
&
5'
6'
DDH
&3
&
&
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
$83*4
&3
9&&
'
6'
4
5'
*1'
4
DDD
Fig 4.
Pin configuration SOT765-1
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
CP
1
clock input
D
2
data input
Q
3
complement output
GND
4
ground (0 V)
Q
5
true output
RD
6
asynchronous reset input (active LOW)
SD
7
asynchronous set input (active LOW)
VCC
8
supply voltage
74AUP1G74_Q100
Product data sheet
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Rev. 1 — 27 May 2015
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74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
7. Functional description
Table 4.
Function table for asynchronous operation[1]
Input
Output
SD
RD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Table 5.
Function table for synchronous operation[1]
Input
Output
SD
RD
CP
D
Qn+1
Qn+1
H
H

L
L
H
H
H

H
H
L
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
 = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
Conditions
VI < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
0.5
+4.6
50
-
0.5
+4.6
V
-
20
mA
mA
VI
input voltage
IOK
output clamping current
VO < 0 V
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
ICC
supply current
-
+50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
Tamb = 40 C to +125 C
[1]
[2]
[1]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
V
mA
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NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
9. Recommended operating conditions
Table 7.
Operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Conditions
Tamb
ambient temperature
t/V
input transition rise and fall rate
Min
Max
Unit
0.8
3.6
V
0
3.6
V
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
40
+125
C
-
200
ns/V
VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 0.8 V
0.70  VCC
-
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
Tamb = 25 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
74AUP1G74_Q100
Product data sheet
VI = VIH or VIL
IO = 1.1 mA; VCC = 1.1 V
0.75  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.11
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.32
-
-
V
IO = 2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.6
-
-
V
0.1
V
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
IO = 1.1 mA; VCC = 1.1 V
-
-
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
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Rev. 1 — 27 May 2015
0.3  VCC V
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74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.1
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.2
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V; per pin
-
-
40
A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.6
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.3
-
pF
VCC = 0.8 V
0.70  VCC
-
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
-
V
[1]
Tamb = 40 C to +85 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
2.0
-
VCC = 0.8 V
-
-
0.30  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.7  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.03
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.30
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.55
-
-
V
-
-
0.1
V
VI = VIH or VIL
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
0.3  VCC V
IO = 1.1 mA; VCC = 1.1 V
-
-
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.5
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.6
A
74AUP1G74_Q100
Product data sheet
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Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V; per pin
-
-
50
A
VCC = 0.8 V
0.75  VCC
-
-
V
VCC = 0.9 V to 1.95 V
0.70  VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.25  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.30  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
[1]
Tamb = 40 C to +125 C
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
VOH
HIGH-level output voltage
LOW-level output voltage
VOL
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.11
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.6  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
0.93
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.17
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.11
V
IO = 1.1 mA; VCC = 1.1 V
-
-
IO = 1.7 mA; VCC = 1.4 V
-
-
VI = VIH or VIL
0.33  VCC V
0.41
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.75
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V; per pin
-
-
75
A
[1]
[1]
One input at VCC  0.6 V, other input at VCC or GND.
74AUP1G74_Q100
Product data sheet
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Rev. 1 — 27 May 2015
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74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Min
Max
(125 C)
-
25.4
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.9
6.7
14.0
2.6
14.2
2.6
14.2
ns
VCC = 1.4 V to 1.6 V
2.4
4.5
7.6
2.3
8.3
2.3
8.6
ns
VCC = 1.65 V to 1.95 V
1.9
3.5
5.7
1.7
6.5
1.7
6.8
ns
VCC = 2.3 V to 2.7 V
1.7
2.6
3.8
1.4
4.4
1.4
4.7
ns
1.5
2.2
3.1
1.2
3.4
1.2
3.7
ns
-
19.6
-
-
-
-
-
ns
2.7
5.6
11.0
2.5
11.4
2.5
11.5
ns
VCC = 1.4 V to 1.6 V
2.4
4.0
6.3
2.2
6.9
2.2
7.3
ns
VCC = 1.65 V to 1.95 V
2.0
3.3
4.9
1.7
5.6
1.7
5.9
ns
VCC = 2.3 V to 2.7 V
1.9
2.7
3.7
1.7
4.0
1.7
4.2
ns
1.8
2.5
3.2
1.5
3.6
1.5
3.8
ns
-
19.2
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.6
5.5
11.0
2.5
11.3
2.5
11.5
ns
VCC = 1.4 V to 1.6 V
2.3
3.9
6.3
2.2
6.8
2.2
7.3
ns
CL = 5 pF
tpd
propagation
delay
CP to Q, Q; see Figure 5
[2]
VCC = 0.8 V
VCC = 3.0 V to 3.6 V
SD to Q, Q; see Figure 6
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 3.0 V to 3.6 V
RD to Q, Q; see Figure 6
VCC = 0.8 V
fmax
maximum
frequency
74AUP1G74_Q100
Product data sheet
[2]
VCC = 1.65 V to 1.95 V
1.9
3.2
5.0
1.8
5.6
1.8
5.9
ns
VCC = 2.3 V to 2.7 V
1.9
2.6
3.6
1.7
4.1
1.7
4.3
ns
VCC = 3.0 V to 3.6 V
1.8
2.4
3.3
1.5
3.6
1.5
3.8
ns
CP; see Figure 5
VCC = 0.8 V
-
53
-
-
-
-
-
MHz
VCC = 1.1 V to 1.3 V
-
203
-
170
-
170
-
MHz
VCC = 1.4 V to 1.6 V
-
347
-
310
-
300
-
MHz
VCC = 1.65 V to 1.95 V
-
435
-
400
-
390
-
MHz
VCC = 2.3 V to 2.7 V
-
550
-
490
-
480
-
MHz
VCC = 3.0 V to 3.6 V
-
619
-
550
-
510
-
MHz
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Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Min
Max
(125 C)
-
28.9
-
-
-
-
-
ns
3.1
7.5
15.8
2.9
16.1
2.9
16.1
ns
VCC = 1.4 V to 1.6 V
2.7
5.1
8.7
2.4
9.4
2.4
9.8
ns
VCC = 1.65 V to 1.95 V
2.5
4.1
6.5
2.2
7.2
2.2
7.6
ns
VCC = 2.3 V to 2.7 V
2.0
3.2
4.6
1.8
5.3
1.8
5.6
ns
1.8
2.8
3.8
1.6
4.1
1.6
4.4
ns
-
23.2
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.9
6.5
12.9
2.8
13.3
2.8
13.5
ns
VCC = 1.4 V to 1.6 V
2.7
4.6
7.5
2.3
7.9
2.3
8.3
ns
VCC = 1.65 V to 1.95 V
2.6
3.9
5.6
2.3
6.3
2.3
6.6
ns
VCC = 2.3 V to 2.7 V
2.3
3.2
4.4
2.0
4.8
2.0
5.2
ns
2.2
3.0
3.9
1.9
4.2
1.9
4.4
ns
CL = 10 pF
tpd
propagation
delay
CP to Q, Q; see Figure 5
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 3.0 V to 3.6 V
SD to Q, Q; see Figure 6
[2]
VCC = 0.8 V
VCC = 3.0 V to 3.6 V
RD to Q, Q; see Figure 6
VCC = 0.8 V
fmax
maximum
frequency
74AUP1G74_Q100
Product data sheet
[2]
-
22.7
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.8
6.4
12.8
2.7
13.2
2.7
13.4
ns
VCC = 1.4 V to 1.6 V
2.6
4.5
7.5
2.3
8.1
2.3
8.4
ns
VCC = 1.65 V to 1.95 V
2.5
3.3
5.8
2.3
6.3
2.3
6.7
ns
VCC = 2.3 V to 2.7 V
2.2
3.2
4.4
2.0
4.9
2.0
5.2
ns
VCC = 3.0 V to 3.6 V
2.0
2.9
4.0
1.9
4.3
1.9
4.5
ns
VCC = 0.8 V
-
52
-
-
-
-
-
MHz
VCC = 1.1 V to 1.3 V
-
192
-
150
-
150
-
MHz
VCC = 1.4 V to 1.6 V
-
324
-
280
-
230
-
MHz
VCC = 1.65 V to 1.95 V
-
421
-
310
-
250
-
MHz
VCC = 2.3 V to 2.7 V
-
486
-
370
-
360
-
MHz
VCC = 3.0 V to 3.6 V
-
550
-
410
-
360
-
MHz
CP; see Figure 5
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Min
Max
(125 C)
-
32.4
-
-
-
-
-
ns
3.5
8.3
17.6
3.3
17.8
3.3
18.0
ns
VCC = 1.4 V to 1.6 V
3.2
5.6
9.5
2.8
10.5
2.8
11.1
ns
VCC = 1.65 V to 1.95 V
2.7
4.6
7.2
2.5
8.1
2.5
8.6
ns
VCC = 2.3 V to 2.7 V
2.4
3.6
5.2
2.2
5.8
2.2
6.2
ns
2.2
3.2
4.4
2.0
4.9
2.0
5.2
ns
-
26.7
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.3
7.3
14.7
3.1
15.2
3.1
15.4
ns
VCC = 1.4 V to 1.6 V
3.2
5.2
8.3
2.9
9.0
2.9
9.5
ns
VCC = 1.65 V to 1.95 V
2.8
4.3
6.4
2.5
7.1
2.5
7.5
ns
VCC = 2.3 V to 2.7 V
2.8
3.7
5.1
2.2
5.5
2.2
5.8
ns
2.5
3.5
4.6
2.4
5.0
2.4
5.2
ns
CL = 15 pF
tpd
propagation
delay
CP to Q, Q; see Figure 5
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
VCC = 3.0 V to 3.6 V
SD to Q, Q; see Figure 6
[2]
VCC = 0.8 V
VCC = 3.0 V to 3.6 V
RD to Q, Q; see Figure 6
VCC = 0.8 V
fmax
maximum
frequency
74AUP1G74_Q100
Product data sheet
[2]
-
26.1
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.2
7.2
14.5
3.1
15.0
3.1
15.2
ns
VCC = 1.4 V to 1.6 V
3.1
5.1
8.4
2.7
9.2
2.7
9.7
ns
VCC = 1.65 V to 1.95 V
2.7
4.3
6.5
2.6
7.3
2.6
7.7
ns
VCC = 2.3 V to 2.7 V
2.6
3.6
5.0
2.4
5.5
2.4
5.8
ns
VCC = 3.0 V to 3.6 V
2.4
3.4
4.6
2.3
5.0
2.3
5.2
ns
VCC = 0.8 V
-
50
-
-
-
-
-
MHz
VCC = 1.1 V to 1.3 V
-
181
-
120
-
120
-
MHz
VCC = 1.4 V to 1.6 V
-
301
-
190
-
160
-
MHz
VCC = 1.65 V to 1.95 V
-
407
-
240
-
190
-
MHz
VCC = 2.3 V to 2.7 V
-
422
-
300
-
270
-
MHz
VCC = 3.0 V to 3.6 V
-
481
-
320
-
300
-
MHz
CP; see Figure 5
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Min
Max
(125 C)
-
42.7
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.2
10.6
22.5
4.0
23.0
4.0
23.3
ns
VCC = 1.4 V to 1.6 V
3.7
7.2
12.0
3.7
13.3
3.7
14.0
ns
VCC = 1.65 V to 1.95 V
3.5
5.8
9.2
3.4
10.4
3.4
11.0
ns
VCC = 2.3 V to 2.7 V
3.3
4.7
6.6
3.0
7.3
3.0
7.8
ns
3.0
4.3
5.8
2.8
6.8
2.8
7.3
ns
-
37.0
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.0
9.5
19.8
3.8
20.8
3.8
21.1
ns
VCC = 1.4 V to 1.6 V
3.8
6.7
10.9
3.7
12.0
3.7
12.7
ns
VCC = 1.65 V to 1.95 V
3.7
5.6
8.4
3.5
9.3
3.5
9.9
ns
VCC = 2.3 V to 2.7 V
3.7
4.8
6.6
3.2
7.2
3.2
7.6
ns
3.4
4.6
6.0
3.1
6.8
3.1
7.1
ns
CL = 30 pF
tpd
propagation
delay
CP to Q, Q; see Figure 5
[2]
VCC = 0.8 V
VCC = 3.0 V to 3.6 V
SD to Q, Q; see Figure 6
[2]
VCC = 0.8 V
VCC = 3.0 V to 3.6 V
RD to Q, Q; see Figure 6
VCC = 0.8 V
fmax
maximum
frequency
74AUP1G74_Q100
Product data sheet
[2]
-
36.4
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.9
9.4
19.5
3.8
20.2
3.8
20.5
ns
VCC = 1.4 V to 1.6 V
3.6
6.6
10.9
3.7
12.0
3.7
12.6
ns
VCC = 1.65 V to 1.95 V
3.5
5.5
8.5
3.5
9.5
3.5
10.1
ns
VCC = 2.3 V to 2.7 V
3.5
4.7
6.5
3.2
7.1
3.2
7.6
ns
VCC = 3.0 V to 3.6 V
3.3
4.4
6.1
3.1
7.1
3.1
7.5
ns
VCC = 0.8 V
-
28
-
-
-
-
-
VCC = 1.1 V to 1.3 V
-
145
-
70
-
70
-
MHz
VCC = 1.4 V to 1.6 V
-
185
-
120
-
110
-
MHz
VCC = 1.65 V to 1.95 V
-
270
-
150
-
120
-
MHz
VCC = 2.3 V to 2.7 V
-
290
-
190
-
170
-
MHz
VCC = 3.0 V to 3.6 V
-
315
-
200
-
190
-
MHz
CP; see Figure 5
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
MHz
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Min
Max
(125 C)
VCC = 0.8 V
-
3.4
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
-
0.6
-
1.2
-
1.2
-
ns
CL = 5 pF, 10 pF, 15 pF and 30 pF
tsu
set-up time
D to CP HIGH; see Figure 5
VCC = 1.4 V to 1.6 V
-
0.3
-
0.6
-
0.6
-
ns
VCC = 1.65 V to 1.95 V
-
0.4
-
0.5
-
0.5
-
ns
VCC = 2.3 V to 2.7 V
-
0.2
-
0.4
-
0.4
-
ns
VCC = 3.0 V to 3.6 V
-
0.3
-
0.4
-
0.4
-
ns
VCC = 0.8 V
-
3.0
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
-
0.5
-
1.2
-
1.2
-
ns
VCC = 1.4 V to 1.6 V
-
0.3
-
0.7
-
0.7
-
ns
D to CP LOW; see Figure 5
th
trec
hold time
recovery time
VCC = 1.65 V to 1.95 V
-
0.4
-
0.7
-
0.7
-
ns
VCC = 2.3 V to 2.7 V
-
0.5
-
0.7
-
0.7
-
ns
VCC = 3.0 V to 3.6 V
-
0.6
-
0.8
-
0.8
-
ns
D to CP; see Figure 5
VCC = 0.8 V
-
1.9
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
-
0.3
-
0.5
-
0.5
-
ns
VCC = 1.4 V to 1.6 V
-
0.2
-
0.2
-
0.2
-
ns
VCC = 1.65 V to 1.95 V
-
0.2
-
0.1
-
0.1
-
ns
VCC = 2.3 V to 2.7 V
-
0.2
-
0.1
-
0.1
-
ns
VCC = 3.0 V to 3.6 V
-
0.2
-
0.1
-
0.1
-
ns
-
0.5
-
0.9
-
0.9
-
ns
VCC = 1.4 V to 1.6 V
-
0.2
-
0.6
-
0.6
-
ns
VCC = 1.65 V to 1.95 V
-
0.2
-
0.4
-
0.4
-
ns
VCC = 2.3 V to 2.7 V
-
0.1
-
0.1
-
0.1
-
ns
VCC = 3.0 V to 3.6 V
-
0.1
-
0.1
-
0.1
-
ns
VCC = 1.1 V to 1.3 V
-
0.5
-
0.3
-
0.3
-
ns
VCC = 1.4 V to 1.6 V
-
0.4
-
0.1
-
0.1
-
ns
VCC = 1.65 V to 1.95 V
-
0.3
-
0
-
0
-
ns
VCC = 2.3 V to 2.7 V
-
0.2
-
0.1
-
0.1
-
ns
VCC = 3.0 V to 3.6 V
-
0.1
-
0.1
-
0.1
-
ns
RD; see Figure 6
VCC = 1.1 V to 1.3 V
SD; see Figure 6
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
tW
pulse width
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Min
Max
(125 C)
VCC = 1.1 V to 1.3 V
-
2.1
-
2.7
-
2.7
-
ns
VCC = 1.4 V to 1.6 V
-
1.1
-
1.5
-
1.5
-
ns
CP HIGH or LOW;
see Figure 5
VCC = 1.65 V to 1.95 V
-
0.9
-
1.6
-
1.6
-
ns
VCC = 2.3 V to 2.7 V
-
0.6
-
1.7
-
1.7
-
ns
VCC = 3.0 V to 3.6 V
-
0.6
-
1.9
-
1.9
-
ns
VCC = 1.1 V to 1.3 V
-
4.2
-
11.3
-
11.5
-
ns
VCC = 1.4 V to 1.6 V
-
2.3
-
6.2
-
6.4
-
ns
VCC = 1.65 V to 1.95 V
-
1.8
-
4.8
-
5.0
-
ns
VCC = 2.3 V to 2.7 V
-
1.2
-
3.3
-
3.5
-
ns
VCC = 3.0 V to 3.6 V
-
1.1
-
2.6
-
2.8
-
ns
VCC = 0.8 V
-
2.8
-
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
2.9
-
-
-
-
-
pF
VCC = 1.4 V to 1.6 V
-
3.0
-
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
3.0
-
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
3.5
-
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
3.9
-
-
-
-
-
pF
SD or RD LOW;
see Figure 6
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
12. Waveforms
W:
9,
&3LQSXW
90
*1'
IPD[
9,
90
'LQSXW
*1'
WK
WK
W VX
W VX
W 3+/
W 3/+
92+
90
4RXWSXW
92/
92+
4RXWSXW
90
92/
W 3/+
W 3+/
DDH
Measurement points are given in Table 10.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
The clock input (CP) to output (Q, Q) propagation delays, the data input (D) to clock input (CP) set-up and
hold times and the clock input (CP) pulse width and maximum frequency
Table 10.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5  VCC
0.5  VCC
VCC
 3.0 ns
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
9,
&3LQSXW
90
*1'
W UHF
9,
6'LQSXW
90
W UHF
*1'
W:
W:
9,
90
5'LQSXW
*1'
W 3/+
W 3+/
W 3+/
W 3/+
92+
90
4RXWSXW
92/
92+
90
4RXWSXW
92/
DDH
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
The set input (SD) and reset input (RD) to output (Q, Q) propagation delays, the set input (SD) and reset
input (RD) pulse widths and the reset input (RD) to clock input (CP) recovery time
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
9&&
9(;7
Nȍ
*
9,
92
'87
57
&/
5/
DDF
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7.
Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Load
VEXT
[1]
VCC
CL
RL
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 k or 1 M
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2  VCC
For measuring enable and disable times RL = 5 k
For measuring propagation delays, setup and hold times and pulse width RL = 1 M.
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
13. Package outline
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74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
14. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
15. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP1G74_Q100 v.1
20150527
Product data sheet
-
-
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP1G74_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
19 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AUP1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
20 of 21
74AUP1G74-Q100
NXP Semiconductors
Low-power D-type flip-flop with set and reset; positive-edge trigger
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 May 2015
Document identifier: 74AUP1G74_Q100