Download

THC63LVD1023B_Rev.3.0_E
THC63LVD1023B
160MHz 67Bits LVDS Transmitter
General Description
Features
The THC63LVD1023B transmitter is designed to suport
Single Link transmission between Host and Flat Panel
Display up to 1080p(60Hz) resolutions and Dual Link
transmission between Host and Flat Panel Display up to
1080p(120Hz).
The THC63LVD1023B converts 67bits of CMOS/TTL
data into LVDS (Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin,
and support double edge inputs.
In Dual Link, the transmit clock frequency of 160MHz,
67bits of RGB data are transmitted at an effective rate
of 1.12Gbps per LVDS channel.
In Asynchronous mode, the THC63LVD1023B has 2
independent 35Bits Transmitter.
• Wide dot clock range suited for TV Signal (480i1080p), PC Signal (VGA-QXGA)
TTL/CMOS Input: 10-160MHz
LVDS Output: 20-160MHz
• PLL requires No external components
• Flexible Input/Output mode
1. Single/Dual TTL IN, Single/Dual LVDS OUT
2. Double edge input for Single TTL IN/Dual LVDS OUT
3. Input port SW for Single TTL IN/Dual LVDS OUT
4. Asynchronous Dual TTL IN/Dual LVDS OUT
•
•
•
•
•
•
•
•
Clock edge selectable
3 LVDS data mapping for simplifying PCB layout.
Pseudo Random pattern generation circuit
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
Backward compatible with THC63LVD1023
144pin LQFP
R2[9:0]
G2[9:0]
B2[9:0]
DATA Port2
32
CONT2[2:1]
Hsync1
Vsync1
DE1
Hsync2
Vsync2
DE2
6
Data Formatter
CONT1[2:1]
35
TA1 +/TB1 +/TC1 +/-
LVDS OUTPUT
Port1
TD1 +/TE1 +/-
R/F
RS
PARALLEL TO SERIAL
32
35
MAP
MODE[3:0]
/PDWN
PARALLEL TO SERIAL
DATA Port1
1) DEMUX
2) MUX
3) Distribution
4) DDR
R1[9:0]
G1[9:0]
B1[9:0]
5) Input Port SW
6) Crosspoint
Block Diagram
TA2 +/TB2 +/TC2 +/-
LVDS OUTPUT
Port2
TD2 +/TE2 +/-
PRBS
ASYNC
TCLK1 +/CLKIN1
CLKIN2
MUX
PLL
TCLK2 +/-
TRANSMITTER CLOCK IN
(10 to 160MHz)
Copyright©2011 THine Electronics, Inc.
(20 to 160MHz)
1/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B16/TD15
B15/TD14
B14/TD13
GND
VCC
B13/TD12
B12/TD11
B11/TD10
B10/TC16
G19/TC15
G18/TC14
G17/TC13
G16/TC12
G15/TC11
GND
VCC
G14/TC10
G13/TB16
G12/TB15
G11/TB14
G10/TB13
R19/TB12
R18/TB11
R17/TB10
R16/TA16
GND
VCC
R15/TA15
R14/TA14
R13/TA13
R12/TA12
R11/TA11
R10/TA10
PGND
PVCC
PGND
Pin Out (top view)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
LGND
TA1TA1+
TB1TB1+
LVCC
LGND
TC1TC1+
TCLK1TCLK1+
LVCC
LGND
TD1TD1+
TE1TE1+
LVCC
LGND
TA2TA2+
TB2TB2+
LVCC
LGND
TC2TC2+
TCLK2TCLK2+
LVCC
LGND
TD2TD2+
TE2TE2+
LGND
B26/TD20
B27/TD21
VCC
GND
B28/TD22
B29/TD23
HSYNC1/TD24
VSYNC1/TD25
DE1/TD26
HSYNC2/TE20
VSYNC2/TE21
DE2/TE22
VCC
GND
CLKIN1
CLKIN2
CONT11/TE23
CONT12/TE24
CONT21/TE25
CONT22/TE26
R/F
RS
MODE3
MAP
MODE1
MODE0
MODE2
ASYNC
N/C
/PDWN
PRBS
Reserved
N/C
PGND
PVCC
PGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N/C
B17/TD16
B18/TE10
B19/TE11
VCC
GND
R20/TE12
R21/TE13
R22/TE14
R23/TE15
R24/TE16
R25/TA20
R26/TA21
R27/TA22
R28/TA23
R29/TA24
VCC
GND
G20/TA25
G21/TA26
G22/TB20
G23/TB21
G24/TB22
G25/TB23
G26/TB24
G27/TB25
G28/TB26
G29/TC20
VCC
GND
B20/TC21
B21/TC22
B22/TC23
B23/TC24
B24/TC25
B25/TC26
Copyright©2011 THine Electronics, Inc.
2/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
Pin Description
Pin Name
ASYNC=L
ASYNC=H
Pin #
TA1+, TA1-
70, 71
TB1+, TB1-
68, 69
TC1+, TC1-
64, 65
TD1+, TD1-
58, 59
TE1+, TE1-
56, 57
TCLK1+, TCLK1-
62, 63
TA2+, TA2-
52, 53
TB2+, TB2-
50, 51
TC2+, TC2-
46, 47
TD2+, TD2-
40, 41
TE2+, TE2-
38, 39
Type
The 1st Link.
The 1st pixel output data when Dual-Link.
LVDS Clock Out for 1st and 2nd Link.
The 2nd Link.
These pins are disabled when Single Link.
LVDS
OUT
TCLK2+, TCLK2-
Description
44, 45
See following table.
ASYNC
MODE0
MODE1
MODE2
Description
H
x
x
L
Case1
H
x
x
H
Case2
L
L
x
x
Case3
L
H
L
x
Case4
L
H
H
L
Case4
L
H
H
H
Case3
Case1: LVDS Clock out for 2nd link.
Case2: LVDS Clock out for 1st link.
Case3: Additional LVDS Clock out.
Identical to TCLK1+/Case4: Not available (High-Impedance)
R19 ~ R10
TB12~TB10,
TA16~TA10
87 - 84,
G19 ~ G10
TC15~TC10,
TB16~TB13
99 - 95,
112 -110,
B19 ~ B10
TE11~TE10,
TD16~TD10,
TC16
108 -106,
TA24~TA20,
TE16~TE12
124 - 115
R29 ~ R20
81 - 76
92 - 88
ASYNC=L
IN
B29 ~ B20
ASYNC=H
Data Inputs.
103 - 100
ASYNC=L
TC20,
G29 ~ G20
The 1st Pixel Data Inputs.
TB26~TB20,
TA26~TA25
136 - 127
TD23~TD20,
TC26~TC21
6, 5, 2, 1,
IN
The 2nd Pixel Data Inputs.
ASYNC=H
Data Inputs.
144 - 139
Copyright©2011 THine Electronics, Inc.
3/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
Pin Description (Continued)
Pin Name
ASYNC=L
CONT11 *1,
CONT12 *1
ASYNC=H
Pin #
TE23,TE24
17, 18
Type
IN
*1
CONT21 ,
CONT22 *1
DE1,DE2
VSYNC1,
VSYNC2
HSYNC1,
HSYNC2
TE25,TE26
19, 20
TD26,TE22
9,12
IN
TD25,TE21
8,11
IN
TD24,TE20
7,10
IN
Description
ASYNC=L: CONTROL Data Inputs.
ASYNC=H: Data Inputs.
ASYNC=L: Data Enable Inputs.
ASYNC=H: Data Inputs.
ASYNC=L: Vsync Inputs.
ASYNC=H: Data Inputs
ASYNC=L: Hsync Inputs.
ASYNC=H: Data Inputs
Clock Input of following cases.
CLKIN1
15
IN
ASYNC
MODE1
MODE0
MODE3
H
x
x
x
L
L
x
x
L
H
L
H
L
H
H
x
MODE0
MODE3
Clock Input of following cases.
ASYNC
CLKIN2
R/F
16
21
IN
IN
MODE1
H
x
x
x
L
H
L
L
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
LVDS swing mode, VREF select. See Fig4, 5.
RS
22
IN
RS
LVDS
Swing
Small Swing
Input Support
VIHM
350mV
N/A
VIMM
350mV
RS=VREFa
VILM
200mV
N/A
a. VREF is Input Reference Voltage.
LVDS mapping table select.
MAP
(See Fig7 to 9 and
24
MAP
VIHM
VILM
VIMM
IN
Table4 to10)
Mapping Mode
Mapping MODE1
Mapping MODE2
Mapping MODE3
Pixel Data Mode.
MODE1, MODE0
25, 26
MODE1
L
H
L
H
IN
MODE0
L
L
H
H
Mode
Dual Link (Dual-in/Dual-out)
Dual Link (Single-in/Dual-out)
Single Link (Dual-in/Single-out)
Single Link (Single-in/Single-out)
*1: CONT## are DATA pins that user can use as data like RGB data.
Copyright©2011 THine Electronics, Inc.
4/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
Pin Name
ASYNC=L
ASYNC=H
Pin #
Type
Description
The use of these multi-function depends on the setting
of MODE<1:0> or ASYNC.
ASYNC=H(MODE<1:0>=Don’t care.)
H: Cross point switching enable.
L: Cross point switching disable.
MODE2
(See Fig.5)
ASYNC=L
27
IN
MODE<1:0>=HH(Single-in/Single-out Mode)
H: Distribution function enable.
L: Distribution function disable.
MODE<1:0>=HL(Single-in/Dual-out Mode)
H: DDR (Double Edge input) function enable.
L: DDR (Double Edge input) function disable.
Input port switching function enable when
MODE<1:0>=HL(Single-in/Dual-out Mode).
MODE3
23
IN
H or Open: Port switch disable.
L: Port switch enable.
Asynchronous function enable.
ASYNC
28
IN
H: Asynchronous mode enable.(MODE<1:0>=Disable)
L: Asynchronous mode disable.(MODE<1:0>=Enable)
/PDWN
PRBS *2
30
31
IN
IN
H: Normal operation,
L: Power down (all outputs are Hi-Z)
PRBS (Pseudo-Random Binary Sequence) generator
is active in order to evaluate eye patterns when
MODE<1:0> = LL (Dual-in/Dual-out mode) or
ASYNC=H
H: PRBS generator is enable.
L: Normal Operation
Reserved
32
IN
Must be tied to GND.
N/C
29, 33, 109
VCC
3, 13, 82, 93,
104, 113,
125, 137
Power
Power Supply Pins for TTL inputs and digital circuitry.
GND
4, 14, 83, 94,
105, 114,
126, 138
Ground
Ground Pins for TTL inputs and digital circuitry.
LVCC
43, 49, 55,
61, 67
Power
Power Supply Pins for LVDS Outputs.
LGND
37, 42, 48,
54, 60, 66, 72
Ground
Ground Pins for LVDS Outputs.
PVCC
35, 74
Power
Power Supply Pins for PLL circuitry.
Must be Open.
PGND
34, 36, 73, 75 Ground Ground Pins for PLL circuitry.
*2: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of
223-1. The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and serialized
into TXOUT output. This function is normally to be used for analyzing the signal integrity of the transmission
channel including PCB traces, connectors, and cables.
Copyright©2011 THine Electronics, Inc.
5/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
Absolute Maximum Ratings
Supply Voltage (VCC)
-0.3V ~ +4.0V
CMOS/TTL Input Voltage
-0.3V ~ (VCC + 0.3V)
LVDS Driver Output Voltage
-0.3V ~ (VCC + 0.3V)
Output Current
-30mA ~ 30mA
Junction Temperature
+125 °C
Storage Temperature Range
-55 °C ~ +125 °C
Reflow Peak Temperature / Time
+260 °C / 10sec.
Maximum Power Dissipation @+25 °C
2.4W
Recommended Operating Conditions
Parameter
Min.
Typ
Max
Units
All Supply Voltage
3.0
3.3
3.6
V
Operating Ambient Temperature
-20
70
°C
MODE<1:0>=LL
Input
20
160
MHz
Dual-in/Dual-out
LVDS Output
20
160
MHz
MODE<1:0>=LH
Input
10
80
MHz
Dual-in/Single-out
LVDS Output
20
160
MHz
Single Edge Input
Input
40
160
MHz
Clock
MODE<1:0>=HL
(MODE2=L)
LVDS Output
20
80
MHz
Frequency
Single-in/Dual-out
Double Edge Input
Input
20
80
MHz
(MODE2=H)
LVDS Output
20
80
MHz
MODE<1:0>=HH
Input
20
160
MHz
Single-in/Single-out
LVDS Output
20
160
MHz
ASYNC=H
Input
20
160
MHz
Asynchronous Mode
LVDS Output
20
160
MHz
Copyright©2011 THine Electronics, Inc.
6/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
Electrical Characteristics
CMOS/TTL DC Specifications
VCC = VCC=PVCC=LVCC
Symbol
Parameter
VIHa
High Level Data Input Voltage
VILa
Low Level Data Input Voltage
Conditions
Min.
RS=Vccor GND
RS=0.6~1.4V
Typ.
Max.
Units
VCC
2.0
VREFb+0.1
RS=Vccor GND
V
V
GND
RS=0.6~1.4V
0.8
V
VREF-0.1
V
VIHCc
High Level Control Input Voltage
2.0
VCC
V
VILCc
Low Level Control Input Voltage
GND
0.8
V
VIHMd
High Level Control Input Voltage
0.8VCC
VCC
V
VIMMd
Middle Level Control Input Voltage
0.6
1.4
V
VILMd
Low Level Control Input Voltage
GND
0.08VCC
V
IINC
Input Current (except MODE3)
GND ≤ V IN ≤ V CC
± 10
μA
Input Current (Only MODE3)
GND ≤ V IN ≤ V CC
± 20
μA
IINCM3
a. CLKIN1,R10~R19,G10~G19,B10~B19,DE1,HSYNC1,VSYNC1,CONT11,CONT12
CLKIN2,R20~R29,G20~G29,B20~B29,DE2,HSYNC2,VSYNC2,CONT21,CONT22
b. VREF is input voltage of RS pin.
c. R/F,MODE0,MODE1,MODE2,MODE3,PDWN,PRBS,ASYNC
d. RS,MAP
LVDS Transmitter DC Specifications
VCC = VCC=PVCC=LVCC
Symbol
Parameter
Conditions
Normal swing
VOD
Differential Output Voltage
RL=100Ω
RS= Vcc
Reduced swing
RS= GND
ΔVOD
VOC
Min.
Typ.
Max.
250
350
450
mV
100
200
300
mV
35
mV
Change in VOD between
complementary output states
Common Mode Voltage
ΔVOC
Change in VOC between
complementary output states
IOS
Output Short Circuit Current
IOZ
Output TRI-State current
Copyright©2011 THine Electronics, Inc.
RL=100Ω
1.125
VOUT=GND, RL=100Ω
/PDWN=GND,
VOUT=GND to VCC
7/26
1.25
1.375
Units
V
35
mV
-24
mA
± 10
μA
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
Electrical Characteristics (Continued)
Supply Current
VCC = VCC=PVCC=LVCC
Symbol
Parameter
Condition
ITCCW
Current
(Worst Case
Pattern) Fig1.
CL=5pF
RS=VCC
105
mA
Single-in/Single-out
CLKIN1=85MHz
121
mA
MODE2=L
CLKIN1=135MHz
157
mA
Distribution Off
CLKIN1=160MHz
179
mA
MODE<1:0>=HH
CLKIN1=65MHz
146
mA
Single-in/Single-out
CLKIN1=85MHz
172
mA
MODE2=H
CLKIN1=135MHz
217
mA
Distribution On
CLKIN1=160MHz
250
mA
MODE<1:0>=HL
CLKIN1/2=65MHz
108
mA
Single-in/Dual-out
CLKIN1/2=85MHz
136
mA
MODE2=L
CLKIN1/2=135MHz
169
mA
CLKIN1/2=160MHz
194
mA
MODE<1:0>=HL
CLKIN1/2=32.5MHz
120
mA
Single-in/Dual-out
CLKIN1/2=42.5MHz
140
mA
MODE2=H
CLKIN1/2=67.5MHz
183
mA
CLKIN1/2=80MHz
199
mA
CLKIN1=32.5MHz
95
mA
MODE<1:0>=LH
CLKIN1=42.5MHz
110
mA
Dual-in/Single-out
CLKIN1=67.5MHz
143
mA
CLKIN1=80MHz
166
mA
CLKIN1=65MHz
167
mA
MODE<1:0>=LL
CLKIN1=85MHz
197
mA
Dual-in/Dual-out
CLKIN1=135MHz
261
mA
CLKIN1=160MHz
301
mA
CLKIN1/2=65MHz
183
mA
ASYNC=H
CLKIN1/2=85MHz
214
mA
Asynchronous
CLKIN1/2=135MHz
286
mA
CLKIN1=160MHz
329
mA
50
μA
MODE3=H or L
DDR Input On
ITCCS
Transmitter Power
Down Supply
Units
CLKIN1=65MHz
DDR Input Off
RL=100Ω
Max.
MODE<1:0>=HH
MODE3=H or L
Transmitter Supply
Typ.
/PDWN = L, All Inputs = Fixed L or H
Current
TCLK1+
Txy+
x= A, B, C, D, E
y=1,2
Fig1. Test Pattern (LVDS Output Full Toggle Pattern)
Copyright©2011 THine Electronics, Inc.
8/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
Switching Characteristics
VCC = VCC=PVCC=LVCC
Symbol
Parameter
Min.
Typ.
Max.
Units
tTCIP
CLK IN Period(Fig4,5)
tTCH
CLK IN High Time(Fig4,5)
0.35tTCIP
tTCL
CLK IN Low Time(Fig4,5)
0.35tTCIP
tTS
TTL Data Setup to CLK IN(Fig4,5)
2.5
ns
tTH
TTL Data Hold from CKL IN(Fig4,5)
0.0
ns
6.25
CLK IN to TCLK+/- Delay(Fig4,5)
tTCD
MODE<1:0>=LL
Dual-in/Dual-out
tTCOP
tLVT
tTOP1
tTOP0
tTOP6
tTOP5
tTOP4
tTOP3
tTOP2
tTPLL
CLK OUT Period(Fig6)
100
ns
0.5tTCIP
0.65tTCIP
ns
0.5tTCIP
0.65tTCIP
ns
(4+3/7)tTCIP
(4+3/7)tTCIP
+2.6
+7.5
6.25
50
ns
0.6
1.5
ns
0.0
+0.15
ns
LVDS Transition Time(Fig2)
Output Data
-0.15
Position0 (Fig6)
Output Data
Position1 (Fig6)
Output Data
Position2 (Fig6)
tTCOP =
Output Data
Position3 (Fig6)
6.25ns~20ns
Output Data
Position4 (Fig6)
Output Data
Position5 (Fig6)
Output Data
Position6 (Fig6)
ns
t TCOP
--------------- – 0.15
7
t TCOP
--------------7
t TCOP
--------------+ 0.15
7
ns
t TCOP
2 --------------– 0.15
7
t TCOP
2 --------------7
t TCOP
2 --------------+ 0.15
7
ns
t TCOP
3 --------------– 0.15
7
t TCOP
3 --------------7
t TCOP
3 --------------+ 0.15
7
ns
t TCOP
4 --------------– 0.15
7
t TCOP
4 --------------7
t TCOP
+ 0.15
4 --------------7
ns
t TCOP
5 --------------– 0.15
7
t TCOP
5 --------------7
t TCOP
5 --------------+ 0.15
7
ns
t TCOP
6 --------------– 0.15
7
t TCOP
6 --------------7
t TCOP
6 --------------+ 0.15
7
ns
10.0
ms
PLL Lock time(Fig3)
DE input period (Fig3-1)
tDEINT
Single-in / Dual-out, DDR Off mode
only(MODE<2:0>=LHL)
4tTCIP
tTCIP*(2n) a
ns
2tTCIP
tTCIP*(2m)a
ns
DE High time (Fig3-1)
tDEH
Single-in / Dual-out, DDR Off mode
only(MODE<2:0>=LHL)
DE Low time(Fig3-1)
tDEL
Single-in / Dual-out, DDR Off mode
only(MODE<2:0>=LHL)
2tTCIP
ns
a. Refer to Fig3-1 for details.
Copyright©2011 THine Electronics, Inc.
9/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
AC Timing Diagrams
Vdiff=(TA+)-(TA-)
TA+
Vdiff
5pF
80%
80%
20%
20%
100Ω
TAtLVT
tLVT
LVDS Output Load
Fig2. LVDS Output Load and Transition Time
CLKINx
x=1,2
2.0V
/PDWN
tTPLL
Vdiff=0V
TCLKx+/x=1,2
Fig3. PLL Lock Time
tDEINT
tTCIP
CLKIN
DE
tDEH
tDEL
Note: In single-in/dual-out, DDR off mode (MODE<2:0>=LHL),
the period between rising edges of DE (tDEINT), high time of DE (tDEH)
should always satisfy following equations.
tDEH = tTCIP * (2m)
tDEINT = tTCIP * (2n)
m, n =integer
Fig3-1. Single IN / Dual OUT, DDR off mode DE input timing
Copyright©2011 THine Electronics, Inc.
10/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
AC Timing Diagrams (Continued)
RS pin
VIHM
VIMM
tTCIP
tTCH
VILM
tTCL
VOD
350mV
200mV
VREF
VCC/2
Input Voltage of RS pin
VCC/2
VCC
CLKINx
x=1,2
VREF
VREF
VREF
GND
Rxn, Gxn, Bxn
HSYNCx
VSYNCx
VREF
DEx
CONTx1
CONTx2
x=1,2 n=0-9
tTS
tTH
VCC
Current Data
VREF
GND
tTCD
TCLKx+/x=1,2
VOD
Txy+/x=1,2
y= A, B, C, D, E
VOC
Current Data
Note:
CLKINx: for R/F=GND, denote as solid line,
for R/F=VCC, denote as dashed line.
x=1,2
Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing
RS pin
VIHM
tTCIP
tTCH
VIMM
VILM
tTCL
VOD
350mV
200mV
VREF
VCC/2
Input Voltage of RS pin
VCC/2
VCC
CLKINx
x=1,2
VREF
VREF
VREF
GND
Rxn, Gxn, Bxn
HSYNCx
VSYNCx
DEx
CONTx1
CONTx2
x=1,2 n=0-9
tTS
tTH
tTS
tTH
VCC
VREF
1st Pixel
Data
2nd Pixel
Data
VREF
GND
tTCD
TCLKx+/x=1,2
VOD
Txy+/x=1,2
y= A, B, C, D, E
VOC
Current Data
Note:
CLKINx: for R/F=GND, denote as solid line,
x=1,2
for R/F=VCC, denote as dashed line.
Fig5. CLKIN Period, High/Low Time, Setup/Hold Timing for Double Edge Input Mode (DDR)
MODE<1:0>=HL, MODE2=H
Copyright©2011 THine Electronics, Inc.
11/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
AC Timing Diagrams (Continued)
tTOP2
tTOP3
tTOP4
tTOP5
tTOP6
tTOP0
tTOP1
Tyx+/-
Tyx6
Tyx5
Tyx4
Tyx3
TCLKx+
Tyx2
Tyx1
Tyx0
Tyx6
Tyx5
Vdiff = 0V
Tyx4
Tyx3
Tyx2
Tyx1
Vdiff = 0V
x = 1,2
y = A,B,C,D,E
tTCOP
Note:
Vdiff = (Tyx+) - (Tyx-), (TCLKx+) - (TCLKx-)
Fig6. LVDS Output Data Position
Copyright©2011 THine Electronics, Inc.
12/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
Input Data Mapping
•Table1. Input Color Data naming rule
X
Y
Z
Description
X=R
Red Color Data
X=G
Green Color Data
X=B
Blue Color Data
Y= None
Single Pixel
Y=E
Dual Pixel
Y=O
Z=0-9
1st Pixel Data
2nd Pixel Data
Bit number 0: LSB (Least Significant Bit)
9: MSB (Most Significant Bit)
•Table2. TTL/CMOS Input Data Mapping (Single-in mode, MODE1=H)
Data Signals
30-bit
24-bit
Transmitter Input Pin Names
18-bit
30-bit
R0
R10
R1
R11
24-bit
18-bit
R2
R0
R12
R12
R3
R1
R13
R13
R4
R2
R0
R14
R14
R14
R5
R3
R1
R15
R15
R15
R6
R4
R2
R16
R16
R16
R7
R5
R3
R17
R17
R17
R8
R6
R4
R18
R18
R18
R9
R7
R5
R19
R19
R19
G0
G10
G1
G11
G2
G0
G12
G12
G3
G1
G13
G13
G4
G2
G0
G14
G14
G14
G5
G3
G1
G15
G15
G15
G6
G4
G2
G16
G16
G16
G7
G5
G3
G17
G17
G17
G8
G6
G4
G18
G18
G18
G9
G7
G5
G19
G19
G19
B0
B10
B1
B11
B2
B0
B12
B12
B3
B1
B13
B13
B4
B2
B0
B14
B14
B12
B5
B3
B1
B15
B15
B13
B6
B4
B2
B16
B16
B14
B7
B5
B3
B17
B17
B15
B8
B6
B4
B18
B18
B16
B9
B7
B5
B19
B19
B17
Copyright©2011 THine Electronics, Inc.
13/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
Input Data Mapping (Continued)
•Table3. TTL/CMOS Input Data Mapping (Dual-in mode, MODE1=L)
Transmitter Input Pin
Names
Data Signals
30-bit
24-bit
18-bit
RE0
30-bit
24-bit
18-bit
R10
RE1
Transmitter Input Pin
Names
Data Signals
30-bit
24-bit
18-bit
RO0
R11
30-bit
24-bit
18-bit
R20
RO1
R22
RE2
RE0
R12
R12
RO2
RO0
R22
R22
RE3
RE1
R13
R13
RO3
RO1
R23
R23
RE4
RE2
RE0
R14
R14
R14
RO4
RO2
RO0
R24
R24
R24
RE5
RE3
RE1
R15
R15
R15
RO5
RO3
RO1
R25
R25
R25
RE6
RE4
RE2
R16
R16
R16
RO6
RO4
RO2
R26
R26
R26
RE7
RE5
RE3
R17
R17
R17
RO7
RO5
RO3
R27
R27
R27
RE8
RE6
RE4
R18
R18
R18
RO8
RO6
RO4
R28
R28
R28
RE9
RE7
RE5
R19
R19
R19
RO9
RO7
RO5
R29
R29
R29
GE0
G10
GO0
G20
GE1
G11
GO1
G22
GE2
GE0
G12
G12
GE3
GE1
GE4
GE2
GE0
GE5
GE3
GE6
G13
G13
G14
G14
G14
GE1
G15
G15
GE4
GE2
G16
GE7
GE5
GE3
GE8
GE6
GE4
GE9
GE7
GE5
BE0
GO2
GO0
GO3
GO1
G23
G23
GO4
GO2
GO0
G24
G24
G24
G15
GO5
GO3
GO1
G25
G25
G25
G16
G16
GO6
GO4
GO2
G26
G26
G26
G17
G17
G17
GO7
GO5
GO3
G27
G27
G27
G18
G18
G18
GO8
GO6
GO4
G28
G28
G28
G19
G19
G19
GO9
GO7
GO5
G29
G29
G29
B10
BE1
G22
BO0
B11
G22
B20
BO1
B22
BE2
BE0
B12
B12
BO2
BO0
B22
B22
BE3
BE1
B13
B13
BO3
BO1
B23
B23
BE4
BE2
BE0
B14
B14
B14
BO4
BO2
BO0
B24
B24
B24
BE5
BE3
BE1
B15
B15
B15
BO5
BO3
BO1
B25
B25
B25
BE6
BE4
BE2
B16
B16
B16
BO6
BO4
BO2
B26
B26
B26
BE7
BE5
BE3
B17
B17
B17
BO7
BO5
BO3
B27
B27
B27
BE8
BE6
BE4
B18
B18
B18
BO8
BO6
BO4
B28
B28
B28
BE9
BE7
BE5
B19
B19
B19
BO9
BO7
BO5
B29
B29
B29
Copyright©2011 THine Electronics, Inc.
14/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
LVDS Output Data Mapping
Previous Cycle
(2nd Pixel Data)
Next Cycle
(2nd Pixel Data)
Current Cycle
(1st Pixel Data)
TCLK1+
Tx1+/Tx11(n-1) Tx10(n-1) Tx16(n)
x= A, B, C, D, E
Tx15(n)
Tx14(n)
Tx13(n)
Tx12(n)
Tx11(n)
Tx10(n)
Tx16(n+1)
Fig7. TTL Data Inputs Mapped to LVDS outputs
MODE0= H (Single-out Mode)
Previous Cycle
Next Cycle
Current Cycle
TCLK1+
Tx1+/Tx11(n-1) Tx10(n-1) Tx16(n)
x= A, B, C, D, E
Tx15(n)
Tx14(n)
Tx13(n)
Tx12(n)
Tx11(n)
Tx10(n)
Tx16(n+1)
Tx2+/x= A, B, C, D, E Tx21(n-1) Tx20(n-1) Tx26(n)
Tx25(n)
Tx24(n)
Tx23(n)
Tx22(n)
Tx21(n)
Tx20(n)
Tx26(n+1)
Fig8. TTL Data Inputs Mapped to LVDS outputs
MODE0= L (Dual-out Mode)
Copyright©2011 THine Electronics, Inc.
15/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table4. LVDS Output Data Mapping (Single-in/Single-out Distribution Off, MODE<1:0>=HH, MODE2=L)
Mapping Mode (Input Pin Name)
LVDS
Mode1
MAP=VIHM
Mode2
MAP=VILM
Mode3
MAP=VIMM
TA10
R14
R12
R10
TA11
R15
R13
R11
TA12
R16
R14
R12
TA13
R17
R15
R13
TA14
R18
R16
R14
TA15
R19
R17
R15
Output Data
TA16
G14
G12
G10
TB10
G15
G13
G11
TB11
G16
G14
G12
TB12
G17
G15
G13
TB13
G18
G16
G14
TB14
G19
G17
G15
TB15
B14
B12
B10
TB16
B15
B13
B11
TC10
B16
B14
B12
TC11
B17
B15
B13
TC12
B18
B16
B14
TC13
B19
B17
B15
TC14
HSYNC1
HSYNC1
HSYNC1
TC15
VSYNC1
VSYNC1
VSYNC1
TC16
DE1
DE1
DE1
TD10
R12
R18
R16
TD11
R13
R19
R17
TD12
G12
G18
G16
TD13
G13
G19
G17
TD14
B12
B18
B16
TD15
B13
B19
B17
TD16
CONT11
CONT11
CONT11
TE10
R10
R10
R18
TE11
R11
R11
R19
TE12
G10
G10
G18
TE13
G11
G11
G19
TE14
B10
B10
B18
TE15
B11
B11
B19
TE16
CONT12
CONT12
CONT12
Copyright©2011 THine Electronics, Inc.
16/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table5. LVDS Output Data Mapping (Single-in/Single-out Distribution On, MODE<1:0>=HH, MODE2=H)
LVDS
Mapping Mode (Input Pin Name)
LVDS
Mapping Mode (Input Pin Name)
Output Data
Mode1
Mode3
MAP=VIMM
Mode1
MAP=VIHM
Mode2
MAP=VILM
Output Data
(1st Link)
(2nd Link)
MAP=VIHM
Mode2
MAP=VILM
Mode3
MAP=VIMM
TA10
R14
R12
R10
TA20
R14
R12
R10
TA11
R15
R13
R11
TA21
R15
R13
R11
TA12
R16
R14
R12
TA22
R16
R14
R12
TA13
R17
R15
R13
TA23
R17
R15
R13
TA14
R18
R16
R14
TA24
R18
R16
R14
TA15
R19
R17
R15
TA25
R19
R17
R15
TA16
G14
G12
G10
TA26
G14
G12
G10
TB10
G15
G13
G11
TB20
G15
G13
G11
TB11
G16
G14
G12
TB21
G16
G14
G12
TB12
G17
G15
G13
TB22
G17
G15
G13
TB13
G18
G16
G14
TB23
G18
G16
G14
TB14
G19
G17
G15
TB24
G19
G17
G15
TB15
B14
B12
B10
TB25
B14
B12
B10
TB16
B15
B13
B11
TB26
B15
B13
B11
TC10
B16
B14
B12
TC20
B16
B14
B12
TC11
B17
B15
B13
TC21
B17
B15
B13
TC12
B18
B16
B14
TC22
B18
B16
B14
TC13
B19
B17
B15
TC23
B19
B17
B15
TC14
HSYNC1
HSYNC1
HSYNC1
TC24
HSYNC1
HSYNC1
HSYNC1
TC15
VSYNC1
VSYNC1
VSYNC1
TC25
VSYNC1
VSYNC1
VSYNC1
TC16
DE
DE
DE1
TC26
DE
DE
DE1
TD10
R12
R18
R16
TD20
R12
R18
R16
TD11
R13
R19
R17
TD21
R13
R19
R17
TD12
G12
G18
G16
TD22
G12
G18
G16
TD13
G13
G19
G17
TD23
G13
G19
G17
TD14
B12
B18
B16
TD24
B12
B18
B16
TD15
B13
B19
B17
TD25
B13
B19
B17
TD16
CONT11
CONT11
CONT11
TD26
CONT11
CONT11
CONT11
TE10
R10
R10
R18
TE20
R10
R10
R18
TE11
R11
R11
R19
TE21
R11
R11
R19
TE12
G10
G10
G18
TE22
G10
G10
G18
TE13
G11
G11
G19
TE23
G11
G11
G19
TE14
B10
B10
B18
TE24
B10
B10
B18
TE15
B11
B11
B19
TE25
B11
B11
B19
TE16
CONT12
CONT12
CONT12
TE26
CONT12
CONT12
CONT12
Copyright©2011 THine Electronics, Inc.
17/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table6. LVDS Output Data Mapping
(Single-in/Dual-out, DDR On or Off, Port Switch Off, MODE<1:0>=HL, MODE2=H or L, MODE3=H or Open)
Mapping Mode (Input Pin Name)
Mapping Mode (Input Pin Name)
LVDS
LVDS
Output Data
Mode1
(1st Link)
Mode3
MAP=VIMM
Output Data
Mode1
MAP=VIHM
Mode2
MAP=VILM
(2nd Link)
TA10
R14
R12
R10
MAP=VIHM
Mode2
MAP=VILM
Mode3
MAP=VIMM
TA20
R14
R12
R10
TA11
R15
R13
R11
TA21
R15
R13
R11
TA12
R16
R14
R12
TA22
R16
R14
R12
TA13
R17
R15
R13
TA23
R17
R15
R13
TA14
R18
R16
R14
TA24
R18
R16
R14
TA15
R19
R17
R15
TA25
R19
R17
R15
TA16
G14
G12
G10
TA26
G14
G12
G10
TB10
G15
G13
G11
TB20
G15
G13
G11
TB11
G16
G14
G12
TB21
G16
G14
G12
TB12
G17
G15
G13
TB22
G17
G15
G13
TB13
G18
G16
G14
TB23
G18
G16
G14
TB14
G19
G17
G15
TB24
G19
G17
G15
TB15
B14
B12
B10
TB25
B14
B12
B10
TB16
B15
B13
B11
TB26
B15
B13
B11
TC10
B16
B14
B12
TC20
B16
B14
B12
TC11
B17
B15
B13
TC21
B17
B15
B13
TC12
B18
B16
B14
TC22
B18
B16
B14
TC13
B19
B17
B15
TC23
B19
B17
B15
TC14
HSYNC1
HSYNC1
HSYNC1
TC24
HSYNC1
HSYNC1
HSYNC1
TC15
VSYNC1
VSYNC1
VSYNC1
TC25
VSYNC1
VSYNC1
VSYNC1
TC16
DE1
DE1
DE1
TC26
DE1
DE1
DE1
TD10
R12
R18
R16
TD20
R12
R18
R16
TD11
R13
R19
R17
TD21
R13
R19
R17
TD12
G12
G18
G16
TD22
G12
G18
G16
TD13
G13
G19
G17
TD23
G13
G19
G17
TD14
B12
B18
B16
TD24
B12
B18
B16
TD15
B13
B19
B17
TD25
B13
B19
B17
TD16
CONT11
CONT11
CONT11
TD26
CONT11
CONT11
CONT11
TE10
R10
R10
R18
TE20
R10
R10
R18
TE11
R11
R11
R19
TE21
R11
R11
R19
TE12
G10
G10
G18
TE22
G10
G10
G18
TE13
G11
G11
G19
TE23
G11
G11
G19
TE14
B10
B10
B18
TE24
B10
B10
B18
TE15
B11
B11
B19
TE25
B11
B11
B19
TE16
CONT12
CONT12
CONT12
TE26
CONT12
CONT12
CONT12
Copyright©2011 THine Electronics, Inc.
18/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table7. LVDS Output Data Mapping
(Single-in/Dual-out, DDR On or Off, Port Switch On, MODE<1:0>=HL, MODE2=H or L, MODE3=L)
Mapping Mode (Input Pin Name)
Mapping Mode (Input Pin Name)
LVDS
LVDS
Output Data
Mode1
Mode3
MAP=VIMM
Mode1
MAP=VIHM
Mode2
MAP=VILM
Output Data
(1st Link)
(2nd Link)
MAP=VIHM
Mode2
MAP=VILM
Mode3
MAP=VIMM
TA10
R24
R22
R20
TA20
R24
R22
R20
TA11
R25
R23
R21
TA21
R25
R23
R21
TA12
R26
R24
R22
TA22
R26
R24
R22
TA13
R27
R25
R23
TA23
R27
R25
R23
TA14
R28
R26
R24
TA24
R28
R26
R24
TA15
R29
R27
R25
TA25
R29
R27
R25
TA16
G24
G22
G20
TA26
G24
G22
G20
TB10
G25
G23
G21
TB20
G25
G23
G21
TB11
G26
G24
G22
TB21
G26
G24
G22
TB12
G27
G25
G23
TB22
G27
G25
G23
TB13
G28
G26
G24
TB23
G28
G26
G24
TB14
G29
G27
G25
TB24
G29
G27
G25
TB15
B24
B22
B20
TB25
B24
B22
B20
TB16
B25
B23
B21
TB26
B25
B23
B21
TC10
B26
B24
B22
TC20
B26
B24
B22
TC11
B27
B25
B23
TC21
B27
B25
B23
TC12
B28
B26
B24
TC22
B28
B26
B24
TC13
B29
B27
B25
TC23
B29
B27
B25
TC14
HSYNC2
HSYNC2
HSYNC2
TC24
HSYNC2
HSYNC2
HSYNC2
TC15
VSYNC2
VSYNC2
VSYNC2
TC25
VSYNC2
VSYNC2
VSYNC2
TC16
DE2
DE2
DE2
TC26
DE2
DE2
DE2
TD10
R22
R28
R26
TD20
R22
R28
R26
TD11
R23
R29
R27
TD21
R23
R29
R27
TD12
G22
G28
G26
TD22
G22
G28
G26
TD13
G23
G29
G27
TD23
G23
G29
G27
TD14
B22
B28
B26
TD24
B22
B28
B26
TD15
B23
B29
B27
TD25
B23
B29
B27
TD16
CONT21
CONT21
CONT21
TD26
CONT21
CONT21
CONT21
TE10
R20
R20
R28
TE20
R20
R20
R28
TE11
R21
R21
R29
TE21
R21
R21
R29
TE12
G20
G20
G28
TE22
G20
G20
G28
TE13
G21
G21
G29
TE23
G21
G21
G29
TE14
B20
B20
B28
TE24
B20
B20
B28
TE15
B21
B21
B29
TE25
B21
B21
B29
TE16
CONT22
CONT22
CONT22
TE26
CONT22
CONT22
CONT22
Copyright©2011 THine Electronics, Inc.
19/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table8. LVDS Output Data Mapping (Dual-in/Single-out, MODE<1:0>=LH)
LVDS
Mapping Mode (Input Pin Name)
LVDS
Mapping Mode (Input Pin Name)
Mode3
MAP=VIMM
Output Data
Mode1
MAP=VIHM
Mode2
MAP=VILM
(2nd Pixel)
TA10(n)
R14
R12
R10
TA11(n)
R15
R13
R11
TA12(n)
R16
R14
TA13(n)
R17
TA14(n)
TA15(n)
Output Data
Mode1
(1st Pixel)
MAP=VIHM
Mode2
MAP=VILM
Mode3
MAP=VIMM
TA10(n+1)
R24
R22
R20
TA11(n+1)
R25
R23
R21
R12
TA12(n+1)
R26
R24
R22
R15
R13
TA13(n+1)
R27
R25
R23
R18
R16
R14
TA14(n+1)
R28
R26
R24
R19
R17
R15
TA15(n+1)
R29
R27
R25
TA16(n)
G14
G12
G10
TA16(n+1)
G24
G22
G20
TB10(n)
G15
G13
G11
TB10(n+1)
G25
G23
G21
TB11(n)
G16
G14
G12
TB11(n+1)
G26
G24
G22
TB12(n)
G17
G15
G13
TB12(n+1)
G27
G25
G23
TB13(n)
G18
G16
G14
TB13(n+1)
G28
G26
G24
TB14(n)
G19
G17
G15
TB14(n+1)
G29
G27
G25
TB15(n)
B14
B12
B10
TB15(n+1)
B24
B22
B20
TB16(n)
B15
B13
B11
TB16(n+1)
B25
B23
B21
TC10(n)
B16
B14
B12
TC10(n+1)
B26
B24
B22
TC11(n)
B17
B15
B13
TC11(n+1)
B27
B25
B23
TC12(n)
B18
B16
B14
TC12(n+1)
B28
B26
B24
TC13(n)
B19
B17
B15
TC13(n+1)
B29
B27
B25
TC14(n)
HSYNC1
HSYNC1
HSYNC1
TC14(n+1)
HSYNC1
HSYNC1
HSYNC1
TC15(n)
VSYNC1
VSYNC1
VSYNC1
TC15(n+1)
VSYNC1
VSYNC1
VSYNC1
TC16(n)
DE1
DE1
DE1
TC16(n+1)
DE1
DE1
DE1
TD10(n)
R12
R18
R16
TD10(n+1)
R22
R28
R26
TD11(n)
R13
R19
R17
TD11(n+1)
R23
R29
R27
TD12(n)
G12
G18
G16
TD12(n+1)
G22
G28
G26
TD13(n)
G13
G19
G17
TD13(n+1)
G23
G29
G27
TD14(n)
B12
B18
B16
TD14(n+1)
B22
B28
B26
TD15(n)
B13
B19
B17
TD15(n+1)
B23
B29
B27
TD16(n)
CONT11
CONT11
CONT11
TD16(n+1)
CONT21
CONT21
CONT21
TE10(n)
R10
R10
R18
TE10(n+1)
R20
R20
R28
TE11(n)
R11
R11
R19
TE11(n+1)
R21
R21
R29
TE12(n)
G10
G10
G18
TE12(n+1)
G20
G20
G28
TE13(n)
G11
G11
G19
TE13(n+1)
G21
G21
G29
TE14(n)
B10
B10
B18
TE14(n+1)
B20
B20
B28
TE15(n)
B11
B11
B19
TE15(n+1)
B21
B21
B29
TE16(n)
CONT12
CONT12
CONT12
TE16(n+1)
CONT22
CONT22
CONT22
Copyright©2011 THine Electronics, Inc.
20/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table9. LVDS Output Data Mapping (Dual-in/Dual-out, MODE<1:0>=LL)
LVDS
Mapping Mode (Input Pin Name)
LVDS
Mapping Mode (Input Pin Name)
Mode3
MAP=VIMM
Output Data
Mode1
MAP=VIHM
Mode2
MAP=VILM
(2nd Link)
TA10
R14
R12
R10
TA20
Output Data
Mode1
(1st Link)
MAP=VIHM
Mode2
MAP=VILM
Mode3
MAP=VIMM
R24
R22
R20
TA11
R15
R13
R11
TA21
R25
R23
R21
TA12
R16
R14
R12
TA22
R26
R24
R22
TA13
R17
R15
R13
TA23
R27
R25
R23
TA14
R18
R16
R14
TA24
R28
R26
R24
TA15
R19
R17
R15
TA25
R29
R27
R25
TA16
G14
G12
G10
TA26
G24
G22
G20
TB10
G15
G13
G11
TB20
G25
G23
G21
TB11
G16
G14
G12
TB21
G26
G24
G22
TB12
G17
G15
G13
TB22
G27
G25
G23
TB13
G18
G16
G14
TB23
G28
G26
G24
TB14
G19
G17
G15
TB24
G29
G27
G25
TB15
B14
B12
B10
TB25
B24
B22
B20
TB16
B15
B13
B11
TB26
B25
B23
B21
TC10
B16
B14
B12
TC20
B26
B24
B22
TC11
B17
B15
B13
TC21
B27
B25
B23
TC12
B18
B16
B14
TC22
B28
B26
B24
TC13
B19
B17
B15
TC23
B29
B27
B25
TC14
HSYNC1
HSYNC1
HSYNC1
TC24
HSYNC1
HSYNC1
HSYNC1
TC15
VSYNC1
VSYNC1
VSYNC1
TC25
VSYNC1
VSYNC1
VSYNC1
TC16
DE1
DE1
DE1
TC26
DE1
DE1
DE1
TD10
R12
R18
R16
TD20
R22
R28
R26
TD11
R13
R19
R17
TD21
R23
R29
R27
TD12
G12
G18
G16
TD22
G22
G28
G26
TD13
G13
G19
G17
TD23
G23
G29
G27
TD14
B12
B18
B16
TD24
B22
B28
B26
TD15
B13
B19
B17
TD25
B23
B29
B27
TD16
CONT11
CONT11
CONT11
TD26
CONT21
CONT21
CONT21
TE10
R10
R10
R18
TE20
R20
R20
R28
TE11
R11
R11
R19
TE21
R21
R21
R29
TE12
G10
G10
G18
TE22
G20
G20
G28
TE13
G11
G11
G19
TE23
G21
G21
G29
TE14
B10
B10
B18
TE24
B20
B20
B28
TE15
B11
B11
B19
TE25
B21
B21
B29
TE16
CONT12
CONT12
CONT12
TE26
CONT22
CONT22
CONT22
Copyright©2011 THine Electronics, Inc.
21/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table10. LVDS Output Data Mapping (Asynchronous Cross point switching Off, ASYNC=H MODE2=L)
LVDS
Mapping
LVDS
Mapping
Output Data
(MAP= Don’t care)
Output Data
(MAP= Don’t care)
(1st Link)
(Input Pin Name)
(2nd Link)
(Input Pin Name)
TA10
TA10
TA20
TA20
TA11
TA11
TA21
TA21
TA12
TA12
TA22
TA22
TA13
TA13
TA23
TA23
TA14
TA14
TA24
TA24
TA15
TA15
TA25
TA25
TA16
TA16
TA26
TA26
TB10
TB10
TB20
TB20
TB11
TB11
TB21
TB21
TB12
TB12
TB22
TB22
TB13
TB13
TB23
TB23
TB14
TB14
TB24
TB24
TB15
TB15
TB25
TB25
TB16
TB16
TB26
TB26
TC10
TC10
TC20
TC20
TC11
TC11
TC21
TC21
TC12
TC12
TC22
TC22
TC13
TC13
TC23
TC23
TC14
TC14
TC24
TC24
TC15
TC15
TC25
TC25
TC16
TC16
TC26
TC26
TD10
TD10
TD20
TD20
TD11
TD11
TD21
TD21
TD12
TD12
TD22
TD22
TD13
TD13
TD23
TD23
TD14
TD14
TD24
TD24
TD15
TD15
TD25
TD25
TD16
TD16
TD26
TD26
TE10
TE10
TE20
TE20
TE11
TE11
TE21
TE21
TE12
TE12
TE22
TE22
TE13
TE13
TE23
TE23
TE14
TE14
TE24
TE24
TE15
TE15
TE25
TE25
TE16
TE16
TE26
TE26
Copyright©2011 THine Electronics, Inc.
22/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
LVDS Output Data Mapping (Continued)
•Table11. LVDS Output Data Mapping (Asynchronous Cross point switching On, ASYNC=H MODE2=H)
LVDS
Mapping
LVDS
Mapping
Output Data
(MAP= Don’t care)
Output Data
(MAP= Don’t care)
(1st Link)
(Input Pin Name)
(2nd Link)
(Input Pin Name)
TA10
TA20
TA20
TA10
TA11
TA21
TA21
TA11
TA12
TA22
TA22
TA12
TA13
TA23
TA23
TA13
TA14
TA24
TA24
TA14
TA15
TA25
TA25
TA15
TA16
TA26
TA26
TA16
TB10
TB20
TB20
TB10
TB11
TB21
TB21
TB11
TB12
TB22
TB22
TB12
TB13
TB23
TB23
TB13
TB14
TB24
TB24
TB14
TB15
TB25
TB25
TB15
TB16
TB26
TB26
TB16
TC10
TC20
TC20
TC10
TC11
TC21
TC21
TC11
TC12
TC22
TC22
TC12
TC13
TC23
TC23
TC13
TC14
TC24
TC24
TC14
TC15
TC25
TC25
TC15
TC16
TC26
TC26
TC16
TD10
TD20
TD20
TD10
TD11
TD21
TD21
TD11
TD12
TD22
TD22
TD12
TD13
TD23
TD23
TD13
TD14
TD24
TD24
TD14
TD15
TD25
TD25
TD15
TD16
TD26
TD26
TD16
TE10
TE20
TE20
TE10
TE11
TE21
TE21
TE11
TE12
TE22
TE22
TE12
TE13
TE23
TE23
TE13
TE14
TE24
TE24
TE14
TE15
TE25
TE25
TE15
TE16
TE26
TE26
TE16
Copyright©2011 THine Electronics, Inc.
23/26
THine Electronics, Inc.
THC63LVD1023B_Rev.3.0_E
Note
1)Cable Connection and Disconnection
Don't connect and disconnect the LVDS cable, when the power is supplied to the system.
2)GND Connection
Connect the each GND of the PCB which THC63LVD1023B and LVDS-Rx on it. It is better for EMI reduction to
place GND cable as close to LVDS cable as possible.
3)Multi Drop Connection
Multi drop connection is not recommended.
TCLK+
LVDS-Rx
THC63LVD1023B
TCLKLVDS-Rx
4)Asynchronous use
Asynchronous use such as following systems are not recommended.
CLKOUT
DATA
IC
CLKOUT
DATA
LVDS-Rx
TCLK-
DATA
IC
TCLK+
THC63LVD1023B
DATA
TCLK+
THC63LVD1023B
CLKOUT
DATA
Copyright©2011 THine Electronics, Inc.
DATA
LVDS-Rx
TCLK-
CLKOUT
IC
CLKOUT
TCLK+
THC63LVD1023B
TCLKTCLK+
THC63LVD1023B
IC
TCLK-
24/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
Package
22.00 BSC.
20.00 BSC.
17.50
1.60 MAX
0.05~0.15
17.50
20.00 BSC.
22.00 BSC.
1.40 +/-0.05
1.00 REF
THC63LVD1023B
0.50 BSC.
0.09~0.20
0.20 +0.07/-0.03
INDEX
S
3.5+/-3.5 degree
0.10
SEATING PLANE
S
GAGE PLANE
0.25mm
0.60 +/-0.15
0.20 MIN
UNIT:mm
Copyright©2011 THine Electronics, Inc.
25/26
THine Electronics, Inc.
THC63LVD1023B _Rev.3.0_E
Notices and Requests
1.)The product specifications described in this material are subject to change without prior notice.
2.)The circuit diagrams described in this material are examples of the application which may not
always apply to the customer's design. We are not responsible for possible errors and omissions in
this material. Please note if errors or omissions should be found in this material, we may not be able
to correct them immediately.
3.)This material contains our copy right, know-how or other proprietary. Copying or disclosing to
third parties the contents of this material without our prior permission is prohibited.
4.)Note that if infringement of any third party's industrial ownership should occur by using this
product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product.
5.)This product is presumed to be used for general electric equipment, not for the applications
which require very high reliability (including medical equipment directly concerning people's life,
aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the
product.
6.)Despite our utmost efforts to improve the quality and reliability of the product, faults will occur
with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are
encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage.
7.)Please note that this product is not designed to be radiation-proof.
8.)Customers are asked, if required, to judge by themselves if this product falls under the category
of strategic goods under the Foreign Exchange and Foreign Trade Control Law.
THine Electronics, Inc.
E-mail: [email protected]
Copyright©2011 THine Electronics, Inc.
26/26
THine Electronics, Inc.
Similar pages