HT16220/HT16220G RAM Mapping 32´8 LCD Controller for I/O MCU PATENTED PAT No. : 099352 Technical Document · Application Note Features · Operating voltage: 2.7V~5.2V · R/W address auto increment · External Crystal 32.768kHz oscillator · Two selectable buzzer frequencies (2kHz or 4kHz) · 1/4 bias, 1/8 duty, frame frequency is 64Hz · Power down command reduces power consumption · Max. 32´8 patterns, 8 commons, 32 segments · Software configuration feature · Built-in internal resistor type bias generator · Data mode and Command mode instructions · 3-wire serial interface · Three data accessing modes · 8 kinds of time base or WDT selection · VLCD pin to adjust LCD operating voltage · Time base or WDT overflow output · HT16220: 64pin LQFP package HT16220G: Gold bumped chip · Built-in LCD display RAM General Description HT16220 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT16220. The HT162X series have many kinds of products that match various applications. HT16220 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 256 patterns (32´8). It also supports serial interface, buzzer sound, watchdog timer or time base timer functions. The HT16220 is a memory mapping and multi-function LCD controller. The software configuration feature of the Selection Table HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 COM 4 4 8 8 8 8 16 SEG 32 32 32 32 48 64 48 Built-in Osc. ¾ Ö Ö ¾ Ö Ö Ö Crystal Osc. Ö Ö ¾ Ö Ö Ö Ö Rev. 2.30 1 November 25, 2014 PATENTED HT16220/HT16220G Block Diagram O S C O D is p la y R A M O S C I C S C o n tro l a n d T im in g C ir c u it R D W R C O M 0 C O M 7 L C D D r iv e r / B ia s C ir c u it D A T A S E G 0 S E G 3 1 V D D V S S V L C D B Z W a tc h d o g T im e r a n d T im e B a s e G e n e r a to r T o n e F re q u e n c y G e n e ra to r B Z IR Q Pin Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G N N N N C C C C 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 C S N C R D W R D A T A V S S V D D V L C D IR Q B Z B Z N C O S C O O S C I T 1 T 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 4 8 4 7 2 3 4 6 5 4 4 4 5 4 6 7 8 H T 1 6 2 2 0 6 4 L Q F P -A 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G N C N C S E G 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 S E G S E G S E G S E G S E G S E G C O M C O M C O M C O M C O M C O M C O M C O M N C T 3 5 4 3 2 1 0 2 7 6 5 4 3 2 1 0 Rev. 2.30 November 25, 2014 PATENTED HT16220/HT16220G Pad Assignment S E G 2 8 S E G 2 7 S E G 2 6 S E G 2 5 S E G 2 4 S E G 2 3 S E G 2 2 S E G 2 1 S E G 2 0 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 2 W R 3 4 3 S E G 1 9 4 2 S E G 1 8 4 1 3 9 S E G 1 7 S E G 1 6 S E G 1 5 3 8 S E G 1 4 3 7 S E G 1 3 3 6 3 5 S E G 1 2 S E G 1 1 3 4 S E G 1 0 3 3 3 2 S E G 9 S E G 8 3 1 S E G 7 4 0 D A T A 4 V S S 5 V D D 6 V L C D 7 (0 ,0 ) IR Q 8 B Z 9 B Z 1 0 O S C O 1 1 O S C I S E G 2 9 R D S E G 3 0 1 S E G 3 1 C S 1 2 2 5 2 7 2 8 2 9 3 0 S E G 6 2 4 S E G 5 2 6 2 3 S E G 4 2 2 S E G 3 2 1 S E G 2 S E G 1 2 0 C O M 7 1 9 S E G 0 1 8 C O M 5 1 7 C O M 4 1 6 C O M 6 1 5 C O M 3 T 3 C O M 2 1 4 C O M 1 1 3 T 2 C O M 0 T 1 Chip size: 95 ´ 99 (mil)2 Bump height: 18mm ± 3mm Min. Bump spacing: 23.102mm Bump size: 76 ´ 76mm2 * The IC substrate should be connected to VDD in the PCB layout artwork. Rev. 2.30 3 November 25, 2014 PATENTED HT16220/HT16220G Pad Coordinates Unit: mm Pad No. X Y Pad No. X Y 1 -1068.102 1142.255 2 -1068.102 941.875 29 973.176 -1144.760 30 1072.194 3 -1068.102 -1144.760 842.776 31 1094.145 4 -130.495 -1068.102 614.987 32 1094.145 5 -1046.545 379.670 33 1094.145 -31.395 67.624 6 -1068.102 274.635 34 1094.145 166.725 7 -1068.102 175.574 35 1094.145 265.745 8 -1068.102 -1.490 36 1094.145 364.846 9 -1068.102 -213.816 37 1094.145 463.865 10 -1068.102 -403.664 38 1094.145 562.966 11 -1068.102 -608.980 39 1094.145 661.984 12 -1068.102 -708.000 40 1094.145 761.086 13 -1068.102 -858.985 41 1094.145 860.104 14 -1068.102 -958.005 42 1094.145 959.206 15 -1068.102 -1124.635 43 1094.145 1058.224 16 -546.419 -1144.760 44 233.365 1142.380 17 -447.320 -1144.760 45 134.264 1142.380 18 -255.590 -1144.760 46 35.245 1142.380 19 -156.490 35.241 -1144.760 47 -63.855 1142.380 20 -1144.760 48 -162.874 1142.380 21 134.340 -1144.760 49 -261.975 1142.380 22 279.715 -1144.760 50 -360.995 1142.380 23 378.815 -1144.760 51 -460.096 1142.380 24 477.835 -1144.760 52 -559.115 1142.380 25 576.935 -1144.760 53 -658.216 1142.380 26 675.954 -1144.760 54 -757.234 1142.380 27 775.056 -1144.760 55 -856.334 1142.380 28 874.074 -1144.760 Rev. 2.30 4 November 25, 2014 PATENTED HT16220/HT16220G Pad Description Pad No. 1 Pad Name CS I/O Description I Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or written to the HT16220 are disabled. The serial interface circuit is also reset But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT16220 are all enabled. 2 RD I READ clock input with pull-high resistor. Data in the RAM of the HT16220 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. 3 WR I WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT16220 on the rising edge of the WR signal. 4 DATA I/O Serial data input or output with pull-high resistor 5 VSS ¾ Negative power supply, ground 6 VDD ¾ Positive power supply 7 VLCD I LCD operating voltage input pad. 8 IRQ O Time base or watchdog timer overflow flag, NMOS open drain output. 9, 10 BZ, BZ O 2kHz or 4kHz tone frequency output pair 11 OSCO O Crystal oscillator output pin 12 OSCI I Crystal oscillator input pin 13~15 T1~T3 I Not connected 16~23 COM0~COM7 O LCD common outputs 24~55 SEG0~SEG31 O LCD segment outputs Absolute Maximum Ratings Supply Voltage .........................................-0.3V to 5.5V Storage Temperature ...........................-50°C to 125°C Input Voltage .............................VSS-0.3V to VDD+0.3V Operating Temperature ..........................-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current Ta=25°C Test Conditions VDD Conditions ¾ ¾ 3V 5V IDD2 3V Operating Current 5V ISTB No load or LCD ON Crystal oscillator No load or LCD OFF Crystal oscillator 3V Standby Current No load, Power down mode 5V VIL 3V Input Low Voltage Typ. Max. Unit 2.7 ¾ 5.2 V ¾ ¾ 50 mA ¾ ¾ 65 mA ¾ ¾ 20 mA ¾ ¾ 30 mA ¾ 1 8 mA ¾ 2 16 mA 0 ¾ 0.6 V 0 ¾ 1.0 V DATA, WR, CS, RD 5V Rev. 2.30 Min. 5 November 25, 2014 PATENTED Symbol VIH Parameter Test Conditions VDD Conditions 3V Input High Voltage IOH1 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 RPH Min. Typ. Max. Unit 2.4 ¾ 3.0 V DATA, WR, CS, RD 4.0 ¾ 5.0 V 3V VOL=0.3V 0.9 1.8 ¾ mA 5V VOL=0.5V 1.7 3.0 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -1.7 -3.0 ¾ mA 3V VOL=0.3V 200 450 ¾ mA 5V VOL=0.5V 250 500 ¾ mA 3V VOH=2.7V -200 -450 ¾ mA 5V VOH=4.5V -250 -500 ¾ mA 3V VOL=0.3V 15 40 ¾ mA 5V VOL=0.5V 100 200 ¾ mA 3V VOH=2.7V -15 -30 ¾ mA 5V VOH=4.5V -45 -90 ¾ mA 3V VOL=0.3V 15 30 ¾ mA 5V VOL=0.5V 70 150 ¾ mA 3V VOH=2.7V -6 -13 ¾ mA 5V VOH=4.5V -20 -40 ¾ mA 100 200 300 kW 50 100 150 kW 5V IOL1 HT16220/HT16220G BZ, BZ, IRQ BZ, BZ DATA DATA LCD Common Sink Current LCD Common Source Current LCD Segment Sink Current LCD Segment Source Current 3V Pull-high Resistor DATA, WR, CS, RD 5V A.C. Characteristics Symbol fSYS Parameter System Clcok Ta=25°C Test Conditions VDD ¾ ¾ LCD Frame Frequency ¾ tCOM LCD Common Period ¾ fCLK1 Serial Data Clock (WR Pin) fLCD Conditions Crystal oscillator External clock source ¾ 32768 ¾ Hz ¾ 32768 ¾ Hz 64 ¾ Hz n: Number of COM ¾ ¾ sec 4 ¾ 150 kHz 4 ¾ 300 kHz ¾ ¾ 75 kHz ¾ ¾ 150 kHz 500 600 ¾ ns Write mode 3.34 ¾ 125 Read mode 6.67 ¾ ¾ Write mode 1.67 ¾ 125 Read mode 3.34 ¾ ¾ Duty cycle 50% 3V Serial Interface Reset Pulse Width (Figure 3) Unit n/fLCD Duty cycle 50% 5V tCS Max. ¾ 3V Serial Data Clock (RD Pin) Typ. Crystal oscillator 5V fCLK2 Min. ¾ CS 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V Rev. 2.30 6 ms ms November 25, 2014 PATENTED Symbol HT16220/HT16220G Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit t r, t f Rise/Fall Time Serial Data Clock (Figure 1) ¾ ¾ ¾ 120 160 ns tSU Setup Time for DATA to WR, RD Serial Data Clock (Figure 2) ¾ ¾ 60 120 ¾ ns th Hold Time for DATA to WR, RD Serial Data Clock (Figure 2) ¾ ¾ 500 600 ¾ ns tSU1 Setup Time for CS to WR, RD Clock Width (Figure 3) ¾ ¾ 500 600 ¾ ns th1 Hold Time for CS to WR, RD Clock Width (Figure 3) ¾ ¾ 700 800 ¾ ns Tone Frequency (2kHz) ¾ Crystal oscillator ¾ 2 ¾ kHz Tone Frequency (4kHz) ¾ Crystal oscillator ¾ 4 ¾ kHz tOFF VDD OFF Times (Figure 4) ¾ VDD drop down to 0V 20 ¾ ¾ ms tSR VDD Rising Slew Rate (Figure 4) ¾ ¾ 0.05 ¾ ¾ V/ms tRSTD Delay Time after Reset (Figure 4) ¾ ¾ 1 ¾ ¾ ms ftone Note: 1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage. V A L ID D A T A tf W R , R D C lo c k 9 0 % 5 0 % 1 0 % tr tC - V tC L K D B D D ts G N D L K V 5 0 % W R , R D C lo c k V D D S V th 0 V G N D 1 V 5 0 % F ir s t C lo c k tS D D 5 0 % u 1 D D - G N D Figure 2 tC ts D D G N D th u W R , R D C lo c k Figure 1 C S V 5 0 % L a s t C lo c k D D tO F F R 0 .9 V D D tR S T D G N D C S Figure 3 Figure 4. Power-on Reset Timing Rev. 2.30 7 November 25, 2014 PATENTED HT16220/HT16220G Functional Description Display Memory - RAM Structure If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. The static display RAM is organized into 64´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can beaccessed by theREAD,WRITEand READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. Buzzer Tone Output A simple tone generator is implemented in the HT16220. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. Time Base and Watchdog Timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued. C O M 7 C O M 6 C O M 5 Command Format The HT16220 can be configured by the software setting. There are two mode commands to configure the HT16220 resource and to transfer the LCD display data. C O M 3 C O M 4 C O M 2 C O M 1 C O M 0 S E G 0 1 0 S E G 1 3 2 S E G 2 5 4 S E G 3 7 6 S E G 3 1 6 3 6 2 D 3 D 2 D 1 D 0 A d d r D a ta D 3 D 2 D 1 D 0 A d d r e s s 6 B its (A 5 , A 4 , ...., A 0 ) A d d r D a ta D a ta 4 B its (D 3 , D 2 , D 1 , D 0 ) RAM Mapping T im e B a s e C lo c k S o u r c e T IM E R /2 5 6 V C L R T im e r W D T /4 W D T E N /D IS D D Q D C K C L R IR Q E N /D IS IR Q E N /D IS R W D T Timer and WDT Configurations Rev. 2.30 8 November 25, 2014 PATENTED The following are the data mode ID and the command mode ID: Mode ID READ Operation Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 Command 100 COMMAND Name HT16220/HT16220G If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to ²1² and the previous operation mode will be reset also. The CS pin returns to ²0², a new operation mode ID should be issued first. Command Code Function TONE OFF 0000-1000-X Turn-off tone output TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz Timing Diagrams READ Mode (Command Code : 1 1 0) C S W R R D D A T A 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 1 1 0 D a ta (M A 1 ) M e m o ry A d d re s s 1 (M A 1 ) A 5 A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 2 (M A 2 ) D 1 D 2 D 3 D a ta (M A 2 ) READ mode (successive address reading) C S W R R D D A T A Rev. 2.30 1 1 0 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) A 0 D 0 D 1 D 2 D a ta (M A ) 9 D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 2 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 3 ) November 25, 2014 PATENTED HT16220/HT16220G WRITE Mode (Command Code : 1 0 1) C S W R 1 D A T A 1 0 A 5 A 3 A 4 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 1 (M A 1 ) D 2 D 1 D 3 1 1 0 D a ta (M A 1 ) A 5 A 3 A 4 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 2 (M A 2 ) D 1 D 2 D 3 D a ta (M A 2 ) WRITE Mode (Successive Address Writing) C S W R 1 D A T A 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s (M A ) D 2 D 1 D 3 D 0 D 2 D 1 D 3 D 0 D a ta (M A + 1 ) D a ta (M A ) D 2 D 1 D 3 D 0 D a ta (M A + 2 ) D 1 D 2 D 3 D 0 D a ta (M A + 3 ) READ-MODIFY-WRITE Mode (Command Code : 1 0 1) C S W R R D D A T A 1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 M e m o ry A d d re s s 1 (M A 1 ) D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 1 0 D a ta (M A 1 ) D a ta (M A 1 ) A 5 1 A 4 A 3 A 2 A 1 A 0 M e m o ry A d d re s s 2 (M A 2 ) D 0 D 1 D 2 D 3 D a ta (M A 2 ) READ-MODIFY-WRITE Mode (Successive Address Accessing) C S W R R D D A T A Rev. 2.30 1 0 1 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D a ta (M A ) D a ta (M A ) 10 D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 2 ) November 25, 2014 PATENTED HT16220/HT16220G Command Mode (Command Code : 1 0 0) C S W R D A T A 1 0 0 C 8 C 7 C 6 C 5 C 4 C 3 C o m m a n d 1 C 2 C 1 C 8 C 0 C o m m a n d ... C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C o m m a n d i C o m m a n d o r D a ta M o d e Mode (Data And Command Mode) C S W R D A T A C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta R D Rev. 2.30 11 November 25, 2014 PATENTED HT16220/HT16220G Application Circuits C S * V D D *V R R D V L C D W R D A T A M C U B Z H T 1 6 2 2 0 *R P ie z o B Z IR Q O S C I C O M 0 ~ C O M 7 S E G 0 ~ S E G 3 1 C r y s ta l 3 2 7 6 8 H z O s c illa to r O S C O 1 /4 B ia s , 1 /8 D u ty L C D Note: P a n e l The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. The voltage applied to VLCD pin must be equal to or lower than VDD. Adjust VR to fit user's LCD panel display voltage (VLCD). Adjust R (external pull-high resistance) to fit user¢s time base clock. Command Summary Name ID Command Code D/C Function Def. READ 1 1 0 A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 1 0 1 A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM READ-MODIFYWRITE 1 0 1 A5A4A3A2A1A0D0D1D2D3 D Read and Write data to the RAM SYS DIS 1 0 0 0000-0000-X C Turn off both system oscillator and LCD Yes bias generator SYS EN 1 0 0 0000-0001-X C Turn on system oscillator LCD OFF 1 0 0 0000-0010-X C Turn off LCD display LCD ON 1 0 0 0000-0011-X C Turn on LCD display Yes TIMER DIS 1 0 0 0000-0100-X C Disable time base output Yes WDT DIS 1 0 0 0000-0101-X C Disable WDT time-out flag output Yes TIMER EN 1 0 0 0000-0110-X C Enable time base output WDT EN 1 0 0 0000-0111-X C Enable WDT time-out flag output TONE OFF 1 0 0 0000-1000-X C Turn off tone outputs CLR TIMER 1 0 0 0000-1101-X C Clear the contents of the time base generator CLR WDT 1 0 0 0000-1111-X C Clear the contents of the WDT stage TONE 4K 1 0 0 010X-XXXX-X C Tone frequency output: 4kHz TONE 2K 1 0 0 0110-XXXX-X C Tone frequency output: 2kHz IRQ DIS 1 0 0 100X-0XXX-X C Disable IRQ output IRQ EN 1 0 0 100X-1XXX-X C Enable IRQ output Rev. 2.30 12 Yes Yes November 25, 2014 PATENTED Name ID Command Code D/C HT16220/HT16220G Function Def. F1 1 0 0 101X-0000-X C Time base clock output: 1Hz The WDT time-out flag after: 4s F2 1 0 0 101X-0001-X C Time base clock output: 2Hz The WDT time-out flag after: 2s F4 1 0 0 101X-0010-X C Time base clock output: 4Hz The WDT time-out flag after: 1s F8 1 0 0 101X-0011-X C Time base clock output: 8Hz The WDT time-out flag after: 1/2s F16 1 0 0 101X-0100-X C Time base clock output: 16Hz The WDT time-out flag after: 1/4s F32 1 0 0 101X-0101-X C Time base clock output: 32Hz The WDT time-out flag after: 1/8s F64 1 0 0 101X-0110-X C Time base clock output: 64Hz The WDT time-out flag after: 1/16s F128 1 0 0 101X-0111-X C Time base clock output: 128Hz The WDT time-out flag after: 1/32s TEST 1 0 0 1110-0000-X C Test mode, user don¢t use. NORMAL 1 0 0 1110-0011-X C Normal mode Note: Yes Yes X : Don¢t care A5~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from a 32.768kHz crystal oscillator or an external 32768Hz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT16220 after power on reset, for power on reset may fail, which in turn leads to malfunctioning of the HT16220. Rev. 2.30 13 November 25, 2014 PATENTED HT16220/HT16220G Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. · Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) · Packing Meterials Information · Carton information Rev. 2.30 14 November 25, 2014 PATENTED HT16220/HT16220G 64-pin LQFP (7mm´7mm) Outline Dimensions C D 4 8 G 3 3 H I 3 2 4 9 F A B E 6 4 1 7 K a J 1 6 1 Symbol Nom. Max. A ¾ 0.354 BSC ¾ B ¾ 0.276 BSC ¾ C ¾ 0.354 BSC ¾ D ¾ 0.276 BSC ¾ E ¾ 0.020 BSC ¾ F 0.005 0.007 0.009 G 0.053 0.055 0.057 H ¾ ¾ 0.063 I 0.002 ¾ 0.006 J 0.018 0.024 0.030 K 0.004 ¾ 0.008 a 0° ¾ 7° Symbol A Rev. 2.30 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. ¾ 9.00 BSC ¾ B ¾ 7.00 BSC ¾ C ¾ 9.00 BSC ¾ D ¾ 7.00 BSC ¾ E ¾ 0.40 BSC ¾ F 0.13 0.18 0.23 G 1.35 1.40 1.45 H ¾ ¾ 1.60 I 0.05 ¾ 0.15 J 0.45 0.60 0.75 K 0.09 ¾ 0.20 a 0° ¾ 7° 15 November 25, 2014 PATENTED HT16220/HT16220G Copyright Ó 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.30 16 November 25, 2014