ISL84581 ® Data Sheet February 9, 2007 Low-Voltage, Single and Dual Supply, 8 to 1 Multiplexer The Intersil ISL84581 device contains precision, bidirectional, analog switches configured as an 8 to 1 multiplexer/ demultiplexer. It was designed to operate from a single +2V to +12V single supply or from dual ±2V to ±6V supplies. The device has an inhibit pin to simultaneously open all signal paths. ON resistance of 39Ω with a dual ±5V supply and 125Ω with a single +3.3V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25°C or 2.5nA at +85°C. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single 3.3V or +5V supply or dual ±5V supplies. The ISL84581 is a single 8 to 1 multiplexer device. Table 1 summarizes the performance of the part. SINGLE 8:1 MUX ±5V RON 39Ω ±5V tON/tOFF 32ns/18ns 12V RON 32Ω 12V tON/tOFF 23ns/15ns 5V RON 65Ω 5V tON/tOFF 38ns/19ns 3.3V RON 125Ω 3.3V tON/tOFF 70ns/32ns Package 16 Ld TSSOP • Fully Specified at 3.3V, 5V, ±5V, and 12V Supplies for 10% Tolerances • ON Resistance (RON) Max, VS = ±4.5V. . . . . . . . . . . 50Ω • ON Resistance (RON) Max, VS = +3V . . . . . . . . . . . 155Ω • RON Matching Between Channels, VS = ±5V. . . . . . . . . <2Ω • Low Charge Injection, VS = ±5V . . . . . . . . . . . . . 1pC (Max) • Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V • Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . ±2V to ±6V • Fast Switching Action (VS = +5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ns • Guaranteed Max Off-leakage . . . . . . . . . . . . . . . . . . . 2.5nA • Guaranteed Break-Before-Make • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Battery Powered, Handheld, and Portable Equipment • Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems • Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” • Application Note AN520 “CMOS Analog Multiplexers and Switches; Specifications and Application Considerations.” • Application Note AN1034 “Analog Switch and Multiplexer Applications” 1 Features • TTL, CMOS Compatible TABLE 1. FEATURES AT A GLANCE CONFIGURATION FN6416.0 • Audio and Video Signal Routing • Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL84581 Pinouts ISL84581 (16 LD TSSOP) TOP VIEW NO1 1 16 V+ NO3 2 15 NO2 COM 3 14 NO4 NO7 4 13 NO0 NO5 5 12 NO6 INH 6 LOGIC 11 ADDC V- 7 10 ADDB GND 8 9 ADDA NOTE: 1. Switches Shown for Logic “0” Inputs. Truth Tables Pin Descriptions ISL84581 PIN FUNCTION INH ADDC ADDB ADDA SWITCH ON V+ Positive Power Supply Input 0 0 0 0 NO0 V- 0 0 0 1 NO1 Negative Power Supply Input. Connect to GND for Single Supply Configurations. 0 0 1 0 NO2 0 0 1 1 NO3 0 1 0 0 NO4 ADDx Address Input Pin 0 1 0 1 NO5 COM Analog Switch Common Pin 0 1 1 0 NO6 NOx Analog Switch Normally Open Pin 0 1 1 1 NO7 1 X X X NONE GND Ground Connection INH Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and 10V. X = Don’t Care. Ordering Information PART NO. BRAND TEMP RANGE (°C) PACKAGE PKG. DWG. # ISL84581IVZ (See Note) 84581IVZ -40 to +85 16 Ld TSSOP (Pb-free) M16.173 ISL84581IVZ-T (See Note) 84581IVZ -40 to +85 16 Ld TSSOP, Tape and Reel (Pb-free) M16.173 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6416.0 February 9, 2007 ISL84581 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V Input Voltages INH, NOx, ADDx (Note 2). . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA Peak Current NOx, COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA ESD Rating HBM (Per Mil-STD-883, Method 3015.7) . . . . . . . . . . . . . . >2.5kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C (Lead Tips Only) Operating Conditions Temperature Range ISL84581IVZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on NOx, COM, ADDx, INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a high effective thermal conductivity test board with direct die attach. See Tech Brief TB379 for details. Electrical Specifications ±5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEMP (°C) (NOTE 5) MIN TYP Full V- - V+ V 25 - 44 60 Ω Full - - 80 Ω 25 - 1.3 4 Ω Full - - 6 Ω 25 - 7.5 9 Ω Full - - 12 Ω 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VINHH, VADDH Full 2.4 - - V Input Voltage Low, VINHL, VADDL Full - - 0.8 V Input Current, IADDH, IADDL, IINHH, IINHL VS = ±5.5V, VINH, VADD = 0V or V+ Full -0.5 - 0.5 μA 25 - 35 50 ns Full - - 60 ns PARAMETER TEST CONDITIONS (NOTE 5) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG VS = ±4.5V, ICOM = 2mA, VNO = 3V (See Figure 5) ON Resistance, RON RON Matching Between Channels, ΔRON VS = ±4.5V, ICOM = 2mA, VNO = 3V (Note 6) VS = ±4.5V, ICOM = 2mA, VNO = ±3V, 0V (Note 7) RON Flatness, RFLAT(ON) NO OFF Leakage Current, INO(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON) VS = ±5.5V, VCOM = ±4.5V, VNO = +4.5V (Note 8) VS = ±5.5V, VCOM = ±4.5V, VNO = +4.5V (Note 8) VS = ±5.5V, VCOM = VNO = ±4.5V (Note 8) DIGITAL INPUT CHARACTERISTICS DYNAMIC CHARACTERISTICS VS = ±4.5V, VNO = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3 (See Figure 1) INHIBIT Turn-ON Time, tON 3 FN6416.0 February 9, 2007 ISL84581 Electrical Specifications ±5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS VS = ±4.5V, VNO = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3 (See Figure 1) INHIBIT Turn-OFF Time, tOFF VS = ±4.5V, VNO = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3 (See Figure 1) Address Transition Time, tTRANS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS 25 - 22 35 ns Full - - 40 ns 25 - 43 60 ns Full - - 70 ns Break-Before-Make Time, tBBM VS = ±5.5V, VNO = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 3) Full 2 7 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2) 25 - 0.3 1 pC NO OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V (See Figure 6) 25 - 3 - pF COM OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V (See Figure 6) 25 - 21 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO = VCOM = 0V (See Figure 6) 25 - 26 - pF OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz, VNOx = 1VRMS (See Figures 4 and 18) 25 - 92 - dB Full ±2 - ±6 V Full -7 - 7 μA Full -1 - 1 μA POWER SUPPLY CHARACTERISTICS Power Supply Range VS = ±5.5V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, I- Electrical Specifications +12V Supply Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEMP (°C) (NOTE 5) MIN TYP Full 0 - V+ V 25 - 37 45 Ω Full - - 55 Ω 25 - 1.2 2 Ω Full - - 2 Ω 25 - 5 7 Ω Full - - 7 Ω 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VINHH, VADDH Full 3.7 3.3 - V Input Voltage Low, VINHL, VADDL Full - 2.7 0.8 V Full -0.5 - 0.5 μA PARAMETER TEST CONDITIONS (NOTE 5) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 10.8V, ICOM = 1.0mA, VNO = 9V (See Figure 5) RON Matching Between Channels, ΔRON V+ = 10.8V, ICOM = 1.0mA, VNO = 9V (Note 6) RON Flatness, RFLAT(ON) V+ = 10.8V, ICOM = 1.0mA, VNO = 3V, 6V, 9V (Note 7) NO OFF Leakage Current, INO(OFF) COM OFF Leakage Current, ICOM(OFF) V+ = 13.2V, VCOM = 1V, 12V, VNO = 12V, 1V (Note 8) V+ = 13.2V, VCOM = 12V, 1V, VNO = 1V, 12V (Note 8) COM ON Leakage Current, ICOM(ON) V+ = 13.2V, VCOM = 1V, 12V, VNO = 1V, 12V, or floating (Note 8) DIGITAL INPUT CHARACTERISTICS Input Current, IADDH, IADDL, IINHH, IINHL 4 V+ = 13.2V, VINH, VADD = 0V or V+ FN6416.0 February 9, 2007 ISL84581 Electrical Specifications +12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS 25 - 24 40 ns Full - - 45 ns 25 - 15 30 ns Full - - 35 ns 25 - 27 50 ns Full - - 55 ns DYNAMIC CHARACTERISTICS V+ = 10.8V, VNO = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 4 (See Figure 1) INHIBIT Turn-ON Time, tON INHIBIT Turn-OFF Time, tOFF V+ = 10.8V, VNO = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 4 (See Figure 1) Address Transition Time, tTRANS V+ = 10.8V, VNO = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 4 (See Figure 1) Break-Before-Make Time Delay, tD V+ = 13.2V, RL = 300Ω, CL = 35pF, VNO = 10V, VIN = 0 to 4 (See Figure 3) Full 2 5 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2) 25 - 2.7 5 pC OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz (See Figure 4 and 18) 25 - 92 - dB NO OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V (See Figure 6) 25 - 3 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO = VCOM = 0V (See Figure 6) 25 - 21 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO = VCOM = 0V (See Figure 6) 25 - 26 - pF Full 2 - 12 V Full -7 - 7 μA POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 13.2V, VINH, VADD = 0V or V+, all channels on or off Electrical Specifications 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Full 0 - V+ V 25 - 81 100 Ω Full - - 120 Ω 25 - 2.2 4 Ω Full - - 6 Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 4.5V, ICOM = 1.0mA, VNO = 3.5V (See Figure 5) ON Resistance, RON RON Matching Between Channels, ΔRON V+ = 4.5V, ICOM = 1.0mA, VNO = 3V (Note 6) RON Flatness, RFLAT(ON) V+ = 4.5V, ICOM = 1.0mA, VNO = 1V, 2V, 3V (Note 7) Full - 11.5 - Ω NO OFF Leakage Current, INO(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO = 4.5V, 1V (Note 8) 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Full 2.4 - - V COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO = 4.5V, 1V (Note 8) COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = VNO = 4.5V (Note 8) DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINHH, VADDH 5 FN6416.0 February 9, 2007 ISL84581 Electrical Specifications 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEMP (°C) (NOTE 5) MIN TYP Full - - 0.8 V V+ = 5.5V, VINH, VADD = 0V or V+ Full -0.5 - 0.5 μA V+ = 4.5V, VNO = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 1) 25 - 43 60 ns Full - - 70 ns 25 - 20 35 ns Full - - 40 ns 25 - 51 70 ns Full - - 85 ns PARAMETER TEST CONDITIONS Input Voltage Low, VINHL, VADDL Input Current, IADDH, IADDL, IINHH, IINHL (NOTE 5) MAX UNITS DYNAMIC CHARACTERISTICS INHIBIT Turn-ON Time, tON INHIBIT Turn-OFF Time, tOFF V+ = 4.5V, VNO = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 1) Address Transition Time, tTRANS V+ = 4.5V, VNO = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 1) Break-Before-Make Time, tBBM V+ = 5.5V, VNO = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 3) Full 2 9 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2) 25 - 0.6 1.5 pC OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz, VNOx = 1VRMS (See Figures 4 and 18) 25 - 92 - dB Full 2 - 12 V Full -7 - 7 μA Full -1 - 1 μA POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Positive Supply Current, I- Electrical Specifications 3.3V Supply PARAMETER Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Full 0 - V+ V 25 - 135 180 Ω Full - - 200 Ω 25 - 3.4 8 Ω Full - - 10 Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3.0V, ICOM = 1.0mA, VNO = 1.5V (See Figure 5) RON Matching Between Channels, ΔRON V+ = 3.0V, ICOM = 1.0mA, VNO = 1.5V (Note 6) RON Flatness, RFLAT(ON) V+ = 3.0V, ICOM = 1.0mA, VNO = 0.5V, 1V, 2V (Note 7) Full - 34 - Ω NO OFF Leakage Current, INO(OFF) V+ = 3.6V, VCOM = 0V, 4.5V, VNO = 3V, 1V (Note 8) 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VINHH, VADDH Full 2.4 - - V Input Voltage Low, VINHL, VADDL Full - - 0.8 V COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 0V, 4.5V, VNO = 3V, 1V (Note 8) COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = VNO = 3V (Note 8) DIGITAL INPUT CHARACTERISTICS 6 FN6416.0 February 9, 2007 ISL84581 Electrical Specifications 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEMP (°C) (NOTE 5) MIN TYP V+ = 3.6V, VINH, VADD = 0V or V+ Full -0.5 - 0.5 μA V+ = 3.0V, VNO = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 1) 25 - 82 100 ns Full - - 120 ns 25 - 37 50 ns Full - - 60 ns 25 - 96 120 ns Full - - 145 ns PARAMETER TEST CONDITIONS Input Current, IADDH, IADDL, IINHH, IINHL (NOTE 5) MAX UNITS DYNAMIC CHARACTERISTICS INHIBIT Turn-ON Time, tON INHIBIT Turn-OFF Time, tOFF V+ = 3.0V, VNO = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 1) V+ = 3.0V, VNO = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 1) Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 3.6V, VNO = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (See Figure 3) Full 3 13 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2) 25 - 0.3 1 pC OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz, VNO = 1VRMS (See Figures 4 and 18) 25 - 92 - dB Full 2 - 12 V POWER SUPPLY CHARACTERISTICS Power Supply Range NOTES: 4. VIN = Input logic voltage to configure the device in a given state. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. ΔRON = RON (MAX) - RON (MIN). 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C. 9. Between any two switches. Test Circuits and Waveforms V+ 3V LOGIC INPUT tr < 20ns tf < 20ns 50% V- C C 0V V+ tON VNO0 SWITCH OUTPUT C 90% VOUT NO0 NO1-NO7 INH 90% 0V LOGIC INPUT COM GND ADDA-C VOUT RL 300Ω CL 35pF tOFF Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS 7 Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT FN6416.0 February 9, 2007 ISL84581 Test Circuits and Waveforms (Continued) 3V LOGIC INPUT tr < 20ns tf < 20ns 50% V+ C V- C C 0V V+ tTRANS NO0 V- NO7 C VOUT VNO0 SWITCH OUTPUT NO1-NO6 90% 0V VOUT COM ADDA-C GND INH CL 35pF RL 300Ω LOGIC INPUT 10% VNOX tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES V+ V- C C 3V LOGIC INPUT OFF OFF ON 0V VOUT RG COM NO SWITCH OUTPUT VOUT 0Ω ΔVOUT ADDX GND VG INH LOGIC INPUT Q = ΔVOUT x CL CL 1nF Repeat test for other switches. FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ tr < 20ns tf < 20ns 3V V- C C LOGIC INPUT COM 0V LOGIC INPUT tBBM FIGURE 3A. tBBM MEASUREMENT POINTS CL 35pF ADDA-C 80% 0V VOUT RL 300Ω NO0-NO7 V+ SWITCH OUTPUT VOUT C GND INH Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 8 FN6416.0 February 9, 2007 ISL84581 Test Circuits and Waveforms V+ C (Continued) V- V+ C V- C C RON = V1/1mA SIGNAL GENERATOR NO NOx VNOX 0V or V+ 1mA ADDX ANALYZER COM 0V or V+ GND 0V or V+ V1 ADDX COM INH GND INH RL FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. RON TEST CIRCUIT V+ V- C C NOx 0V or V+ ADDX IMPEDANCE ANALYZER COM GND INH FIGURE 6. CAPACITANCE TEST CIRCUIT Detailed Description The ISL84581 multiplexer offers precise switching capability from bipolar ±2V to ±6Vsupplies or a single 2V to 12V supply. When powered with dual ±5V supplies the part has low onresistance (39Ω) and high speed operation (tON = 38ns, tOFF = 19ns). It has an inhibit pin to simultaneously open all signal paths. The device is especially well suited for applications using ±5V supplies. With ±5V supplies the performance (RON, Leakage, Charge Injection, etc.) is best in class. High frequency applications also benefit from the wide bandwidth and high off isolation. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain 9 ESD protection diodes from the pin to V+ and to V- (see Figure 7). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from 1V below V+ to FN6416.0 February 9, 2007 ISL84581 1V above V-. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1kΩ OPTIONAL PROTECTION DIODE V+ LOGIC VCOM VNOx VOPTIONAL PROTECTION DIODE FIGURE 7. INPUT OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL84581 construction is typical of most CMOS analog switches, in that it has three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL84581 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. The part performs equally well when operated with bipolar or single voltage supplies.The minimum recommended supply voltage is 2V single supply or ±2V dual supply. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and “Typical Performance Curves” on page 11 for details. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 100MHz (see Figures 16 and 17). Figures 16 and 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off Isolation is the resistance to this feed through. Figure 18 details the high Off Isolation of the ISL84581. At 10MHz, Off Isolation is about 55dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. V+ and GND power the internal logic setting the digital switching point of the level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. Logic-Level Thresholds V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This ISL84581 is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH level is about 3.3V. This is still below the CMOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. 10 FN6416.0 February 9, 2007 ISL84581 Typical Performance Curves TA = +25°C, Unless Otherwise Specified 70 VCOM = (V+) - 1V ICOM = 1mA V- = -5V 60 +85°C 40 +25°C 30 -40°C 20 400 RON (Ω) RON (Ω) 50 V- = 0V 300 200 +85°C 120 110 100 90 80 70 60 50 90 80 70 60 50 40 30 60 -40°C VS = ±3V +85°C +25°C -40°C VS = ±5V +85°C +25°C 40 100 -40°C 30 -40°C 20 2 3 4 5 6 7 V+ (V) 8 9 10 11 -5 12 FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE 225 200 -4 -3 -1 -2 RON (Ω) V+ = 3.3V -40°C V- = 0V V- = 0V +85°C 40 35 +25°C 30 V+ = 5V +85°C V- = 0V 25 +25°C -40°C -40°C 0 1 5 45 +85°C +25°C 4 50 V+ = 2.7V V- = 0V -40°C 75 160 140 120 100 80 60 100 90 80 70 60 50 40 3 ICOM = 1mA V+ = 12V +85°C +25°C 2 60 55 125 100 1 0 VCOM (V) FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE ICOM = 1mA 175 150 RON (Ω) VS = ±2V +85°C +25°C 50 +25°C 0 ICOM = 1mA 2 VCOM (V) 3 4 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE 11 20 5 0 2 4 6 8 10 12 VCOM (V) FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FN6416.0 February 9, 2007 ISL84581 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 200 500 400 -40°C 200 tOFF (ns) -40°C V- = 0V 200 +85°C 150 50 0 100 V- = 0V 80 85°C +85°C +25°C 25°C 40 20 -40°C 0 0 2 85°C +85°C -40°C 60 +25°C 100 25°C +25°C 50 +85°C 100 0 250 +25°C 100 +25°C 3 4 5 6 7 8 9 10 11 12 -40°C 2 3 4 5 6 8 7 10 9 11 12 V+ (V) V+ (V) FIGURE 12. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE 300 FIGURE 13. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE 250 VCOM = (V+) - 1V VCOM = (V+) - 1V V- = 0V 250 200 tRANS (ns) 200 tRANS (ns) VCOM = (V+) - 1V V- = -5V -40°C 150 +25°C 300 tON (ns) VCOM = (V+) - 1V V- = -5V 150 100 150 100 +25°C +25°C +85°C +85°C 50 50 -40°C -40°C 0 0 2 3 4 5 6 7 8 9 10 11 12 V+ (V) FIGURE 14. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE 12 13 2 3 4 5 6 V± (V) FIGURE 15. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE FN6416.0 February 9, 2007 ISL84581 VIN = 0.2VP-P to 5VP-P GAIN 0 -3 VS = ±3V GAIN 0 -3 0 PHASE VIN = 0.2VP-P to 4VP-P 3 0 PHASE 45 45 90 90 135 180 135 180 RL = 50Ω RL = 50Ω 1 10 100 600 1 10 FREQUENCY (MHz) 100 600 FREQUENCY (MHz) FIGURE 17. FREQUENCY RESPONSE FIGURE 16. FREQUENCY RESPONSE -10 3 V+ = 3V to 12V or -20 VS = ±2V to ±5V RL = 50Ω -30 2 V+ = 3.3V V- = 0V 1 -40 -50 V+ = 12V V- = 0V 0 -60 Q (pC) OFF ISOLATION (dB) PHASE (°) NORMALIZED GAIN (dB) VS = ±5V 3 PHASE (°) NORMALIZED GAIN (dB) Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) ISOLATION -70 V+ = 5V V- = 0V -1 VS = ±5V -2 -80 -90 -3 -100 -110 1k -4 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 18. OFF ISOLATION 100M 500M -5 -2.5 0 2.5 5 7.5 10 12 VCOM (V) FIGURE 19. CHARGE INJECTION vs SWITCH VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: 193 PROCESS: Si Gate CMOS 13 FN6416.0 February 9, 2007 ISL84581 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M E1 2 INCHES GAUGE PLANE -B1 B M 0.05(0.002) -A- SYMBOL MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - A1 3 L A D -C- e α A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE c 0.10(0.004) C A M 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - B S 0.002 D 0.193 0.201 4.90 5.10 3 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 N α NOTES: 0.006 E1 e A2 MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 0.70 6 16 8o 0o - 6.50 7 8o 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6416.0 February 9, 2007