HA-2542 Data Sheet October 1999 70MHz, High Slew Rate, High Output Current Operational Amplifier File Number Features • Stable at Gains of 2 or Greater The HA-2542 is a wideband, high slew rate, monolithic operational amplifier featuring an outstanding combination of speed, bandwidth, and output drive capability. Utilizing the advantages of the Intersil D.I. technology this amplifier offers 350V/µs slew rate, 70MHz gain bandwidth, and ±100mA output current. Application of this device is further enhanced through stable operation down to closed loop gains of 2. For additional flexibility, offset null and frequency compensation controls are included in the HA-2542 pinout. The capabilities of the HA-2542 are ideally suited for high speed coaxial cable driver circuits where low gain and high output drive requirements are necessary. With 5.5MHz full power bandwidth, this amplifier is most suitable for high frequency signal conditioning circuits and pulse video amplifiers. Other applications utilizing the HA-2542 advantages include wideband amplifiers and fast samplehold circuits. • Gain Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 70MHz • High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 300V/µs (Min) • High Output Current . . . . . . . . . . . . . . . . . . . 100mA (Min) • Power Bandwidth . . . . . . . . . . . . . . . . . . . . . 5.5MHz (Typ) • Output Voltage Swing . . . . . . . . . . . . . . . . . . . ±10V (Min) • Monolithic Bipolar Dielectric Isolation Construction Applications • Pulse and Video Amplifiers • Wideband Amplifiers • Coaxial Cable Drivers • Fast Sample-Hold Circuits • High Frequency Signal Conditioning Circuits Pinout For more information on the HA-2542, please refer to Application Note AN552 (Using the HA-2542), or Application Note AN556 (Thermal Safe-Operating-Areas for High Current Op Amps). For a lower power version of this product, please see the HA-2842 data sheet. HA-2542 (PDIP, CERDIP) TOP VIEW NC 1 14 NC NC 2 13 BAL BAL 3 -IN 4 Ordering Information PART NUMBER TEMP. RANGE (oC) +IN 5 PACKAGE PKG. NO. HA1-2542-5 0 to 75 14 Ld CERDIP F14.3 HA3-2542-5 0 to 75 14 Ld PDIP E14.3 1 2899.3 12 COMP + 11 V+ 10 OUT V- 6 9 NC NC 7 8 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA-2542 Absolute Maximum Ratings Thermal Information Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . .35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Output Current . . . . . . . . . . . . . . . . 50mA Continuous, 125mAPEAK Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 95 N/A Maximum Junction Temperature (Note 1, Hermetic Packages) . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Range HA-2542-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175oC for ceramic packages, and below 150oC for plastic packages. By using Application Note AN556 on Safe Operating Area equations, along with the thermal resistances, proper load conditions can be determined. Heatsinking will be required in many applications. See the “Application Information” section to determine if heat sinking is required for your application. 2. θJA is measured with the component mounted on an evaluation PC board in free air. VSUPPLY = ±15V, RL = 1kΩ, CL ≤ 10pF, Unless Otherwise Specified Electrical Specifications TEMP. (oC) MIN TYP MAX UNITS 25 - 5 10 mV Full - 8 20 mV Average Offset Voltage Drift Full - 14 - µV/oC Bias Current 25 - 15 35 µA Full - 26 50 µA Average Bias Current Drift Full - 45 - nA/oC Offset Current 25 - 1 7 µA Full - - 9 µA Input Resistance 25 - 100 - kΩ Input Capacitance 25 - 1 - pF Common Mode Range Full ±10 - - V PARAMETER TEST CONDITIONS HA-2542-5 0oC TO 75oC INPUT CHARACTERISTICS Offset Voltage Input Noise Voltage 0.1Hz to 100Hz 25 - 2.2 - µVP-P Input Noise Density f = 1kHz, RG = 0Ω 25 - 10 - nV/√Hz Input Noise Current Density f = 1kHz, RG = 0Ω 25 - 3 - pA/√Hz VO = ±10V 25 10 30 - kV/V Full 5 20 - kV/V Full 70 100 - dB 25 2 - - V/V 25 - 70 - MHz Output Voltage Swing Full ±10 ±11 - V Output Current (Note 3) 25 100 - - mA Output Resistance 25 - 5 - Ω TRANSFER CHARACTERISTICS Large Signal Voltage Gain VCM = ±10V Common Mode Rejection Ratio Minimum Stable Gain Gain Bandwidth Product AV = 100 OUTPUT CHARACTERISTICS 2 HA-2542 VSUPPLY = ±15V, RL = 1kΩ, CL ≤ 10pF, Unless Otherwise Specified (Continued) Electrical Specifications TEST CONDITIONS HA-2542-5 0oC TO 75oC TEMP. (oC) MIN TYP MAX UNITS 25 4.7 5.5 - MHz Differential Gain (Note 5) 25 - 0.1 - % Differential Phase (Note 5) 25 - 0.2 - Degree Harmonic Distortion (Note 7) 25 - <0.04 - % Rise Time 25 - 4 - ns Overshoot 25 - 25 - % Slew Rate 25 300 350 - V/µs 10V Step to 0.1% 25 - 100 - ns 10V Step to 0.01% 25 - 200 - ns 25 - 30 - mA Full - 31 40 mA Full 70 79 - dB PARAMETER Full Power Bandwidth (Note 4) VPEAK = 10V TRANSIENT RESPONSE (Note 6) Settling Time POWER SUPPLY CHARACTERISTICS Supply Current VS = ±5V to ±15V Power Supply Rejection Ratio NOTES: 3. RL = 50Ω, VO = ±5V, Output duty cycle must be reduced for IOUT > 50mA (e.g. ≤50% duty cycle for 100mA). Slew Rate 4. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = ----------------------------- . 2πV PEAK 5. Differential gain and phase are measured at 5MHz with a 1V differential input voltage. 6. Refer to Test Circuits section of this data sheet. 7. VIN = 1VRMS; f = 10kHz; AV = 10. Test Circuits and Waveforms IN + OUT - 500Ω VIN 500Ω NOTES: 8. VS = ±15V. VOUT 9. AV = +2. 10. CL ≤ 10pF. TEST CIRCUIT 3 Vertical Scale: VIN = 2.0V/Div., VOUT = 5.0V/Div. Horizontal Scale: 200ns/Div. LARGE SIGNAL RESPONSE HA-2542 Test Circuits and Waveforms (Continued) VIN VOUT Vertical Scale: 100mV/Div. Horizontal Scale: 50ns/Div. Vertical Scale: 100mV/Div. Horizontal Scale: 10ns/Div. VS = ±15V, RL = 1kΩ. Propagation delay variance is negligible over full temperature range. SMALL SIGNAL RESPONSE PROPAGATION DELAY NOTES: SETTLING POINT 2.5kΩ 11. AV = -2. 12. Feedback and summing resistors must be matched (0.1%). 13. HP5082-2810 clipping diodes recommended. 5kΩ 14. Tektronix P6201 FET probe used at settling point. 1kΩ 500Ω VIN 15. For 0.01% settling time, heat sinking is suggested to reduce thermal effects and an analog ground plane with supply decoupling is suggested to minimize ground loop errors. V+ - VOUT + V- SETTLING TIME TEST CIRCUIT (SEE NOTES 11 - 15.) Schematic Diagram BAL R11 R7 R8 R10 75Ω R9 QP15 QP13 QP14 BAL R25 5kΩ R12 75Ω QP16 QP34 R26 5kΩ R15 QP35 QP33 R14 QN12 QP32 QP5 QP31 QP7 QP11 QN23 QN42 +IN QN44 C1 QN2 QN1 QP36 -IN QN R6 R18 COMP DZ45 QN18 4 HA-2542 Application Information (Refer to Application Note AN552 for Further Information) The Intersil HA-2542 is a state of the art monolithic device which also approaches the “ALL-IN-ONE” amplifier concept. This device features an outstanding set of AC parameters augmented by excellent output drive capability providing for suitable application in both high speed and high output drive circuits. Primarily intended to be used in balanced 50Ω and 75Ω coaxial cable systems as a driver, the HA-2542 could also be used as a power booster in audio systems as well as a power amp in power supply circuits. This device would also be suitable as a small DC motor driver. The applications shown in Figures 2 through Figure 4 demonstrate the HA-2542 at gains of +100 and +2 and as a video cable driver for small signals. Power Dissipation Considerations At high output currents, especially with the PDIP package, care must be taken to ensure that the Maximum Junction Temperature (TJ, see “Absolute Maximum Ratings” table) is not exceeded. As an example consider the HA-2542 in the PDIP package, with a required output current of 20mA at VOUT = 5V. The power dissipation is the quiescent power (1.2W = 30V x 40mA) plus the power dissipated in the output stage (POUT = 200mW = 20mA x (15V - 5V)), or a total of 1.4W. The thermal resistance (θJA) of the PDIP package is 100oC/W, which increases the junction temperature by 140oC over the ambient temperature (TA). Remaining below TJMAX requires that TA be restricted to ≤ 10oC (150oC - 140oC). Heatsinking would be required for operation at ambient temperatures greater than 10oC. MAXIMUM TA WITHOUT HEATSINK (oC) Note that the problem isn’t as severe with the CERDIP package due to it’s lower thermal resistance, and higher TJMAX. Nevertheless, it is recommended that Figure 1 be used to ensure that heat sinking is not required. 120 VOUT = ±5V VS = ±15V 100 80 60 CERDIP 40 20 PDIP 0 0 5 10 15 20 25 30 35 40 45 OUTPUT CURRENT (100% DUTY CYCLE, mA) 50 FIGURE 1. MAXIMUM OPERATING TEMPERATURE vs OUTPUT CURRENT Allowable output power can be increased by decreasing the quiescent dissipation via lower supply voltages. For more information please refer to Application Note AN556, “Thermal Safe Operating Areas for High Current Op Amps”. Prototyping Guidelines For best overall performance in any application, it is recommended that high frequency layout techniques be used. This should include: 1) mounting the device through a ground plane: 2) connecting unused pins (NC) to the ground: 3) mounting feedback components on Teflon standoffs and or locating these components as close to the device as possible: 4) placing power supply decoupling capacitors from device supply pins to ground. 5 HA-2542 Frequency Compensation The HA-2542 may be externally compensated with a single capacitor to ground. This provides the user the additional flexibility in tailoring the frequency response of the amplifier. A guideline to the response is demonstrated on the typical performance curve showing the normalized AC parameters versus compensation capacitance. It is suggested that the user check and tailor the accurate compensation value for each application. As shown additional phase margin is achieved at the loss of slew rate and bandwidth. For example, for a voltage gain of +2 (or -1) and a load of 500pF/2kΩ, 20pF is needed for compensation to give a small signal bandwidth of 30MHz with 40o of phase margin. If a full power output voltage of ±10V is needed, this same configuration will provide a bandwidth of 5MHz and a slew rate of 200V/µs. If maximum bandwidth is desired and no compensation is needed, care must be given to minimize parasitic capacitance at the compensation pin. In some cases where minimum gain applications are desired, bending up or totally removing this pin may be the solution. In this case, care must also be given to minimize load capacitance. For wideband positive unity gain applications, the HA-2542 can also be over-compensated with capacitance greater than 30pF to achieve bandwidths of around 25MHz. This over-compensation will also improve capacitive load handling or lower the noise bandwidth. This versatility along with the ±100mA output current makes the HA-2542 an excellent high speed driver for many power applications. Typical Applications IN 30 20 10 0 0 + OUT - -45 990Ω -90 10Ω -135 -180 PHASE (DEGREES) GAIN (dB) 40 Frequency (0dB) = 44.9MHz, Phase Margin (0dB) = 40o FREQUENCY RESPONSE FIGURE 2. NONINVERTING CIRCUIT (AVCL = 100) + OUT - 50Ω 6 4 2 0 0 50Ω -45 -90 -135 -180 Frequency (dB) = 56MHz, Phase Margin (3dB) = 40o FREQUENCY RESPONSE FIGURE 3. NONINVERTING CIRCUIT (AVCL = 2) 6 PHASE (DEGREES) IN GAIN (dB) 8 HA-2542 Typical Applications IN (Continued) 75Ω + OUT - IN 1kΩ 75Ω 1kΩ OUT 1V/Div.; 100ns/Div. PULSE RESPONSE FIGURE 4. VIDEO CABLE DRIVER (AVCL = 2) RT 1 14 2 13 3 12 - 4 + NOTES: 16. Suggested compensation scheme 5pF - 20pF. CCOMP 11 V+ 5 10 6 9 7 8 17. Tested Offset Adjustment Range is |VOS +1mV| minimum referred to output. 18. Typical range is ±20mV with RT = 5kΩ. FIGURE 5. SUGGESTED OFFSET VOLTAGE ADJUSTMENT AND FREQUENCY COMPENSATION 7 HA-2542 Typical Performance Curves 10 1000 100 INPUT NOISE VOLTAGE 10 10 INPUT NOISE CURRENT VS = ±12V SIX REPRESENTATIVE UNITS 8 OFFSET VOLTAGE (mV) 100 INPUT NOISE CURRENT (pA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 1000 6 4 2 0 -2 -4 -6 -8 1 100K 1 1 10 100 1K 10K -10 -60 -40 -20 0 FIGURE 6. INPUT NOISE VOLTAGE AND INPUT NOISE CURRENT vs FREQUENCY BIAS CURRENT (µA) INPUT RESISTANCE (Ω) 80 100 120 VS = ±12V SIX REPRESENTATIVE UNITS 27 25 10K V+ + - 100 60 29 100K V- 40 FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE TA = 25oC VS = ±15V 1000 20 TEMPERATURE (oC) FREQUENCY (Hz) 900Ω 23 21 19 17 15 13 11 100Ω 9 10 100K 1M 10M FREQUENCY (Hz) 7 -60 100M -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 8. INPUT RESISTANCE vs FREQUENCY FIGURE 9. BIAS CURRENT vs TEMPERATURE 18 120 TA = 25oC 17 VS = ±15V SIX REPRESENTATIVE UNITS 16 110 CMRR 15 14 100 13 (dB) BIAS CURRENT (µA) -40 12 90 11 10 80 9 PSRR 8 7 5 7 9 11 SUPPLY VOLTAGE (±V) 13 FIGURE 10. BIAS CURRENT vs SUPPLY VOLTAGE 8 15 70 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (oC) FIGURE 11. PSRR AND CMRR vs TEMPERATURE 120 HA-2542 Typical Performance Curves (Continued) 32 VS = ±15V TA = 25oC RL = 2kΩ 120 28 CMRR 100 -55oC 26 +PSRR 80 24 (dB) SUPPLY CURRENT (mA) 30 22 -PSRR 60 20 40 18 25oC 20 0 16 14 125oC 12 4 6 8 10 12 SUPPLY VOLTAGE (±V) 100 14 100K 1M 10M FIGURE 13. PSRR AND CMRR vs FREQUENCY 500 55 RL = 100Ω 400 AV = 2 ±15V AV = 2 ±10V 50 45 300 AV = 2 200 ±5V AV = 10 AV = 10 0 -50 -25 0 25 50 75 TEMPERATURE (oC) VS = ±7 30 ±10V 20 ±5V 15 100 VS = ±15 35 VS = ±8 25 ±15V AV = 10 100 VS = ±12 40 AVOL (kV/V) SLEW RATE (V/µs) 10K FREQUENCY (Hz) FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE, AT VARIOUS TEMPERATURES 10 -60 125 FIGURE 14. SLEW RATE vs TEMPERATURE AT VARIOUS SUPPLY VOLTAGES -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 120 FIGURE 15. OPEN LOOP GAIN vs TEMPERATURE, AT VARIOUS SUPPLY VOLTAGES 12.0 1.4 10.0 -55oC 8.0 +VOUT 6.0 25oC +VOUT 125oC +VOUT NORMALIZED TO VALUE AT 0pF OUTPUT VOLTAGE SWING (V) 1K 4.0 2.0 0.0 -2.0 -4.0 -6.0 -8.0 25oC -10.0 -55oC -12.0 -VOUT -VOUT 125oC -VOUT 7 9 11 SUPPLY VOLTAGE (±V) 13 15 FIGURE 16. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE, AT VARIOUS TEMPERATURES 9 1.2 PHASE MARGIN 1.1 1.0 0.9 0.8 0.7 SLEW RATE 0.6 -14.0 5 1.3 BANDWIDTH 0.5 0 5 10 15 20 COMPENSATION CAPACITANCE (pF) FIGURE 17. NORMALIZED AC PARAMETERS vs COMPENSATION CAPACITANCE 25 HA-2542 HA-2542 AV = 10 VS = ±15V TA = 25oC MAXIMUM SWING RL = 1kΩ 10 8 4 UNDISTORTED SWING RL = 100Ω MAXIMUM SWING UNDISTORTED SWING 0 1 10 FREQUENCY (Hz) 60 HA-2542 TA = 25oC RL = 1kΩ VS = ±15V AV = 1000 50 GAIN (dB) UNDISTORTED SWING 6 4 RL = 100Ω MAXIMUM SWING UNDISTORTED SWING 1 AV = 100 25oC 12 125oC 9 GAIN 6 -55oC 3 PHASE + - AV = 10 VAV = 2 0 0.1 1 10 FREQUENCY (MHz) FIGURE 20. FREQUENCY RESPONSE CURVES 10 100 100K -55oC V+ VIN 30 10 100 FIGURE 19. OUTPUT VOLTAGE SWING vs FREQUENCY 0 20 10 FREQUENCY (Hz) GAIN (dB) 70 RL = 1kΩ MAXIMUM SWING 8 0 0.1 100 FIGURE 18. OUTPUT VOLTAGE SWING vs FREQUENCY 40 10 2 2 0.1 HA-2542 AV = 10 VS = ±10V TA = 25oC 12 25oC GAIN = +2 500Ω VS = ±8V RL = 1kΩ 500Ω CL ≤ 10pF VIN ≤ 90mV 125oC 1M 10M FREQUENCY (Hz) 0 -45 -90 -135 -180 PHASE (DEGREES) OUTPUT VOLTAGE (V) 12 6 (Continued) OUTPUT VOLTAGE (V) Typical Performance Curves 100M FIGURE 21. HA-2542 CLOSED LOOP GAIN vs TEMPERATURE HA-2542 Die Characteristics DIE DIMENSIONS: SUBSTRATE POTENTIAL (POWERED UP): 106 mils x 73 mils x 19 mils 2700µm x 1850µm x 483µm VTRANSISTOR COUNT: METALLIZATION: 43 Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PROCESS: Bipolar Dielectric Isolation PASSIVATION Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ Metallization Mask Layout HA-2542 -IN +IN BAL BAL V- 11 OUTPUT V+ COMP HA-2542 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) LEAD FINISH c1 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 12 NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 14 14 8 Rev. 0 4/94 HA-2542 Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D) N 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 A1 D1 e B1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 C D 0.735 0.775 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 0.204 14 0.355 18.66 19.68 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 10.92 7 3.81 4 14 9 Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 13 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029