For Communications Equipment MN86074 Image Processing LSI Overview The MN86074 boosts image quality by applying various image processing techniques to the analog signal from an image sensor. Features include correction of laser printer dot spreading at the pixel level, processing to enhance the compression ratio, reproduction of halftone images with 64-gradation, two-dimensional MTF correction using moire suppression, and infinite shading for all pixels using a division technique. These combine to yield top image reproduction quality. Features Image processing that yields top image quality • Infinite shading for all pixels using a division technique • Error dispersion processing that reproduces halftone images with 64-gradation User-programmable gamma curve • Two dimensional MTF correction • High-quality reduction with a user-specified scaling factor Preserves halftone gradation Preserves fine black lines for text High-speed processing requiring only 2 ms per line for an A3 page at 200 dpi Built-in analog processing circuits: offset correction circuit, gain correction circuit, and 8-bit analog-to- Gain control: Analog control using an external operational amplifier and the built-in field effect transistor (FET) An external resistor determines the follow-up range. (The standard range is from +6 dB to –12 dB.) Built-in circuits: Gain control circuit + FET A/D converter: Half flash converter Number of bits: 8 Conversion speed: 0.1 to 1.5 MHz Shading correction • Infinite shading for all pixels using a division technique Distortion correction levels relative to A/D converter's dynamic range 0 – 75%................... 6-bit precision 75 – 87.5%............... 5-bit precision 87.5 – 93.8%............ 4-bit precision MTF correction: • Laplacian transforms (processing for text images) Reference to five pixels Halftone processing • Error dispersion processing: Reproduction of 64gradation using 6-bit processing Gamma correction: digital converter Drive signal generator for CCDs, CISs, and other • User-definable by loading a conversion curve image sensors Binary coded: Conversion levels: 6 bits to 6 • Fixed slice Brief Specifications Image processing speed: 0.1 to 1.5 million pixels per second Pixels per line: max. 8192 pixels-blanking pixels 1-line interval: max. 8192 pixels Offset correction: negative feedback to preamplifier The chip controls the feedback voltage using A/D conversion data from black pixel runs. Built-in circuits: Feedback voltage control circuit + source follower circuit Slice level: User-specified 5-bit value Reduction in primary scanning direction: • Decimation with image clock or line enable Reduction ratio in primary scanning direction: Binary coded 0.78% to 100% Halftone processing: 50 to 100% (in 0.78% increments) Reduction correction in primary scanning direction • Black pixel preservation (for reduction in primary scanning direction) MN86074 For Communications Equipment Line density correction in secondary scanning direction Power supply • Three-line OR processing (for line density conversion in secondary scanning direction from 7.7 • Digital circuits, DVDD : 5.0 V line/mm to 3.85) Clock inputs • Analog circuits, AVDD : 5.0 V • A/D converter reference voltages · Image clock × 16 VREFH: 5.0 to 3.0V · Image clock × 8 VREFL: 2.0 to 0.0V Sensor interfaces • CCD sensor Applications Generates the following drive signals: FSH (øSH), FCK1, 2 (ø1, 2), FR (øR), FSP (øSP) • Contacting image sensor Generates the following drive signals: FSH (SI), FSP (CLK). FSP (CLK): 75% or 87.5%. Memory interfaces • Line lengths up to 2048 pixels 64-Kbit SRAM ×1 • Line lengths of 2049 to 4096 pixels 64-Kbit SRAM ×2 or 256-Kbit SRAM ×1 • Line lengths of 4097 to 8192 pixels 256-Kbit SRAM ×1 Image bus interface • Serial mode with request (VREQ) input and enable (VSEN), clock (VSCK), and data (VSDA) outputs Scanning modes • Free scanning • Cycle scanning System interface • Interface to 8-bit microprocessors (Intel format) Image data I/O function • Image data output after shading correction (8 bits) • Image data output after multivalue smoothing (6 bits) • Image data input sent from external A/D converter (8 bits) Output ports • 8 pins (pins double as image data I/O pins) Mechanism drive interface • User-defined timing pulse output Facsimile equipment For Communications Equipment MN86074 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 MXD2 MXD3 MXD4 MXD5 MXD6 MXD7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 CS WR RD RESET DVSS Pin Assigment 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DVSS SYNC MCLKI FCK2 FCK1 FSH FSP FR PMT PEAK CLAMP ABC GCDA VINIG AGDR AGUR AGOUT FETG FETS FETD AVDD MXD1 MXD0 MOE MWE MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MAST DVDD (TOP VIEW) QFH084-P-1212 DVDD MOD0 MOD1 VPD0 VPD1 VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 VREQ VSCK VSEN VSDA OFHC OFOUT VREFH ADIN VREFL AVSS MN86074 For Communications Equipment Pin Function Chart Analog pins (10) OFOUT OFHC ADIN FETS FETD FETG AGOUT AGUR AGDR VINIG VREFH VREFL AVDD AVSS DVDD DVDD DVSS DVSS Image bus interface (5) POD0 POD1 POD2 POD3 POD4 POD5 POD6 POD7 VADD0 VADD1 VADD2 VADD3 VADD4 VADD5 VADD6 VADD7 Parallel I/O and output port (8) VGSD0 VGSD1 VGSD2 VGSD3 VGSD4 VGSD5 CKVG PDEL MXD0 MXD1 MXD2 MXD3 MXD4 MXD5 MXD6 MXD7 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 Memory interface (25) PEAK CLAMP ABC GCDA SCD0 SCD1 SCD2 SCD3 SCD4 SCD5 SCD6 SCD7 MWE MOE PMT Mechanism drive interface (1) FCK2 FCK1 FR FSP FSH VPD0 VPD1 VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 MN86074 System interface (14) Clock (3) MAST MCLKI SYNC Analog pins CNT (4) D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 CS WR RD RESET Power supply (8) VREQ VSEN VSCK VSDA MOD1 MOD0 Sensor interface (5) Mode selection (2) 84pin QFP For Communications Equipment MN86074 Application Circuit Example #1: Line lengths up to 2048 pixels MN86074 Memory configuration: 64-Kbit SRAM × 1 MA0 to 10 MA13, 14 MWE WE MOE DE A11, 12 A0 to 10 MXD0 to 7 I/O0 to 7 Application Circuit Example #2: Line lengths of 2049 to 4096 pixels MN86074 Memory configuration: 64-Kbit SRAM × 2 MA0 to 10 MA11 MA13,14 MWE WE A11, 12 MOE DE A0 to 10 MXD0 to 7 I/O0 to 7 CS WE A11, 12 DE A0 to 10 I/O0 to 7 CS MN86074 For Communications Equipment Application Circuit Example #3: Line lengths of 4097 to 8192 pixels MN86074 Memory configuration: 256-Kbit SRAM × 1 MA0 to 12 MA13, 14 MWE WE NOE DE A13, 14 A0 to 12 MXD0 to 7 I/O0 to 7 For Communications Equipment MN86074 Package Dimensions (Unit: mm) QFH084-P-1212 14.0±0.2 12.0±0.2 63 43 42 84 22 1 21 +0.10 .05 0.15 -0 3.2max. (1.0) +0.10 0.2–0.05 0.1 M 2.8±0.2 0.5 0.1 0.1±0.1 (1.0) 14.0±0.2 12.0±0.2 (1.0) 64 SEATING PLANE 0 to 10° 0.5±0.2