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
PI2007
®
Cool-ORing Series
Universal High Side Active ORing Controller IC
Description
Features
®
The PI2007 Cool-ORing solution is a universal
high-speed Active ORing controller IC designed for
use with N-channel MOSFETs in redundant power
system architectures. The PI2007 Cool-ORing
controller enables an extremely low power loss
solution with fast dynamic response to fault
conditions, critical for high availability systems. The
PI2007 controls single or parallel MOSFETs to
address Active ORing applications protecting
against power source failures. The PI2007 has an
internal charge pump enabling an ideal solution in
12V or 36-75V bus high-side Active ORing
applications.

The gate drive output turns the MOSFET on in
normal steady state operation, while achieving highspeed turn-off during input power source fault
conditions, that causes reverse current flow. The
controller auto-resets once the fault clears. The
MOSFET drain-to-source voltage is monitored to
detect reverse current flow. The PI2007 has an
internal charge pump to drive the gate of a high side
N-Channel MOSFET above the VC input. There is
an internal shunt regulator at the VC input for high
voltage applications.
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Fast dynamic response to power source failure,
with 80ns reverse current turn off delay time.
4A gate discharge current
Forward Over Current Fault indication
Accurate MOSFET drain-to-source voltage
sensing
Internal charge pump
FET check at initial power-up
100V for 100ms, operation in high side
application
VC under voltage fault detection
Applications
N+1 Redundant Power Systems
Servers & High End Computing
Telecom Systems
High-side Active ORing
High current Active ORing
Package Information
The PI2007 is offered in the following packages:
 10 Lead 3mm x 3mm DFN package
Typical Applications:
Figure 1: PI2007 High Side Active ORing for 12V
Bus applications
Figure 2: PI2007 referenced to Vin in high voltage
high side Acti ve ORing applications
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 1 of 19

Pin Description
Pin Name
Pin
Number
PGND
1
Gate Turn Off Switch Return: This pin is the high current return path for the gate driver
during turn off. Connect this pin to the low side of the VC coupling capacitor and SGND.
2
Gate Drive Output: This pin drives the gate of the external N-channel MOSFET. Under
normal operating conditions and when VSP-SN > 6mV, the GATE pin pulls high to
approximately 2*VC with respect to the SGND pin. The controller turns the gate off
during a reverse current fault that is below the reverse voltage threshold (-6mV) and
when VC is in Under Voltage (7.15V).
VC
3
Controller Input Supply: This pin is the supply pin for the control circuitry and gate
driver. Connect a 1μF capacitor between the VC pin and the SGND pin. Voltage on this
pin is regulated to 11.7V with respect to SGND by an internal shunt regulator. For high
voltage supply applications connect a shunt resistor between the SGND and PGND pins
and the supply return, as shown in Figure 2.
SGND
4
VC Return: This pin is the return (ground) for the control circuitry. Connect this pin to
the low side of VC decoupling capacitor.
VR
5
Controller Input Supply With Limiting Resistor: This pin is connected internally to VC
through a 420Ω resistor needed for Bus voltages greater than 10V and less than 14V.
Leave this pin open if unused.
SP
6
Positive Sense Input: Connect SP pin to the Source pin of the external N-channel
MOSFETs. The polarity of the voltage difference between SP and SN provides an
indication of current flow direction through the MOSFET.
NC
7, 10
SN
8
Negative Sense Input: Connect SN to the Drain pin of the external N-channel MOSFET.
The polarity of the voltage difference between SP and SN provides an indication of
current flow direction through the MOSFET.
9
Fault Status Output: This open collector pin pulls low to indicate one of the several
potential fault conditions may exist. The FT pin will pull low after a reverse or forward
fault has been detected with a defined delay time (8μs). In addition, the FT pin will pull
low when the controller input voltage is below the VC under-voltage threshold VVC-SGND <
7V. When VVC-SGND > 7.15V and 6mV < VSP-SN < 275mV this pin clears (High). In high
voltage applications this output must be translated with reference to the system return
with external circuitry, see Figure 19. Leave this pin open if unused.
GATE
FT
Description
Not Connected: Leave pins floating.
Package Pin-Outs
10 Lead DFN (3mm x 3mm)
Top view
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 2 of 19

Absolute Maximum Ratings
Note: All voltage nodes are referenced to SGND
VR
-0.3V to 17.3V / 40mA
SP, FT
-0.3V to 17.3V / 10mA
GATE
-0.3V to 24V / 5A peak
PGND
-0.3V to 3V / 5A peak
SGND, VC
40mA
SN (Continuous, TA ≤ 85°C)
-0.3V to 80V / 10mA
SN (100ms Pulse, TA ≤ 85°C)
100V / 10mA
o
o
Storage Temperature
-65 C to 150 C
Operating Junction Temperature
-40 C to 140°C
o
o
260 C
Soldering Temperature for 20 seconds
ESD Rating
2kV HBM
Electrical Specifications
Unless otherwise specified: -40C < TJ < 125C, VC =10.5V, VR open, CVc = 1uF, CGATE_PGND = 1nF,
SGND=PGND=0V
Parameter
Symbol
Min
VVC-SGND
8.5
Typ
Max
Units
Conditions
10.5
V
1.5
2.0
mA
11.7
12.5
V
IVC=3mA
10

Delta IVC=10mA
VC Supply
Operating Supply Range
(3)
Quiescent Current
IVC
VC Clamp Voltage
VVC-CLM
VC Clamp Shunt Resistance
11
RVC
VC Under-Voltage Rising Threshold
VVCUVR
6.1
7.15
8.0
V
VC Under-Voltage Falling Threshold
VVCUVF
6
7.00
7.9
V
No VC limiting Resistor
VC = 10.5V
VC Under-Voltage Hysteresis
VVCUV-HS
100
150
200
mV
VR Supply (VR pin connected to Vin, VC pin to bypass capacitor Figure 1) Recommended for 12V Bus
applications
Operating Supply Range
VVR-SGND
10
14
V
Biased from VR pin
Quiescent Current
Bias Resistor
IVR
3.0
5.5
10
mA
RBias
300
420
550
Ω
VR = 14V
DIFFERENTIAL AMPLIFIER AND COMPARATORS
Common Mode Input Voltage
VCM
-3
3
V
VSP-SN
-80
400
mV
SP-SN
SP Input Bias Current
ISP
35
55
75
μA
SP=SN=VC
SN Input Bias Current
ISN
35
55
75
μA
SP=SN=VC
7
9
mA
VSN = 80V,SP=VC=0V
Differential Operating Input Voltage
SN Leakage Current
Picor Corporation • picorpower.com
(1)
ISN_Lg
PI2007
SP to VC, SN to VC
Rev 1.3
Page 3 of 19

Electrical Specifications (Continued)
Unless otherwise specified: -40C < TJ < 125C, VC =10.5V, VR open, CVc = 1uF, CGATE_PGND = 1nF,
SGND=PGND=0V
Parameter
Symbol
Min
Typ
Max
Units
Conditions
DIFFERENTIAL AMPLIFIER AND COMPARATORS (Continued)
Gate Enable Threshold
VRVS-EN
+1
+6
+11
mV
VSN = 10.5V @ 25°C
Reverse Comparator Threshold
VRVS-TH
-11
-6
-2
mV
VSN = 10.5V @ 25°C
Reverse Comparator Hysteresis
Reverse Fault to Gate Turn-off
Response Time
Forward Comparator Threshold
VRVS-HY
10
12
14
mV
80
150
ns
VFWD-TH
250
275
300
mV
VSN = 10.5V @ 25°C
VSP-SN = +50mV to -50mV
step to 90% of VG max
VSN = 10.5V @ 25°C
Forward Comparator Hysteresis
VFWD-HY
15
25
35
mV
VSN = 10.5V @ 25°C
-20
-15
μA
VG=VG-Hi –1V, IVC=3mA
tRVS
GATE DRIVER
Gate Source Current
Pull Down Peak Current to PGND(1)
Pull-down Gate Resistance to
PGND(1)
AC Gate Pull-down Voltage to
PGND(1)
DC Gate Pull-down Voltage
Gate Drive Voltage to VC
Gate Fall Time
Gate Voltage
IG-SC
IG-PGND
1.5
RG-PGND
4.0
A
0.3

VG-PGND
0.2
V
0.8
1.2
V
IG=100mA, in reverse fault
7.0
8.0
11
V
IG =-20μA, IVC=3mA
8.0
9.0
11
V
IG =-2μA, IVC=3mA
10
25
ns
0.7
1
V
0.7
1
V
90% to 10% of VG max.
IG =10μA, SP= SN=open
VC = 4.5V
IG =10μA, SP=0V; VC=0V
5.5V ≤ SN ≤ 80V
VG-SGND
VG-Hi
VG-PGND = 1.5V @ 25C
tG-F
VG-UVLO
GATE DRIVER (VR pin connected to Vin, VC pin to bypass capacitor Figure 1)
Gate Drive Voltage to VR
VG-Hi
4.5
7.0
9.5
V
IG =-20μA, 10V VR
5.0
8.0
9.5
V
IG =-2μA, 10V VR
0.2
0.5
V
IFT =1.5mA, VC > 4.5V
μA
VFT=14V, VSP-SN > +6mV
μs
VSP-SN = ± 50mV step to
90% of VGST max
14V
14V
Fault Status: FT
Fault Output Low Voltage
V FT
Fault Output High Source Current
IFT
-1
TFT-DLY
4
Fault Delay time
8
16
Note 1: These parameters are not production tested but are guaranteed by design, characterization, and
correlation with statistical process control.
Note 2: Current sourced by a pin is reported with a negative sign.
Note 3: Refer to the VC Bias section in the Application Information for details on the VC requirement to meet the
MOSFET VGS requirement.
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 4 of 19

Functional Description:
The PI2007 Cool-ORing controller IC is designed to
drive single or parallel N-channel MOSFETs in high
side Active ORing applications. The PI2007 used
with an external MOSFET can function as an ideal
ORing diode in the high side of a redundant power
system, significantly reducing power dissipation and
eliminating the need for heatsinking.
An N-channel MOSFET in the conduction path offers
extremely low on-resistance resulting in a dramatic
reduction of power dissipation versus the
performance of a diode used in conventional ORing
applications due to its high forward voltage drop.
This can allow for the elimination of complex heat
sinking
and
other
thermal
management
requirements.
Due to the inherent characteristics of the MOSFET,
current will flow in the forward and reverse directions
while the gate remains above the gate threshold
voltage. Ideal ORing applications should not allow
reverse current flow, so the controller has to be
capable of very fast and accurate detection of
reverse current caused by input power source
failures, and very fast turn off of the gate of the
MOSFET. Once the gate voltage falls below the gate
threshold, the MOSFET is off and the body diode will
be reverse biased preventing reverse current flow
and subsequent excessive voltage droop on the
redundant bus.
Differential Amplifier:
The PI2007 integrates a high-speed low offset
voltage differential amplifier to sense the difference
between the Sense Positive (SP) pin voltage and
Sense Negative (SN) pin voltage with high accuracy.
The amplifier output is connected to the Reverse
and Forward comparators.
Reverse Current Comparator: RVS
The reverse current comparator provides the critical
function in the controller, detecting negative voltage
caused by reverse current. When the SN pin is 6mV
higher than the SP pin, the reverse comparator will
force the gate discharge circuit to turn off the
MOSFETs in typically 80ns.
The reverse comparator will hold the gate low until
the SP pin is 6mV higher than the SN pin. The
reverse comparator hysteresis is shown in Figure 3.
There is a bias current path from SN to SP during
the reverse fault condition. The bias current is
proportional to the voltage between SN and SP.
The maximum SN pin bias current is 9mA when
VSN=80V and VSP=0V and assumes that the
MOSFET is in the off condition. Refer to Figure 15
in the Application Information section for more
details.
Forward Voltage Comparator: FWD
The FWD comparator detects when a forward
voltage condition exists and SP is above 275mV
(typical) positive with respect to SN. When SP-SN is
more than 275mV, the FWD comparator will assert
the Gate Status low to report a fault condition.
VC and Internal Voltage Regulator:
The PI2007 has a separate input VC that provides
power to the control circuitry, charge pump and gate
driver. An internal regulator clamps the VC voltage
(VVC-SGND) to 11.7V.
The internal regulator circuit has a comparator to
monitor the VC voltage and pulls the GATE pin low
when the VC is lower than the VC Under-Voltage
Threshold.
In 12V Bus applications (10V to 14V) the VR input
pin can be connected to the input voltage eliminating
the need for an external limiter. An internal 420Ω
resistor is connected between the VR pin and the
internal regulator VC pin.
Charge Pump:
The PI2007 has an integrated charge pump that
approximately doubles the VC voltage with
reference to the SGND pin, to drive the N-Channel
MOSFET gate to a voltage higher than the input
voltage at 15µA minimum source current.
Gate Driver:
The gate driver (GATE) output is configured to drive
an external N-channel MOSFET. In the high state,
the gate driver applies a 20µA typical current source
to the MOSFET gate from the integrated charge
pump. The Charge Pump voltage is limited to
2*(VVC –VSGND -1V).
When a reverse current fault is initiated, the gate
driver pulls the GATE pin low to the PGND pin and
discharges the MOSFET gate with 4A typical peak
capability.
Fault Indication: FT
Figure 3: Reverse comparator hysteresis: VSP - VSN
Picor Corporation • picorpower.com
The FT pin is an open collector NPN that will be
pulled low when the Gate pin is low. The FT pin is
also pulled low when VVC-SGND is below UVLO or
during the following fault conditions as indicated in
the table below:
PI2007
Rev 1.3
Page 5 of 19

1
2
3
Reverse:
Forward:
Forward
Condition
VSP - VSN ≤ -6mV
VSP - VSN ≥ +275mV
VSP - VSN ≤ +6mV
Indication of possible faults
Input supply shorted
Open FET, Gate short or open, High current
Shorted FET on power-up
Figure 4: PI2007 Controller Internal Block Diagram
Figure 5: PI2007 State Diagram for gate drive.
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 6 of 19

Figure 6: Timing diagram for two PI2007 controllers in a high side Active ORing application
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 7 of 19

Typical Characteristics:
Figure 7: Controller bias current vs. temperature
Figure 10: VC UVLO threshold vs. temperature
Figure 8: Reverse Fault to Gate Turn-off Response
Time vs. temperature.
Figure 11: Reverse comparator threshold vs.
temperature.
Figure 9: Gate drive voltage to VC vs. temperature.
Figure 12: Gate source current vs. temperature
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 8 of 19

Figure 13: PI2007 performance in response to a fault (input short), configured for a +48V application as shown in
Figure 17.
Application Information:
The PI2007 is designed to replace ORing diodes in
high current redundant power architectures.
Replacing a traditional diode with a PI2007 controller
IC and a low on-state resistance N-channel MOSFET
will result in significant power dissipation reduction as
well as board space reduction, efficiency improvement
and additional protection features.
This section
describes in detail the procedure to follow when
designing with the PI2007 Active ORing controller and
N-Channel MOSFETs. Two different Active ORing
design examples are presented.
at the CVC termination to keep SGND noise free when
the Gate is turned off in response to a fault.
In 12V system applications, where the input voltage
(Vin) is between 10V and 14V, connect the VR pin to
Vin and connect SGND and PGND to the Vin return.
A 420Ω internal resistor is connected between the VR
pin and the VC pin.
In high voltage applications, above 14V, a bias
resistor (RPG) and low current low forward voltage
drop Schottky diode are required. Connect one
terminal of RPG to the SGND and PGND and the other
terminal to ground (Vin return). The Schottky diode
anode will be connected to the SGND pin and its
cathode connected at the VC pin. See typical
application drawings on page 1.
VC Bias:
The PI2007 has a separate input (VC) that provides
power to the control circuitry, the charge pump and
the gate driver. An internal regulator clamps the VC
voltage (VVC-SGND) to 11.7V.
A bypass ceramic
capacitor (CVC = 1μF) has to be connected between
VC and SGND to hold VVC-SGND steady. Also, the Gate
turn off return (PGND) should be connected to SGND
Recommended Schottky:
PMEG3005AEA: from NXP or equivalent
RPG selection for input voltage greater than 14V:
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 9 of 19

Select the resistor (RPG) value at the minimum input
voltage to avoid a voltage drop that may reduce VVCSGND lower than VC under voltage lockout.
Select the value of RPG using the following equations:
R PG 
VVC  min  VVC CLMMax
I VC _ Max  0.1mA
RPG maximum power dissipation:
PdR PG 
(VVC  max  VVC CLMMin ) 2
R PG
Figure 14: Constant current bias circuit
Where:
VVC  min :
Pulling the Q2 base (EN) to the system return (RTN)
will turn off the transistor and the controller returns
(SGND pin and PGND pin) will float and eventually
the MOSFET will be turned off. An open collector
device can be used to enable and disable the PI2007.
VC pin minimum applied voltage with
respect to Vin return
VVC  max : VC pin maximum applied voltage with
respect to Vin return
VVC CLMMax : Controller maximum clamp voltage, 12.5V
VVC CLMMin : Controller minimum clamp voltage, 11.0V
The constant current circuit should guarantee current
greater than the PI2007 maximum Quiescent current
(IVC), 2.0mA.
I VC _ Max : Controller maximum bias current, use
RLIMIT can be calculated from the following equation:
2.0mA plus 0.1mA for margin
R LIMIT 
Example: 40V <VVC <50V
R PG 
VVC min  VVC CLMMax 40V  12.5V

 13.1k
I VC _ Max  0.1mA
2.1mA
V Z _ MIN : Minimum Zener diode voltage
V BE (on) : Q2 Base-Emitter On maximum voltage, for
default use V BE (on) =0.7V
(V
 VVC  CLMMin ) 2 50V  11V 
 VC  max

 116mW
RPG
13.1k
IVC _ MAX : PI2007 Quiescent Current, maximum
IVC=2.0mA
Alternative Bias Circuit with Device Enable:
Constant current circuit
In a wide operating input voltage range the size of RPG
may be become large to support power dissipation. A
simple constant current circuit can be used instead of
RPG to reduce power dissipation and can be used as a
device enable.
Zener Diode Selection:
Select a Zener diode with a low reverse current
requirement to minimize RZ. Zener diodes with higher
break down voltage will have lower reverse current
and reduce Q2 collector current variation. Zener
diodes with a breakdown voltage of 6V and higher will
require low bias current and accurate voltage
breakdown.
As shown in Figure 14, the constant current circuit
consists of an NPN transistor (Q2), Zener diode DZ,
current limit resistor (RLIMIT) and Zener bias resistor
(RZ). RLIMIT and RZ can be very low power resistors
and Q2 is a signal transistor where its CollectorEmitter Voltage (VCEO) is equal or greater than the
input operating voltage and supports 2.5mA at the
operating input voltage.
Picor Corporation • picorpower.com
I VC _ MAX
Where:
2
PdRPG
VZ _ MIN  V BE (on)
RZ maximum value can be calculated with the
following equation:
Note that the surface mount resistors have limited
operating voltage capability. Be sure to pick a
resistor package that can meet the maximum
operating voltage (Vin).
PI2007
Rev 1.3
Page 10 of 19

RZ 
Vin _ MIN  VZ _ MAX
I Z  I B _ MAX
Where:
Vin _ MIN : Min input voltage
VZ _ MAX : Zener diode maximum breakdown voltage
IZ :
Zener diode required reverse current
I B _ MAX : Q2 required maximum base current which
calculated from the following equation:
I B _ MAX 
I C _ MAX
hFE _ MIN
I C _ MAX : Q2 maximum expected collector current.
Figure 15: SN leakage current vs. SN voltage during
input fault condition (input short)
hFE _ MIN : Q2 minimum gain.
Fault Indication:
N-Channel MOSFET Selection:
FT is an open collector output and its return is
Several factors affect MOSFET selection including
cost, on-state resistance (RDS(on)), DC current rating,
short pulse current rating, avalanche rating, power
dissipation, thermal conductivity, drain-to-source
breakdown voltage (BVdss), gate-to-source voltage
rating (Vgs), and gate threshold voltage (Vgs(TH)).
referenced to SGND. When SGND is referenced to
system ground, FT should be pulled up to the logic
voltage via a resistor (10KΩ). When the SGND pin is
floating on a bias resistor (RPG) or in a constant
current circuit, a level shift circuit can be added to
make the FT pin output referenced to the system
ground. See Figure 19. Leave FT unconnected if
not used.
The first step is to select a suitable MOSFET based on
the BVdss requirement for the application. The BVdss
voltage rating should be higher than the applied Vin
voltage plus expected transient voltages.
Stray
parasitic inductance in the circuit can also contribute
to significant transient voltage conditions, particularly
during MOSFET turn-off after a reverse current fault
has been detected.
Note that in case of an input fault condition, where
the input voltage (Vin) and the VC pin are at
ground and the SN pin is at a high voltage, a
parasitic path between SN and VC will draw bias
current (leakage current) from the output as a
function of the voltage between SN and grounded
VC (VSN-GND) based on the following equation:
I SN _ Lg 
In Active ORing applications when one of the input
power sources is shorted, a large reverse current is
sourced from the circuit output through the MOSFET.
Depending on the output impedance of the system,
the reverse current may get very high in some
conditions before the MOSFET is turned off. Make
sure that the MOSFET pulse current capability can
withstand the peak current.
Such high current
conditions will store energy even in a small parasitic
element. Note that PI2007 has a very fast response
time to a fault condition achieving 80ns typical and
150ns maximum.
This fast response time will
minimize the reverse peak current to keep stored
energy and MOSFET avalanche energy very low to
avoid damage (breakdown) to the MOSFET.
V SN GND  12V
R PAR
Where:
I SN _ Lg :
SN leakage current during input short
V SN GND : Voltage difference between SN pin (or load
voltage) and ground.
R PAR :
Resistor in the parasitic path, 10KΩ typical
and 8kΩ minimum
Peak current during input short is calculated as
follows, assuming that the output has very low
impedance and it is not a limiting factor:
I PEAK 
Picor Corporation • picorpower.com
PI2007
VS * t RVS
LPARASITIC
Rev 1.3
Page 11 of 19

Where:
I PEAK :
Peak current in the MOSFET right before it
is turned off.
VS :
Input voltage or load voltage at MOSFET
Trise MOSFET  Rth JA  Pd MOSFET  Rth JA  Is 2  R DS ( on) ,
Where:
Rth JA :
source before input short condition did
occur.
t RVS :
RDS(on) and PI2007 sensing:
Reverse fault to MOSFET turn-off time. This
The PI2007 senses the MOSFET source-to-drain
voltage drop via the SP and SN pins to determine the
status of the current through the MOSFET. When the
MOSFET is fully enhanced, its source-to-drain voltage
is equal to the MOSFET on-state resistance multiplied
by the source current, VSD = RDS(on)*Is. The reverse
current threshold is set for -6mV and when the
differential voltage between the SP & SN pins is more
negative than -6mV, i.e. SP-SN-6mV, the PI2007
detects a reverse current fault condition and pulls the
MOSFET gate pin low, thus turning off the MOSFET
and preventing further reverse current. The reverse
current fault protection disconnects the power source
fault condition from the redundant bus, and allows the
system to keep running.
will include PI2007 delay and the MOSFET
turn off time.
LPARASITIC : Circuit parasitic inductance
And the MOSFET avalanche energy during an input
short is calculated as follows:
E AS 
1.3 * V( BR ) DSS
1
2
*
* LPARASITIC * I PEAK
2 *1.3V( BR ) DSS  VS
Where:
E AS :
Junction-to-Ambient thermal resistance
Avalanche energy
V( BR ) DSS : MOSFET breakdown voltage
MOSFET RDS(on) and maximum steady state power
dissipation are closely related. Generally the lower the
MOSFET RDS(on), the higher the current capability and
the lower the resultant power dissipation. This leads to
reduced thermal management overhead, but will
ultimately be higher cost compared to higher RDS(on)
parts. It is important to understand the primary design
goal objectives for the application in order to
effectively trade off the performance of one MOSFET
versus another.
Power dissipation in active ORing circuits is derived
from the total source current and the on-state
resistance of the selected MOSFET .
MOSFET power dissipation:
Pd MOSFET  Is 2  R DS ( on)
Where :
Is :
Source Current
RDS(on) : MOSFET on-state resistance
Note:
In the calculation use RDS(on) at maximum MOSFET
temperature because RDS(on)
is temperature
dependent. Refer to the normalized RDS(on) curves in
the MOSFET manufacturers datasheet. Some
MOSFET RDS(on) values may increase by 50% at
125°C compared to values at 25°C.
The Junction Temperature rise is a function of power
dissipation and thermal resistance.
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 12 of 19

 40C

TJ max  75C  
 (15 A)2  4.48m   115C
W


Typical application Example 1:
Requirement:
Redundant Bus Voltage = 12V (±10%, 10.8V to
13.2V)
Load Current = 15A (assume through each redundant
path)
Maximum Ambient Temperature = 75°C
Recalculate
based
on
increased
temperature, 115°C.
At 115°C RDS(on) will increase by 32%.
Junction
RDS ( on)  3.5m 1.32  4.62m
 40C

TJ max  75C  
 (15 A)2  4.62m   116.5C
 W

Solution:
A single PI2007 with a suitable external MOSFET for
each redundant 12V power source should be used,
configured as shown in the circuit schematic in Figure
16.
VC Bias: Vin maximum input is 13.2V, this is higher
than the 11V VC Clamp Voltage (VVC-SGND) minimum.
Use the high side PI2007 internal resistor between VR
pin and VC pin will fit for this application.
Select a suitable N-Channel MOSFET:
Most
industry standard MOSFETs have a Vgs rating of +/12V or higher. Select an N-Channel MOSFET with a
low RDS(on) which is capable of supporting the full load
current with some margin, so a MOSFET capable of
at least 18A in steady state is reasonable. An
exemplary MOSFET having these characteristic is the
FDS6162N7 from Fairchild.
Since the MOSFET requires only 4.5V for full
enhancement then the PI2007 internal resistor
between VR pin and VC pin will fit for this application.
Connect VR to Vin at the source of the MOSFET and
connect a 1μF ceramic capacitor between VC pin and
SGND pin.
From FDS6162N7 datasheet:
 N-Channel MOSFET
 VDS= 20V
 ID = 23A continuous drain current
 ID(Pulse) = 60A Pulsed drain current
 VGS(MAX)= 12V
2
 RθJA= 40°C/W when mounted on a 1in PCB
pad of 2 oz copper
 RDS(on)=2.9mΩ typical and 3.5mΩ maximum at
ID=23A, VGS≥4.5V, TJ=25°C
Fault Indication:
Connect FT pin to the logic input and to the logic
power supply via a 10KΩ resistor.
Reverse current threshold is:
Is.reverse 
Vth.reverse  6mV

 2.07 A
Rds (on)
2.9m
Power dissipation:
RDS(on) is 3.5mΩ maximum at 25°C & 4.5Vgs and will
increase as the temperature increases. Add 25°C to
maximum ambient temperature to compensate for the
temperature rise due to power dissipation. At 100°C
(75°C + 25°C) RDS(on) will increase by 28%.
RDS ( on)  3.5m 1.28  4.48m maximum at 100°C
Trise  RthJA  Is 2  RDS ( on)
Figure 16: PI2007 in 12V bus high side Active ORing
configuration
Maximum Junction temperature
TJ max  TA  Trise
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 13 of 19

RDS ( on)  18m 1.50  27m maximum at 95°C
Typical application Example 2:
Requirement:
+48V High Side Redundant
Bus Voltage = +48V (+36V to +60V, 100V for 100ms
transient)
Load Current = 5A load (assume through each
redundant path)
Maximum Ambient Temperature = 60°C
Solution:
Maximum Junction temperature after 10s
 50C

TJ max  60C  
 (5.0 A)2  27m   93.75C
 W

For continuous operation refer the MOSFET
datasheet for RθJA under continuous operation and
plug it in place of 50°C/W.
A single PI2007 with a suitable MOSFET for each
redundant +48V power source should be used and
configured as shown in Figure 17 or Figure 18. Figure
17 is configured with the VC biased from the return
line through a bias resistor. Figure 18 is configured
with the VC biased from the return line through the
constant current circuit.
VC Bias: Since the bus voltage is higher than 14V,
connect VC pin to the high side of the input voltage
and connect a bias resistor (RPG) or a constant current
circuit between PI2007 SGND pin and ground (Vin
return), as shown in Figure 17 and Figure 18. Place a
low forward voltage drop Schottky diode and a 1μF
ceramic capacitor between SGND pin and VC pin.
Also connect PGND pin to SGND at the coupling
capacitor terminal.
Recommended Schottky: PMEG3005AEA from NXP
or equivalent
Select a suitable N-Channel MOSFET: Select the
N-Channel MOSFET with voltage rating higher than
the input voltage, Vin, plus any expected transient
voltages, with a low RDS(on) that is capable of
supporting the full load current with margin. For
instance, a 100V rated MOSFET with 10A current
capability is suitable. An exemplary MOSFET having
these characteristic is IRF7853PbF from International
Rectifier.
RPG selection:
R PG 
VVC  min  VVC CLMMax
36V  12.5V

 11.19k
I VC _ Max  0.1mA
2.0mA  0.1mA
Select RPG=11kΩ 1%
From the IRF7853PbF datasheet:
N-Channel MOSFET
VDS= 100V
ID = 8.3A maximum continuous drain current at
25°C
ID-PULSE = 66A pulsed drain current
VGS(MAX) = 20V
2
RθJA= 50°C/W on 1in copper, t ≤ 10seconds
RθJA for continuous operation not provided
RDS(on)=14.4mΩ typical at VGS=10V, TJ=25°C
RDS(on)=18mΩ maximum at VGS=10V, TJ=25°C
RPG maximum power dissipation:
PdR PG 
(VVC  max  VVC CLMMin ) 2 60V  11V 2

 218mW
R PG
11k
Use ¼ W Resistor in 1206 package
Reverse current threshold is:
Is.reverse 
Vth.reverse  6mV

 333mA
R DS ( on)
18m
Power dissipation:
Rds(on) is 18mΩ maximum at 25°C & 10Vgs and will
increase as the temperature increases. Add 20°C to
maximum ambient temperature to compensate for the
temperature rise due to power dissipation. At 80°C
(60°C + 20°C) Rds(on) will increase by 40%.
RDS ( on)  18m 1.40  25.2m maximum at 80°C
Maximum Junction temperature
 50C

TJ max  60C  
 (5.0 A)2  25.2m   91.5C
 W

Figure 17: PI2007 in high side +48V application, VC
is biased through a bias resistor
Recalculate maximum RDS(on) at 95°C.
At 95°C Rds(on) will increase by 50%:
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 14 of 19

Pd Q 2  2.29mA  [60V  11V  (9.8V  0.7V )]  91.37mW
VC bias through Constant current circuit
The transistor Power De-rating vs. temperature curve
in the manufacturer datasheet shows that the device
can operate up to 110°C.
Select an NPN transistor with VCEO equal or higher
than the input voltage (Vin) plus any expected
transient voltage and capable of handling the
expected maximum power dissipation. Any NPN
transistor with VCEO ≥ 100V in a small footprint is
suitable. An exemplary NPN is FJV1845 from
Fairchild:
From the FJV1845 datasheet:
NPN Silicon Transistor
VCEO= 120V Collector-Emitter maximum voltage
IC = 50mA maximum collector current
hFE = 150 minimum at IC=3mA
VBE(sat)= 0.55V to 0.65V Base-Emitter saturation
voltage at 25°C
Select Zener Diode: Select the Zener diode with low
bias current, a Zener diode with VZ=10 in small foot
print is suitable for this application. An exemplary
Zener diode MM3Z10VST1 from ON Semiconductor
From the MM3Z10VST1 datasheet:
10V, 200mW Zener Diode
VZ= 9.80V to 10.2V Zener voltage range
IR = 10μA will hold the Zener breakdown voltage
at 9.8V
R LIMIT 
VZ _ MIN  V BE (on)
I VC _ MAX

Figure 18: PI2007 in high side +48V application, VC
is biased through constant current circuit.
9.8V  0.7V
 4.33k
2.1mA
Fault Indication:
Or 4.32kΩ 1%
I B _ MAX 
I C _ MAX
hFE _ MIN

PI2007 SGND pin in this application is floating and
FT is referenced to SGND. The FT output can be
referenced to system return (RTN) by adding a level
shift circuit as shown in Figure 19.
3.5mA
 23.33A
150
Q1: 2SA1579T106R, 120V PNP transistor from
Rohm.
RZ Calculation:
Use 100μA as minimum for the Zener diode reverse
leakage current and Q2 base current combined.
RZ 
Vin _ MIN  VZ _ MAX
I Z  I B _ MAX

Q2: DTC114EET1G, 50V NPN with bias resistors from
ON semiconductor.
36V  10.2V
 258k
100A
D1: 30V general purpose diode.
Select RZ= 249kΩ 1%
Maximum Q2 collector current:
I C _ MAX 
VZ _ MAX  VBE _ MIN
RLIMIT _ MIN

10.2V  0.50V
 2.29mA
4.32k * 0.98
Maximum Q2 power dissipation
Pd Q 2  I C _ MAX  [Vin MAX  VVC CLM  (VZ _ MIN  V EB _ MAX )]
Figure 19: FT level shift circuitry
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 15 of 19

High and Low Side Active ORing for the Same
Source:
PI2007 and Picor PI2003 controllers can be
configured to meet ATCA application that requires low
and high side ORing as shown in Figure 20. See
PICOR Application Notes for more details of the
design procedure for this application.
Figure 20: PI2007 and PI2003 configured for a combined high and low side ORing application
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 16 of 19

Layout Recommendation:
Use the following general guidelines when designing
printed circuit boards. An example of the typical land
pattern for a DFN PI2007 and SO-8/PowerPak
MOSFET is shown in Figure 21 and Figure 22:

It is best to connect the gate of the MOSFET to
the GATE pin of the controller with a short trace. A
gate resistor (RG) is added to slow down the gate
turn off if needed.

The VC bypass capacitor should be located as
close as possible to the VC and SGND pins.
Place the PI2007 and VC bypass capacitor on the
same layer of the board. The VC pin and CVC
PCB trace should not contain any vias.

In an application where SGND is floating, a low
forward voltage drop Schottky diode has to be
added in parallel with CVC to protect the controller
during an input voltage short fault.

PGND pin of the controller carries high peak
current during gate pull down, Connect PGND pin
with a wide trace to the CVC terminal at SGND.
Make sure that SGND trace and PGND trace
connect only at CVC terminal.

Connections from the SP and SN pins to the
MOSFET source and drain pins respectively
should be as short as possible

Connect all MOSFET source pins together with a
wide trace to reduce trace parasitics and to
accommodate the high current input. Similarly,
connect all MOSFET Drain pins together with a
wide trace to accommodate the high current
output.
Figure 21: PI2007 controller and MOSFET layout
recommendation in a floating application.
Figure 22: PI2007 controller and MOSFET layout
recommendation in a non-floating application
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 17 of 19

Package Drawing: 10 Lead DFN
Thermal Resistance Ratings
Parameter
(4)
Maximum Junction-to-Ambient
Symbol
θJA
Typical
53
Unit
C/W
Note 4: In accordance with JEDEC JESD 51
Ordering Information
Part Number
PI2007-00-QEIG
Package
Transport Media
3mm x 3mm 10 Lead DFN
T&R
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 18 of 19

Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when
in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper
application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is
extended to the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR
LIMITED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this
warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping
instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges
incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective
within the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to
improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any
product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general
policy does not recommend the use of its components in life support applications wherein a failure or malfunction
may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life
support applications assumes all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC
modules and accessory components, fully configurable AC-DC and DC-DC power
supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor
for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a
failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale,
which are available upon request.
Specifications are subject to change without notice.
Vicor Corporation
25 Frontage Road
Andover, MA 01810
USA
Picor Corporation
51 Industrial Drive
North Smithfield, RI 02896
USA
Customer Service: [email protected]
Technical Support: [email protected]
Tel: 800-735-6200
Fax: 978-475-6715
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 19 of 19
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