CC2533 Datasheet

CC2533
www.ti.com
SWRS087 – JUNE 2010
An Optimized System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 Remote Control
Applications
Check for Samples: CC2533
FEATURES
1
• RF/Layout
– 2.4-GHz IEEE 802.15.4 Compliant RF
Transceiver
– Excellent Receiver Sensitivity and
Robustness to Interference
– Programmable Output Power Up to 4.5 dBm
– Boost-Mode TX at 7 dBm
– Very Few External Components
– Only a Single Crystal Needed for
Asynchronous Networks
– Space-Saving 6-mm × 6-mm QFN40
Package
– Suitable for Systems Targeting Compliance
With Worldwide Radio-Frequency
Regulations: ETSI EN 300 328 and EN 300
440 (Europe), FCC CFR47 Part 15 (US), and
ARIB STD-T-66 (Japan)
– Pin- and Software-Compatible With the
CC2530Fxxx Series
• Low Power
– Active-Mode RX (CPU Idle): 25 mA
– Active Mode TX at 0 dBm (CPU Idle):
28.5 mA
– Power Mode 1 (4 ms Wake-Up): 0.2 mA
– Power Mode 2 (Sleep Timer Running): 1 mA
– Power Mode 3 (External Interrupts): 0.5 mA
– Wide Supply-Voltage Range (2 V–3.6 V)
• Microcontroller
– High-Performance and Low-Power 8051
Microcontroller Core With Code Prefetch
– 64- or 96-KB In-System-Programmable
Flash
– 4- or 6-KB RAM With Retention in All Power
Modes
– Hardware Debug Support
•
234
•
Peripherals
– Powerful Five-Channel DMA
– IEEE 802.15.4 MAC Timer, General-Purpose
Timers (One 16-Bit, Two 8-Bit)
– IR Generation Circuitry
– 32-kHz Sleep Timer With Capture
– CSMA/CA Hardware Support
– Accurate Digital RSSI/LQI Support
– Battery Monitor Comparator
– Random Number Generation
– AES Security Coprocessor
– Two Powerful USARTs With Support for
UART and SPI
– I2C Interface
– 23 General-Purpose I/O Pins
– Watchdog Timer
Development Tools
– CC2533 Remote Control Development Kit
for RF4CE
– CC2533 Development Kit
– CC2533EMK Evaluation Modules
– SmartRF™ Software
– Packet Sniffer
– IAR Embedded Workbench™ Available
APPLICATIONS
•
•
•
•
ZigBee™ RF4CE Remote Control Target and
Device
2.4-GHz IEEE 802.15.4 Systems Based on
TIMAC or SimpliciTI™ Network Protocol
Consumer Electronics
Electronic Shelf Labeling
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartRF, SimpliciTI, RemoTI are trademarks of Texas Instruments.
IAR Embedded Workbench is a trademark of IAR Systems AB.
ZigBee is a trademark of ZigBee Alliance.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CC2533
SWRS087 – JUNE 2010
www.ti.com
DESCRIPTION
The CC2533 is an optimized system-on-chip (SoC) solution for IEEE 802.15.4 based remote-control systems. It
enables single-chip remote controls to be built with low bill-of-material cost when used as a flexible SoC. It also
provides a simple path to adding RF4CE capability to a device or target when used in the wireless network
processor configuration of the RemoTI™ RF4CE stack. Robust network nodes can be built with very low total
bill-of-material costs.
The CC2533 combines the excellent performance of a leading RF transceiver with a single-cycle 8051 compliant
CPU, up to 96-KB in-system programmable flash memory, up to 6-KB RAM, and many other powerful features.
The CC2533 has efficient power modes with RAM and register retention below 1 µA, making it highly suited for
low-duty-cycle systems where ultralow power consumption is required. Short transition times between operating
modes further ensure low energy consumption.
Combined with the golden-unit-status RemoTI stack from Texas Instruments, the CC2533 provides a robust and
complete ZigBee RF4CE remote-control solution. It is also ideal for implementing the target side of a
remote-control system in a network processor configuration with an SPI/UART/I2C interface. The CC2533 comes
complete with reference designs and example software that implement a remote control system to ensure
efficient design-in.
The CC2533 exists in three memory-size configurations:
CC2533F32 – 32-KB Flash, 4-KB RAM
CC2533F64 – 64-KB Flash, 4-KB RAM
CC2533F96 – 96-KB Flash, 6-KB RAM
2
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CC2533
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XOSC_Q2
32-MHz
CRYSTAL OSC
XOSC_Q1
P2_4
32.768-kHz
CRYSTAL OSC
P2_3
P2_2
DEBUG
INTERFACE
P2_1
HIGHSPEED
RC-OSC
DCOUPL
POWER-ON RESET
BROWN OUT
CLOCK MUX
and
CALIBRATION
SFR Bus
RESET
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
WATCHDOG
TIMER
RESET_N
SLEEP TIMER
32-kHz
RC-OSC
POWER MANAGEMENT CONTROLLER
P2_0
SCL
2
I C
P1_7
SDA
P1_6
PDATA
P1_5
P1_4
8051 CPU
CORE
P1_3
XRAM
IRAM
P1_2
SFR
P1_1
DMA
4/6 KB RAM
FLASH
32/64/96-KB
FLASH
MEMORY
ARBITRATOR
P1_0
P0_7
RAM
UNIFIED
P0_6
IRQ CTRL
P0_4
P0_3
P0_2
P0_1
P0_0
I/O CONTROLLER
P0_5
FLASH CTRL
RADIO REGISTERS
BATTERY AND TEMPERATURE
MONITOR
CSMA/CA STROBE PROCESSOR
DEMODULATOR
and
AGC
FIFO and FRAME CONTROL
USART 1
SYNTH
USART 0
SFR Bus
RADIO DATA INTERFACE
MODULATOR
TIMER 2
(IEEE 802.15.4 MAC TIMER)
DIGITAL
TIMER 3 (8-Bit)
RECEIVE
FREQUENCY
SYNTHESIZER
TIMER 1 (16-Bit, IR Gen)
TRANSMIT
ANALOG
MIXED
TIMER 4 (8-Bit)
RF_P
RF_N
B0301-04
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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CC2533
SWRS087 – JUNE 2010
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ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage
MIN
MAX
–0.3
3.9
V
–0.3
VDD + 0.3,
≤ 3.9
V
10
dBm
–40
125
°C
All pads, according to human-body model, JEDEC STD 22, method
A114
2
kV
According to charged-device model, JEDEC STD 22, method C101
500
V
All pads excluding RF pads, according to machine model, JEDEC STD
22, method A115
200
V
All supply pins must have the same voltage
Voltage on any digital pin
Input RF level
Storage temperature range
ESD
(1)
(2)
(2)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CAUTION: ESD-sensitive device. Precautions should be used when handling the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
–40
125
°C
2
3.6
V
Operating ambient temperature range, TA
Operating supply voltage
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
Boldface limits apply over the entire operating range, TA = –40°C to 125°C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to
2507 MHz.
PARAMETER
Icore
Core current consumption
TEST CONDITIONS
MIN
Digital regulator on. 16-MHz RCOSC running. No radio,
crystals, or peripherals active.
Medium CPU activity: normal flash access (1), no RAM access
3.6
32-MHz XOSC running. No radio or peripherals active.
Medium CPU activity: normal flash access (1), no RAM access
6.6
32-MHz XOSC running, radio in RX mode, –50-dBm input
power, no peripherals active, CPU idle
21.6
32-MHz XOSC running, radio in RX mode at –100-dBm input
power (waiting for signal), no peripherals active, CPU idle
25.1
32-MHz XOSC running, radio in TX mode, 0-dBm output
power, no peripherals active, CPU idle
28.5
32-MHz XOSC running, radio in TX mode, 4.5-dBm output
power, no peripherals active, CPU idle
32.3
32-MHz XOSC running, radio in boost mode TX, 7-dBm output
power, no peripherals active, CPU idle
38.8
Power mode 1. Digital regulator on; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD,
and sleep timer active; RAM and register retention
(1)
4
TYP MAX UNIT
mA
7.7
mA
mA
29.8
mA
mA
40.6
mA
mA
0.2
0.3
mA
Power mode 2. Digital regulator off; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, and
sleep timer active; RAM and register retention
1
1.5
mA
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
0.4
0.7
mA
During reset with supply voltage of 1.2 V
54
mA
Normal flash access means that the code used exceeds the cache storage, so cache misses happen frequently.
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ELECTRICAL CHARACTERISTICS (continued)
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
Boldface limits apply over the entire operating range, TA = –40°C to 125°C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to
2507 MHz.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Peripheral Current Consumption (Adds to core current Icore for each peripheral unit activated)
Iperi
Timer 1
Timer running, 32-MHz XOSC used
90
mA
Timer 2
Timer running, 32-MHz XOSC used
90
mA
Timer 3
Timer running, 32-MHz XOSC used
60
mA
Timer 4
Timer running, 32-MHz XOSC used
70
mA
Sleep timer
Including 32.753-kHz RCOSC
0.6
mA
Battery monitor
When comparing
93
mA
Erase
0.2
mA
6
mA
Flash
Burst-write peak current
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Power mode 1 → active
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
4
ms
Power mode 2 or 3 → active
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
0.1
ms
Initially running on 16-MHz RCOSC, with 32-MHz XOSC
OFF
0.6
ms
Active → TX or RX
With 32-MHz XOSC initially on
RX/TX and TX/RX turnaround
192
ms
192
ms
2507
MHz
RADIO PART
RF frequency range
Programmable in 1-MHz steps, 5 MHz between channels
for compliance with [1]
Radio baud rate
As defined by [1]
250
Radio chip rate
As defined by [1]
2
Flash page size
2394
kbps
MChip/s
1
Flash erase cycles
KB
20 K Cycles
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CC2533
SWRS087 – JUNE 2010
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RF RECEIVE SECTION
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C, VDD = 3 V, and fc = 2440 MHz, unless
otherwise noted.
Boldface limits apply over the entire operating range, TA = –40°C to 125°C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to
2507 MHz.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Receiver sensitivity
PER = 1%, as specified by [1]
[1] requires –85 dBm
Saturation (maximum input level)
PER = 1%, as specified by [1]
[1] requires –20 dBm
10
dBm
Adjacent-channel rejection, 5-MHz
channel spacing
Wanted signal –82 dBm, adjacent modulated channel at
5 MHz, PER = 1%, as specified by [1].
[1] requires 0 dB
49
dB
Adjacent-channel rejection, –5-MHz
channel spacing
Wanted signal –82 dBm, adjacent modulated channel at
–5 MHz, PER = 1%, as specified by [1].
[1] requires 0 dB
49
dB
Alternate-channel rejection, 10-MHz
channel spacing
Wanted signal –82 dBm, adjacent modulated channel at
10 MHz, PER = 1%, as specified by [1]
[1] requires 30 dB
57
dB
Alternate-channel rejection, –10-MHz
channel spacing
Wanted signal –82 dBm, adjacent modulated channel at
–10 MHz, PER = 1%, as specified by [1]
[1] requires 30 dB
57
dB
Channel rejection
≥ 20 MHz
≤ –20 MHz
Wanted signal at –82 dBm. Undesired signal is an IEEE
802.15.4 modulated channel, stepped through all channels
from 2405 to 2480 MHz. Signal level for PER = 1%.
57
57
dB
Co-channel rejection
Wanted signal at –82 dBm. Undesired signal is 802.15.4
modulated at the same frequency as the desired signal. Signal
level for PER = 1%.
–2
dB
–97
–93
–89
dBm
Blocking/desensitization
Measured according to ETSI EN 300 440-1 V1.6.1 (2010-04)
blocking/desensitization. Wanted signal 3 dB above sensitivity
limit, interferer at 10×, 20× and 50× bandwidth from receiver
channel band edge. Limit > –45dBm for class-2 receiver.
–250 MHz from band edge
–100 MHz from band edge
–50 MHz from band edge
50 MHz from band edge
100 MHz from band edge
250 MHz from band edge
Spurious emission. Only largest spurious
emission stated within each band.
Conducted measurement with a 50-Ω single-ended load.
Suitable for systems targeting compliance with EN 300 328,
30 MHz–1000 MHz
EN 300 440, FCC CFR47 Part 15, and ARIB STD-T-66.
1 GHz–12.75 GHz
Frequency error tolerance (1)
Symbol rate error tolerance
(1)
(2)
6
(2)
-37
-35
-40
-38
-33
-32
dBm
<
–80
–57
dBm
[1] requires minimum 80 ppm
±150
ppm
[1] requires minimum 80 ppm
±1000
ppm
Difference between center frequency of the received RF signal and local oscillator frequency.
Difference between incoming symbol rate and the internally generated symbol rate
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz, unless
otherwise noted.
Boldface limits apply over the entire operating range, TA = –40°C to 125°C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to 2507
MHz.
PARAMETER
TEST CONDITIONS
Nominal output power
Delivered to a single-ended 50-Ω load through a balun using 4.5
dBm output-power setting
[1] requires minimum –3 dBm
Boost mode
Delivered to a single-ended 50-Ω load through a balun using boost
mode TX settings
Programmable output-power
range
Spurious emissions
(2)
UNIT
1
–3
4.5
7
8
dBm
7
dBm
27
dB
dBm
–45
Error vector magnitude (EVM)
Optimum load impedance
Differential impedance as seen from the RF port (RF_P and RF_N)
towards the antenna
(4)
MAX
–60
–60
–60
–56
–54
–48
–39
–60
Measured as defined by [1] using 4.5 dBm output-power setting
[1] requires maximum 35%.
(2)
(3)
TYP
4.5 dBm output power setting (1)
25 MHz–1000 MHz (outside restricted bands) (2) (2)
25 MHz–2400 MHz (within FCC restricted bands) (2)
25 MHz–1000 MHz (within ETSI restricted bands) (2)
1800–1900 MHz (ETSI restricted band) (2)
5150–5300 MHz (ETSI restricted band) (2)
At 2 × fc and 3 × fc (FCC restricted band) (2)
At 2 × fc and 3 × fc (ETSI EN 300-440 and EN 300-328) (3)
1 GHz–12.75 GHz (outside restricted bands) (2)
At 2483.5 MHz and above (FCC restricted band) (2)
fc= 2480 MHz (4) (2)
(1)
MIN
3%
69 + j29
Ω
Texas Instruments CC2533 EM reference design is suitable for systems targeting compliance with EN 300 328, EN 300 440, FCC
CFR47 Part 15, and ARIB STD-T-66.
Measurement conducted according to stated regulations. Only largest spurious emission stated within each band.
Margins for passing conducted requirements at the third harmonic can be improved by using a simple band-pass filter connected
between matching network and RF connector (1.8 pF in parallel with 1.6 nH); this filter must be connected to a good RF ground.
Margins for passing FCC requirements at 2483.5 MHz and above when transmitting at 2480 MHz can be improved by using a lower
output-power setting or having less than 100% duty cycle.
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32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
32
Crystal frequency accuracy
requirement (1)
UNIT
MHz
–40
40
ppm
ESR
Equivalent series resistance
6
60
Ω
C0
Crystal shunt capacitance
1
7
pF
CL
Crystal load capacitance
10
16
pF
Start-up time
Power-down guard time
(1)
0.3
The crystal oscillator must be in power down for a
guard time before it is used again. This
requirement is valid for all modes of operation. The
need for power-down guard time can vary with
crystal type and load.
ms
3
ms
Including aging and temperature dependency, as specified by [1]
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
32.768
Crystal frequency accuracy
requirement (1)
–40
UNIT
kHz
40
ppm
ESR
Equivalent series resistance
40
130
kΩ
C0
Crystal shunt capacitance
0.9
2
pF
CL
Crystal load capacitance
12
16
pF
Start-up time
0.4
(1)
s
Including aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Calibrated frequency (1)
32.753
Frequency accuracy after calibration
±0.2%
Temperature coefficient (2)
MAX
UNIT
kHz
0.4
%/°C
Supply-voltage coefficient (3)
3
%/V
Calibration time (4)
2
ms
(1)
(2)
(3)
(4)
8
The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
Frequency drift when temperature changes after calibration
Frequency drift when supply voltage changes after calibration
When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is 0.
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16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Frequency (1)
MAX
Uncalibrated frequency accuracy
±18%
Calibrated frequency accuracy
±0.6%
MHz
±1%
Start-up time
10
Initial calibration time (2)
(1)
(2)
UNIT
16
ms
50
ms
The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
RSSI/CCA CHARACTERISTICS
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
RSSI range
MAX
UNIT
100
dB
Absolute uncalibrated RSSI/CCA accuracy
±4
dB
RSSI/CCA offset
73
dB
1
dB
Step size (LSB value)
FREQEST CHARACTERISTICS
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
FREQEST range
FREQEST accuracy
MAX
UNIT
±250
kHz
±40
kHz
FREQEST offset
20
kHz
Step size (LSB value)
7.8
kHz
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C, VDD = 3 V, and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
Phase noise, unmodulated carrier
MIN
TYP
At ±1-MHz offset from carrier
–110
At ±2-MHz offset from carrier
–117
At ±5-MHz offset from carrier
–122
MAX
UNIT
dBc/Hz
BATTERY MONITOR CHARACTERISTICS
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Settling time
Step size
Calibrated accuracy
MAX
2
For voltages up to 2.5 V
24
For voltages above 2.5 V
169
UNIT
µs
mV
mV
Across 1.95 V to 2.5 V, with single-point calibration at 1.95 V
2
20
mV
Across 2.5 V to 3.6 V, with single-point calibration at 1.95 V
10
55
mV
TYP
MAX
UNIT
32
MHz
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
System clock, fSYSCLK
tSYSCLK = 1/fSYSCLK
TEST CONDITIONS
MIN
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
16
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CONTROL INPUT AC CHARACTERISTICS (continued)
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESET_N low duration
See item 1, Figure 1. This is the shortest pulse that is recognized as
a complete reset-pin request. Note that shorter pulses may be
recognized but might not lead to complete reset of all modules within
the chip.
1
ms
Interrupt pulse duration
See item 2, Figure 1.This is the shortest pulse that is recognized as
an interrupt request.
20
ns
RESET_N
1
2
Px.n
T0299-01
Figure 1. Control Input AC Characteristics
10
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SPI AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
250
UNIT
SCK period
Master, RX and TX
SCK duty cycle
Master
ns
t2
SSN low to SCK
Master
63
t3
SCK to SSN high
Master
63
t4
MOSI early out
Master, load = 10 pF
7
ns
t5
MOSI late out
Master, load = 10 pF
10
ns
t6
MISO setup
Master
90
ns
t7
MISO hold
Master
10
ns
t1
SCK period
Slave, RX and TX
250
ns
50%
ns
ns
SCK duty cycle
Slave
t2
SSN low to SCK
Slave
63
t3
SCK to SSN high
Slave
63
t8
MISO early out
Slave, load = 10 pF
t9
MISO late out
Slave, load = 10 pF
t10
MOSI setup
Slave
35
ns
t11
MOSI hold
Slave
10
ns
Operating frequency
50%
ns
ns
ns
0
ns
95
ns
Master, TX only
8
Master, RX and TX
4
Slave, RX only
8
Slave, RX and TX
4
MHz
SCK
t2
t3
SSN
t4
D0
MOSI
t6
MISO
X
t5
X
D1
t7
D0
X
T0478-01
Figure 2. SPI Master AC Characteristics
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SCK
t2
t3
SSN
t8
D0
MISO
X
t10
MOSI
X
t9
D1
t11
D0
X
T0479-01
Figure 3. SPI Slave AC Characteristics
12
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DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
MHz
fclk_dbg
Debug clock frequency (see Figure 4)
t1
Allowed high pulse on clock (see Figure 4)
35
ns
t2
Allowed low pulse on clock (see Figure 4)
35
ns
t3
RESET_N low to first falling edge on debug clock (see Figure 5)
167
ns
t4
Falling edge on clock to RESET_N high (see Figure 5)
83
ns
t5
RESET_N high to first debug command (see Figure 5)
83
ns
t6
Debug data setup (see Figure 6)
2
ns
t7
Debug data hold (see Figure 6)
4
t8
Clock-to-data delay (see Figure 6)
ns
Load = 10 pF
30
ns
Time
DEBUG_ CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 4. Debug Clock – Basic Timing
Time
DEBUG_ CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 5. Data Setup and Hold Timing
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Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC253x)
P2_1
DEBUG_DATA
(from CC253x)
P2_1
t6
t8
t7
T0438-01
Figure 6. Debug Enable Timing
TIMER INPUT AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
Input capture pulse duration
14
TEST CONDITIONS
MIN
Synchronizers determine the shortest input pulse that can be recognized.
The synchronizers operate at the current system clock rate (16 MHz or 32
MHz).
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TYP MAX
UNIT
tSYSCLK
1.5
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DC CHARACTERISTICS
TA = 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Logic-0 input voltage
Logic-1 input voltage
V
50
nA
2.5
Logic-0 input current
Input equals 0 V
–50
Logic-1 input current
Input equals VDD
–50
I/O-pin pullup and pulldown resistors
V
50
20
Logic-0 output voltage, 4-mA pins
Output load 4 mA
Logic-1 output voltage, 4-mA pins
Output load 4 mA
Logic-0 output voltage, 20-mA pins
Output load 20 mA
Logic-1 output voltage, 20-mA pins
Output load 20 mA
UNIT
0.5
nA
kΩ
0.5
2.4
V
V
0.5
2.4
V
V
DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2533 pinout is shown in Figure 7 and a short description of the pins follows.
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3/ XOSC32K_Q2
P2_4/ XOSC32K_Q1
39
38
37
36
35
34
33
32
AVDD6
DVDD1
40
31
30
RBIAS
2
29
AVDD4
SDA
3
28
AVDD1
NC
4
27
AVDD2
P1_5
5
26
RF_N
P1_4
6
25
RF_P
P1_3
7
24
AVDD3
P1_2
8
23
XOSC_Q2
9
DCOUPL
CC2533
RHA Package
(Top View)
22
12
13
14
15
16
17
18
19
P0_3
P0_2
P0_1
P0_0
21
20
XOSC_Q1
AVDD5
RESET_N
10
11
P0_4
DVDD2
P0_5
P1_1
GND
Ground Pad
P0_6
SCL
P0_7
1
P1_0
NC
P0076-04
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 7. Pinout Top View
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Table 1. Pin Descriptions
PIN NAME
PIN
PIN TYPE
DESCRIPTION
AVDD1
28
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD2
27
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD3
24
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD4
29
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD5
21
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD6
31
Power (analog)
2-V–3.6-V analog power-supply connection
DCOUPL
40
Power (digital)
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
DVDD1
39
Power (digital)
2-V–3.6-V digital power-supply connection
DVDD2
10
Power (digital)
2-V–3.6-V digital power-supply connection
GND
—
Ground
The ground pad must be connected to a solid ground plane.
NC
1, 4
Unused pins
No connect
P0_0
19
Digital I/O
Port 0.0
P0_1
18
Digital I/O
Port 0.1
P0_2
17
Digital I/O
Port 0.2
P0_3
16
Digital I/O
Port 0.3
P0_4
15
Digital I/O
Port 0.4
P0_5
14
Digital I/O
Port 0.5
P0_6
13
Digital I/O
Port 0.6
P0_7
12
Digital I/O
Port 0.7
P1_0
11
Digital I/O
Port 1.0 – 20-mA drive capability
P1_1
9
Digital I/O
Port 1.1 – 20-mA drive capability
P1_2
8
Digital I/O
Port 1.2
P1_3
7
Digital I/O
Port 1.3
P1_4
6
Digital I/O
Port 1.4
P1_5
5
Digital I/O
Port 1.5
P1_6
38
Digital I/O
Port 1.6
P1_7
37
Digital I/O
Port 1.7
P2_0
36
Digital I/O
Port 2.0
P2_1
35
Digital I/O
Port 2.1
P2_2
34
Digital I/O
Port 2.2
P2_3/
XOSC32K_Q2
33
Digital I/O,
analog I/O
Port 2.3/32.768 kHz XOSC
P2_4/
XOSC32K_Q1
32
Digital I/O,
analog I/O
Port 2.4/32.768 kHz XOSC
RBIAS
30
Analog I/O
External precision bias resistor for reference current
RESET_N
20
Digital input
Reset, active-low
RF_N
26
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
25
RF_P
2
I2C clock or
digital I/O
Can be used as I2C clock pin or digital I/O. Leave floating if not used.
3
I2C clock or
digital I/O
Can be used as I2C data pin or digital I/O. Leave floating if not used.
XOSC_Q1
22
Analog I/O
32-MHz crystal oscillator pin 1 or external clock input
XOSC_Q2
23
Analog I/O
32-MHz crystal oscillator pin 2
SCL
SDA
16
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CIRCUIT DESCRIPTION
XOSC_Q2
32-MHz
CRYSTAL OSC
XOSC_Q1
P2_4
32.768-kHz
CRYSTAL OSC
P2_3
P2_2
DEBUG
INTERFACE
P2_1
HIGHSPEED
RC-OSC
DCOUPL
POWER-ON RESET
BROWN OUT
CLOCK MUX
and
CALIBRATION
SFR Bus
RESET
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
WATCHDOG
TIMER
RESET_N
SLEEP TIMER
32-kHz
RC-OSC
POWER MANAGEMENT CONTROLLER
P2_0
SCL
2
I C
P1_7
SDA
P1_6
PDATA
P1_5
P1_4
8051 CPU
CORE
P1_3
XRAM
IRAM
P1_2
SFR
P1_1
DMA
4/6 KB RAM
FLASH
32/64/96-KB
FLASH
MEMORY
ARBITRATOR
P1_0
P0_7
RAM
UNIFIED
P0_6
IRQ CTRL
P0_4
P0_3
P0_2
P0_1
P0_0
I/O CONTROLLER
P0_5
FLASH CTRL
RADIO REGISTERS
BATTERY AND TEMPERATURE
MONITOR
CSMA/CA STROBE PROCESSOR
DEMODULATOR
and
AGC
FIFO and FRAME CONTROL
USART 1
SYNTH
USART 0
SFR Bus
RADIO DATA INTERFACE
MODULATOR
TIMER 2
(IEEE 802.15.4 MAC TIMER)
DIGITAL
RECEIVE
TIMER 3 (8-Bit)
FREQUENCY
SYNTHESIZER
TIMER 1 (16-Bit, IR Gen)
TRANSMIT
ANALOG
MIXED
TIMER 4 (8-Bit)
RF_P
RF_N
B0301-04
Figure 8. CC2533 Block Diagram
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A block diagram of the CC2533 is shown in Figure 8. The modules can be roughly divided into one of three
categories: CPU- and memory-related modules; modules related to peripherals, clocks, and power management;
and radio-related modules. In the following subsections, a short description of each module that appears in
Figure 8 is given.
For more details about the modules and their usage, see the corresponding chapters in the CC253x User's
Guide (SWRU191).
CPU and Memory
The 8051 CPU core used in the CC253x device family is a single-cycle 8051-compatible core. It has three
different memory-access buses (SFR, DATA, and CODE/XDATA) with single-cycle access to SFR, DATA, and
the main SRAM. It also includes a debug interface and an 18-input extended interrupt unit.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode
(power modes 1–3).
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory access points, access
of which can map to one of three physical memories: an 8-KB SRAM, flash memory, and XREG/SFR registers. It
is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The 4- or 6-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The 6-KB
SRAM is an ultralow-power SRAM that retains its contents even in the lowest power modes (PM2/3). This is an
important feature for low-power applications.
The 64- or 96-KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces. In addition to holding program code and constants, the
non-volatile memory allows the application to save data that must be preserved such that it is available after
restarting the device. Using this feature, one can, e.g., use saved network-specific data to avoid the need for a
full start-up and network find-and-join process.
Clocks and Power Management
The digital core and peripherals are powered by a 1.8-V low-dropout voltage regulator. It provides power
management functionality that enables low-power operation for long battery life using different power modes.
Five different reset sources exist to reset the device.
Peripherals
The CC2533 includes many different peripherals that allow the application designer to develop advanced
applications.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is
possible to perform in-circuit debugging and external flash programming elegantly.
The device contains flash memory for storage of program code. The flash memory is programmable from the
user software and through the debug interface. The flash controller handles writing and erasing the embedded
flash memory. The flash controller allows page-wise erasure and 4-bytewise programming.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. CPU interrupts can be enabled
on each pin individually. Each peripheral that connects to the I/O pins can choose between two different I/O pin
locations to ensure flexibility in various applications.
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A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors anywhere in
memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) achieve
highly efficient operation by using the DMA controller for data transfers between SFR or XREG addresses and
flash/SRAM.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR Generation Mode, where it counts Timer 3 periods and the output is ANDed with
the output of Timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 (the MAC Timer) is specially designed for supporting an IEEE 802.15.4 MAC or other time-slotted
protocol in software. The timer has a configurable timer period and a 24-bit overflow counter that can be used to
keep track of the number of periods that have transpired. A 40-bit capture register is also used to record the
exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmission
ends, as well as two 16-bit output compare registers and two 24-bit overflow compare registers that can send
various command strobes (start RX, start TX, etc.) at specific times to the radio modules.
Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable
prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of
the counter channels can be used as a PWM output.
The sleep timer is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz RC oscillator periods.
The sleep timer runs continuously in all operating modes except power mode 3 (PM3). Typical applications of
this timer are as a real-time counter or as a wake-up timer to come out of power mode 1 (PM1) or 2 (PM2).
The battery monitor comparator enables simple voltage monitoring in the devices that do not include an ADC. It
is designed such that it is accurate in the voltage areas around 2 V, with lower resolution at higher voltages.
The random-number generator uses a 16-bit LFSR to generate pseudorandom numbers, which can be read by
the CPU or used directly by the command strobe processor. It can be seeded with random data from noise in the
radio ADC.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The core is able to support the security operations required by IEEE 802.15.4 MAC security, the
ZigBee network layer, and the application layer.
A built-in watchdog timer allows the CC2533 to reset itself in case the firmware hangs. When enabled by
software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. It can
alternatively be configured for use as a general 32-kHz timer.
USART 0 and USART 1 are each configurable as either a SPI master/slave or a UART. They provide double
buffering on both RX and TX, as well as hardware flow control, and are thus well suited to high-throughput
full-duplex applications. Each has its own high-precision baud-rate generator, thus leaving the ordinary timers
free for other uses.
The I2C module provides a digital peripheral connection with two pins and supports both master and slave
operation.
Radio
The CC2533 features an IEEE 802.15.4-compliant radio transceiver. The RF core controls the analog radio
modules. In addition, it provides an interface between the MCU and the radio which makes it possible to issue
commands, read status, and automate and sequence radio events. The radio also includes a packet-filtering and
address-recognition module.
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TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
TEMPERATURE
6
6
5.5
5
5
4
Output Power (dBm)
Output Power (dBm)
OUTPUT POWER
vs
FREQUENCY
4.5
4
3.5
3
2394
3
2
1
2414
2434
2454
2474
Frequency (MHz)
0
-40
2494 2507
0
40
Temperature (°C)
80
G001
120
G002
Figure 9.
Figure 10.
SENSITIVITY
vs
FREQUENCY
SENSITIVITY
vs
TEMPERATURE
-95
-92
-93
-96
Sensitivity (dBm)
Sensitivity (dBm)
-94
-97
-98
-95
-96
-97
-98
-99
-99
-100
2394
2414
2434
2454
2474
Frequency (MHz)
2494 2507
-100
-40
0
40
Temperature (°C)
G003
Figure 11.
20
80
120
G004
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
SENSITIVITY
vs
SUPPLY VOLTAGE
SENSITIVITY
vs
ERROR VECTOR MAGNITUDE
-94
-90
-95
-92
Sensitivity (dBm)
Sensitivity (dBm)
-96
-97
-94
-96
-98
-98
-99
-100
-100
2
2.4
2.8
Supply Voltage (V)
3.2
3.6
0
5
10
15
20
25
30
35
Error Vector Magnitude (%)
40
45
G005
G006
Figure 13.
Figure 14.
SENSITIVITY
vs
FREQUENCY OFFSET
ALTERNATE CHANNEL REJECTION
(802.15.4 INTERFERER)
vs
CARRIER LEVEL
70
0
-10
65
Alternate Channel Rejection (dB)
-20
Sensitivity (dBm)
-30
-40
-50
-60
-70
-80
60
55
50
45
-90
-100
-400
-300
-200
-100
0
100
200
Frequency Offset (ppm)
300
400
40
-95
-85
-75
-65
Carrier Level (dBm)
-55
-50
G007
Figure 15.
G008
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
POWER MODE 3 CURRENT
vs
TEMPERATURE
75
4
50
3
Power Mode 3 Current (µA)
Interferer Rejection (dB)
INTERFERER REJECTION (802.15.4 INTERFERER)
vs
INTERFERER FREQUENCY
(CARRIER AT –82 dBm, 2440 MHz)
25
0
-25
2400
2
1
2420
2440
2460
Interferer Frequency (MHz)
2480
0
-40
0
40
Temperature (°C)
G009
80
120
G010
Figure 17.
Figure 18.
Recommended RF Settings
This section contains a summary of the register settings that must be updated from their default value to have
optimal performance. The following settings should be set for both RX and TX. Although not all settings are
necessary for both RX and TX, it is recommended for simplicity (allowing one set of settings to be written at the
initialization of the code).
Table 2. Recommended RF Register Settings
22
Register Name
Value
FRMCTRL0
0x43
FRMCTRL1
0x00
TXFILTCFG
0x09
FSCAL1
0x00
IVCTRL
0x0F
FSCTRL
0x55
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Boost-Mode TX Settings
This section contains the register settings for boost-mode TX. Note that it is recommended to add two additional
components (a capacitor and an inductor) adjacent to the capacitor C253 in Figure 19 in order to reduce
third-harmonic spurious emission to simplify passing regulations. There are three do not mount pads on the EM
reference design. Two of these should be used to mount the additional components. The capacitor (0.9 pF)
should be mounted to the pad on the chip side of C253 (to the left of C253 in Figure 19). The inductor (4.3 nH)
should be mounted between C253 and the antenna on the pad closest to C253 (to the right of C253 in
Figure 19). Using this filter lowers the output power 0.12 dB when using boost-mode TX and 0.4 dB at regular full
power.
Table 3. Boost Mode TX Register Settings
Register Name
Value
FRMCTRL0
0x43
FRMCTRL1
0x00
TXFILTCFG
0x09
FSCAL1
0x00
IVCTRL
0x0F
FSCTRL
0xF5
TXCTRL
0x74
TXPOWER
0xFD
Table 4. Recommended Output Power Settings (1)
(1)
TXPOWER Register Setting
Typical Output Power (dBm)
Typical Current Consumption (mA)
Boost mode TX
7
38.8
0xEC
4.5
32.3
0xDC
3
30.4
0xCC
1.7
29.6
0xBC
0.3
28.5
0xAC
–1
27.9
0x9C
–2.8
26.7
0x8C
–4.1
26.3
0x7C
–5.9
25.8
0x6C
–7.7
25.5
0x5C
–9.9
25.3
0x4C
–12.4
25.1
0x3C
–14.9
25.0
0x2C
–16.6
24.9
0x1C
–18.7
24.9
0x0C
–20.4
23.3
Measured on Texas Instruments CC2533 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz, unless otherwise noted.
See Table 2 for recommended register settings.
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2533. A typical application circuit is shown in
Figure 19. Typical values and description of external components are shown in Table 5.
2-V to 3.6-V
Power Supply
Optional 32-kHz Crystal
C331
XTAL
C401
3 SDA
AVDD6 31
P2_4/XOSC32K_Q1 32
P2_2 34
P2_1 35
P2_0 36
P1_7 37
P1_6 38
2 SCL
P2_3/XOSC32K_Q2 33
1 NC
DVDD1 39
DCOUPL 40
C321
R301
RBIAS 30
AVDD4 29
AVDD1 28
4 NC
L252
C251
Antenna
(50 W)
C252
AVDD2 27
C253
5 P1_5
RF_N 26
L251
CC2533
6 P1_4
RF_P 25
L261
DIE ATTACH PAD
7 P1_3
AVDD3 24
XOSC_Q2 23
9 P1_1
XOSC_Q1 22
18 P0_1
19 P0_0
16 P0_3
17 P0_2
14 P0_5
15 P0_4
13 P0_6
11 P1_0
10 DVDD2
20 RESET_N
8 P1_2
12 P0_7
C261
C262
AVDD5 21
XTAL
Power-Supply Decoupling Capacitors Are Not Shown
Digital I/O Not Connected
C221
C231
S0383-02
Figure 19. CC2533 Application Circuit
Table 5. Overview of External Components (Excluding Supply Decoupling
Capacitors)
Component
24
Description
Value
C221
32-MHz xtal loading capacitor
27 pF
C231
32-MHz xtal loading capacitor
27 pF
C251
Part of the RF matching network
18 pF
C252
Part of the RF matching network
1 pF
C253
Part of the RF matching network
2.2 pF
C261
Part of the RF matching network
18 pF
C262
Part of the RF matching network
1 pF
C321
32-kHz xtal loading capacitor
15 pF
C331
32-kHz xtal loading capacitor
15 pF
C401
Decoupling capacitor for the internal digital regulator
1 mF
L252
Part of the RF matching network
2 nH
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CC2533
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SWRS087 – JUNE 2010
Table 5. Overview of External Components (Excluding Supply Decoupling
Capacitors) (continued)
Component
Description
Value
L261
Part of the RF matching network
2 nH
R301
Resistor used for internal biasing
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. The recommended balun shown
consists of C262, L261, C252, and L252.
If a balanced antenna such as a folded dipole is used, the balun can be omitted.
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See the 32-MHz Crystal Oscillator section for details. The load capacitance seen by the 32-MHz
crystal is given by:
1
CL =
+ Cparasitic
1
1
+
C221 C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C321 C331
(2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage-Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
REFERENCES
1. IEEE Std. 802.15.4-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications
for Low-Rate Wireless Personal Area Networks (LR-WPANs)
http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf
2. CC253x User's Guide – CC253x System-on-Chip Solution for 2.4 GHz IEEE 802.15.4 and ZigBee
Applications (SWRU191)
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25
CC2533
SWRS087 – JUNE 2010
www.ti.com
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC2533F32RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2533
F32
CC2533F32RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2533
F32
CC2533F64RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2533
F64
CC2533F64RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2533
F64
CC2533F96RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2533
F96
CC2533F96RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2533
F96
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
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(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Mar-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CC2533F32RHAR
VQFN
RHA
40
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
CC2533F32RHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
CC2533F64RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
CC2533F64RHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
CC2533F96RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
CC2533F96RHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2533F32RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
CC2533F32RHAT
VQFN
RHA
40
250
210.0
185.0
35.0
CC2533F64RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
CC2533F64RHAT
VQFN
RHA
40
250
210.0
185.0
35.0
CC2533F96RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
CC2533F96RHAT
VQFN
RHA
40
250
210.0
185.0
35.0
Pack Materials-Page 2
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