Application Report
Lit. Number – Month Year
I2C Implementation Using the N2HET
MCU Safety Application
Haixiao Weng
ABSTRACT
This application report describes how the Hercules N2HET peripheral can be used to
implement I2C master mode with interrupt capability and zero CPU overhead. The solution
applies to all the Hercules MCUs that have N2HET modules such as TMS570 series and
RM series devices.
Contents
1
Introduction .................................................................................................................................. 2
2
Examples ...................................................................................................................................... 3
3
CPU Side Software Description................................................................................................... 4
4
N2HET Emulated I2C..................................................................................................................... 8
5
Transmit/Receive Buffer Description ........................................................................................ 12
Reference ........................................................................................................................................... 13
Figure 1.
Figure 2.
Figure 3.
Figures
Hercules N2HET Emulated I C Implementation Overview ............................................ 3
The N2HET Emulated I2C Example Waveform ............................................................... 4
N2HET Emulated I2C FlowChart .................................................................................... 11
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Tables
I2C master write three data to slave ............................................................................... 5
I2C master read three data from slave ........................................................................... 7
I2C master write two data to slave, re-start, read two data from slave ........................ 8
N2HET Emulated I2C State Machine ............................................................................... 8
Pseudo C Expression Description.................................................................................. 9
N2HET Emulated I2C Master Summary......................................................................... 10
Transmit buffer Field Descriptions ............................................................................... 12
Receive buffer Field Descriptions ................................................................................ 13
2
1
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1 Introduction
The N2HET peripheral is a complex high-performance RISC coprocessor that operates
independently from the main CortexTM R4F CPU and can be used to implement complex timed
I/O operations running in the background. This is the enhanced version of the HET in
TMS470(M) series and the NHET in TMS570LS20x series. More information on the N2HET can
be found in the Hercules TRM and datasheet.
In this application report, the N2HET is used to implement I2C master interface. The goal is to
provide hardware I2C-module-like functionality with independent background
transmission/reception, features include:
• Speed: support both I2C standard and fast-mode.
• Interrupt: receive, transmit, NACK, and timeout interrupt.
• Address mode: 7-bit address space.
• Clock stretching
• Types of messages:
− Single message where a master writes data to a slave;
− Single message where a master reads data from a slave;
− Combined messages, where a master issues at least two reads and/or writes to
slaves repeated START bit mode.
The N2HET program runs in the background, independent of the main CortexTM R4F CPU, and
performs all the tasks associated with the I2C communication. The incoming data stream
delivered to an N2HET device I/O pin is decoded. Upon the reception of a full character, the
CortexTM R4F CPU program is notified, and it then can directly fetch the entire received data
byte from the N2HET internal RAM. For outgoing data streams, the CortexTM R4F CPU just
passes the data to be transmitted to the N2HET program and initiates the transmission. After
this, the entire transmission is handled by the N2HET program, and a data stream is output to
an N2HET device I/O pin. During this process, the CortexTM R4F CPU is free for applicationrelated tasks. Figure 1 shows a conceptual overview of the interaction among different
components. It illustrates the hardware setup for the attached example as well.
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I2C Implementation Using the N2HET
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3.3 V
Hercules MCU
2K ohm
TM
Cortex -R4F CPU
Main Application
Program
Data
Embedded
I2C Module
SDA
SCL
Interrupts
Rx/Tx /NACK Interrupts
Data
N2HET Co-Processor
I2C Master N2HET
Program
HET0 (SDA)
HET2 (SCL)
Figure 1.
Hercules N2HET Emulated I2C Implementation Overview
2 Examples
Two example CCS projects are provided to demo the N2HET emulated I2C master, one works
for the TMS570LS series and the other one works for the RM4x series. The N2HET clock is set
to 89.6MHz and the N2HET emulated I2C speed is set to fast mode – 400kbit/s. Suppose you
follow the hardware setup in Figure 1, import the examples to CCS5.3, download the code to a
TMS570LS1227, TMS570LS3137, RM46L852 or RM48L950 device, and run it, the following
waveform will show up on the SDA and SCL connections. The pink curve represents the SDA
line and the blue curve represents the SCL line. The waveform includes three parts (please
check the attached excel sheet for details):
1) the N2HET emulated I2C write 3 bytes to the slave
2) the N2HET emulated I2C read 3 bytes from the slave
3) a combined message, the N2HET emulated I2C write 2 bytes to the slave, following with a
repeated start, then, the N2HET emulated I2C read 2 bytes from the slave.
I2C Implementation Using the N2HET
3
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If you port the examples to a different Hercules device other than those listed in the form
paragraph, please check the device datasheet to make sure that your device’s HCLK frequency
can tolerance 179.2MHz. Otherwise, please adjust the PLL settings to slow down the HCLK,
meanwhile, adjust the HCLK to VCLK2 ratio in CLKCNTL register (@0xFFFFFFD0) and
HETPFR register (@0xFFF7B804 for N2HET1 or @0xFFF7B904 for N2HET2) to keep the same
LRP – 0.625ns. If the use case requires a slower I2C speed (e.g. 100kbit/s), please slow down
the LRP 4 times as well.
4
Master transmit
3 bytes to slave
Master receive 3
bytes from slave
Combined Message: Master
transmit 2 bytes, receive 2 bytes
3.5
Amplitude
3
2.5
2
1.5
1
0.5
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Time (ms)
SCL
Figure 2.
SDA
The N2HET Emulated I2C Example Waveform
3 CPU Side Software Description
This section discusses CortexTM R4F CPU side software of the attached example, and does not
explain the N2HET program. The N2HET program will be explained in next section.
I. Initialize the I2C module.
The attached example uses the Hercules MCU I2C module as the I2C slave. So, what the
application code does first is to initialize the on-chip I2C module, setting the PINMUX and
configuring the I2C. In sys_main.c:
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I2C Implementation Using the N2HET
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(*(volatile unsigned int *)(0xFFFFEA38))=0x83E70B13;
(*(volatile unsigned int *)(0xFFFFEA3C))=0x95A4F1E0;
*(volatile unsigned int *) 0xFFFFEB10 = 0x02020101; // SCL 0[17], SDA 0[25],
(*(volatile unsigned int *)(0xFFFFEA38))=0x0;
(*(volatile unsigned int *)(0xFFFFEA3C))=0x0;
i2cInit(0,
I2C2_ADDR);/** - set i2c mode */
II. Initialize the N2HET
hetInit() sets N2HET pin 0 and 2 as open drain output, load the N2HET program into N2HET
RAM. Then, the application enables the CPU IRQ and N2HET interrupt and start the N2HET
Program. In sys_main.c:
hetInit();
hetREG1->INTENAS = 0xFFFFFFFFU;//enable the HET interrupt
asm(" cpsie i"); //enable the CPU IRQ interrupt
hetREG1->GCR = 0x01010001;//start HET program
III. Start test for “single message where a master writes data to a slave”
Table 1.
Start
I2C master write three data to slave
Address(010_0111)
Data(0000_0001)
0
ACK
ACK
Data (1010_0101)
Data (0000_0010)
ACK
ACK
Stop
To start a transfer, the CortexTM R4F CPU needs to write Start bit, address bits, R/W bit, numer
of bytes to be transferred, and Stop bit to the transmit buffer of N2HET emulated I2C Master.
The HetI2CPutAddr() organize all of them into one write to the N2HET RAM.
HetI2CPutAddr() has a few input parameters, in the following example: I2C2_ADDR is the slave
I2C 7-bit address; RW represents whether it is master transmit message (‘0’) or it is master
receive message (‘1’); NumofBytes represents the number of data to be transmitted or received;
IntEna represents whether a transmit interrupt will be generated once the data is moved to shift
register; StopBit represents whether the stop bit will append to the end of transfer. In this
example, the parameters passed are: (0x27, 0, 3, 1, 1), which means: the slave address to be
talked is 0x27, it is a master transmit action, the master will transmit 3 data to slave (the address
byte itself is not included), the transmit interrupt will be generated, and the stop bit will append to
the end of the transfer. In sys_main.c:
HetI2CPutAddr(I2C2_ADDR, RW, NumOfBytes, IntEna, StopBit);
IV. Transmit 3 bytes data from N2HET emulated I2C Master to the slave.
Once the address bits move to the shift register, a transmit interrupt will be generated. Inside
the interrupt service routine, HetI2CPutData() write the data to be transmitted into the transmit
buffer. In het.c:
I2C Implementation Using the N2HET
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void het1HighLevelInterrupt(void)
{
uint32_t vect = hetREG1->OFF1;
switch (vect)
{
case 11: /*--------------------------->
Transmit interrupt */
if(Data_Send_HET<3)
{
HetI2CPutData(*I2C1_txptr++, IntEna);
Data_Send_HET++;
}
V. Slave receive 3 bytes data
Once the I2C module receives data, an I2C receive interrupt will be triggered. The received
data will be copied to the main memory. In i2c.c:
void i2cInterrupt(void)
{
register unsigned char vect = (i2cREG1->IVR & 0x00000007);
/*-------------------------------------------------------------------------*/
switch (vect)
{
case 0:
i2cREG1->STR = 0x000007FF;
break;
case 4: /*--------------------------->
Receive interrupt */
*I2C2_rxptr++ = i2cREG1->DRR; // read the data
Data_Rece_I2C++;
break;
VI. Process stop bit
After all three data has been sent to the slave, the stop bit will be generated. Once the slave
receives this stop bit, it will set the global variable Stop_Rece_I2C to 1. At this point, the test
for “single message where a master writes data to a slave” completes. In i2c.c:
case 6: /*--------------------------->
*/
Stop_Rece_I2C = 1;
break;
stop condition detection interrupt
The application will wait for a short period and continue with the test for “single message where
a slave writes data to a master”. In sys_main.c:
while(Stop_Rece_I2C == 0);//wait until master transmit completes.
Stop_Rece_I2C = 0;
for(wait_counter=0;wait_counter<0x18;wait_counter++); //wait some time.
VII. Start test for “single message where a slave writes data to a master”
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I2C Implementation Using the N2HET
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Table 2.
Start
I2C master read three data from slave
Address(010_0111)
Data(0100_0001)
1
ACK
ACK
Data (0000_1000)
Data (0100_0010)
ACK
noACK
Stop
The message starts with a slave address write. In this case, the parameters passed are:
(0x27, 1, 3, 0, 1), which means: the slave address to be talked is 0x27, it is a master receive
action, the master will receive 3 data from slave (the address byte itself is not included), the
transmit interrupt will not be generated, and the stop bit will append to the end of the transfer.
In sys_main.c:
RW = 1; //Read
IntEna = 0;//no transmit interrupt
HetI2CPutAddr(I2C2_ADDR, RW, NumOfBytes, IntEna, StopBit);
VIII. Slave sends 3 bytes data
Once the I2C module receives 7-bit addressing bits and R/W bit (‘1’ in this case), an I2C slave
transmit interrupt will be triggered. The data to be transmitted will be copied to the I2C transmit
buffer. In i2c.c:
case 5: /*--------------------------->
Transmit interrupt */
i2cREG1->DXR = *I2C2_txptr++; // send the data
Data_Send_I2C++;
break;
IX. N2HET emulated I2C Master receives 3 bytes data from slave.
Once the N2HET emulated I2C receives the data, a receive interrupt will be generated. Inside
the interrupt, the received data will be copied to the main memory. In het.c:
case 15: /*--------------------------->
Receive interrupt */
*I2C1_rxptr++ = (hetRAM1->Instruction[0x2C].Data>>8) & 0xFF;//read data
Data_Rece_HET++;
break;
X. Process with stop bit
Same as step VI, after the transfer completes, the stop bit will be sent out. Once the slave
receives the stop bit, an interrupt will be triggered. Then the application can continue with the
next test - Combined messages, where a master issues at least two reads and/or writes to
slaves - repeated START bit mode.
XI. Start “combined message in repeated START bit mode”
The N2HET emulated I2C Master will first write 2 data bytes to slave and then read 2 data
bytes from slave. Two start bit and only one stop bit will be sent out in this procedure.
I2C Implementation Using the N2HET
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Table 3.
Start
I2C master write two data to slave, re-start, read two data from slave
Address(010_0111)
0
Data(0001_1110)
ACK
Data(1000_0101)
ACK
ACK
ReStart
Data (0101_1010)
ACK
Address(010_0111)
Data (1000_0110)
1
ACK
noACK
Stop
The message starts with a slave address write. In this case, the parameters passed are:
(0x27, 0, 2, 1, 0), which means: the slave address to be talked is 0x27, it is a master transmit
action, the master will transmit 2 data to slave (the address byte itself is not included), the
transmit interrupt will be generated, and no stop bit append to the end of the transfer. In
sys_main.c:
RW = 0; //write
IntEna = 1;//transmit interrupt
StopBit = 0; //no stop bit for the first transfer
NumOfBytes = 2; //write 2 data, 1 repeat address, read 2 data
HetI2CPutAddr(I2C2_ADDR, RW, NumOfBytes, IntEna, StopBit);
Please note that in repeated START bit mode, only the final start bit has matching stop bit.
XII. N2HET emulated I2C Master transmit 2 bytes data to the slave. After that, it receives 2 bytes
data from the slave.
This step is similar to step VIII and IX. After two bytes of data is sent out to the slave, the
application initiates another transfer – receive two bytes of data from slave. Please note that,
no stop bit is inserted between the write and read. After all the transfer complete, the
application code reaches a while(1) loop. The user can check the received data I2C1_RxData
and I2C2_RxData against the data transmitted I2C2_TxData and I2C1_TxData.
4 N2HET Emulated I2C
This section explains the N2HET program. You can skip it if you use the example as it is.
This N2HET program emulates the I2C master as a state machine. Table 4 illustrates the key
part of a typical I2C master and the related N2HET state machine index. Table 5 explains the
pseudo C functions used in Table 4.
Table 4.
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N2HET Emulated I2C State Machine
I2C Master
Function
Pseudo C Expression
N2HET State
Machine Index
Generate
START Bit
while (Data_Valid() == 0);
Writ_SDA(1);
Writ_SCL(1);
while (Read_SCL()==0) {
// Clock stretching
// Consider timeout here
State0
I2C Implementation Using the N2HET
State1
State2
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Write/Read a
data/address
bit
Generate
STOP Bit
}
Writ_SDA(0);
Writ_SCL(0);
Writ_SDA(x);
//read: x=1, write: x=bit to be written
Writ_SCL(1);
while (Read_SCL()==0) {
// Clock stretching
// Consider timeout here
}
Read_SDA();//Read data bit in
Writ_SCL(0);
Writ_SDA(0);
Writ_SCL(1);
while (Read_SCL()==0) {
// Clock stretching
// Consider timeout here
}
Writ_SDA(1);
Table 5.
State3
State4
State5
State6
State7
State8
State9
Pseudo C Expression Description
Pseudo C Expression
Description
Data_Valid()
Writ_SDA(x);
Check whether the transmit buffer has valid data not
Write a bit ‘x’ to Pin SDA. Write ‘1’ doesn’t impact the Open-Drain Pin
Status. Write ‘0’ clear SDA.
Write a bit ‘x’ to Pin SCL. Write ‘1’ doesn’t impact the Open-Drain Pin
Status. Write ‘0’ clear the SCL.
Read the current status of Pin SCL.
Read the current status of Pin SDA.
Writ_SCL(x);
Read_SCL();
Read_SDA();
2
Figure 3 discuss the N2HET program flow of the I C master implementation, in other words, how the N2HET
program switches among those states in Table 4. Note that when it is indicated that data is stored at or loaded
from an N2HET program location, this always refers to the data field that is embedded in the instruction.
2
N2HET program State0, which indicates the emulated I C is in idle mode, constantly polls the transmit buffer
(data field of Master_Start). If the “Valid” bit is ‘1’ in this buffer, it will process and copy the transmit buffer into the
TM
data shift register (data field of SDA_SHFT). A transmit interrupt can be issued to the Cortex R4F CPU at this
point. Meanwhile, the clock shift register (data field of SCL_SHFT) is initialized as well. If the data to be
transmitted is an address, it will save the “R/W” bit and “Stop” bit in data field of State0 and the “Num_of_Bytes”
to be transferred in the data field of ByteRecTran. For more details, please refer to the 5 transmit/receive buffer
description. The N2HET program will switch to State1 to send the start bit or switch to State4 to transmit/receive
data according to the start bit settings in the transmit buffer.
The transmitted data bit is sent to SDA pin after the falling edge of the SCL and the received data bit is sampled
(shift in) after the rising edge of the SCL. As described by the clock stretching, the slave may hold the SCL low if
it is not ready. The N2HET program implements a counter to deal with such saturation. If the counter overflows, a
TM
timeout interrupt will be issued to the Cortex R4F CPU. Upon reception of all 8 data bits (one byte), a receive
TM
interrupt can be issued to the Cortex R4F CPU. Then the R4F CPU can read out the data from CleanRecDat.
th
Or, if it is a transmit message, the master expect the 9 bit to be ACK, if no ACK is received, a NACK interrupt
can be generated. This N2HET program also implements a double-buffering scheme, effectively allowing the
N2HET program to transmit/receive a byte while one is waiting to be written/read out by the application program.
I2C Implementation Using the N2HET
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Once all the planned data bytes are received or transmitted, the N2HET program will check for the “Stop” bit, and
2
determine whether to shift out the stop bit. After sending out the stop bit, the I C message is over and the N2HET
TM
program will be back to the idle state waiting for command from Cortex R4 CPU.
The I2C N2HET program function takes 72 words of N2HET program memory. A minimum of 6 and a
maximum of 33 (worst case) HET instructions are executed in one LRP. In the attached examples,
HCLK=179.2MHz, VCLK2=89.6MHz, and the LRP is set to 0.625us to run the I2C in fast mode – 400kbit/s.
Therefore, each LRP only has 56 time slots. Here, we recommend only one I2C fast mode master instance per
N2HET. If running I2C in standard mode – 100kbit/s, each LRP should have enough time slots to run 2 instances
I2C master.
Table 6.
N2HET Emulated I2C Master Summary
Feature
2
I C Master, with clock stretching, no arbitration; Support
transmit, receive and combined messages; Provide transmit,
receive, NACK and timeout interrupt
10
I2C Implementation Using the N2HET
Performance
Number of
Instances
400kbit/s
100kbit/s
1 per N2HET
2 per N2HET
Overwrite this text with the Lit. Number
HET Start
State 0
N
Move data to SDA Shift register
Prepare SCL Shift register
Clear the transmit buffer
Save R/W bit and “include stop” bit to State0
Set number of bytes to be transferred to ByteRecTran
Y, include
START bit
Data Valid?
Y, but No
START bit
Shift Out SDA
State 1
Shift Out SCL
State 2
Read_SCL()==1
N
Y
Shift Out SDA
State 3
Shift Out SCL
State 4
Shift Out SDA
State 5
Shift Out SCL
State 6
N
Read_SCL()==1
Y
N
N
All n bytes transfer
completed?
Y
N
Y
Shift in SDA
All 9 bit transfer
completed?
Shift Out SCL
State 7
Generate Stop bit?
Y
Shift Out SDA
State 8
Shift Out SCL
State 9
Y
Shift Out SDA
Figure 3.
N
Read_SCL()==1
2
N2HET Emulated I C FlowChart
I2C Implementation Using the N2HET
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5 Transmit/Receive Buffer Description
I. Transmit buffer (hetRAM1->Instruction[0].Data)
31
30
29
22
Start_bit
15
Data_Transmit
14
Note:
Name
6-0
Reserved
14-7
Num_of_Bytes
17
18
12
19
Stop_bit
18
17
16
Tran_Int
Valid
Start
6
0
Reserved
This buffer is write only.
Bits
16
20
Num_of_Bytes
Table 7.
15
ACK
7
Stop
21
Value
0
0 byte will be transmitted or received.
1
1 byte will be transmitted or received.
7Fh
127 bytes will be transmitted or received.
Stop bit included? Only take effect when Start bit is ‘1’
0
Don’t send out stop bit
1
Send out stop bit
Start
Start bit included?
0
Send out start bit before the data frame, which mean it is an address frame
1
Do not send out start bit before the data frame, which mean it is not an address frame
Valid
Data is valid?
0
Data is not valid. The N2HET program ignores it.
1
Data is valid. The N2HET program move it to the shift register.
Tran_Int
Stop_bit
21
ACK
29-22
Data_Transmit
31-30
Start_bit
Description
Number of bytes to be transmitted or received (exclude the address)
Stop
20-19
Transmit buffer Field Descriptions
Generate transmit interrupt?
0
No transmit interrupt will be generated.
1
A transmit interrupt will be generated after the data is moved to the shift register
1h
Represents the stop bit (01b) to be sent out to SDA
Send out ACK bit?
0
Send out ACK bit ‘0’
1
Do not Send out ACK bit
Data to be transmitted. If Start is ‘1’, it is the 7 address bits + the R/W bit.
2h
Represents the start bit (10b) to be sent out to SDA
I2C Implementation Using the N2HET
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II. Receive buffer (hetRAM1->Instruction[0x2C].Data)
31
16
Reserved
15
8
Data_Received
Note:
7
6
ACK
0
Reserved
This buffer is read only
Table 8.
Bits
Name
6-0
Reserved
7
ACK
15-8
Data_Received
31-16
Reserved
Value
Receive buffer Field Descriptions
Description
Send out ACK bit?
0
Send out ACK bit ‘0’
1
Do not Send out ACK bit
Data byte received.
Reference
1.
2.
3.
4.
TMS570LS1227 Technical Reference Manual (SPNU515)
TMS570LS1227 Data Sheet (SPNS192)
RM46L852 Technical Reference Manual (SPNU514)
RM46L852 Data Sheet (SPNS185)
I2C Implementation Using the N2HET
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