Media: Hercules_MCU_1Day_LaunchPad_Training.pdf

Hercules™ Safety Microcontrollers
1 Day Safety MCU Workshop
Agenda:
• Introduction
• What is Functional Safety & Safety Standards Overview
• IEC 61508 & ISO 26262 Safety Standards
• Safety System Architectures
• SafeTI™
• Hercules Safety Concept
• Development Tools: Hardware kits, Software tools
• Printed Circuit Board Design Considerations
• Lab 1: Hercules™ Safety MCU Demos
• Hercules™ Architecture
• Embedded Flash Memory tools
• Real Time Interrupt (RTI)
• Vectored Interrupt Manager (VIM)
• Direct Memory Access (DMA)
• General-purpose I/O (GIO) & NHET Timer Co-processor
• Lab 2: PWM Generation using the NHET & Clock Monitor
• Communication Interfaces: Multi-Buffered Serial Peripheral Interface (MibSPI),
CAN, FlexRay, EMAC, USB, UART, LIN
• External Memory Interface (EMIF) / Parameter Overlay (POM)
• Multi-buffered Analog-to-Digital Converter (MibADC)
• Lab 3: MibADC Light Sensor & SCI Communication
• Additional Hercules Information: Web, Forum, WIKI & Training
2
Hercules™ Software Install Instructions
Required Software
Three software titles will be used to during the lab exercises of this
workshop: Hercules Safety MCU Demos, Code Composer Studio v5.x,
HALCoGen
Software Download & Install Location:
Hercules Safety MCUs
• Hercules Safety MCU Demos
• The Demo software can be downloaded here:
Hercules Safety MCU Demos LINK
• A standard install of the software is required
• Code Composer Studio
• CCS can be downloaded here:
CCSv5 Download LINK
• A full install (Complete Feature Set) is acceptable, but at
a minimum a custom install where the ‘Safety MCUs’
processor support is selected will be necessary.
• Select the FREE LICENSE option the first time CCS is run:
• HALCoGen
• HALCoGen can be downloaded here:
HALCoGen Download LINK
• A standard install of the software is required
3
Hercules™ Safety MCU: Introduction
4
TI Embedded Processing Portfolio
Microcontrollers
16-bit
32-bit
Real-time
32-bit
M4F ARM
Applications Processors / DSP
32-bit
R4F ARM`
32-bit
ARM+
32-bit
ARM+DSP
DSP
ARM9
ARM Cortex-A8
ARM9/Cortex-A8
plus C64x+
C55x, C64x+
C647x
Industry-Std
Core,
High-Perf GPP
Industry-Std Core +
DSP for Signal Proc.
Leadership DSP
Performance
Accelerators
4800 MMACs/
1.07 DMIPS/MHz
24,000 MMACS
MMU, Cache
Up to 3 MB
L2 Cache
VPSS, USB,
EMAC, MMC
1G EMAC, SRIO,
DDR2, PCI-66
Lin/Win O/S +
Video, Imag, MM
Comm, WiMAX,
Industrial/
Medical Imaging
ARM Core Offerings
MSP430
C2000
Tiva™ C Series
Hercules™
TMS570/RM4
Ultra-low
Power
Fixed &
Floating Point
Industry Std
Low Power
Up to 25 MHz
Up to 300 MHz
<100 MHz
Flash
1 KB to 256 KB
Flash
32 KB to 512 KB
Flash
Up to 256 KB
Flash
Up to 3 MB
Analog I/O, ADC
LCD, USB, RF
PWM, ADC,
CAN, SPI, I2C
USB, ENET,
ADC, PWM, CAN
Timer co-proc
Measurement,
Sensing, General
Purpose
Motor Control,
Digital Power,
Lighting
Host
Control
10/28/2013
Floating Point
Over 350 DMIPS
ENET,ADC, CAN
Safety Critical
Transportation,
Industrial &
Medical
MMU
USB, LCD,
MMC, EMAC
Linux/WinCE
User Apps
Software, Tools & BSPs
5
TM
TI Hercules MCU Platform
ARM® Cortex™ Based Microcontrollers
RM
Industrial and Medical
Safety MCUs
TMS570
Hercules™
Safety MCU
Platform
Transportation and
Safety MCUs
TMS470M
Value Line Transportation
& Safety MCUs
• Industrial Applications
• Medical Applications
• -40 to 105°C Operation
• ENET, USB, CAN & UART
• Developed to Safety Standards
• IEC 61508 SIL-3
• Cortex-R – over 350 DMIPs
• Transportation Applications
• Automotive Q100 Qualification
• -40 to 125°C Operation
• FlexRay, ENET, CAN, LIN/UART
• Developed to Safety Standards
• ISO 26262 ASIL-D
• IEC 61508 SIL-3
• Cortex-R – over 280 DMIPs
• Transportation Applications
• Automotive Q100 Qualification
• -40 to 125°C Operation
• CAN, LIN/UART Connectivity
• Supports Safety for
• IEC 61508 Systems
• Cortex-M – to 100 DMIPS
6
Hercules™ Safety MCU Applications
Aerospace & Railway
Industrial
Communications Gateway
Flight Control
Industrial Motor
Control
Avionics / Autopilot
Manufacturing /
Robotics
Wind Power
Anti-Skid Control
Elevator
Escalator
Motor Control
Automotive
Industrial
Automation / PLC
Airbag
Braking / Stability Control
Sensor & Communications
Gateway
Solar Power
Hybrid & Electric Vehicles
Radar / Collision Avoidance
(ADAS)
Infusion Pumps
Oxygen
Concentrators
Active Suspension
Chassis / Domain Control
Electric Power Steering
Anesthesia
Respirators
Medical
7
TI Transportation & Safety MCU Technology
RM4
Cortex
TMS570
Cortex
TMS470M
R4
Cortex
TMS470
TMS370C16
R4F
M3
12F021
ARM7
15F035
TMS370C8
18F05
2013
33F10
2006
33F12
2000
1990’s
1980’s
8
Hercules™ RM Cortex™-R Roadmap
2012
High
RM48L9x – 220MHz R4F
!
3MB Flash, 256kB RAM
SafeTI ISO & IEC
Features:
Lock Step
Architecture
RM48L5x – 200MHz R4F
2MB Flash, 192kB RAM
SafeTI ISO & IEC
2014
2013
CAN CAN
CAN
ISO ISO 13849
Ethernet
QEP/PWM
USB
IEC IEC 61508
!
SafeTI
!
RM46L8x – 220MHz R4F
1.25MB Flash, 192kB RAM
SafeTI ISO & IEC
Mid
Next Gen High
SafeTI ISO & IEC
Next Gen Mid
SafeTI ISO & IEC
RM46L4x – 200MHz R4F
1MB Flash, 128kB RAM
SafeTI ISO & IEC
Low
CAN
Production
Sampling
RM42x – 100MHz R4
384kB Flash, 32kB RAM
SafeTI ISO & IEC
!
Next Gen Low
SafeTI ISO & IEC
CAN
Development
9
RM46x Block Diagram
Dual Core Lockstep ARM Cortex-R4F w/ Floating Point
Features
IEC
CAN
Performance / Memory
•
•
•
•
Up to 220 MHz ARM Cortex-R4F w/ Floating Point
Up to 1.25MB Flash and 192KB Data SRAM w/ECC
Dedicated 64KB Data Flash (EEPROM Emulation)
16 Channel DMA
RM46x
ARM
Cortex™-R4F
ARM
Cortex-R4F
Temperature Range
-40°C - 105°C
Memory
Power & Clocking
Up to 1.25MB
Flash (w/ ECC)
CLKMON
Up to 192KB
SRAM (w/ ECC)
Up to 220 MHz
Note: Above reflects max configuration of each module – some functions are multiplexed.
VMON
Safety & System
64KB EEPROM (emulated)
Memory Protection Unit
Safety
• Dual CPUs in Lockstep
• CPU Logic Built in Self Test (LBIST)
• Up to 12 CPU MPU regions
• Flash & RAM w/ ECC (w/ bus protection)
• Memory Built-in Self Test (PBIST)
• Cyclic redundancy checker module (CRC)
• Select peripheral RAMs protected by Parity
Communication Networks
• 10/100 MAC
• USB: Host and Device
• 3 CAN Interfaces
• 5 SPI (3 Multi-Buffered)
• 2 UART, 1 I2C
Enhanced I/O Control
• 2x High End Timer Coprocessor (N2HET) w/DMA
• Up to 44 pins plus 6 monitor channels
• Pins can be used as Hi-Res PWM or Input Capture
• Motor Control Timers
• 7x ePWM (14 ch), 6x eCAP, 2x eQEP
• 2 x12-bit Multi-Buffered ADC
• 24 total input channels (16 shared)
• Calibration and Self Test
• Up to 101 GPIO pins (16 dedicated)
OSC/PLL
Debug
Lockstep CPU Fault
Detection
CPU BIST
SRAM BIST
CRC
JTAG
OS Timers
Calibration
Windowed Watchdog
DMA w/ Memory Protection Unit
Enhanced System Bus and Vectored Interrupt Manager
Analog
Communications
Control Peripherals
12-bit MibADC1 – 24ch
10/100 EMAC
2x High End Timer (N2HET)
USB Host & Device
ePWM (14ch)
(16 shared channels)
12-bit MibADC2 – 16ch
(16 shared channels)
Memory Interface
SDRAM EMIF
3x CAN (64mb)
eCAP (6x)
3x Multi-Buffer SPI , 2x SPI
eQEP (2x)
2x UART
Input / Output
I2C
GIO/INT (16)
Packages
Targeted Applications
144p QFP
(20x20mm)
337p BGA
(16x16mm)
 General IEC61508
Safety Applications
 Industrial, Medical,
Energy
10
Hercules™ TMS570 Roadmap
2012
High
TMS570LS31x – 180MHz R4F
3MB Flash, 256kB RAM
SafeTI ISO & IEC
2013
!
2MB Flash, 192kB RAM
SafeTI ISO & IEC
Features:
Lock Step
Architecture
TMS570LS21x – 180MHz R4F
ISO ISO 26262
Ethernet
QEP/ePWM
CAN CAN
CAN
2014
FlexRay
IEC IEC 61508
!
SafeTI
TMS570LS12x – 180MHz R4F
!
1.25MB Flash, 192kB RAM
SafeTI ISO & IEC
Mid
Next Gen High
SafeTI ISO & IEC
Next Gen Mid
SafeTI ISO & IEC
TMS570LS11x – 180MHz R4F
1MB Flash, 128kB RAM
SafeTI ISO & IEC
CAN
Low
TMS570LS04x – 80MHz R4
Production
384kB Flash, 32kB RAM
SafeTI ISO & IEC
Sampling
TMS570LS03x – 80MHz R4
Development
256kB Flash, 24kB RAM
SafeTI ISO & IEC
Next Gen Low
SafeTI ISO & IEC
!
CAN
11
TMS570LS31x/21x Block Diagram
Dual Core Lockstep ARM Cortex-R4F w/ Floating Point
Features
IEC
ISO
CAN
Performance / Memory
•
•
•
•
Up to 180 MHz ARM Cortex-R4F w/ Floating Point
Up to 3MB Flash and 256KB Data SRAM
Dedicated 64KB Data Flash (EEPROM Emulation)
16 Channel DMA
TMS570LS31x
Temperature
ARM
Cortex™-R4F
ARM
Cortex-R4F
Up to 180 MHz
Note: Above reflects max configuration of each module – some functions are multiplexed.
Lockstep CPU Fault
Detection
AEC Q100
Memory
Power & Clocking
Up to 3MB
Flash (w/ ECC)
CLKMON
Up to 256KB
SRAM (w/ ECC)
Memory Protection Unit
Safety
• Dual CPUs in Lockstep
• CPU Logic Built in Self Test (LBIST)
• Up to 12 CPU MPU regions
• Flash & RAM w/ ECC (w/ bus protection)
• Memory Built-in Self Test (PBIST)
• Cyclic redundancy checker module (CRC)
• Select peripheral RAMs protected by Parity
Communication Networks
• 10/100 MAC
• FlexRay w/DMA
• 3 CAN Interfaces
• 5 SPI (3 Multi-Buffered)
• 2 UART (1 LIN capable), 1 I2C
Enhanced I/O Control
• 2x High End Timer Coprocessor (N2HET) w/DMA
• Up to 44 pins plus 6 monitor channels
• Pins can be used as Hi-Res PWM or Input Capture
• 2 x12-bit Multi-Buffered ADC
• 24 total input channels (16 shared)
• Calibration and Self Test
• Up to 120 GPIO pins (16 dedicated)
-40°C - 125°C
OSC/PLL
VMON
Safety & System
64KB EEPROM (emulated)
CPU BIST
Debug
SRAM BIST
CRC
JTAG
ETM, RTP, DMM
OS Timers
Windowed Watchdog
DMA w/ Memory Protection Unit
Enhanced System Bus and Vectored Interrupt Manager
Analog
Communications
Control Peripherals
12-bit MibADC1 – 24ch
10/100 EMAC
High End Timer 1
(N2HET1 = 32ch)
(16 shared channels)
12-bit MibADC2 – 16ch
2ch FlexRay
(16 shared channels)
3x CAN (64mb)
Memory Interface
3x Multi-Buffer SPI , 2x SPI
SDRAM/ASYNC EMIF
High End Timer 2
(N2HET2 = 14ch)
2x UART (1 LIN capable)
Input / Output
I2C
GIO/INT (16)
Packages
Targeted Applications
144p QFP
(20x20mm)
337p BGA
(16x16mm)
 IEC 61508 and ISO
26262 Safety
Applications
 Automotive, Rail,
Aerospace (COTS), Off
Road
12
What is Functional Safety &
Safety Standards Overview
13
International Functional Safety Standards
Automotive and
Transportation
DO-178B
(railway)
HEV/EV Cars
Industrial and
Medical
DO-254
EN 50128
(cots
aerospace)
IEC
60601
IEC
50156
(medical
equipment)
(furnaces)
Hercules
Sensor &
communications
gateway
TM
Safety MCU
Radar / Collision
Avoidance (ADAS)
IEC 60880
IEC
61511
(nuclear
power
stations)
(process
industry)
Active suspension, ABS,
electric power steering,
airbag and more!
IEC 62061
ISO 13849
(machinery)
Manufacturing, robotics,
industrial automation,
motor control
ISO 26262
IEC 61508
(automotive)
(safety)
Wind & Solar Power
Railway Systems
Aerospace Systems
 Safety critical systems are everywhere
 Systems need to manage hazardous failures
 Many systems need to be safety-certified
Anesthesia machines,
respirators, ventilators,
oxygen concentrators
14
What is Functional Safety?
• Basic Functional Safety Concepts:
– All systems will have some inherent, quantifiable failure rate. It is not possible
to develop a system with zero failure rate.
– For each application, there is some tolerable failure rate which does not lead
to unacceptable risk.
– Acceptable failure rates vary per application, based on the potential for direct
or indirect physical injury in the event of system malfunction.
– Categories can be developed to quantify similar levels of risk. These are
known as Safety Integrity Levels, or SILs.
ISO 26262
DO-254
Design Assurance Levels
ASIL Levels
IEC 61508
QM
A
SIL Levels
B
1
A
C
2
B
D
3
C
E
4
D
Quality Managed
15
Functional Safety Definitions
IEC 61508 Definition:
– Safety is the freedom from unacceptable risk of physical injury or of
damage to the health of people, either directly, or indirectly as a
result of damage to property or to the environment.
– Functional Safety is part of the overall safety that depends on a
system or equipment operating correctly in response to its inputs.
ISO 26262 Definition:
– Absence of unacceptable risk due to hazards caused by malfunctional behavior of electrical and/or electronic systems
16
Other Safety Concepts & Definitions
• Fault:
– Operational issue in a system which may lead to a failure.
• Failure:
– Result of a fault which leads to an inability to execute safety critical functionality
• Fault Tolerance :
– Ability to continue safe operation after a fault.
• Fail Safe System:
– System where a fault which may lead to failures is detected and the system is put into a safe state
such that faults may not propagate to other systems
• Fail Functional/Operational System:
– System where a fault which may lead to failures is detected and the system can continue
operation without loss of safety function.
• Reliability
– Ability to execute operations in system without failure (generally independent of consideration for
a safety function)
• Availability
– Amount of time in which a safety function is available divided by total system operation
time. Systems with high reliability and fail functional systems tend to have higher availability than
fail safe systems
• Security
– Ability to detect, resist, or prevent tampering with product functionality.
17
Safety Failures and their Causes
• Failures in a functional safety system can
be broadly classified into two categories:
Systematic and Random failures
Failures
Systematic
Random
• Systematic Failures
– Result from a failure in design or manufacturing
– Often a result of failure to follow best practices
– Rate of systematic failures can be reduced through continual and
rigorous process improvement
• Random Failures
– Result from random defects inherent to process or usage condition
– Rate of random failures cannot generally be reduced; focus must be
on the detection and handling of random failures in the application.
Note: Software failures are considered to be systematic
18
Functional Safety vs. Quality/Reliability
• High quality and reliability do not guarantee safety.
• Methods to ensure quality and reliability have high overlap to methods
used to manage systematic safety failures.
• Requirements to manage safety of random hardware failures in
applications typically do not overlap quality, reliability and security
requirements.
When faced with a potential system over temperature fault that causes
wiring to melt resulting in a system failure:
− A reliability engineer would approach the problem by designing the
system with high temperature wiring
− A functional safety engineer would approach the problem by designing
the system to detect the over temperature condition and placing the
system into a safe state before the wiring could melt.
19
Functional Safety vs. Security
• A secure system is capable of detecting, resisting or
preventing tampering from the outside world
• A functionally safe system is capable of detecting faults
and preventing damage to the outside world
Secure System:
Avoids system manipulation from the
outside world
Functional Safe System:
Does not create an unacceptable risk
to the health of people, the system or
the environment
20
Safety Goals
• Safety Goals must defined for a safety system
– Example: Automotive Air Bag System:
• Air bag must deploy in the event of an accident
• Air bag must not inadvertently deploy when there is not an accident.
• Safety goals are used to help determine the level of functional safety is
necessary in a system.
• These safety levels are usually referred to as Safety Integrity Levels or
SILs.
• Different safety standards have different metrics and naming
classifications for SILs.
21
ISO 26262 vs IEC 61508 Safety Integrity Levels
• ISO 26262 was developed to
meet automotive industry
specific needs as replacement
for IEC 61508.
• IEC 61508 defines 4 safety
integrity levels (SIL-1,2,3,4)
• ISO26262 defines a Quality
Managed level in addition to 4
safety integrity levels
(ASIL-A,B,C,D)
ISO 26262
ASIL Levels
IEC 61508
SIL Levels
Quality Managed
1
A
2
B
3
C
4
D
QM
• There is no direct correlation
between IEC61508 SIL and ISO
26262 ASIL levels
22
Aerospace DO-254 Design Assurance Levels
• DO-254 Consists of 5 ‘Design Assurance Levels’ (DALs)
• DAL-A is the most stringent, DAL-E is the least
• An FAA ‘Designated Engineering Representation’ (DER) must audit &
approve
DO-254
ISO 26262
Design Assurance Levels
ASIL Levels
IEC 61508
A
SIL Levels
QM
Quality Managed
B
1
A
C
2
B
D
3
C
E
4
D
23
Determining ISO 26262 ASIL Level
• To determine the ASIL level of a system a Risk Assessment must be
performed for all Hazards identified.
• Risk is comprised if three components: Severity, Exposure & Controllability
S = Severity
Class
C = Controllability
Description
Class
Description
S0
No injuries
C0
Controllable in general
S1
Light and moderate injuries
C1
Simply controllable
S2
Severe and life-threatening injuries (survival probable)
C2
Normally controllable
S3
Life-threatening injuries (survival uncertain), fatal injuries
C3
Difficult to control or uncontrollable
E = Exposure
Class
Description
E0
Incredible
E1
Very low probability
E2
Low probability
E3
Medium probability
E4
High probability
Accident
Causal Factor1
Hazard
Causal Factorn
Risk = S x (E * C)
Safety Goal1
Safety Goaln
24
ASIL Determination Table
Risk = Severity x (Exposure * Controllability)
Controllability
Severity
S1
Light and moderate injuries
S2
Severe and life-threatening
injuries (survival probable)
Exposure
C1Simply
C2 Normal
C3 Difficult
E1 Very Low
QM
QM
QM
E2 Low
QM
QM
QM
E3 Medium
QM
QM
ASIL A
E4 High
QM
ASIL A
ASIL B
E1 Very Low
QM
QM
QM
E2 Low
QM
QM
ASIL A
E3 Medium
QM
ASIL A
ASIL B
ASIL A
ASIL B
ASIL C
E1 Very Low
QM
QM
ASIL A
E2 Low
QM
ASIL A
ASIL B
E3 Medium
ASIL A
ASIL B
ASIL C
E4 High
ASIL B
ASIL C
ASIL D
E4 High
S3
Life-threatening injuries
(survival uncertain), fatal
injuries
25
Hardware Failure Modes
ISO 26262 Failure Rates
Non Safety Related
Safety Related
Safe Fault
Failure Rate λ
Safe Fault
Detected
Multiple
Point Fault
Perceived
Multiple
Point Fault
Latent
Multiple
Point Fault
Residual /
Single
Point Fault
λSPF – Single Point Faults
λRF
– Residual Faults
λMPFDP – Detected/Perceived Multi Point Faults
λMPFL – Latent Multi Point Faults
λMPF – λMPFDP + λMPFL = Multi Point Faults
λS
– Safe Faults
λ = λSPF + λRF + λMPF + λS
FIT = Failures In Time = 1 failure in 109 device hours
26
Fault Metrics
• Minimize single point and residual faults.
 Detected and handled by system within system safety response time.
Metric
ASIL B
ASIL C
ASIL D
Single point fault metric
• Minimize latent multi point faults.
 Detected and handled within hours through test algorithms.
Metric
ASIL B
ASIL C
ASIL D
Latent fault metric
27
IEC 61508 Failure Rates
Failure Rate λ
• λS – Safe failure rate
– No impact on safety function
– λSD – Safe detected failure rate
– λSU – Safe undetected failure rate
• λD – Dangerous failure rate
– Impact on safety function
– λDD – Dangerous detected failure rate
– λDU – Dangerous undetected failure rate
λ = λS + λD = (λSD + λSU) + (λDD + λDU)
FIT = Failures In Time = 1 failure in 109 device hours
28
IEC 61508 Safe Failure Fraction & SIL
Determination
λDU
Safe Failure Fraction (SFF) = 1 –
λ
High Demand System
Hardware Fault Tolerance = 0 (single channel)
Hardware Fault Tolerance = 1 (redundant)
• 1 Fault may lead to loss of safety function.
• 2 or more faults needed to loss of safety function.
Hardware Fault Tolerance
Safe Failure Fraction
(High Demand System)
HFT = 0
HFT = 1
0 … < 60
-
SIL1
60 … < 90
SIL1
SIL2
90 … < 99
SIL2
SIL3
≥ 99
SIL3
SIL4
29
Safety System Architectures
30
Safety System Architectures
• There are numerous system architectures
designed for functional safety. This section
describes a few of the most common, but is not
exhaustive.
• General terminology is “XooY”
– X out of Y
– X out of Y total units must fail for total system to fail
31
1oo1 Processing Architecture
Sensor
Embedded
Processor
+
Output
Circuit
Actuator
• “One out of One” subsystem failure creates system failure
• Most minimal system configuration possible
• No internal diagnostics
• No fault redundancy
32
1oo2 Processing Architecture
Sensor
Sensor
Embedded
Processor
Embedded
Processor
+
Output
Circuit
Actuator
• “One out of Two” subsystems must fail for system to fail
• Two controllers with independent I/O
– Both controllers must command an output for output to occur
– Failure in both systems required for inadvertent activation
• Often implemented in airbag systems with a 32b main MCU and an 8b
secondary MCU used to energize squib charges
33
2oo2 Processing Architecture
Sensor
Sensor
Embedded
Processor
Embedded
Processor
+
Output
Circuit
Actuator
• “Two out of Two” subsystems must fail for system to fail
• Each system can energize the output
– Used when it is undesirable for output to be de-energized
– Fault tolerant of open circuit faults in either subsystem
34
1oo1D Processing Architecture
Sensor

Safety

Embedded
Processor
Diagnostic
Circuit(s)
+
Output
Circuit
Actuator
• Expansion of 1oo1 system to include a diagnostic channel
• Diagnostic channel can inhibit system output if a failure is detected in the
functional system
• Additional failure rate potential due to failure in the diagnostic circuits
(annunciation failure)
• TI Hercules “lockstep” processor implementations are a 1oo1D system
35
2oo3 Processing Architecture
Sensor
Sensor
+
Embedded
Processor
Embedded
Processor
Output
Circuit
A
A
B
B
C
C
Voting Circuit
Sensor
Embedded
Processor
Actuator
• 2 out of 3 subsystems must fail before system fails
• Used in many fail operation/fail tolerant systems
36
2oo2D Processing Architecture
Sensor

Safety
+

Embedded
Processor
Diagnostic
Circuit(s)
Sensor

Safety


Output Circuit
Embedded
Processor
Diagnostic
Circuit(s)
Actuator
• Effectively a 2oo2 system where each channel is a 1oo1D system
• Provides a single level of fault tolerance
– Upon single channel failure the system reverts to a 1oo1D system
– Provides high fault detection rates
37
SafeTI™
38
TI’s SafeTI™ design packages for functional
safety are robust and help speed certification
Standards-specific SafeTI
solution bundles
www.ti.com/safeti
39
SafeTI™- Safety Development Process
TI follows a development flow to
TS-16949 that is internally and externally audited annually
SafeTI-61508 devices
are developed per the
IEC 61508:2010
requirements
SafeTI-26262 devices
are developed per the
ISO 26262:2011
requirements
SafeTI development process has been externally
assessed & certified
40
SafeTI™ Development Process Certification by TÜV SÜD
•
TÜV SÜD is an internationally
recognized and accredited
independent assessor of compliance
to quality, safety, and security
standards.
•
TÜV-SÜD has certified the functional
safety development process for
•
•
SafeTI-61508
•
SafeTI-26262
The certification demonstrates TI’s
commitment to have a process
suitable for developing hardware
components that are compliant to
ISO 26262 and IEC 61508
41
Hercules Safety Documents
• Documents provided by TI some under NDA to assist in the
safety certification process:
– Hercules TMS570/RM Device Safety Manual (SM)
•
Details product safety architecture and recommended usage
NDA
– Safety Analysis Report Summary (SAR1)
•
Summary of FIT rate and FMEDA at DEVICE level for IEC 61508
and ISO 26262
NDA
– Detailed Safety Analysis Report (SAR2)
•
Full details of all safety analysis executed down to MODULE level for
IEC 61508 and ISO 26262
NDA
– Safety Case Report (SCR)
•
Summary of compliance to IEC 61508 and/or ISO 26262
42
SafeTI™ Compiler Qualification Kit
•
Assists in qualifying the TI ARM C/C++
Compiler to functional safety standards
•
Model-based tool qualification methodology
developed by Validas
•
Assessed by TÜV Nord to comply with both
IEC 61508 and ISO 26262
Approved by
•
Includes:
•
Qualification Support Tool
•
Documentation:
• Tool Classification Report
• Tool Qualification Plan
• Tool Qualification Report
• Tool Safety Manual
ACE SuperTest qualification suite
TI compiler validation test cases
Test Automation Unit (TAU)
24hrs of Validas consulting services
TI ARM Compiler
•
•
•
•
IEC 61508
ISO 26262
NOTE: There is a fee for this kit. See the web site listed below for more details.
http://www.ti.com/tool/safeti_cqkit
43
The SafeTI™ Diagnostic Library: Hercules Safety MCUs
SafeTI Diagnostic Library
Initialization & startup
diagnostics
Periodic diagnostics
I/O diagnostics
Internal/external
watch dog
Exception &
Error Handler
– Initializing and Enabling Safety
diagnostics/Features prescribed
by the Hercules Safety Manual.
– Fault injection to allow testing of
application fault handling
– Error Signaling Module (ESM)
handler callback routine.
– Profiling for measuring time
spent in diagnostic test/fault
handling
Application layer
RTOS
Provides simple interfaces and a
framework for
Hardware Abstraction Layer (HALCoGen/MCAL)
10110000111000100010001110110001000011101001010101
101001010100001110110100100110010110
1000101010010100101
Integrated interface for
SafeTI™ Design Package
companion
PMIC/Watchdog
(TPS6538x)
communication
Functions map
directly to the
Hercules
Safety Manual
Power Management
TPS65381
http://www.ti.com/tool/safeti_diag_lib
44
SafeTI™ Motor Control Example
Hercules RM46x MCU
Lockstep
CPUs
Angle (SMO)
ARM®
Cortex™R4F
Angle
Check
&
Select
SPI
Resolver
eQEP
Encoder
eCAP
Hall
Sensor
Angle
PWM (x6)
Angle
Speed
Ref
PWM
Speed
Torque
PID
DRV3201 Bridge Driver
eTPWM
PWM
FOC Software Control Loop
Torque
Flux
Speed
FDBK
Speed
Estimation
Typical Flow
Phase
Currents
ADC 1
Voltage
Monitor
Bridge
Err Mon
Current
Monitor
3x
Angle
DCBus V
SMO
Angle
Estimation
Core &
I/O Voltage
Diagnose
ADC 2
DCBus V
TPS65381 Power Supply & Safety Companion
5.0V
Links to Product Web Pages:
Currents
Temp
Monitor
PWM
Reset
Safety Flow
Phase
Currents
Phase
ADC
Check
MOSFETs
High-end
Timer
PWM
Check
PWM
FDBK
Torque/Flux
Ref
Motor
Sensors
Error Mon
Error Signal
LBIST
OSC Mon
ABIST
Temp Mon
3.3V
1.2V
Watchdog
Enable
Hercules RM46x MCU
TPS65381 Power Supply & Safety Companion
DRV3201 Bridge Driver
45
Safety Designers Count on SafeTI™
TI’s 20+ years of Designing Solutions for Safety
Markets help provide:
• Embedded Processing + Analog solutions that work
together
• Functional Safety integrated in device hardware
• Tools and Software prepared for safety
• Comprehensive Safety Documentation
 Enable faster and easier customer Safety Certification
46
Hercules™ Cortex™-R4F Safety Concept
47
Rationale of the Hercules™ Safety Concept
• “Safe Island” approach
• Region of device common to all safety functions is heavily protected by
hardware diagnostic measures
– CPU
– CPU Interrupts
– System control of power, reset, clock
– OS critical IP: DMA, OS timer
• Once a known safe region can be guaranteed, logic in this region can
be used to provide diagnostic coverage on other regions
• This partition has shown to give strong safety metrics while minimizing
impact of safety on system BOM cost
48
Hercules Cortex-R4F MCU safety features
Logical / physical
design optimized to
reduce probability of
common cause
failure
Dual Core Lockstep Cycle by Cycle CPU
Fault Detection
• Safe Island Hardware diagnostics (RED)
ECC for flash / RAM /
interconnect evaluated
inside the Cortex R4F
CPU Self Test
Controller requires
little S/W overhead
Lockstep
CPUs
ARM®
Cortex™R4F
Memory
Flash
w/ ECC
• Non Safety Critical Functions (BLACK)
Power, Clock, & Safety
OSC PLL
PBIST/LBIST
RAM
w/ ECC
POR
ESM
Flash
EEPROM w/ ECC
CRC
RTI/DWWD
Calibration
CPU Fault Detection
• Blended HW diagnostics (BLUE)
Memory Interface
JTAG Debug
Embedded Trace
External Memory
Parity or CRC in
Serial and Network
Communication
Peripherals
On-Chip Clock and
Voltage Monitoring
DMA
Enhanced System Bus and Vectored Interrupt Module
Parity on all
Peripheral, DMA and
Interrupt controller
RAMS
Memory BIST on all
RAMS allows fast
memory test at
startup
Serial
Interfaces
Network
Interfaces
Dual
ADC
Cores
Available
Dual
High-end
Timers
Available
GIO
Error Signaling
Module w/ External
Error Pin
IO Loop Back, ADC
Self Test, …
Dual ADC Cores with
shared channels
49
1oo1D Dual Core Safety Concept
• Unique design to reduce common
cause failures
– Second CPU mirrored and
rotated
– Cycle delayed lockstep
– Guard ring per CPU
– Duplicated clock tree per CPU
Compare
Error
Output + Control
CCM
Cycle Delay
Self
Test
ARM®
Cortex™-R4F
• CPU Compare Module (CCM)
– Self-test capability
– Self-test error injection/error
forcing
– Output error injection
Cycle Delay
Input + Control
50
CPU Self Test Controller (STC/LBIST)
Clock
controller
ROM
ROM
interface
Clock cntrl
FSM
STC BYPASS/
ATE Interface
Test
controller
STC
PCR
ARM®
Cortex™-R4F
VBUS
Interface
DBIST
CNTRL
REG Block
&
Compare
Block
DBIST
CNTRL
ERR
ESM
•
•
•
•
Provides High Diagnostic Coverage
Significantly Lowers S/W and Runtime Overhead
No SW BIST (Built In Self Test) Code overhead in Flash
Simple to configure and start BIST via register
51
Programmable Memory BIST (PBIST)
Functional
Read/Write
Datapath
• All on-chip RAMS can be tested
VBUS I/f
• Simple register setup and
configuration
Cfg
block
Tester I/f
Ext
block
PBIST
Controller
Data
path/
ROM I/f
• Typically run at startup, but can
be executed during the
application
• Multiple Memory Test Algorithms
RAM
ROM
block
Collars
To / From
Memories
(RAM
groups)
Data
Logger
• Detects multiple failure modes
• Provides a mechanism to determine if runtime faults were caused by hard or soft error.
This capability can be used to improve availability through inline recovery from soft error.
52
Flash / RAM ECC Protection
Cortex-R4
64 Inst.
Flash
8 Stage
Pipeline
64 Data
Error
8 ECC
8 ECC
32 Data Bits
4 ECC Bits
RAM
ECC Logic
32 Data Bits
4 ECC Bits
• ECC evaluated in the Cortex R4 CPU
– Single Bit Error Correction and Double Bit Error Detection (SECDED)
– ECC evaluated in parallel to processing data/instructions
– No latency or performance impact
– Protects Busses from CPU to Flash and RAM
53
Safety Aspects of Network Interfaces
• Networked peripherals (Ethernet, FlexRay, DCAN, and SCI/LIN) are
considered grey-channel / black-channel communications
• In such communications application level protocols (time redundancy, CRC in
data packet, etc.) are necessary
54
Error Signaling Module (ESM)
ESM
Low Level Interrupt
Handling
Errors for Group 1
INTEN
To Interrupt
Manager
INTLVL
High Level Interrupt
Handling
Errors for Group 2
ERROR
SIGNAL
CONTROL
LOW TIME
COUNTER PRELOAD
nERROR pin
LOW TIME
COUNTER
Errors for Group 3
55
Clock Monitoring
• External clock prescaler (ECLK)
• Allows external monitoring of CPU clock frequency
• Configurable pin (GIO or ECLK)
• Oscillator monitor
• Detects failure if oscillator frequency exceeds defined min/max thresholds
• Selectable hardware response on oscillator fail
– Reset device
– Switch to internal ‘low power oscillator’ (LPO) clock source
• FMPLL slip detector
• Indicates PLL slip if phase lock is lost
• Selectable hardware response on PLL slip
– Reset device
– Switch to internal ‘low power oscillator’ (LPO) clock source
– Switch to external oscillator clock source
LPO
Input from
Oscillator
CLK Signal to
CLK Control Module
FMPLL
Bypass on Slip
Slip
Detector
BPOS
Reset on Slip
BPOS
ROS
To Device Reset
56
Dual Clock Comparator (DCC)
• The DCC module is used to measure the frequency of a clock signal
using a second clock signal as a reference.
• Allows application to ensure that a fixed frequency ratio is maintained
between two clock signals
• Supports the definition of a programmable tolerance window in terms of
number of reference clock cycles
• Supports continuous monitoring without requiring application intervention
• Alternatively can be used in a single-sequence mode for spot measurements
• Flexible clock source selection for Counter 0 and Counter 1 resulting in
several specific use cases
0
Preload 0
Clock 0
Counter 0
Clock 0 Sources
Clock 0 Select
Preload 1
Clock 1 Sources
Clock 1
0
Valid Preload 0
=
Valid Counter 0
=
Clock
Compare
ERROR
Counter 1
Clock 1 Select
PLLMUL
57
Digital Windowed Watch Dog (DWWD)
• The DWWD module will reset the MCU or generate a non maskable interrupt to
the CPU if the application fails to service the watchdog to within the appropriate
time window.
•
•
•
•
•
•
Optional safety diagnostic that can detect a runaway CPU
Includes a 25-bit down counter
Alerts the Error Signaling Module when a CPU interrupt is generated
Supports multiple service windows: 100%, 50%, 25%, 12.5%, 3.125%
Servicing requires a specific two part key sequence
Once enabled can only be disabled by a system or power on reset
Down
Counter
0
DWWD Preload
100%
Window
50%
Window
25%
Window
Window Open
Window Open
Window Open
Down Counter
Window Open
W Open
W Open
12.5%
Window
Open
Open
6.25%
Window
O
O
3.125%
Window
=
O
RESET
Digital
Windowed INTERRUPT
Watch
ESM
Dog
O
•PLLMUL
58
Memory Protection Unit (MPU)
• A Dedicated Memory Protection Unit (MPU) is implemented for select bus masters
Lockstep ®
ARM
CPUs
™- ®
ARM
Cortex
Cortex™R4F
160MHz
® R4F
ARM
Cortex™160MHz
R4F
CPU Fault
Detection
Memory
Power, Clock, & Safety
Flash w/ ECC
OSC PLL
POR
RAM w/ ECC
PBIST
CRC
Memory Protection
LBIST
RTI
Calibration
Memory Interface
EMIF
Embedded Trace
Enhanced System Bus and Vectored Interrupt Management
MibSPI
128 Buffers; 4 CS
Network I/F
FlexRay
2 ch FlexRay
Transfer
Unit
8K Message RAM
(FTU)
CAN1 (64mb)
MibSPI
128 Buffers; 4 CS
MibSPIP
128 Buffers; 4 CS
• A memory region is defined which
allows read and write access for
the bus master
JTAG Debug
DMA
DMA
Serial I/F
• Bus masters include the CPU,
DMA, HTU and the FTU
ADC
Timers / IO
MibADC1
High End
High
End
Timer
Timer
(NHET)
Transfer
Unit
128 words,
32 ch
(HTU)
64 Buffers
12-bit, 16ch
(8ch shared)
CAN2 (64mb)
CAN3 (32mb)
MibADC2
UART1 (LIN1)
64 Buffers
12-bit, 16ch
(8ch shared)
UART2 (LIN2)
GIOA/INTA (8)
GIOB (8)
• Access outside the defined region
can be any of the mode
• Read Only: Read access allowed for
the memory accesses outside the
region. Write accesses are blocked
• No Access: Read and write access is
blocked.
• In the event of a memory
protection violation an error is
indicated
59
Dual Analog to Digital Converters
• Dual12-bit ADC Cores:
Self-Test & Calibration
-
-
-
Up to 16 analog channels can be
shared between the 2 cores for safety
critical conversions/comparison
Internal ADC reference voltages can be
used to check converter functionality.
AD1IN[7..0]
MibADC1
AD1IN[23..8] /
AD2IN[15..0]
VccAD
VssAD
VrefHi
VrefLo
Self Test Mode enables in application
detection of opens/shorts on ADC
inputs
ADC calibration logic can improve
accuracy or be used to detect drift
between multiple test results.
MibADC2
AD2EVT
To Peripheral Bus
-
MibADC 1 supports dedicated analog
inputs & shared inputs with MibADC 2
To Peripheral Bus
AD1EVT
Self-Test & Calibration
Note: Not all Hercules MCUs are available with dual ADCs
60
Voltage Monitor
• Supply Voltage Monitor (VMON)
– Holds reset until core and I/O rails in expected range (removes power
sequencing requirements)
– Asserts reset if core or I/O supply exceeds defined min/max
thresholds
– Asserts reset when core supply is below specified min voltage and
asynchronously sets all I/O pins to high impedance mode
+
-

61
Exida Has Certified TMS570LS20216S
IEC 61508 SIL 3 Capable
•
Future Hercules TMS570 and RM
products are planned to be assessed
by Exida and/or TÜV-SÜD
•
To get a Safety Certificate, Hercules
MCUs are assessed for:
•
–
Development Process
–
Product Safety Architecture/Concept
–
Silicon
TI has chosen to work with TÜV-SÜD
(DAkkS accredited) and Exida (ANSI
accredited) for both IEC 61508:2010
and ISO 26262:2011
62
Hercules Safety MCUs Provides Developers
TM
Hercules MCUs
provide developers
of safety-critical
applications:
Hardware Safety Architecture
• Lockstep CPUs
• CPU & RAM Built-in Self Test
• Flash & RAM ECC
• Clock Monitoring
• Voltage Monitoring
Protection against random and systematic failures
Headroom for application differentiation
Simplified development and system certification
Application Headroom
Safety Certification & Documentation
Over 350 DMIPs of
processing power
63
Hercules™ MCU Development Tools
64
Hercules™ IDEs, Compilers and RTOS Support
IDEs & Compilers
RTOS Support
• TI Code Composer Studio – compiler
qualification kit
•
• Embedded Workbench for ARM is
certified by TÜV SÜD as suitable for
use to IEC 61508 and ISO 26262
FreeRTOS: FreeRTOS.org
Portable, open source, royalty free, mini
Real Time Kernel.
•
SafeRTOS: High Integrity Systems
Design assurance package for IEC61508,
others
•
µC/OS: Micrium
Certifiable design package for IEC61508,
others
•
SCIOPTA: SCIOPTA RTOS
Kernel certified by TUV for IEC 61508
and EN50128 Hercules to SIL-3
• CoDeSys programming system and
runtime system for IEC 61131-3
programmable logic controllers
•
CODESYS: Smart Software Solutions
Control and safety runtime system for
Industrial PLCs
• TargetLink code generation from
MathWorks Simulink/Stateflow,
certified for IEC 61508
• SMXRTOS: Micro Digital
Modular RTOS that meets the needs of
small to medium-size embedded systems
• Processor-In-the-Loop (PIL) with
MathWorks Simulink
• AUTOSAR OS/RTE:
- Vector MICROSAR Safe
- ElektroBit tresos
- ETAS RTA-OS & RTA-RTE
- TI MCAL available for AUTOSAR v4.0.3
• MDK-ARM with uVision IDE and ARM
C/C++ Compilation Tools
• MULTI IDE and Green Hills Compiler
certified to ISO 26262 and IEC 61608
• Tantino-Cortex-R4 with professional
HiTOP Debugger/IDE
• HET IDE with Synapticad
WaveViewer or WaveFormer Pro
65
Hercules™ MCU Software Tools
Demos, Libraries & Example Code
MiddleWare
• MISRA-compliant embedded TCP/IP stack
that supports both IPv4 and IPv6 protocols.
• USB Host & Device, File systems, etc…
Safety MCU Demos
• Safety Feature Highlight
• Ambient Light & Temperature Demo
• LED Light Show
• Maze Game
• Source Code Viewable via CCS
HALCoGen
•
•
•
•
•
User Input on High Abstraction Level
Graphical-based code generation
Easy configuration
Quick start for new projects
Supports CCS, IAR, KEIL & GHS
IDEs
Motor Software
• InstaSPIN-BLDC MotorWare™ Project
• Sensored FOC with redundant SMO
MotorWare™ Project
Libraries
• DSP & Math Library: Optimized for
ARM® Cortex-R4 & CMSIS Compliant
• SafeTI™ Diagnostic Library:
Executable form of the safety manual
• MISRA-compliant CANopen real-time
protocol and device driver used in medical
automation and automotive equipment.
lwIP
• Ethernet Driver and light weight IP Stack
USB
• USB Device Driver & CDC Class
• Many MiddleWare options available from
RTOS providers
Flash Programming
Automated offline Programmers:
• Data I/O
• BP Micro Systems
In Circuit JTAG Programmers:
• SMH Technologies
• Checksum
• XJTAG
• CCS UniFlash
Example Code
• Hercules Code Repository WIKI
66
Code Composer Studio
• Based on Eclipse industry standard
for embedded debug tools
–
–
–
–
–
–
Modern window environment
Advanced source code editor
Scalable multi-core/processor environment
Program and Debug Application via JTAG
Test Automation via Scripting
Available for Windows & Linux
• Support across TI’s Embedded
Processing Portfolio
–
–
–
–
–
MSP430
Stellaris/Tiva
C2000
Hercules
C5000 & C6000 DSP
• Hercules™ Debug Features
– 6 Hardware Breakpoints
– Unlimited Software Breakpoints
– Integrated Flash Programming
CCS Licensing Options
–
–
–
–
Evaluation: Free, time limited licences for evaluation
Node Locked: Tied to a specific computer
Floating: Can be shared across multiple
Free/Dev Kit: Can be used with Hercules kits w/ XDS100 emulators
http://www.ti.com/tool/ccstudio
67
Code Composer Studio Components:
Menus and Icons
Help
Watch
Window
Target Connection
 Source & object files
 File dependencies
 Compiler, assembler
& linker build
options
Source Code View
Disassembly
Window
CPU
Window
Memory
Window
68
HALCoGen: Hardware Abstraction Layer Code Generator
Features
•
User Input on High Abstraction Level
• Graphical-based code generation
• Easy configuration
• Quick start for new projects
•
Generates C Source Code
• ANSI Conforming
• Clear, structured, coding style
• Customizable code for user maintenance
•
Supported Drivers
• System Modules
• Safety Init, MPU, PMU, PMM, PCR
• LBIST, PBIST, VIM, ESM, CRC
• EMIF, POM, DMA, PINMUX
• Peripheral Modules
• RTI, GIO, ADC
• SCI/LIN, CAN, MIBSPI / SPI, I2C
• USB, Ethernet
• Timer Co-processor (NHET)
• eCAP, eQEP, ePWM
•
Interactive Help System
•
•
•
•
•
Describes tool features and functions
Provides detailed dependency graphs
Provides useful example code
Tool tip help available
Native support for CCS, KEIL, IAR
and GHS IDEs
69
NHET Timer Co-Processor Development Tools
Algorithm
Library
Drag & Drop
Instructions
Waveform
View
NHET ASM
Code
Pin
Selection
NHET
Registers
• Graphical Programming Environment
• Output Simulation Tool
• Generates CCS-ready software modules
• Includes functional examples from TI
• Graphical Waveform Viewer
• Input Generation Tool
• Seamless interface to coding tool
• Upgradable to Full SynaptiCAD
70
TM
Hercules Development Kit Overview
SafeTI™-HSK
Motor Control Kit
Spin 3 phase Brushless DC and
Brushless AC Motors
Starting at $499
Evaluate Hercules MCU and
TPS65381 Combination for Safetycritical Applications
TMS570LS31, LS12
$499
RM48, RM46
controlCARD
TMS570LS31
RM48
HDK
Initial Software Development and
Short-run Builds for System
Prototypes
Starting at $99
Get Started on Development with
Hercules MCU Platform
TMS570LS31,
LS12
RM48, RM46
USB Stick
$199
LS31, LS12, LS04
RM48, RM46, RM42
LaunchPad
Low-cost Option to Evaluate
Hercules MCU Platform
$79
Lowest cost Option to Evaluate
Hercules MCU Platform
TMS570LS31
RM48
$19.99
TMS570LS04
71
RM42
71
TM
Development
Evaluation
Hercules Development Kits
TMDXRM48USB – RM48 USB Stick Kit
TMDX570LS31USB – TMS570 USB Stick Kit
TMDX470MF066USB – TMS470M USB Stick Kit
•
•
•
•
•
•
•
$79
USB Powered
On Board USB XDS100v2 JTAG Debug
On Board SCI to PC Serial Communication
Access to Select Signal Pin Test Points
LEDs, Temp Sensor & Light Sensor
Accelerometer
CAN transceiver
TMDXRM48HDK – RM48 Development Kit
TMDXRM46HDK – RM46 Development Kit
TMDXRM42HDK – RM42 Development Kit
TMDX570LS31HDK – TMS570 Development Kit
TMDX470MF066HDK – TMS470M Development Kit
• On Board USB XDS100v2 JTAG Debug
• External high speed emulation via JTAG
• CAN Tranceivers
• LEDs, Temp Sensor & Light Sensor
$199
• TRACE pads for ETM/RTP/DMM (TMS570 & RM48)
• RJ45 10/100 ENET (TMS570 & RM48 & RM46)
• USB-A Host Interface (RM48 & RM46)
• USB-B Device Interface (RM48 & RM46)
Software Included in Each Kit:
• CCStudio IDE: C/C++ Compiler/Linker/Debugger
• HALCoGen Peripheral Driver Generation Tool
• CCS and nowFlash Flash Programming Tools
• HET IDE: Simulator & Assembler
• GUI Demo with Project/Code Examples
72
Hercules™ LaunchPad
LaunchPad Demos
LAUNCHXL-RM42
• LAUNCHXL-TMS57004
•
BoosterPack XL Interface
On Board JTAG (XDS100v2)
Kit Overview
GIO Push Button
Hercules™ Safety MCU
•
USB powered
•
On board USB XDS100v2 JTAG debug
•
On board SCI to PC serial communication
•
GIO & NHET LEDs
•
Ambient Light sensor
•
40 pin BoosterPack XL Header
•
Footprint for an Expansion header (not
populated) to bring out all MCU Pins
Ambient Light Sensor
$19.99
•
USB Cable
•
Quick Start Guide
73
TM
Hercules Motor Control Development Kits
•
•
•
•
DRV8301-RM48-KIT
DRV8301-RM46-KIT
DRV8301-TMS570LS31-KIT
DRV8301-TMS570LS21-KIT
Demo Software
Teknic 7 Amp, 6000 RPM Motor
with encoder and hall sensors
Hercules Safety MCU
ControlCard
Software Included In the Kit
Starting at
$499
DRV 8301 60V, 60A EVM with
self protection and
programmable gain amplifiers
• InstaSPIN-BLDC MotorWare™ Project
• Sensored FOC with redundant SMO
MotorWare™ Project
• Demonstration Examples
• Code Composer Studio IDE
• ARM Cortex-R4 CMSIS DSP Library
• HALCoGen Driver Generation Tool
• High End Timer IDE
74
SafeTI™ Hitex Safety Kit
Hitex Safety Kit Software
• SAFETI-HSK-RM48
• SAFETI-HSK-570LS31
TPS65381 Power Supply &
Safety Monitor
On Board Display
Kit Overview
ControlCard Interface
Hercules™ Safety MCU
$499
• Cost effective entry into functional safety
related to ISO26262 and IEC61508
• Evaluation board supporting all safety
features according to the safety manual
• Error injection and reaction monitoring by
second µC connected to GUI
• Full source code available for modification
of the application or including the library in
your own application
• Evaluation version of compiler and
debugger included
• Evaluation version of SafeRTOS included
• User friendly documentation
•
•
http://www.hitex.com/safeti
75
Hercules™ LaunchPad
$19.99
USB XDS100v2 JTAG
SCI to USB
• Main Features
– USB Powered
– On Board USB XDS100v2 JTAG Debug
– On Board SCI to PC Serial Communication
– BoosterPack XL Interface
– Access to Select Signal Pin Test Points
– GIO Push Button
– 1 White GIO LED
– 1 White NHET LED
– 1 Red nERROR LED
– Ambient Light Sensor
– 100p QFP Packaged MPU
• $19.99 USD
– TMS570 Orderable Part #
• LAUNCHXL-TMS57004
– RM42 Orderable Part #
• LAUNCHXL-RM42
JTAG LED
SCI TX LED
SCI RX LED
Power LEDs
PORRST
Button
Peripheral
Pin Access
RST
Button
GIO Push
Button
BoosterPack
XL Interface
BoosterPack
XL Interface
100p Hercules
QFP MCU
Light
Sensor
NHET LED
GIO LED
76
Microcontroller USB Stick Kit
USB XDS100v2 JTAG
SCI to USB
• Main Features
– USB Powered
– On Board USB XDS100v2 JTAG Debug
– On Board SCI to PC Serial Communication
– Access to Select Signal Pin Test Points
– 6 White NHET LEDs
– 2 RGB Tri Color NHET LEDs
– Temp Sensor, Light Sensor and Accelerometer
– CAN Communication transceiver
– 337p BGA Packaged MCU
Power LED
Error LED
$79
JTAG LED
SCI TX LED
SCI RX LED
PORRST
Button
RST
Button
Peripheral Pin
Access
White LEDs
NHET1 [17, 31, 0]
337p Hercules
BGA MCU
• $79 USD
Tri-Color LED
– TMS570 Orderable Part # TMDX570LS31USB NHET1 [16, 27, 04]
– RM48 Orderable Part # TMDXRM48USB
– Code Composer Studio IDE included
Peripheral Pin
Tri-Color LED
NHET1 [20, 05, 02]
White LEDs
NHET1 [25, 18, 29]
Access
Light
Sensor
Temp
Sensor
CAN Interface
77
Hercules™ Development Kit (HDK)
USB mini-B: XDS100v2 JTAG
SCI to USB
Micro SD Card Slot
• Main Features
– On Board USB XDS100v2 JTAG Debug
– External High Speed JTAG Connector
– On Board SCI to PC Serial Communication
PORRST Button
– Access Signal Pin Test Points
RST Button
– Board Expansion Connectors
20 pin
– 6 White NHET LEDs
JTAG
– 2 RGB Tri Color NHET LEDs
– Temp Sensor and Light Sensor
– Micro SD Card Slot (SPI mode)
– RJ45 10/100 Ethernet Interface
337p (BGA)
Hercules MCU
– USB-B Device Interface (RM48 & RM46 Only)
– USB-A Host Interface (RM48 & RM46 Only)
– 2 CAN Communication Transceivers
– 337p BGA Packaged MCU
$199
USB – A
Host
USB – B
Device
RM48 Only
RJ-45
RM48 Only
+5 - 12V
DC Power Input
• $199 USD
–
–
–
–
TMS570LS31 Orderable Part # TMDX570LS31HDK
TMS570LS12 Orderable Part # TMDX570LS12HDK
RM48 Orderable Part # TMDXRM48HDK
RM46 Orderable Part # TMDXRM46HDK
Options
Switch
CAN1
Light
Sensor
Temp
Sensor
CAN2
GIO Push Button
78
Printed Circuit Board Design
Considerations
79
MCU Package Selection – 100p (PZ) QFP
Typical Package Information:
• Package Size = 14x14 mm
• 16 x16 mm including leads
• 25 pins on each side
• 0.5 mm pin pitch
80
MCU Package Selection – 144p (PGE) QFP
Typical Package Information:
• Package Size = 20 x 20 mm
• 22 x 22 mm including leads
• 36 pins on each side
• 0.5 mm pin pitch
81
MCU Package Selection – 337p (ZWT) BGA
Typical Package Information:
• Package Size = 16 x 16 mm
• 337 ball grid array
• 0.8 mm ball pitch
82
MCU Crystal Selection – TMS570 & RM48
5 MHz to 20MHz
TI strongly encourages each customer to
submit samples of the device to the
resonator/crystal vendors for validation. The
vendors are equipped to determine what load
capacitors
will
best
tune
their
resonator/crystal to the microcontroller
device for optimum start-up and operation
over temperature/voltage extremes.
Typical Crystal Connections:
• OSCIN & OSCOUT pins
• BGA Packages: Kelvin GND
• Frequency Range: 5 to 25MHz
83
External JTAG Headers
20 Pin CTI
14 Pin TI
60 Pin MIPI
20 Pin ARM
84
External XDS JTAG Emulators
XDS200
XDS100v2
• Entry level JTAG emulator
• USB interface
• 3 models based on JTAG headers (14pin TI, 20pin TI,
20/10pin ARM)
• Free CCS XDS100v2 license available
• $79
• Excellent balance of performance and cost
• USB interface (Ethernet version available)
• 20pin TI, 14pin TI, 20pin ARM and 10pin ARM
connectors
• $295
XDS560v2
• High performance JTAG emulator
• USB or USB + Ethernet interfaces
• Includes multiple JTAG adapters (14pin TI, 20pin TI,
20pin ARM, 60pin MIPI, some include 60pin TI)
• System Trace
• $995 - $1495
Pro Trace
•
•
•
•
•
•
Trace Receiver & XDS560v2 JTAG emulator
USB + Ethernet interfaces
MIPI60 and 60pin TI adapters
DSP & ARM Trace to pins
System Trace
$3495
85
Power Supply Requirements
VIN
Hercules MCU:
Power I/C
TMS570LS31x/21x/12x/04x and RM48x/46x/42x
VCCP
3.3V
VCCIO
3.3V
ADREFHI
VCCAD
VCC
VCCPLL
3.3V
1.2V
3.3V
3.3V
1.2V
1.2V
VSS
ADREFLO
VSSAD
master reset
(SYSESR.PORRST=1)
device reset
GND
nPORRST
nRST
system reset (bi-directional).
If not connected, an external
PU is recommend
- Reset logic
- Supply voltage supervisor
DWWD,
sw reset,
osc fault
86
Power Supply Requirements
VIN
Hercules MCU:
Power I/C
TMS570LS31x/21x/12x/11x & RM48x/46x
ADREFHI
5.0V
5.0V
VCCAD
5.0V
VCCP
3.3V
VCCIO
3.3V
VCC
VCCPLL
3.3V
1.2V
1.2V
1.2V
VSS
ADREFLO
VSSAD
master reset
(SYSESR.PORRST=1)
device reset
GND
nPORRST
nRST
system reset (bi-directional).
If not connected, an external
PU is recommend
- Reset logic
- Supply voltage supervisor
DWWD,
sw reset,
osc fault
87
Hercules & TPS65381 Safety Companion IC
VIN
(5.8V – 36V)
Hercules MCU:
TPS65381
TMS570LS31x/21x/12x/11x & RM48x/46x
ADREFHI
VCCAD
VCCP
VCCIO
5.0V
CAN
5.0V
5.0V
3.3V
3.3V
1.2V
3.3V
LBIST
VCC
VCCPLL
1.2V
ABIST
1.2V
VSS
OSC MON
ADREFLO
GND
Over Temp
MON
VSSAD
master reset
(SYSESR.PORRST=1)
nPORRST
Reset Logic
Watchdog
CS
SOMI
SPI
SIMO
SPICLK
nERROR
Note: Some Hercules MCU ADCs are only 3.3V capable
MCU
Error Monitor
Package: 32-Pin HTSSOP PowerPAD™
For more information about the TPS65381 go to : http://www.ti.com/product/tps65381-q1
88
ADC Decoupling Capacitors
TMS570LSx or RM4x MCU
ADREFHI
ADREFLO
VCCAD
VSSAD
To 3.3V Power Supply
100nF
Via to Ground Plane
To 3.3V Power Supply
100nF
Via to Ground Plane
89
Exercise: Hercules Safety MCU Demos
90
Lab1: Hercules™ Safety MCU Demos
• To launch the demo software go to:
•
→ Programs → Texas Instruments → Hercules → Hercules Safety
MCU Demos
91
Hercules Cortex™-R4F Architecture Overview:
Memory Map, Clocking, Exceptions
92
High Performance Cortex-R4F floating-point CPU
ARM ® v7R CortexTM ISA
fully backward Compatible
to ARM7/9/11
Lockstep CPUs:
Single core programming
model – second core
checks the first.
Supports ARM, Thumb
and Thumb-2 instructions
Up to 220 MHz CPU
Clock Speed
Fast MULT, DIV, and
SQRT enables modelbased control; simplifies
algorithm
implementation
Single / double
precision IEEE 754
floating-point
ARM®
Cortex™-R4F
Up to 220 MHz
Floating point and
integer instructions
operate in parallel
Superscalar, SIMD,
8 stage pipeline delivers
1.6 DMIPS/MHz
12 region memory
protection
Broad IDE/Compiler Support:
CCS, KIEL, IAR, GHS, etc…
• Over 350 DMIPS of performance
• High performance floating point
• ARM-based: broad industry adoption
Scalable ARM Based
Solutions from TI:
Stellaris®, Concerto™
Hercules™& Sitara™
93
Cortex-R4F Features
• 32-bit ARM and 16/32-bit Thumb2 instruction set
• Integer unit with integral Embedded ICE-RT logic
• Dynamic branch prediction with a global history buffer and return stack
• Floating Point Unit
• Low interrupt latency
• Non-maskable interrupt
• Harvard level one memory system with:
– Tightly-Coupled Memories (TCM) interfaces with support for error correction or
parity checking memories
– Memory Protection Unit (MPU)
• Level two memory interface:
– Single 64-bit master interface
– 64-bit slave interface, TCM RAM blocks and cache RAM blocks.
• Debug interface to a CoreSight® ETM-R4® or CoreSight DAP
94
Cortex-R4F Pipeline
AGU
(Address
Generation
Unit)
64
bit
Fetch
1st
Stage
Fetch
2nd
Stage
Instruction
formatting
/ Branch
prediction
Prefetches if
branches/returns
predicted to be
taken
Instruction
decode
Register
read and
Instruction
issue
Data
Cache
access
1st
Stage
Data
Cache
access
2nd
Stage
Shift
ALU
Write
Back
MAC
1st
Stage
MAC
2nd
Stage
MAC 3rd
Stage
Branch
1st
Stage
Branch
2nd
Stage
Branch
3rd
Stage
FP
Register
read
FP
1st
Stage
FP
2nd
Stage
Data
Formatting
Round
&
WriteBack
Floating Point
95
Data Types
• The processor supports following data types
– Double Word (64 bit)
– Word (32 bit)
– Half Word (16 bit)
– Byte (8 bit)
• Although the processor supports unaligned accesses, TI does not
recommend using unaligned accesses for bus performance
– Above data types should be aligned at their respective size boundary
– Most unaligned accesses are converted into multiple aligned accesses
• The TMS570 devices store their data in word invariant big endian
format (BE32) due to a modification in the memory interface
• The RM4 devices store their data in little endian format (LE)
96
Memory Map
TMS570LS31x and RM48x
• Flash starts at 0x00000000 and CPU
RAM starts at 0x08000000 by default
• Flash is mirrored outside of CPU TCM
space for ECC diagnostics
• Code execution is only allowed from
Flash, RAM and external asynch memory
by default
• System and peripheral control registers’
space is defined to be “strongly-ordered”
by default
• CPU accesses to “Reserved” areas
results in an Abort exception
• Behavior on accesses to reserved
locations within defined frames specified
in datasheet
97
Clock Sources and Domains: TMS570LS31x/21x
Clock Source #
OSCIN
0
/1..64
X92..184
/1..8
/1..32
GCLK1 & GCLK2 (to CPUs)
1
HCLK (to System Bus)
3
External Clock 1
Low Power
Oscillator
/1..64
X92..184
80 KHz
4
10 MHz
5
/1..8
/1..32
0
1
4
5
6
7
• Global Clock Module (GCM) manages all
clock sources and domains
• Flexible mapping of clock sources and
domains
• Unused clock sources and domains can be
disabled to save power
• Asynchronous clock domains used for
communication interfaces with strict tolerance
limits, e.g. CAN, EMAC, FlexRay
VCLK (to Peripheral Bus)
/1..16
VCLK2 (to NHET/HTU)
/1..16
VCLK3 (to EMIF/ENET)
6
7
External Clock 2
/1..16
/1,2,4, or 8
RTI1CLK (to RTI & DWWD)
VCLK
0
1
3
4
5
6
7
VCLK
VCLKA1 (to DCANx)
0
1
3
4
5
6
7
VCLK
VCLKA2 (to FlexRay/FTU)
98
Clock Sources and Domains: RM48x/RM46x
Clock Source #
OSCIN
0
/1..64
X92..184
/1..8
GCLK1 & GCLK2 (to CPUs)
1
/1..32
HCLK (to System Bus)
3
External Clock 1
Low Power
Oscillator
/1..64
X92..184
80 KHz
4
10 MHz
5
/1..8
7
External Clock 2
0
1
4
5
6
7
• Global Clock Module (GCM) manages all
clock sources and domains
• Flexible mapping of clock sources and
domains
• Asynchronous clock domains used for
communication interfaces with strict tolerance
limits, e.g. CAN, EMAC, USB
VCLK (to Peripheral Bus)
/1..16
VCLK2 (to NHET/HTU)
/1..16
VCLK3 (to EMIF/ENET)
6
/1..32
• Unused clock sources and domains can be
disabled to save power
/1..16
/1,2,4, or 8
RTI1CLK (to RTI & DWWD)
VCLK
0
1
3
4
5
6
7
VCLK
VCLKA1
(to DCANx)
0
1
3
4
5
6
7
VCLK
VCLKA3 (to USB)
DIVR
VCLKA3_DIVR
(to USB HOST)
99
Phase-Locked-Loops (PLL1 and PLL2)
OSCIN, fOSCIN
NR
ODPLL
R
/1..8
/1..32
PLL1CLK, fPLL1
PLL1
/1..64
ODPLL
REFCLKDIV
PLLCTL2
PLLDIV
NF
/1..256
PLLMUL
NR2
PLLCTL1
ODPLL2
R2
/1..8
/1..32
PLL2CLK, fPLL2
PLL2
/1..64
ODPLL
REFCLKDIV
PLLCTL3
PLLDIV
NF2
/1..256
PLLMUL
•
•
•
•
PLLCTL3
PLL1 is configured using PLLCTL1 and PLLCTL2 registers
PLL2 is configured using PLLCTL3 register
TRM describes procedure for configuring frequency modulation settings for PLL1
Frequency modulation not available for PLL2
100
Reset Sources
• Power-on Reset
– Asserted by external voltage supervisor, or by internal voltage monitor
• Oscillator fail
– Asserted by internal clock monitor when enabled by software
• CPU Reset
– Asserted by CPU self-test controller after LBIST operation completes
• Software Reset
– Asserted by software writing to the exception control register
• External Reset
– Asserted by external circuitry driving the warm reset (nRST) signal LOW
• Debug Reset
– Asserted by ICEPICK JTAG module
101
Hercules™: Flash Tools
102
nowECC
<return_value> nowECC [options] -i <input_file> [-o <output_file>]
• Generates ECC data for program flash
• Command-line executable
• Return value = 0 indicates no error during operation
– Separate error codes to differentiate each type of error
• Input_file is only required parameter
– Can be Extended Tektronix, Intel Hex, Motorola-S, COFF or ELF format
• Output_file specifies the name of the output file to be generated
– If no name is specified, ECC is appended to input file specified
103
Options for Flash Programming
• On-board programming using Code Composer Studio v5.x/CCS UniFlash
– Requires JTAG connection
– Emulators Supported:
• Blackhawk BHUSB560M
• Spectrum Digital XDS200, XDS510USB, XDS560RUSB
• Signum JTAGjet
• Texas Instruments XDS100v2, XDS560
• On-board programming via customer boot-loader code
– Must use Texas Instruments released API routines
– Multiple communication interfaces can be used
– Necessary to validate program and erase routines
• Off-board programming
– Single-device or Concurrent programming
– Supports high degree of automation
104
UniFlash Flash Programming Tool
•
•
•
•
PC-based software tool
Communicates with microcontroller via JTAG
Can be used to program and erase flash memory
Based on Eclipse – Supports Windows and Linux
UniFlash WIKI
105
Flash Application Programming Interface (API)
• Distributed only as an object library file
• Supports flash operations out of on-chip RAM
• Supports operations at max specified device clock frequency
• Library routines for
– Blank check
– Compaction
– Erase
– Program zeros
– Program data
– Calculate checksum
– Verify
• Routines also manage ECC
106
Real-Time Interrupt Module (RTI)
107
RTI: Counter Block Diagram
RTI Counter Features:
•
Two independent counter blocks for generating different time
bases
•
Each block consists of
– One 32-bit prescale counter
– One 32-bit free-running counter
– Two capture registers for capturing the prescale and
free-running counters
•
External event can be used for incrementing free-running
counter 0
– Can be used for synchronizing with FlexRay bus
communication cycle or external system clock input
Compare
Up Counter
RTICLK
Up Counter
=
Free Running
Counter
NTU0: Fray Macro Tick
To Compare Unit
NTU1: Fray Start of Cyc
NTU2: PLL2
NTU3: EXTCLKIN1
Capture Up
Counter
Capture Event Source 1
Capture Event Source 2
Capture Free
Running Counter
External
Control
NOTE: Counter Block 1 does not contain external NTU inputs
108
RTI: Compare Block Diagram
RTI Compare Features:
• Four compare interrupts and DMA requests
– Each can use either of the two available free-running counters
– Automatic update of compare values to minimize CPU intervention
– Option to generate DMA request as well as the compare interrupt
• Two counter-overflow interrupts
– Generated when a free-running counter overflows and goes to zero
Update Compare
+
DMA Enable
Compare
DMA Req
Counter Block 0
Counter Block 1
=
INT Req
Interrupt Enable
109
Vectored Interrupt Manager (VIM)
110
VIM: Block Diagram
VIM RAM
C H A N N E L
FIQ
Phantom Interrupt
IRQ
Address ISR0
P
e
r
i
p
h
e
r
a
l
Address ISR1
B
u
s
D E C O D E R
M A P P I N G
INT94
P R I O R I T Y
INT0
I
n
t
e
r
f
a
c
e
Address ISR93
Address ISR94
IRQVECTADDR [31:0]
REGISTERS
IRQACK
}
Vector Interrupt
Interface
from CPU
VBUS P
111
VIM: Connection Block Diagram
Peripherals – Interrupt Requests
ESM
ADC
SCI
SPI
DCAN
VIM
Special Interrupts
CPU Interrupts
NHET
– Interrupt Enable
– Interrupt Priority
– Interrupt Mapping
– Interrupt Generation
VBUSP
RTI
GCM
CPU
VIC PORT
112
VIM: Main Features
• VIM Hardware
– Dedicated Vector Interrupt interface to ARM CPU
– Hardware relocation of the IRQ vector address
– Hardware assistance for prioritizing and controlling interrupt sources
• VIM Functions
–
–
–
–
–
96 interrupt requests
Map interrupt request to interrupt channel via programming.
Provides programmable priority through interrupt request mapping
Prioritizes the interrupt channels to the CPU
Provides the CPU with the address of the interrupt service routine (ISR)
• VIM Modes
– Legacy ARM7 Mode (FIQ/IRQ)
– Vectored interrupt (FIQ/IRQ)
– Hardware vectored interrupt (IRQ only)
113
Direct Memory Access (DMA)
114
DMA: Main Features
• 32 channels with individual
enable
• 64 DMA requests
– Software and hardware
DMA requests (event
synchronization)
• Supports 8, 16, 32 or 64 bit
transactions
• Multiple addressing modes for
source/destination
– fixed, incrementing,
indexed
• Channel chaining capability
• 1 FIFO (First In First Out)
• One AHB master port (64 bit
wide) to interface with the bus
matrix
• One slave port to interface with
VBUS for register interface
• Memory Protection for the
address range DMA can access
• Auto Initiation
Note: Not all Hercules MCUs are available with a DMA
115
DMA: How to Start a Transfer?
• Software requests
– By setting bit x in SWCHENAS [31:0] register transfer (channel x) will
be triggered.
• Hardware requests
– An active DMA request signal will trigger a DMA transaction.
– Up to 64 DMAREQ lines can be handled.
– Since DMA controller is clocked by HCLK, the duration of all DMA
requests signals must be at least HCLK long.
• Triggered by other control packet
– When a control packet finishes the programmed number of transfers
it can trigger another channel to initiate its transfers.
116
DMA: Channel Interrupts
• Each channel can be configured to generate interrupts
on several transfer conditions:
– FTC (Frame Transfer Complete) interrupt
– LFS (Last Frame Transfer Started) interrupt
– HBC (First Half of Block Complete) interrupt
– BTC (Block Transfer Complete) interrupt
– BER (Bus Error) interrupt
117
Memory Protection
0xFFFFFFFF
Region 3
System + Peripherals
Region 2
3
0xFFF78000
0x08003FFF
Region 1
RAM
0x08000000
Region 0
No access restriction
Access restriction apply
0x00000000
118
General-Purpose I/O (GPIO)
119
GIO Main Features
• Two ports (GIOA/B), each with 8 bidirectional and bit-programmable I/O pins
• External interrupt capability
– Programmable interrupt detection on single or both edges
– Programmable edge detection polarity
– Programmable interrupt priority
• Possible pin configurations:
Data direction
Data input/output
Data set/clear
Open drain
Pull-up/Pull-down
GIOA[7:0] / INT[7:0]
GIOA
GIOB[7:0] / INT[7:0]
GIOB
External
Interrupt Block
VBUSP (Peripheral Bus)
–
–
–
–
–
VIM
120
GIO Block Diagram
GIOPSL
GIOPULDIS
GIODIRx
External
pin
OPEN
DRAIN
LOGIC
GATES
GIOPDRx
GIODSETx
GIODCLRx
GIODINx
Falling edge
Interrupt disable
Rising edge
Interrupt enable
Low priority
High priority
GIOPOL
GIOINTDET
GIOFLG
GIOENASET
GIOLVLSET
GIOENACLR
GIOLVLCLR
Low-levelinterrupt
handling
To
VIM
High-levelinterrupt
handling
To
VIM
Peripheral Bus / VBUS
GIODOUTx
121
GIO Cell Configuration
GIOPSL[x]
GIOPULDIS[x]
Pull-up
3-state Output Buffer
GIOPDR[x]
GIODOUT[x]
GIO pin
GIODIR[x]
GIODIN[x]
Input Buffer
Pull-down
Register
Description
GIOPSL
Selects the pull type at pin (pull-up / pull-down)
GIOPULDIS
Disables the pull control capability at pin
GIOPDR
Controls the open drain configuration of the pin
GIODOUT
Controls what information is sent to external pin when configured as output
GIODIN
Receives information from external pin
GIODIR
Controls the direction of the pin (input / output)
122
High-End Timer (N2HET)
123
High End Timer (NHET)
• User-programmable Timing Co-Processor
Address/Data Bus
• Provides high level and complex timing
functions with low CPU overhead
Host
interface
CPU wait control
Global & prescale control
register
Shadow registers
Prescaler
• 128 word instruction RAM with Parity protection
• Dedicated DMA functionality (HTU) to transfer
data from NHET to Data Ram w/o CPU
Timer
RAM
Program RAM
Control RAM
Data RAM
• Conditional program execution based on pin
conditions and compares
Instruction Register
Execution
Unit
Address Register
Register A, B, T
Interrupt Control
32 bit ALU
Operation Control
Input/
Output
Unit
• 32 input/output (I/O) channels (pins) for
complex or classical timing functions such as
capture, compare, PWM, GPIO
Compare
• Suppression filters eliminate undesired input
frequencies
32 High Resolution Channels
Synchronizers
32 I/O Channels
I/O Control
Register
• Multiple 25-bit virtual counters for timers, event
counters, and angle counters
• High Resolution I/Os and coarse resolutions
implemented by sub loops for multiple
resolution capability
124
NHET: Application Examples
Pulse Width Modulation
Other Features
•
Single / multi channel PWMs
•
Frequency Modulated Output
•
PWM with synchronous / asynchronous duty
cycle update
•
Pulse width count (using PWCNT)
•
Time stamp (using WCAP)
•
Event counter (using ECNT)
•
Pulse accumulator example (using ECNT )
•
Multi-resolution scheme
•
•
PWM with synchronous period update
Phase shift PWM's using RADM64 instruction
Frequency and Pulse Measurements
•
Pulse width and period measurement (using PCNT)
•
Period measurement using PCNT in HR mode, HRshare feature and 64 bit read access with “auto
read/clear” bit set
125
NHET: Command Line Assembler
• Invoking the NHET assembler (hetp.exe):
hetp [options] input file
• Options:
– -c32
– -hc32
– -nx
– -l
– -x
produces an output file containing assembler directives for the TMS570
CodeGen Tools
produces a C file and a header file. (used together with the -nx option)
specifies the x-th HET module on the device (used together with -hc32
option)
(lowercase L) produces a listing file with the same name as the input file
with a .lst extension.
produces a cross-reference table and appends it to the end of listing file.
• Example:
hetp -hc32 -n0 pwm.het
• Input:
pwm.het contains the assembly source of the HET program
• Output:
pwm.c
provides a C array, which contains the HET
program opcode
pwm.h
provides a C structure, which allows a simple
access to the NHET fields from other C code
126
High-End Timer Transfer Unit (HTU)
127
HTU: Block Diagram
Transfer Unit (TU)
8 - Requests
Register Bank
High
End
Timer
(NHET)
8 - Requests
(Quiet)
Local RAM
9 - Address
8 Double Control
Packets
32 - Data
128
HTU: Main Features
• CPU and DMA independent
• Support 32 or 64 bits transaction
• Master Port to access directly
system memory
• Addressing modes for HET address
(8 byte or 16 byte) and system
memory address (fixed, 32 bit or
64bit)
• HTU master accesses protected by
dedicated Memory protection Unit
• One Slave port to interface with
VBUS for register interface
• Maximum of 8 double control
packets supporting dual buffer
configuration
• Each type of interrupt can be routed
to either two different host CPUs
• One shot, circular and auto switch
buffer transfer modes
• Request lost detection
• Control packet information is stored
in RAM protected by parity
• Event synchronization (HET transfer
requests)
129
Exercise: PWM Generation using the NHET
130
Overview
• In this exercise we will:
– Create a new HALCoGen Project
– Configure HALCoGen to generate
• A basic PWM with a period of 1 second and a duty cycle of 75%
– Use the PWM to toggle the NHET[08] LED on the board
– Generate and Import code into Code Composer Studio
– Build and Deploy our code to the microcontroller
• Required Hardware:
– Windows Based PC (WinXP, Vista, 7)
– TMS570 LaunchPad or RM4 LaunchPad
• Required Software:
– HALCoGen
– Code Composer Studio
131
HALCoGen GUI Overview
Menus and Icons
Module Selection/Configuration
Help
Device
Block
Diagram
Output/Status
132
HALCoGen Help
• HALCoGen’s embedded help window provides full documentation of
each communication drivers, implemented functions, file dependencies
and examples.
133
HALCoGen File Dependencies and Function Listing
File
Information
Control
File
Explorer
File
Dependency
Diagram
Function
Listing
134
Set up a New HALCoGen Project
• To launch HALCoGen go to:
•
→ Programs → Texas Instruments → Hercules → HALCoGen
• Create a new project:
• File → New → Project
•
For the TMS570 Kit:
–
–
•
1
Choose Family: TMS570LS04x
Device: TMS570LS0432PZ
3
For the RM4 Kit:
–
–
Choose Family: RM42x
Device: RM42L432PZ
2
4
•
•
Then define a name: ‘PWM’
Location: “C:\myWorkspace”
135
Driver Enable
•
In ‘Driver Enable’ tab enable the HET driver.
1
2
3
136
NHET PWM Configuration
•
In ‘HET’  ‘PWM 0-7’ tab:
•
Configure PWM 0 to 75% Duty Cycle, with a Period 1000000.00uS on Pin 8
137
N2HET Output Configuration
•
In the ‘HET’  ‘Pin 8-15’ tab:
•
•
Enable the output on Pin 8
Generate Code: File → Generate Code
138
Setting up Code Composer Studio
• Launch Code Composer Studio (CCS)
– Start → Programs → Texas Instruments → Code Composer Studio v5
→ Code Composer Studio v5
• When it launches, CCS will ask you to select a workspace, we will chose
“C:\myWorkspace”
• Once CCS loads, go to
File → New → CCS Project
139
Setting up our Project
• Our project name needs to match the name of our HALCoGen Project:
‘PWM’
• Make sure that your project
‘Family’ is set to ARM
•
Next, set the Variant
to “Cortex R”
•
Choose: TMS570LS0432
For the RM4 kits:
–
•
3
2
For the TMS570 kits:
–
•
1
Choose : RM42L432
4
5
Then set the ‘Connection’ to the
Texas Instruments XDS100v2
•
Then select ‘Empty Project
•
Then click ‘Finish’
6
140
Setting up our Project
•
Next we need to add our ‘include’ directory to the project from the CCS “Project
Explorer”
•
Right click on the
‘PWM’ project in
the Project
Explorer
•
Then choose
‘Properties’
1
2
141
Setting up our Project
•
•
•
Then in the
‘Properties’ window
expand the ‘Build ->
1
ARM Compiler’
category and select
‘Include Options’
2
Then select the ‘+’
button to add the
directory with our
‘.h’ header files
In the ‘Add directory
path’ window, click
the ‘Workspace…’
button
3
4
•
Finally, select the ‘include’
folder that HALCoGen
created for us that
contains all our ‘.h’ header
files
142
Enter Code into the CCS Project
•
Expand the project and open the “sys_main.c” file from the ‘source’ folder in
the CCS “Project Explorer”
3
1
2
143
Code Composer Studio
• In the Code Composer Project and enter the following code:
– Inside User Code 1, insert the code below.
/* USER CODE BEGIN (1) */
#include "het.h"
/* USER CODE END */
– Then in User Code 3, insert the code below.
/* USER CODE BEGIN (3) */
hetInit();
while(1);
/* USER CODE END */
144
Compiling the Project
• The code is now complete and we are ready to build our project.
– Go to Project → Build All
NOTE: It may take a 3 to 5 minutes to compile the RTS (Run Time Support Library) the first
time a project is built.
145
Programming the Flash
• We are now ready to program the flash.
– Go to Run → Debug
– A new window should appear as it programs the flash memory.
• This may take a few moments.
146
Testing our Program
•
Click the green arrow on the debug tab to run our program
–
Alternatively the program can be run without the debugger connected by pressing the PORRST
button on the LaunchPad
•
•
Clicking the red square on the debug tab to terminate the debugger’s connection
Hitting the reset button on the board and observe the behavior of the NHET LED
•
Congratulations! You have completed the exercise.
147
Possible Errors
•
RM42x kits:
A build error may occur when using some versions of Code Composer Studio
before v5.5
This error occurs because certain versions of CCS do not include the RTS (Run Time Support
Library) for the little endian non floating point Cortex-R4 (rtsv7R4_T_le_eabi.lib) by default.
To resolve this issue:
1)
Open the “Properties” for the CCS project
1)
In the “General” Settings:
•
Set the “Device endianness:” to “little”
•
Set the “Runtime support library:” to
“<automatic>”
2)
Re-Build the CCS project
NOTE: It may take 3 to 5 min to compile the
RTS Library after this configuration change is
made.
148
Possible Errors
•
TMS570 kits:
A build error may occur when using some versions of CCS before v5.5
This error occurs because certain versions of CCS set the floating point RTS (Run Time Support
Library) for the big endian for non floating point Cortex-R4 MCUs by default.
To resolve this issue:
1)
Open the “Properties” for the CCS project
1)
In the “General” Settings:
•
Set the “Runtime support library:” to
“<rtsv7R4_T_be_eabi.lib>”
NOTE: It may take 3 to 5 min to compile the
RTS Library after this configuration change is
made.
149
Multi-Buffered Serial Peripheral Interface
(MibSPI)
150
SPIDAT0
SPIDAT1
SPI – Block Diagram & Features
VBUS Write
16
TX BUF
16
TX SHIFT REGISTER
SIMO
RX SHIFT REGISTER
SOMI
16
RX BUF
16
SPI BUF
VBUS Read
nCS[7:0]
CHARLEN
PRESCALE
PHASE
POLARITY
Mode
Generation
Logic
•
•
•
•
•
•
•
•
•
•
16-bit Shift Registers
Double-buffered TX and RX
Master or Slave Mode
Up to 4 SIMO / SOMI in parallel
Selectable MSbit or LSbit first transfer
Unused pins available as GP I/O
CLK frequency VCLK/2 to VCLK/256
2- to 16-bit character length
Selectable CLK phase and polarity
Interrupt / DMA requests when
• TX buffer empty
• RX buffer full
nENA
CLK
151
MibSPI – Block Diagram, Features
TX DATA
CTRL
TX DATA
CTRL
TX DATA
CTRL
TX DATA
CTRL
VBUS Write
16
TX SHIFT REGISTER
SIMO
RX SHIFT REGISTER
SOMI
16
RX DATA
STATUS
RX DATA
STATUS
RX DATA
STATUS
RX DATA
STATUS
VBUS Read
nCS[7:0]
CHARLEN
PRESCALE
PHASE
POLARITY
Mode
Generation
Logic
•
•
•
•
•
•
•
•
•
•
•
•
•
nENA
•
16-bit Shift Registers
Up to 128 buffers for TX and RX
Up to 8 transfer groups
15 sources to trigger transfers
Memory protected by parity
Master or Slave Mode
Up to 4 SIMO / SOMI in parallel
Selectable MSbit or LSbit first transfer
Unused pins available as GP I/O
CLK frequency VCLK/2 to VCLK/256
2- to 16-bit character length
Selectable CLK phase and polarity
Programmable interrupt and DMA
request generation conditions
Up to 16 DMA requests
CLK
152
SPI / MibSPI Safety Features
• Parity Error detection for all reads from MibSPI RAM
• Continuous monitoring of transmitted data in master and slave modes
• Detection of slave de-synchronization (master mode only)
• Timeout for a non-responsive slave (master mode only)
• Receiver overrun interrupt condition to prevent data loss
• Detection of a mismatch in data length
13
153
Transfer Mode – Five Pin Option
SLAVE
MASTER
(MASTER = 1 ; CLKMOD = 1)
MSB
(MASTER = 0 ; CLKMOD = 0)
Hardware Handshake
SIMO
SIMO
SOMI
SOMI
LSB
MSB
SPIDAT1
LSB
SPIDAT0
SPICLK
WRITE TO SPIDAT1
SPICLK
nSCS[7:0]
nSCS
nENABLE
nENABLE
WRITE TO SPIDAT0
WRITE TO SPIDAT1 (MASTER)
nSCS
WRITE TO SPIDAT0 (SLAVE)
nENABLE
SPICLK
SIMO
SOMI
12
154
Clock Options
CLOCK POLARITY = 0, CLOCK PHASE = 0
WRITE SPIDAT
SPICLK
1
SPISIMO
SPISOMI
2
3
4
5
6
7
8
MSB
D6
D5
D4
D3
D2
D1
LSB
D7
D6
D5
D4
D3
D2
D1
D0
SAMPLE IN
RECEPTION
CLOCK PHASE = 0
(SPICLK WITHOUT DELAY)
- DATA IS OUTPUT ON THE RISING EDGE OF SPICLK
- INPUT DATA IS LATCHED ON THE FALLING EDGE OF SPICLK
- A WRITE TO THE SPIDAT REGISTER STARTS SPICLK
155
SPI / MibSPI Parallel Mode
• In order to achieve higher data flow, the parallel mode of the SPI / MibSPI enables
the module to send data over more than one data line (Parallel 2, or 4).
• Figure of Parallel Mode with Shift register MSB first:
SIMO0
SIMO1
SIMO2
SIMO3
SIMO4
SIMO5
SIMO6
SIMO7
PSIMO[7:0]
Parallel Mode
MULTIPLEXER
Shift Register as in
SPI / MibSPI
15
14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
SOMI0
SOMI1
SOMI2
SOMI3
SOMI4
SOMI5
SOMI6
SOMI7
DEMULTIPLEXER
SOMI[7:0]
• Notes:
– When parallel mode is used, the data length must be set as 16 bits
– If parity is enabled one additional SPICLK will trigger the parity bit transfer
156
Timing Setup – Delay Register (SPIDELAY)
CSHOLD = 0 (set CS high after transmission)
CSHOLD = 1 (held active/ dotted line)
SCSx
WDELAY
ENAx
tC2EDELAY = (C2EDELAY /
SPICLK)
tT2EDELAY = (T2EDELAY /
SPICLK)
SPICLK
tC2TDELAY = (C2TDELAY / VCLK) + 2
tT2CDELAY = (T2CDELAY / VCLK) + 1
VBUSPCLK
SOMI
DATA
157
Controller Area Network
(DCAN)
158
DCAN Features Overview
• Full CAN according to protocol version 2.0 part A, B
• Standard and Extended Identifiers
• Programmable Bit Timing, Bit rates up to 1 MBit/s
• Up to 128 Message Objects (MO)
• Identifier Masks for each Message Object
• Programmable FIFO mode for Message Objects
• Dual clock feature
• Possible automatic retransmission of a frame in case of lost arbitration or error
• Bus diagnostic: Bus off, Bus error passive, Bus error warning, Bus stuck dominant
• Frame error report: CRC, Stuff, Form, Bit and Acknowledgement errors
• Programmable loop-back modes for self-test operation
• Suspend modes for debug support
• Parity check mechanism for all RAM modules
159
DCAN Block Diagram & Features
VCLK
VCLKA
CAN_RX
CAN_TX
• Full CAN (protocol version 2.0 A, B)
DCAN
• CAN Core
– Handles all CAN protocol functions
CAN_CLK
CAN Core
Message
RAM
Me ssage Ha ndler
Message
RAM
Interface
• Message Handler
– Controls data transfer between CAN
core, message interface registers
and RAM
– Handles acceptance filtering and
interrupt/DMA requests
• Message RAM
– Up to 64 Message Objects
Registers & MO access
Test Modes
only
Module Interface
INT requests DMA requests
CTRL
VBUSP
(8, 16 or 32 bit)
• Registers & Message Object access (IFx)
– Status and configuration registers for
module setup and indirect Message
Object access through interface
registers (IFx)
• Module Interface
– 2-bit interface to VBUS peripheral
clock domain
160
CAN Bus
• Two wire differential bus (usually twisted pair)
• Max. bus length depend on transmission rate
– 40 meters @ 1 Mbps
CAN
NODE A
CAN
NODE B
CAN
NODE C
CAN_H
120
120
CAN_L
161
CAN Node
Wired-AND Bus Connection
CAN_H
120
120
CAN_L
CAN Transceiver
(EX: TI SN65HVD23x)
TX
RX
CAN Controller
(Hercules MCU)
http://www.ti.com/product/sn65hvd232
162
CAN Message Format
• Data is transmitted and received using Message Frames
• 8 byte data payload per message
• Standard and Extended identifier formats
Standard Frame: 11-bit Identifier (CAN v2.0A)

Arbitration
Field
S
O
F
Control
Field
R I
11-bit
D r0 DLC
Identifier T
R E
Data Field
0…8 Bytes Data
CRC
ACK
E
O
F
Extended Frame: 29-bit Identifier (CAN v2.0B)
Arbitration Field
S
O
F
11-bit
Identifier
Control
Field
R
S I
18-bit
R D Identifier T r1 r0 DLC
R
R E
Data Field
0…8 Bytes Data
CRC
ACK
E
O
F
163
FlexRay / Transfer Unit
(Available on select TMS570 MCUs Only)
164
FlexRay Feature Overview
• Open Bus System
• Support of redundant transmission channels
• Data rate of 20 Mbit/sec (10Mbit/sec per channel)
• Support of a fault tolerant synchronized global time base
• Static and dynamic data transmission (scalable)
– Deterministic data transmission
– Arbitration free transmission
• Fault tolerant and time triggered services implemented in hardware
• Support of optical and electrical physical layers
165
FlexRay Block Diagram
RX_A
FlexRay Module
Port A
Protocol Controller
A
Transient Buffer RAM - A
Global Time
Unit
TX_A
RX_B
Port B
Protocol Controller
B
System
Universal
Control
Transient Buffer RAM - B
Frame &
Symbol
Processing
TX_B
FlexRay Transfer Unit (FTU)
Direct
Access
Transfer Unit
State Machine
Input
Buffer
Message Handler
Output
Buffer
Interrupt
Control
Message RAM
VBUS IF
(Slave)
VBUS IF
(Master)
Peripheral Bus
Network
Management
BCLK
SCLK
VBUSCLK
80MHz
Interrupts
166
FlexRay Communication Structure
Cycle [n]
static
segment
dynamic
segment
slot 1 slot 2 slot 3
hea
der
payload
…
Cycle […]
Cycle [n+1]
symbol
window
slot
m-1
trailer
CID
NIT
slot m
static
segment
dynamic
segment
m
+
1
m
+
2
m
+
3
hea
der
symbol
window
NIT
dynamic
slot m+4
payload
m
+
5
m
+
6
dynamic
slot 7
trailer
.
.
.
m
+
x
CID
the payload length can vary
167
1 1 1 1 1
Startup Frame Indicator
Sync Frame Indicator
Null Frame Indicator
Payload Preamble Indicator
Reserved Bit
FlexRay Message Frame Format
Frame ID
Payload
Length
Header
CRC
Cycle
Count
11 bits
7 bits
11 bits
6 bits
Header Segment
Data 0
Data 1
Data n
0 … 254 bytes
Payload Segment
CRC
CRC
CRC
24 bits
Trailer Segment
FlexRay Frame 5 + (0 … 254) + 3 Bytes
168
FlexRay Communication Cycle
Channel A
Communication Cycle
1
Static Segment
Dynamic Segment
Fixed Time Division Multiple Access
Flexible Time Division Multiple Access
D1
C1
A1
5
4
3
2
7
6
D2
E2
C2
Channel B
time
1
A4
4
3
2
B
C1
5 6
7
C2
A3
time
Silence
Silence
Physical Frame
169
FTU Data Transfer Scheme
Event Trigger
Trigger
CPU
Interrupt
FTU
Header Partition
TCR
Data RAM
Array of
Struct {
Header,
Payload }
Data (Payload)
Partition
VBUS
(Peripheral Bus)
Protocol Controller
State Machine
Control
TBA
FlexRay Bus
Message RAM
FlexRay Core
170
FlexRay Transfer Unit Key Features
• Data Transfer without CPU interaction
– From FlexRay Message RAM to Data RAM (Read)
– From Data RAM to FlexRay Message RAM (Write)
• Transfer Types
– data and header section
– header section only
– data section only
• Transfer Configuration RAM (with Parity)
– Configures the transfer sequence
– Parity protection
• Triggers to Start a Transfer
– CPU driven (single transfer sequence)
– Event driven (single or continuous transfer sequence)
171
FlexRay Transfer Unit Key Features…
• Different Transfer Conditions
– If the status flags (header section) of the respective
message buffer has been updated
– If the data section of the respective message buffer has
been updated
– Always
• Maskable interrupt generation when Message Buffer transfer
is finished
• Memory Protection Unit
– One memory section (start- and end address) can be
defined
– No memory section is setup after reset
172
Ethernet Media Access Controller (EMAC)
173
EMAC Sub System: Features
• EMAC Module
–
–
–
–
Synchronous 10/100 Mbps operation
Standard MII or RMII to external physical layer device (PHY)
Master port for transfers to/from internal and external RAM
Transmit and Receive Quality-of-Service (QoS) support
• EMAC Control Module
– Ether-Stats and 802.3-Stats statistics gathering
– 8 kB local EMAC descriptor memory (CPPI RAM)
• Enough to transfer up to 512 Ethernet packets without CPU intervention
– Programmable interrupt logic
• Allows restriction of back-to-back interrupt generation
• MDIO Module
– Implements the 802.3 serial management interface
– Can control up to 32 Ethernet PHYs using a shared 2-wire bus
– Used to configure each PHY connected to the EMAC
174
EMAC Block Diagram
Host CPU Interface
EMAC Sub System
MII/RMII
Bus
EMAC Module
EMAC Interrupts
Control Module
DMA
Bus
DMA Master
MDIO
Bus
MDIO Module
8K CPPI RAM
Interrupt
Combiner
C0
Interrupts
MDIO Interrupts
175
MII Connections
System
Core
EMAC
2.5 MHz
or
25 MHz
Physical
Layer
Device
(PHY)
Transformer
MDIO
RJ-45
http://www.ti.com/product/dp83640
176
RMII Connections
System
Core
EMAC
50 MHz
Physical
Layer
Device
(PHY)
Transformer
MDIO
RJ-45
http://www.ti.com/product/dp83640
177
Universal Serial Bus (USB)
(Available on select RM MCUs Only)
178
USB Controller: Features
• One full-speed USB device port
– Compliant to USB Specification Rev 2.0 and Rev 1.1
– Interfaces host processor and the external USB transceiver (PHY)
• Two USB host ports
– Compliant to USB Specification Rev 2.0
– Based on Open Host Controller Interface (OHCI), Release 1.0a
– Support for Overcurrent protection and automatic power switching
• Second host port terminals are shared with device port terminals
– Can use 2 USB host ports, or 1 USB host port and 1 USB device port
179
USB Host Port Connections
http://www.ti.com/product/tusb1105
180
USB Device Port Connections
http://www.ti.com/product/tusb1105
181
Serial Communication Interface (SCI/UART/LIN)
182
SCI Features
• Programmable Frame Format
1
Start Bit
1 to 8 Data Bits
0 or 1 Address Bit
0 or 1 Parity Bit
1 or 2 Stop Bits
• Asynchronous Communications Format
• 2 Multiprocessor Modes with Wake-up Capability
Idle-Line Mode; Address-Bit Mode
• Programmable Baud Rate
– More than 16 700 000 different Baud Rates
– Max 3.125Mbps with 100MHz VCLK
• Error Detection
– Parity, Overrun and Framing Error
– Break Detect
• Noise Protection Capability
• Double-buffered Receive and Transmit Function
183
SCI Block Diagram
TRANSMITTER
ADDR Bit
SCITX
Shift Register
TX EMPTY
TXRDY
TX Interrupt
TX INT ENA
Transmit Buffer
VCLK
TXENA
BAUD CLOCK
GENERATOR
SCI BAUD
SCIRX
RECEIVER
Shift Register
RX ERROR
BRK DET
WAKE UP
INT ENA
ERROR Interrupt
INT ENA
P/O/F ERROR
INT ENA
RX WAKE
Receive Buffer
RXRDY
RX Interrupt
RX INT ENA
184
SCI Frame Format
START
0
(LSB)
1
2
3
4
5
6
5
6
7 PARITY STOP
(MSB)
IDLE-LINE mode
address bit
START
0
(LSB)
1
2
3
4
7
(MSB)
ADDR PARITY STOP
ADDRESS-BIT mode
185
Typical LIN Applications (TMS570)
Passenger´s Door
Lock, window
Mirror
Rear Door Lock,
window
Light
Levelizer
Climate Control
Fan
Rear Wiper
Wipers
Damper
Compressor
Steering
wheel
CAN
Dashboard
BCM
Gateway
Sun Roof
Door Control
Driver´s Seat
Levelizer
Light
Mirror
Driver´s Door
Lock, window
Rear Door Lock,
window
186
LIN Key Features
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
INTERFACE
CHECKSUM
CALCULATOR
ID PARITY
CHECKER
BIT MONITOR
TXRX ERROR
DETECTOR
(TED)
TIMEOUT
CONTROL
COUNTER
LINRX
COMPARE
LINTX
FSM
SYNCHRONIZER
SCI
MASK
FILTERS
8 RECEIVE
BUFFERS
DMA
CONTROL
8 TRANSMIT
BUFFERS
LIN
• Compatible with LIN 1.3 or 2.0
• LIN 2.0 Master Compliant
• HW LIN protocol handler
– Multi-buffered receive and
transmit units
– Automatic checksum
generation
and validation
– ID masks for message
filtering
– DMA capability
• Synch break detection
• Slave automatic synchronization
• Optional baud rate update
• Synchronization validation
• Automatic bit monitoring
• Automatic error detection
187
External Memory Interface (EMIF) /
Parameter Overlay Module (POM)
188
EMIF: Block Diagram
CPU
DMA
Other Bus
Masters
Switch Central Resource
(SCR)
EMIF
EMIF_nCS[0]
EMIF_nRAS
EMIF_nCAS
EMIF_CLK
EMIF_CKE
SDRAM
Interface
EMIF_nCS[2,3,4]
EMIFnOE
EMIF_nWAIT
EMIF_RnW
Asynchronous
Interface
EMIF_nWE
EMIF_BA[1:0]
EMIF_nDQM[1:0]
EMIF_DATA[15:0]
EMIF_ADDR[21:0]
Shared SDRAM
and
Asynchronous
Interface
189
EMIF: Main Features
• Asynchronous Memory Support
–
–
–
–
–
–
–
Interfaces to SRAM memories as well as NOR Flash memories
22 address lines, 3 chip selects of up to 16MB each
16-bit data bus width
Programmable cycle timings
Select strobe mode option
Extended wait mode with programmable timeout period
Data bus parking
• Synchronous DRAM Memory Support
–
–
–
–
–
–
–
One, Two and Four Bank SDRAM devices
22 address lines, 1 chip select
Devices with Eight, Nine, Ten, and Eleven Column Addresses
CAS latency of two or three clock cycles
16-bit data bus width
3.3V LVCMOS Interface
Support for SDRAM Self-Refresh and Powerdown modes
190
Parameter Overlay Module
• Redirects program memory accesses to
internal/external memory interface (overlay)
• Provides up to 32 programmable memory
regions to replace non-volatile memory
External
Memory
(Overlay)
– Programmable region start address
– Programmable region size (64 Bytes up to 256kBytes
in power of 2 steps)
EMIF
• Up to 4 MByte of external overlay memory
– 22 bit start address size
SCR
• Overlay memory is memory mapped
Other Master
Access
– Writable by any master (e.g. CPU, DMA, DMM, etc.)
POM
Data
Program
Memory
Data
Wrapper
Address
Address
191
POM - Overlay Region Example
Program Memory
Overlay Memory
0x00000000
1K Bytes
0x00001000
64 Bytes
64 Bytes
0x00000400
0x00024400
1K Bytes
192
Multi-Buffered Analog to Digital Converter
(MibADC)
193
MibADC Block Diagram
VrefLO
VSSA
10/12-bit
Analog – Digital Converter
Calibration &
Error
Correction
(Successive Approximation)
ADC RAM
Ctrl
CAP Dis.
Chn
FIFO Empty
GROUP1
Event Logic
GROUP2
Sequencer and Memory Interface
Controller
EVENT
DMA
Requests
ADCLK
ADEVT
VCCA
Sample Cap
Discharge
Chnsel Swtsel
(Test / Cal)
Internal
Event 1
.
.
Internal
Event 7
VrefHI
Self-Test
& Calibration
24:1 Multiplexer
ADIN23
.
.
.
.
.
.
.
.
.
.
.
ADIN0
GIO Control
3 Magnitude
Threshold Interrupt
Sources
Interrupt
Threshold + Counters
Prescaler
EVENT,GROUP1
GROUP2
GROUP1
FIFO
GROUP2
FIFO
3
Conversion
Group
Selection
DMA requests
Result Formatting
- Channel ID Mask
- 8/10/12 bit Mode Mask
w/ Parity
w/ RAM Test
w/ Autoinitialization
5
3
Interrupt
Requests
EVENT
FIFO
VCLK
24
PERIPHERAL BUS (VBUSP)
194
MibADC ADC Implementation
• Available Dual12-bit ADC cores:
Self-Test & Calibration
MibADC1
To Peripheral Bus
AD1EVT
MibADC2
To Peripheral Bus
– MibADC1 (AD1IN + ADSIN = 24 ch)
MibADC2 (ADSIN = 16 ch)
AD1IN[7..0]
– 16 analog channels shared between the
2 cores for safety critical
conversions/comparison
– Internal ADC reference voltages can be
used to check converter functionality
– Self Test Mode enables application to
detect opens/shorts on ADC inputs
– ADC calibration logic can improve
accuracy or be used to detect drift
between multiple test results
 offset error correction
ADSIN[23..8]
VccAD
VssAD
VrefHi
VrefLo
AD2EVT
Self-Test & Calibration
Note: Not all Hercules MCUs are available with dual ADCs
195
MibADC Operation Modes
Conversion
Mode
• Normal active mode for converting the selected external input voltage
Sample
Capacitor
Discharge
Mode
• Active mode that grounds the ADC sampling capacitor
Calibration
Mode
• Special active mode for calibration using internal reference voltages
Self-Test Mode
Power-Down
Mode
• Active mode for failure-detection using internal reference voltages
• Inactive mode in which the ADC internal clock is stopped
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MibADC Conversion Groups
Input Channel Select Registers
31
Event group select
(ADEVSEL)
0
1
Event
group
FIFO
12
value
8
value
ADG2SEL
ADG1SEL
31
0
1
31
0
1
9
1
value
Group 1
FIFO
3
value
Group 2
FIFO
read
read
read
ADEVBUFFER
ADG1BUFFER
ADG2BUFFER
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MibADC Conversion Result
VCCAD VSSAD
Vin
S/H
VREFLO
12bit
RESET
Analog – Digital Converter
(successive approximation)
ACQ11:0 ADCLK Start
12 bit ADC:
VREFHI
OUT
12
EOC
DIGITAL_RESULT = 4096 * (Vin – VREFLO) / (VREFHI - VREFLO)
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MibADC Interrupts
Group
Conversion End
• All channels that are assigned to a particular group are converted
Group Memory
Threshold
• Number of conversion results exceed threshold register value
Group Memory
Overrun
• Number of ADC conversions exceed the number of buffers allocated for that
conversion group
Magnitude
Threshold
• Magnitude comparison of conversion result on up to three channels.
Programmable compare between two channels’ conversion results or a
channel’s conversion result with a threshold value
Parity Error
• On parity error the ADC module sends a parity error signal to the System module
199
Exercise:
Using the MibADC to collect Ambient Light Sensor data
200
ADC Exercise Overview
• In this exercise we will:
– Acquire data from the ambient light sensor using the ADC module
– Send the converted ADC value back through the SCI/UART module to the
PC.
00111011000100100110
201
Set up a New HALCoGen Project
• To launch HALCoGen go to:
•
→ Programs → Texas Instruments → Hercules → HALCoGen
• Create a new project:
• File → New → Project
•
For the TMS570 Kit:
–
–
•
1
Choose Family: TMS570LS04x
Device: TMS570LS0432PZ
3
For the RM4 Kit:
–
–
Choose Family: RM42x
Device: RM42L432PZ
2
4
•
•
Then define a name: ‘ADC’
Location: “C:\myWorkspace”
202
Driver Enable
•
Enable the SCI and ADC drivers in the ‘Driver Enable’ sub tab of the device
203
SCI Configuration
• Select the SCI tab and then the “SCI/LIN Data Format” subtab
• Ensure that the SCI module is setup with the following parameters:
– Baud rate: 9600
– Data bits: 8
– Enable Parity (odd), 1 Stop bit
204
ADC Group Configuration
•
In the ‘ADC’ tab and ‘ADC1 Group 1’ Subtab, Configure FIFO Size, Trigger Source and
ADC channel as shown below
Only one conversion per software trigger is done
SW Trigger as Trigger Source
Ambient light sensor is connected to MibADC1 Pin9
•
Generate code: File → Generate Code or click
205
MibADC Exercise
•
Insert the following code in the corresponding sections within the ‘sys_main.c’ file
–
USER CODE BEGIN (0) - #include header section
/* USER CODE BEGIN (0) */
#include "sci.h"
#include "adc.h"
#include "stdlib.h"
unsigned char command[8];
/* USER CODE END */
206
MibADC Exercise
–
USER CODE BEGIN(3) - Main() section
void main(void)
{/* USER CODE BEGIN (3) */
adcData_t adc_data; //ADC Data Structure
adcData_t *adc_data_ptr = &adc_data; //ADC Data Pointer
unsigned int NumberOfChars, value; //Declare variables
sciInit(); //Initializes the SCI (UART) module
adcInit(); //Initializes the ADC module
while(1) // Loop to acquire and send ADC sample data via the SCI (UART)
{
adcStartConversion(adcREG1, 1U); //Start ADC conversion
while(!adcIsConversionComplete(adcREG1, 1U)); //Wait for ADC conversion
adcGetData(adcREG1, 1U, adc_data_ptr); //Store conversion into ADC pointer
value = (unsigned int)adc_data_ptr->value;
NumberOfChars = ltoa(value,(char *)command);
sciSend(scilinREG, 2, (unsigned char *)"0x"); //Sends '0x' hex designation chars
sciSend(scilinREG, NumberOfChars, command); //Sends the ambient light sensor data
sciSend(scilinREG, 2, (unsigned char *)"\r\n"); //Sends new line character
}
/* USER CODE END */}
–
Now build and load your program on the microcontroller
207
Testing your code
• Upon completion open your preferred terminal program.
– Note: A terminal program is included in CCS. To enable it go to ‘View’ -> Other and select
‘Terminal’ from the ‘Show View’ menu. If the ‘Terminal’ option is not available it can be added as
an eclipse plug-in by following these instructions:
http://processors.wiki.ti.com/index.php/How_to_install_the_terminal_plugin_in_CCSv5
• Setup the terminal program with the following properties:
– Baud rate: 9600
– Data bits: 8
– Odd parity, 1 Stop bit
•
Click the ‘Run’ button to run the program
Now you should see the ADC results in the terminal program
•
Use a flashlight to change the light level supplied to the ambient light sensor on
the board and notice the output values change in the terminal program.
208
Enabling the CCS Terminal
1) Select View → Other
3) Enter the proper communication
settings for the ‘Terminal Tab’
2) Then select ‘Terminal’ from the ‘Show
View’ menu.
209
Additional Hercules™ Information
210
Additional Information
Hercules Web Page: www.ti.com/hercules
RM4 Web Page: www.ti.com/rm4
TMS570 Web Page: www.ti.com/tms570
TMS470M Web Page: www.ti.com/tms470m
–
–
–
–
–
Data Sheets
Technical Reference Manual
Application Notes
Software & Tools Downloads and Updates
Order Evaluation and Development Kits
Engineer 2 Engineer Support Forum:
www.ti.com/hercules-support
–
–
–
–
News and Announcements
Useful Links
Ask Technical Questions
Search for Technical Content
Hercules WIKIs:
RM4 WIKI: www.ti.com/hercules-rm4-wiki
TMS570 WIKI: www.ti.com/hercules-tms570-wiki
TMS470M WIKI: www.ti.com/hercules-tms470m-wiki
– How to guides
– Intro Videos
– General Information
211
Want Additional Training?
Hercules™ Training Videos: www.ti.com/herculestraining
Safety Critical Design and Programming with Hercules™ Microcontrollers:
Day 1
• Welcome and Intro
• Hercules™ Product Overview / MCU
Roadmap
• Safety Standards and Hercules
Safety Features / Exercise
• HALCoGen / Exercise
• Code Composer Studio /
Demonstration
• Compiler
• Flash Overview
• Flash Tools: nowFlash, nowECC /
Exercise
Day 2
Day 3
• Summary / Questions
• ARM ® Cortex™ -R4F CPU
• System Module Overview
• Device setup/startup, Real Time
Interrupt Module, Vectored
Interrupt Manager
• CRC Controller, CPU Compare
Module, Error Signaling Module,
Dual Clock Compare, JTAG
Security Module
• General Purpose I/Os / Exercise
• Direct Memory Access Controller
(DMA)
• Serial Communication Interface
(SCI/UART) / Exercise
• Summary / Questions
• Multi-Buffer ADC (MIBADC) /
Exercise
• Multi-Buffer Serial Peripheral
Interface (SPI / MIBSPI-P)
• DCAN
• FlexRay
• External Memory Interface (EMIF) /
Parameter Overlay Module (POM)
• Ethernet
• USB Host / Device
• HET (High End Timer) IDE
• N2HET & Transfer Unit / Exercise
• Summary / Questions / Survey
212
Thank You!
Please fill out the Training Class Survey
213