For Audio Equipment MN66271RA Signal Processing LSI for Compact Disc Players Overview The MN66271RA is a CD signal processing LSI that, on a single chip, combines optics servos for the CD player (focus, tracking, and traverse servos), digital signal processing (EFM demodulation and error correction), digital servo processing for the spindle motor, digital filter, and D/A converter, so thus covers all signal processing functions from the head's RF amplifier onward. (Spindle motor servo) CLV digital servo (Audio circuits) Digital filter using 8 times oversampling Built-in D/A converter (1-bit D/A converter) Built-in differential operational amplifier (±PWM output) Features (Optics servo) Focus, tracking, and traverse servos Automatic adjustment functions for FO/TR gain, FO/TR offset, and FO/TR balance Built-in D/A converter for drive voltage output Built-in dropout countermeasures Anti-shock functions Built-in track cross counter Support for both linear motor and screw-based traverse mechanisms Support for 3- and 1-beam systems Digital Signal Processing (Digital signal processing) Built-in DSL and PLL Frame synchronization detection, holding, and insertion Subcode data processing Subcode Q data CRC check Built-in subcode Q data register CIRC error detection and correction C1 decoder: duplex error correction C2 decoder: triplex error correction Built-in 16-K bits of RAM for use in deinterleaving Audio data interpolation Averaging or retention of previous values Soft muting Digital attenuation (256 levels) Software attenuation (256 levels) Audio data peak level detection function Automatic cuing detection function Digital audio interface (EIAJ format) Audio data serial interface (Other) Built-in playback pitch control function (±13%) Operating voltage 4.5 to 5.5 V Applications CD Players MN66271RA For Audio Equipment 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD X2 X1 VSS SBCK SUBC PDO PCK EFM AVSS2 AVDD2 VCOF PLLF DSLF DRF IREF ARF WVEL PLAY TES Pin Assignment 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 BCLK LRCK SRDATA DVDD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK SUBQ DMUTE STAT RST SMCK PMCK BYTCK CLDCK FCLK IPFLAG FLAG CLVS CRC DEMPH RESY RST2 TEST AVDD1 OUTL AVSS1 OUTR RSEL CSEL PSEL MSEL SSEL (TOP VIEW) QFS080-P-1414 LDON BDO RFDET TRCRS OFT VDET RFENV TE FE TBAL FBAL VREF FOD TRD KICK ECS ECM PC TVD TRV For Audio Equipment MN66271RA 70 RST2 Block Diagram PWM (R) 8 TIMES OVER SAMPLING DIGITAL FILTER DIGITAL DEEMPHASIS 1 BIT DAC LOGICS PWM (L) 74 AVSS1 72 AVDD1 DIGITAL AUDIO INTERFACE 24 23 36 OFT 38 SERVO TIMING GENERATOR RFDET 39 BDO 35 VDET TRCRS 37 INPUT PORT OUTPUT PORT SERVO CPU D/A CONVERTER INTERPOLATION SOFT MUTING DIGITAL ATTENUATION PEAK DETECT AUTO CUE MICROCOMPUTER INTERFACE 34 RFENV TE 33 32 FE VDD VSS DVDD1 DVSS1 RST TEST 60 57 4 5 18 71 A/D CONVERTER 6 CLV SERVO CIRC ERROR CORRECTION 16K SRAM DEINTERLEAVE EFM DEMODULATION SYNC INTERPOLATION SUBCODE DEMODULATION DSL•PLL VCO SUBCODE BUFFER 65 FLAG 64 IPFLAG TIMING GENERATOR PITCH CONTROL VCO 9 MLD 7 MCLK 8 MDATA 49 VCOF 61 BYTCK 19 SMCK 63 FCLK 20 PMCK 77 CSEL 79 MSEL 59 X2 58 X1 17 STAT + 53 52 48 47 45 46 44 76 78 OUTL – 80 SSEL 14 SQCK 15 SUBQ PCK EFM PLLF DSLF IREF DRF ARF RSEL PSEL 73 66 67 13 62 56 55 68 69 OUTR + CLVS CRC BLKCK CLDCK SBCK SUBC DEMPH RESY 75 – 51 AVSS2 50 AVDD2 TX ECM PC 2 LRCK 3 SRDATA 1 BCLK 16 DMUTE 21 TRV 26 KICK 29 V 25 REF ECS 22 TVD 27 TRD 28 FOD 31 TBAL 30 FBAL 41 TES 12 TLOCK 11 FLOCK 42 PLAY 40 LDON 43 WVEL 10 SENSE MN66271RA For Audio Equipment Pin Descriptions Pin No. 1 Symbol BCLK I/O O Function Description SRDATA bit clock output 2 LRCK O Left/right channel discrimination signal output 3 SRDATA O Serial data output 4 DV DD1 I Power supply for digital circuits 5 DVSS1 I Ground for digital circuits 6 TX O Digital audio interface output signal 7 MCLK I Microcomputer command clock input (Data is latched at rising edge.) 8 MDATA I Microcomputer command data input 9 MLD I Microcomputer command load signal input. 10 SENSE O Sense signal output (OFT, FESL, NACEND, NAJEND, POSAD, and SFG) "L" level: load. 11 FLOCK O Focus servo convergence signal. "L" level: convergence. 12 TLOCK O Tracking servo convergence signal. "L" level: convergence. 13 BLKCK O Subcode block clock signal (fBLKCK =75 Hz, normal playback) 14 SQCK I External clock input for subcode Q register 15 SUBQ O Subcode Q data output 16 DMUTE I Muting input. 17 STAT O Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, and SQOK) 18 RST I Reset input. 19 SMCK O "H" level: muting. "L" level: reset. If MSEL is at "H" level, 8.4672 MHz clock signal output. If MSEL is at "L" level, 4.2336 MHz clock signal output. 20 PMCK O 88.2 kHz clock signal output 21 TRV O Traverse forced feed output 22 TVD O Traverse drive output 23 PC O Spindle motor ON signal. "L" level: ON. 24 ECM O Spindle motor drive signal (forced mode output) 3-State 25 ECS O Spindle motor drive signal (servo error signal output) 26 KICK O Kick pulse output 27 TRD O Tracking drive output 28 FOD O Focus drive output 29 VREF I Reference voltage for DA output (TVD, ECS, TRD, FOD, FBAL, and 30 FBAL O Focus balance adjustment output 31 TBAL O Tracking balance adjustment output 32 FE I Focus error signal input (analog input) TBAL) 33 TE I Tracking error signal input (analog input) 34 RFENV I RF envelope signal input (analog input) 35 VDET I Vibration detection signal input. "H" level: vibration detected. 36 OFT I Offtrack signal input. "H" level: offtrack. 37 TRCRS I Track cross signal input 38 RFDET I RF detection signal input. "L" level: detected. 39 BDO I Dropout signal input. "H" level: dropout. 40 LDON O Laser ON signal output. "H" level: ON. For Audio Equipment MN66271RA Pin Descriptions (continued) Pin No. 41 Symbol TES I/O O Function Description Tracking error shunt signal. "H" level: shunt. 42 PLAY O Play signal output. 43 WVEL O Double-speed status signal output. "L" level: double-speed. "H" level: play. 44 ARF I RF signal input 45 IREF I Reference current input pin DSL bias pin 46 DRF I 47 DSLF I/O DSL loop filter pin 48 PLLF I/O PLL loop filter pin 49 VCOF I/O VCO loop filter pin for pitch control 50 AV DD2 I Power supply for analog circuits (DSL, PLL, and D/A converter output) 51 AV SS2 I Ground for analog circuits (DSL, PLL, and D/A converter output) 52 EFM O EFM signal output 53 PCK O PLL derived clock output with fPCK=4.3218 MHz 54 PDO O Phase comparator output for EFM and PCK signals 55 SUBC O Subcode serial output data output 56 SBCK I Serial clock input for subcode serial output 57 VSS I Ground for oscillator circuit 58 X1 I Crystal oscillator circuit input pin. f=16.9344 MHz. 59 X2 O Crystal oscillator circuit output pin. f=16.9344 MHz. 60 VDD I Power supply for oscillator circuit 61 BYTCK O Byte clock signal output 62 CLDCK O Subcode frame clock signal output pin (fCLDCK=7.35 kHz) 63 FCLK O Crystal frame clock signal output (fFCLK=7.35 kHz) 64 IPFLAG O Interpolation flag signal output. 65 FLAG O Flag signal output 66 CLVS O "H" level: interpolation. Spindle servo phase synchronization signal output. "H" level: CLV. "L" level: rough servo. 67 CRC O Subcode CRC check result output. 68 DEMPH O De-emphasis detection signal output. "H" level: OK. "L" level: no good. 69 RESY O Frame resynchronization signal. "H" level: ON. "H" level: synchronized. "L" level: out of sync. 70 RST2 I Reset pin for stopping operation of circuits past D/A converter 71 TEST I Test pin. 72 AV DD1 I Power supply for analog circuits (common use for by left and right channel Keep this pin at "H" level. audio outputs) 73 OUTL O Left channel audio output 74 AV SS1 I Ground for analog circuits (common use for left and right channel audio 75 OUTR O Right channel audio output 76 RSEL I RF signal polarity selection pin. outputs) "H" level: bright level is "H. "L" level: bright level is "L. 77 CSEL I Test pin. Keep this pin at "L" level. MN66271RA For Audio Equipment Pin Descriptions (continued) Pin No. 78 Symbol PSEL I/O I 79 MSEL I Function Description Test pin. Keep this pin at "L" level. Frequency selection pin for SMCK pin output. "H" level: SMCK=8.4672 MHz. "L" level: SMCK=4.2336 MHz. 80 SSEL I SUBQ pin output mode selection pin. "H" level: buffered subcode Q mode. Package Dimensions (Unit: mm) QFS080-P-1414 16.2±0.2 14.0±0.2 60 41 40 80 16.2±0.2 14.0±0.2 0.825 61 21 0.15 SEATING PLANE 0 to 10° 1.1±0.1 0.15 +0.10 -0.05 +0.10 0.3 -0.05 2.1±0.3 0.65 2.0±0.2 20 0.1±0.1 1 0.55±0.1