BGS15M2A12 SP5T Diversity Antenna Switch with MIPI RFFE Interface Data Sheet Revision 3.0 - 2016-02-22 Power Management & Multimarket Edition 2016-02-22 Published by Infineon Technologies AG 81726 Munich, Germany c 2016 Infineon Technologies AG All Rights Reserved. LEGAL DISCLAIMER The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. BGS15M2A12 Revision History Document No.: BGS15M2A12__v3.0.pdf Revision History: Rev. v3.0 Previous Version: 2.1 Page Subjects (major changes since last revision) 9 IL/RL/ISO/H2/H3 limits updated in Table 6 16 Marking layout updated in Figure 6 16 Carrier tape drawing updated in Figure 7 Trademarks of Infineon Technologies AG TM TM TM TM TM TM TM TM TM TM TM µHVIC , µIPM , µPFC , AU-ConvertIR , AURIX , C166 , CanPAK , CIPOS , CIPURSE , CoolDP , CoolGaN , TM TM TM TM TM TM TM TM TM TM COOLiR , CoolMOS , CoolSET , CoolSiC , DAVE , DI-POL , DirectFET , DrBlade , EasyPIM , EconoBRIDGE , TM TM TM TM TM TM TM TM TM EconoDUAL , EconoPACK , EconoPIM , EiceDRIVER , eupec , FCOS , GaNpowIR , HEXFET , HITFET , TM TM TM TM TM TM TM TM TM TM HybridPACK , iMOTION , IRAM , ISOFACE , IsoPACK , LEDrivIR , LITIX , MIPAQ , ModSTACK , my-d , TM TM TM TM TM TM TM TM TM NovalithIC , OPTIGA , OptiMOS , ORIGA , PowIRaudio , PowIRStage , PrimePACK , PrimeSTACK , PROFET , TM TM TM TM TM TM TM TM TM PRO-SIL , RASIC , REAL3 , SmartLEWIS , SOLID FLASH , SPOC , StrongIRFET , SupIRBuck , TEMPFET , TM TM TM TM TM TRENCHSTOP , TriCore , UHVIC , XHP , XMC . Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Trademarks updated November 2015 Data Sheet 3 Revision 3.0 - 2016-02-22 BGS15M2A12 Contents 1 Features 5 2 Product Description 5 3 Maximum Ratings 6 4 Operation Ranges 8 5 RF Characteristics 9 6 MIPI RFFE Specification 11 7 Pin Configuration and Function 14 8 Package Information 15 9 Packing Information 16 List of Figures 1 2 3 4 5 6 7 BGS15M2A12 Block diagram . . . . . . . . . . . . . . . . MIPI to RF Time . . . . . . . . . . . . . . . . . . . . . . . BGS15M2A12 Pin Configuration (top view) . . . . . . . . ATSLP-12-5 Package Outline (top, side and bottom views) Land Pattern and Stencil Mask . . . . . . . . . . . . . . . Marking Layout (top view) . . . . . . . . . . . . . . . . . . ATSLP-12-5 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 14 15 15 16 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 7 8 8 9 10 10 11 11 11 13 14 List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 Ordering Information . . . . Maximum Ratings, Table I . Maximum Ratings, Table II . Operation Ranges . . . . . RF Input Power . . . . . . . RF Characteristics . . . . . IMD2 Testcases . . . . . . IMD3 Testcases . . . . . . MIPI Features . . . . . . . . Startup Behavior . . . . . . Register Mapping . . . . . . Truth Table, Register_0 . . Pin Definition and Function Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision 3.0 - 2016-02-22 BGS15M2A12 BGS15M2A12 SP5T Diversity Antenna Switch with MIPI RFFE Interface 1 Features • Suitable for multi-mode LTE / WCDMA diversity Applications • Ultra-low insertion loss and harmonics generation • 5 high-linearity, interchangeable RX ports • 0.1 to 2.7 GHz coverage • High port-to-port-isolation • No decoupling capacitors required if no DC applied on RF lines • Integrated MIPI RFFE interface operating in 1.1 to 1.95 V voltage range • Software programmable MIPI RFFE USID • Small form factor 1.1 mm x 1.9 mm • No power supply blocking required • High EMI robustness • RoHS and WEEE compliant package 2 Product Description The BGS15M2A12 RF MOS switch is specifically designed for LTE and WCDMA diversity applications. This SP5T offers low insertion loss and low harmonic generation. The switch is controlled via a MIPI RFFE controller. The on-chip controller allows power-supply voltages from 1.1 to 1.95 V. Unlike GaAs technology, external DC blocking capacitors at the RF Ports are only required if DC voltage is applied externally. The BGS15M2A12 RF Switch is manufactured in Infineon’s patented MOS technology, offering the performance of GaAs with the economy and integration of conventional CMOS including the inherent higher ESD robustness. The device has a very small size of only 1.1 x 1.9 mm2 and a maximum height of 0.65 mm. Table 1: Ordering Information Type Package Marking BGS15M2A12 ATSLP-12-5 55 Data Sheet 5 Revision 3.0 - 2016-02-22 BGS15M2A12 RX01 RX02 ANT RX03 RX04 RX05 SP5T VIO VDD SCLK MIPI-RFFE Controller SDATA SSEL1 GND SSEL2 Figure 1: BGS15M2A12 Block diagram 3 Maximum Ratings Table 2: Maximum Ratings, Table I at TA = 25 ◦C, unless otherwise specified Parameter Symbol Min. Typ. Max. Frequency Range f 0.1 – Supply voltage VDD -0.5 – Storage temperature range TSTG Values -55 – Unit Note / Test Condition – GHz 1) 3.6 V – 150 ◦ C – C – Junction temperature Tj – – 125 ◦ RF input power at all Rx ports PRF_Rx – – 32 dBm CW VESD_HBM -1 – +1 kV Digital, digital versus RF -1 – +1 kV RF -8 – +8 kV ANT versus system GND, 3) ESD capability, HBM 4) ESD capability, system level VESD_ANT with 27 nH shunt inductor 1) There is also a DC connection between switched paths. The DC voltage at RF ports VRFDC has to be 0V. 3) Human Body Model ANSI/ESDA/JEDEC JS-001-2012 (R=1.5 kΩ, C=100 pF). 4) IEC 61000-4-2 (R=330 Ω, C=150 pF), contact discharge. Data Sheet 6 Revision 3.0 - 2016-02-22 BGS15M2A12 Table 3: Maximum Ratings, Table II at TA = 25 ◦C, unless otherwise specified Parameter Maximum DC-voltage on RF- Symbol VRFDC Values Min. Typ. Max. 0 – 0 Unit Note / Test Condition V No DC voltages allowed on Ports and RF-Ground RF-Ports RFFE Supply Voltage VIO -0.5 – RFFE Control Voltage Levels VSCLK, -0.7 – VSDATA 3.6 V – VIO+0.7 V – (max. 3.6) Data Sheet 7 Revision 3.0 - 2016-02-22 BGS15M2A12 4 Operation Ranges Table 4: Operation Ranges Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. VDD 1.6 – 3.4 V – Supply current IDD – 75 200 µA – Supply current in standby IDD – 0.5 1 µA VIO=low or MIPI low-power Supply voltage 2) 2) mode mode RFFE supply voltage VIO 1.1 1.8 1.95 V – VIH 0.7*VIO – VIO V – RFFE input low voltage VIL 0 – 0.3*VIO V – RFFE output high voltage1) VOH 0.8*VIO – VIO V – RFFE output low voltage VOL 0 – 0.2*VIO V – RFFE control input capaci- CCtrl – – 2 pF – IVIO – 15 – µA Idle State 85 ◦ – 1) RFFE input high voltage 1) 1) tance RFFE supply current Ambient temperature TA -30 25 C 1) SCLK and SDATA 2) T = −30 ◦C ... 85 ◦C, V A DD = 1.6 ... 3.4 V Table 5: RF Input Power Parameter Rx ports (50 Ω) Data Sheet Symbol PRF_Rx Values Min. Typ. Max. – – 28 8 Unit Note / Test Condition dBm – Revision 3.0 - 2016-02-22 BGS15M2A12 5 RF Characteristics Table 6: RF Characteristics at TA = −30 ◦C...85 ◦C, PIN = 0 dBm, Supply Voltage VDD= 1.6 V...3.4 V, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. – 0.30 0.40 dB 100 to 1000MHz – 0.35 0.50 dB 1000 to 2000MHz – 0.40 0.55 dB 2000 to 2700MHz – 0.55 0.75 dB 2700 to 3800MHz 25 31 – dB 100 to 1000MHz 22 28 – dB 1000 to 2000MHz 20 26 – dB 2000 to 2700MHz 14 20 – dB 2700 to 3800MHz 28 38 – dB 100 to 1000MHz 23 34 – dB 1000 to 2000MHz 20 30 – dB 2000 to 2700MHz 27 – dB 2700 to 3800MHz -100 -95 dBc 25 dBm, 50 Ω, CW mode -90 -85 dBc 25 dBm, 50 Ω, CW mode 1) Insertion Loss IL All Rx Ports 1) Return Loss All Rx Ports RL 1) Isolation All Rx Ports ISO 18 1) Harmonic Generation (UMTS Band 1, Band 5) 2nd harmonic generation rd 3 harmonic generation PH2 – PH3 – 1) Intermodulation Distortion (UMTS Band 1, Band 5) 2nd order intermodulation IMD2 low – -105 -100 dBm IMT, US Cell (see Tab. 7) order intermodulation IMD3 – -110 -105 dBm IMT, US Cell (see Tab. 8) order intermodulation IMD2 high – -115 -110 dBm IMT, US Cell (see Tab. 7) MIPI to RF time1) tINT – 1.5 2 µs Power up settling time1) tPUP – 10 25 µs rd nd 3 2 Switching Time 1) On 50 % last SCLK falling edge to 90 % ON, see Fig. 2 After power down mode application board without any matching components. Data Sheet 9 Revision 3.0 - 2016-02-22 BGS15M2A12 Table 7: IMD2 Testcases Band CW tone 1 (MHz) CW tone 1 (dBm) IMT 1950 20 US Cell 835 20 CW tone 2 (MHz) 190 (IMD2 low) 4090 (IMD2 high) 45 (IMD2 low) 1715 (IMD2 high) CW tone 2 (dBm) -15 -15 Table 8: IMD3 Testcases Band CW tone 1 (MHz) CW tone 1 (dBm) CW tone 2 (MHz) CW tone 2 (dBm) IMT 1950 20 1760 -15 US Cell 835 20 790 -15 SDATA TINT SCLK 90% RF Signal Figure 2: MIPI to RF Time Data Sheet 10 Revision 3.0 - 2016-02-22 BGS15M2A12 6 MIPI RFFE Specification All sequences are implemented according to the ’MIPI Alliance Specification for RF Front-End Control Interface’ document version 1.10 - 26. July 2011. Table 9: MIPI Features Feature Supported Register write command sequence Yes Comment Register read command sequence Yes Extended register write command sequence No Up to 4 Bytes Extented register read command sequence No Up to 4 Bytes Register 0 write command sequence Yes Trigger function Yes Trigger assignment to each control register is supported Programmable USID Yes 3 register command sequence Status Register Yes Register for debugging Reset Yes By VIO, Power Mode and RFFE_STATUS Group SID Yes SSEL1 and SSEL2 pins Yes External pins for changing USID: SSEL1=0 & SSEL2=0 → 1000, SSEL1=0 & SSEL2=1 → 1010, SSEL1=1 & SSEL2=0 → 1001, SSEL1=1 & SSEL2=1 → 1011 To be connected to VIO or GND Full speed write Yes Half speed read Yes Full speed read Yes Table 10: Startup Behavior Feature State Comment Power status ACTIVE The chip is in active mode after startup. RF-mode is ’All Isolation’ Trigger function ENABLED Trigger function is enabled after startup. Trigger function can be disabled via PM_TRIG register. Table 11: Register Mapping Register Address 0x0000 0x001D Register Name REGISTER_0 PRODUCT_ID Data Sheet Data Bits 7:0 7:0 Function Description MODE_CTRL PRODUCT_ID Switch control This is a read-only register. However, during the programming of the USID a write command sequence is performed on this register, even though the write does not change its value. 11 Default 00000000 11010100 Broadcast_ID Support No No Trigger Support Yes No R/W R/W R Revision 3.0 - 2016-02-22 BGS15M2A12 Table 11: Register Mapping – Continued from previous page Register Address 0x001E Register Name 0x001C 0x001F 0x001A Function Description MANUFACTURER_ID Data Bits 7:0 MANUFACTURER_ID [7:0] PM_TRIG 7:6 PWR_MODE This is a read-only register. However, during the programming of the USID, a write command sequence is performed on this register, even though the write does not change its value. 00: Normal operation 01: Default settings (STARTUP) 10: Low power (LOW POWER) 11: Reserved If this bit is set, trigger 2 is disabled. When all triggers disabled, if writing to a register that is associated to trigger 2, the data goes directly to the destination register. If this bit is set, trigger 1 is disabled. When all triggers disabled, if writing to a register that is associated to trigger 1, the data goes directly to the destination register. If this bit is set, trigger 0 is disabled. When all triggers disabled, if writing to a register that is associated to trigger 0, the data goes directly to the destination register. A write of a one to this bit loads trigger 2’s registers. A write of a one to this bit loads trigger 1’s registers. A write of a one to this bit loads trigger 0’s registers. These are read-only bits that are reserved and yield a value of 0b00 at readback. These bits are read-only. However, during the programming of the USID, a write command sequence is performed on this register even though the write does not change its value. Programmable USID. Performing a write to this register using the described programming sequences will program the USID in devices supporting this feature. These bits store the USID of the device. 0: Normal operation 1: Software reset Command sequence received with parity error - discard command. Command length error Address frame parity error = 1 MAN_USID RFFE_STATUS 5 TRIGGER_MASK_2 4 TRIGGER_MASK_1 3 TRIGGER_MASK_0 2 TRIGGER_2 1 TRIGGER_1 0 TRIGGER_0 7:6 5:4 MANUFACTURER_ID [9:8] 3:0 USID 7 SOFTWARE RESET 6 COMMAND_FRAME_ PARITY_ERR COMMAND_LENGTH_ERR ADDRESS_FRAME_ PARITY_ERR DATA_FRAME_ PARITY_ERR 5 4 3 Data Sheet SPARE Data frame with parity error 12 Default 00011010 Broadcast_ID Support No Trigger Support No 00 Yes No 0 No No 0 No No 0 No No 0 Yes No 0 Yes No 0 Yes No 00 No No R/W R R/W R/W 01 See Tab. 9 0 No No 0 No No 0 0 R/W R 0 Revision 3.0 - 2016-02-22 BGS15M2A12 Table 11: Register Mapping – Continued from previous page Register Address 0x001B Register Name GROUP_SID Data Bits 2 1 0 Function Description Default READ_UNUSED_REG WRITE_UNUSED_REG BID_GID_ERR Read command to an invalid address Write command to an invalid address Read command with a BROADCAST_ID or GROUP_SID 7:4 3:0 RESERVED GROUP_SID Trigger Support R/W No R/W 0 0 0 0 0 Group slave ID Broadcast_ID Support No Table 12: Modes of Operation (Truth Table, Register_0) REGISTER_0 Bits State Mode D7 D6 D5 D4 D3 D2 D1 D0 1 Isolation x x x x x 0 0 0 2 RX01 x x x x x 0 0 1 3 RX02 x x x x x 0 1 0 4 RX03 x x x x x 0 1 1 5 RX04 x x x x x 1 0 0 6 RX05 x x x x x 1 0 1 Data Sheet 13 Revision 3.0 - 2016-02-22 BGS15M2A12 7 Pin Configuration and Function 1 12 11 13 2 3 10 4 5 9 8 6 7 Figure 3: BGS15M2A12 Pin Configuration (top view) Table 13: Pin Definition and Function Pin No. Name Function 1 SLK MIPI RFFE clock 2 VIO MIPI RFFE power supply 3 RX05 RX port 5 4 RX04 RX port 4 5 RX03 RX port 3 6 RX02 RX port 2 7 RX01 RX port 1 8 SSEL1 MIPI USID select port 1 (to be connected to VIO or GND) 9 SSEL2 MIPI USID select port 2 (to be connected to VIO or GND) 10 ANT Antenna port 11 VDD Power supply 12 SDATA MIPI RFFE data 13 GND RF ground Data Sheet 14 Revision 3.0 - 2016-02-22 BGS15M2A12 8 Package Information Top view Bottom view Pin 1 marking 7 8 0.2 ±0.05 12x 9 6 5 11 4 12 0.4 B 10 3 2 1 0.1 A 0.1 A 0.1 B 0.1 B 0.2 ±0.05 0.2 ±0.05 12x 4 x 0.4 = 1.6 A 0.4 0.05 MAX. STANDOFF 1.9 ±0.05 1.1±0.05 0.75 ±0.05 0.6 ±0.05 2 x 0.4 = 0.8 Figure 4: ATSLP-12-5 Package Outline (top, side and bottom views) 0.4 0.4 0.25 0.8 0.4 0.4 0.8 0.25 0.25 0.25 0.25 Copper Solder mask Stencil apertures Figure 5: Land Pattern and Stencil Mask Data Sheet 15 Revision 3.0 - 2016-02-22 BGS15M2A12 12 Type code Date code (YW) Pin 1 marking Figure 6: Marking Layout (top view) 9 Packing Information 4 2.1 Pin 1 marking 8 0.75 1.3 Figure 7: ATSLP-12-5 Carrier Tape Data Sheet 16 Revision 3.0 - 2016-02-22 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG