2FAD-C20R

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LA N IA
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Features
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Lead free versions available
RoHS compliant (lead free version)*
New Product Development
Integrated Passive Device
RF Low Pass Filter Performance
ESD Protection to IEC61000-4-2 Spec.
2FAD-C20R Series - Integrated Passive & Active Device using CSP
General Information
The 2FAD-C20R devices, manufactured using Thin Film
On Silicon technology provide ESD protection and EMI
filtering for the data port of portable electronic devices
such as cell phones, modems and PDAs. The device
incorporates six low pass filter channels. Each channel
has a series 100 ohm resistor assuring a minimum of
-30 dB attenuation from 800 MHz to 3 GHz. The device
is suitable for EMI filtering of GSM, CDMA, W-CDMA,
WLAN and Bluetooth frequencies.
SOLDER
BUMPS
SILICON
DIE
Each external port of the six channels includes a back-toback 6.5 Volt Zener diode for ESD protection. Two
additional standalone 6.5 Volt Zener diodes are available
for ESD protection on power lines or USB data ports. The
ESD protection provided by the component enables an
eight line data port to withstand a minimum ±8 KV
Contact / ±15 KV Air Discharge when tested according to
the ESD method specified in IEC 61000-4-2. The device
measures 2.04 mm x 2.64 mm and is available in a 20 pin
(4 x 5 array) CSP package intended to be mounted
directly onto an FR4 printed circuit board. The CSP
device meets typical thermal cycle and bend test
specifications without the use of an underfill material.
E
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Figure 1 – CSP Format
Electrical & Thermal Characteristics
Electrical Characteristics
(TA = 25 °C unless otherwise noted)
Zener Diode
Breakdown Voltage @ 1 mA
Leakage Current @ 3 V
ESD Performance (Note 1 & 2)
Withstand: Contact Discharge
Withstand: Air Discharge
Let Through: Contact Discharge
Let Through: Air Discharge
Channel Specification
Resistance
Capacitance @ 1 V & 1 MHz
Filter Attenuation: 800 MHz – 3000 MHz
Symbol
Minimum
Nominal
Maximum
Unit
VBR
IR
6
7.2
8
1
V
uA
±150
±150
kV
kV
V
V
±8
±15
R
C
90
110
55
-30
100
50
-40
Ω
pF
dB
-40
-60
25
25
+85
+125
100
°C
°C
mW
Thermal Characteristics
(TA = 25 °C unless otherwise noted)
Operating Temperature
Storage Temperature
Total Power Dissipation @ 70 °C
Note:
TJ
Tstg
PD
1. The IEC 61000-4-2 test method will be adapted for component level testing. The device will provide the specified ESD protection
performance on the “EXT1 – EXT8” pins only.
2. “Let Through” is a measure of the component of an incident ESD transient that the protection device allows through to the
downstream circuitry.
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAD-C20R Series - Integrated Passive & Active Device using CSP
Mechanical Characteristics
This is a Silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the Silicon die,
provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is
0.5 mm and the dimensions for the CSP packaged device are shown in Fig. 2 below.
248.5 ± 45
(9.78 ± 1.78)
858 ± 40
(33.78 ± 1.57)
BUMP A1/PIN 1
INDICATOR
A1
BOURNS
LOGO
B1
A2
B2
C1
D1
C2
D2
300
DIA.
(11.81)
500
(19.69)
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A3
B3
C3
A4
B4
C4
D3
2597 ± 45
(102.24 ± 1.78)
D4
500
(19.69)
A5
225 ± 20
(8.86 ± 0.79)
348.5 ± 45
(13.72 ± 1.78)
B5
248.5 ± 45
(9.78 ± 1.78)
C5
D5
45 ± 45
(1.78 ± 1.78)
45 ± 45
(1.78 ± 1.78)
1997 ± 45
(78.62 ± 1.78)
DIMENSIONS =
MICRONS
(MILS)
Fig. 2 – Device Mechanical Drawing
Reliability
Reliability data exists and continues to be gathered on an ongoing basis for Bourns Integrated Passive and Active Devices using CSP
packaging.
“Package level” testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy
Chain component is available from Bourns for this purpose. (Part No: 2TAD-C25R) This is a 5 x 5 array, featuring 0.5 mm pitch solder
bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2FAD-C20R and is thus deemed a worse
case for Thermal Cycle testing.
“Silicon level” reliability performance will be assured by similarity to other integrated passive CSP devices from Bourns.
Individual Channel Schematic
This section contains the schematic (See Fig. 3 below) for the single channel in the integrated passive device. Note that the electrical
parameters of primary interest are (a) DC Resistance (b) ESD performance and (c) low pass filter attenuation. In terms of DC
parameters it should be noted that all resistor values have a tolerance of ±10 %. This schematic consists of a series 100 ohm
resistance and two Back to Back Zener 6.5 Volt diodes for ESD protection.
Key Design Parameters
Source Impedance: 50 Ω
100 Ω
EXT1 - EXT6
INT1 - INT6
Load Impedance: 50 Ω
DC Channel Resistance: 100 Ω ±10 %
±6.5 V
Channel Capacitance: 55 pF Max @ 1 V & 1 MHz
VBR: 6 V Min, 8 V Max @ IBR = 1 mA.
IR: 1 uA Max @ VR = 3 V
Filter Attenuation: -30 dB Minimum
Fig. 3 - Channel Schematic
@ 800 MHz - 3000 MHz
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAD-C20R Series - Integrated Passive & Active Device using CSP
Block Diagram
Marking
Figure 4 contains a block diagram of the CSP device. This diagram includes the pin
names and basic electrical connections associated with each channel.
100 Ω
EXT1
INT1
The device will be laser marked on the
backside according to the following
Fig. 5 scheme below. Position A1, on
the Bump Grid is located at the top left
of the die when the die is orientated so
that the mark is read in the normal fashion.
±6.5 V
PIN A1
LOCATION
1 2 3 4 5
A
100 Ω
EXT2
±6.5 V
FAD
B
INT2
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Lotcode
C
D
100 Ω
EXT3
INT3
±6.5 V
Fig. 5 – Backside Laser Mark
PCB Design and SMT Processing
100 Ω
EXT4
INT4
±6.5 V
Please consult Bourns’ Thin Film on
Silicon using CSP Users Guide
Application Note for notes on PCB
design and SMT processing.
2FAD-C20R Frequency Response
100 Ω
EXT5
INT5
±6.5 V
0
-20
-40
100 Ω
EXT6
1 MHz
700 MHz
3 GHz
-6 dB
-50 dB
-34 dB
INT6
±6.5 V
-60
1.0 MHz
GROUND
x6
±6.5 V
10 MHz
100 MHz
FREQUENCY
2 FAD - C20R ____
Thinfilm
Model
Chipscale
No. of Solder Bumps
EXT8
Fig. 4 – Device Block Diagram
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
5.0 GHz
How to Order
±6.5 V
EXT7
1.0 GHz
Packaging Option
R = Tape and Reel
Packaged 3000 pcs. / 7 ” reel
Terminations
LF = Sn/Ag/Cu (lead free)
Blank = Sn/Pb
2FAD-C20R Series - Integrated Passive & Active Device using CSP
Device Pin Out
The Pin-Out for the device is shown in Fig. 6. Note also that the device is shown with bumps facing up.
INT3
INT4
INT5
D
INT2
INT6
C
EXT8
INT1
B
GROUND X 6
A
EXT2
EXT6
1
EXT3
2
3
4
EXT4
Function
INT1
Ground
Ground
Ground
EXT8
INT2
INT3
INT4
INT5
INT6
Pin Out
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
5
EXT5
Fig. 6 (a) - Device Pin Out “Bumps Up” View
Packaging
Pin Out
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
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EXT7
EXT1
Function
EXT2
EXT3
EXT4
EXT5
EXT6
EXT1
Ground
Ground
Ground
EXT7
Fig. 6 (b) - Pin Listings
The product will be dispensed in an 8 mm x 4 mm Tape and Reel format - see Fig. 7 diagram below. The Tape and Reel package will
conform to customer specification.
0.3 ± 0.05
(.01 ± .002)
4.0 ± 0.1
(.16 ± .004)
1.5 ± 0.1/-0
(.06 ± .004/-0)
DIA.
2.0 ± 0.05
(.08 ± .002)
R
1.75 ± 0.1
(.07 ± .004)
0.3
MAX.
(0.01)
0.9 ± 0.05
(.04 ± .002)
8.0 ± 0.3
(.31 ± .01)
2.77 ± 0.05
(.11 ± .002)
3.5 ± 0.05
(.14 ± .002)
2.19 ± 0.05
(.09 ± .002)
4.0 ± 0.1
(.16 ± .004)
ORIENTATION
OF COMPONENT
IN POCKET
R 0.25 TYP.
(0.001)
DIMENSIONS =
Fig. 7 - Tape and Reel Drawing
BACKSIDE FACING UP
MILLIMETERS
(INCHES)
Reliable Electronic Solutions
Asia-Pacific: TEL +886- (0)2 25624117 • FAX +886- (0)2 25624116
Europe: TEL +353 214 515 225 • FAX +353 214 515 292
The Americas: TEL +1-951 781-5492 • FAX +1-951 781-5700
www.bourns.com
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAD-C20R REV. D, 02/05
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