2FAF-C10R

oH
VE S CO
AV R M
AI SIO PL
LA N IA
BL S NT
E
Features
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*R
■
■
■
■
Applications
Lead free versions available
RoHS compliant (lead free version)*
Bidirectional EMI filtering
ESD protection > 25 k volts
Protects 4 data lines
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■
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Cell phones
PDAs and notebooks
Digital cameras
MP3 players and GPS
2FAF-C10R - Integrated Passive & Active Device
General Information
The 2FAF-C10R device, manufactured using Thin Film on Silicon
technology, provides ESD protection and EMI filtering for the data
ports of portable electronic devices such as cell phones, modems
and PDAs. The device incorporates four low pass filter channels
where each channel has a series 100 ohm resistor assuring a
minimum of –28 dB attenuation from 800 MHz to 3 GHz. The device
is suitable for EMI filtering of GSM, CDMA, W-CDMA, WLAN and
Bluetooth frequencies.
Each internal and external port of the four channels includes a TVS
diode for ESD protection. The ESD protection provided by the
component enables a data port to withstand a minimum ±8 KV
Contact / ±15 KV Air Discharge per the ESD test method specified in
IEC 61000-4-2. The device measures 1.33 mm x 2 mm and is
available in a 10 bump CSP package intended to be mounted directly
onto an FR4 printed circuit board. The CSP device meets typical
thermal cycle and bend test specifications without the use of an
underfill material.
SOLDER
BUMPS
SILICON
DIE
E
T
E
L
O
S
B
O
Electrical Characteristics (@ TA = 25 °C Unless Otherwise Noted)
Per Line Specification
Resistance
Capacitance @ 2.5 V, 1 MHz
Rated Standoff Voltage
Breakdown Voltage @ 1 mA
Forward Voltage @ 10 mA
Leakage Current @ 3.3 V
Filter Attenuation @ 800-3000 MHz
Symbol
Min.
Nom.
Max.
Unit
R
80
100
120
—
C
24
30
36
pF
VWM
VBR
0.8
IR
0.05
S21
V
6.0
VF
ESD Protection: IEC 61000-4-2
Contact Discharge
Air Discharge
Power Dissipation per Resistor
5.0
-28
V
V
0.1
-35
µA
dB
±8
±15
kV
kV
PD
100
mW
Thermal Characteristics (@ TA = 25 °C Unless Otherwise Noted)
Parameter
Operating Temperature Range
Storage Temperature Range
Symbol
Min.
Nom.
Max.
Unit
TJ
-40
+25
+85
°C
TSTG
-55
+25
+150
°C
*RoHS Directive 2002/95/EC Jan 27 2003, including Annex
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAF-C10R - Integrated Passive & Active Device
Mechanical Characteristics
This is a silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the silicon die,
provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is
0.5 mm and the dimensions for the packaged device are shown below.
0.3
DIA.
(0.012)
0.245 - 0.255
(0.0096 - 0.0100)
C1
A1
B2
C3
A3
1.981 - 2.032
(0.0780 - 0.0800)
E
T
E
L
O
S
B
O
0.495 - 0.505
(0.0195 - 0.0199)
0.432 - 0.559
(0.017 - 0.022)
A4
1.285 - 1.375
(0.0506 - 0.0541)
C4
B5
0.180 - 0.280
(0.0071 - 0.0110)
0.330 - 0.457
(0.013 - 0.018)
A6
C6
0.180 - 0.280
(0.0071 - 0.0110)
0.430 - 0.440
(0.0169 - 0.0173)
DIMENSIONS =
MILLIMETERS
(INCHES)
0.430 - 0.440
(0.0169 - 0.0173)
1.285 - 1.375
(0.0506 - 0.0541)
Reliability Data
Reliability data is gathered on an ongoing basis for Bourns® Integrated Passive and Active Devices.
“Package level” testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy
Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5 mm pitch
solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2FAF-C10R and is thus deemed
suitable for Thermal Cycle testing.
“Silicon level” reliability performance is based on similarity to other integrated passive CSP devices from Bourns.
Frequency Response
0
Loss - dB
-10
-20
-30
-40
-50
-60
0.1
1.0
10.0
100.0
1000.0
1000.0
Frequency - MHz
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAF-C10R - Integrated Passive & Active Device
Block Diagram
PCB Design and SMT Processing
The CSP device block diagram below includes the pin names and basic electrical
connections associated with each channel.
EXT1
R1:
100 ohms
Please consult the “Bourns Design
Guide Using CSP” for notes on PCB
design and SMT Processing.
INT1
How to Order
2 FAF - C10R __
GND
Thinfilm
E
T
E
L
O
S
B
O
Model
Chipscale
EXT2
INT2
Packaging Option
R = Tape and Reel
Packaged 5000 pcs. / 7 ˝ reel
R2:
100 ohms
EXT3
GND
EXT4
R3:
100 ohms
INT3
INT4
R4:
100 ohms
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
No. of Solder Bumps
Terminations
LF = Sn/Ag/Cu (lead free)
__ = Sn/Pb
2FAF-C10R - Integrated Passive & Active Device
Device Pin Out
The Pin-Out for the device is shown below. Note also that the device is shown with bottom side solder pads facing up.
A
B
C
1
EXT1
INT1
2
EXT2
INT2
3
4
EXT3
5
EXT4
6
Packaging
Pin Out
A1
A3
A4
A6
B2
GND
Function
EXT1
EXT2
EXT3
EXT4
GND
Pin Out
C1
C3
C4
C6
B5
E
T
E
L
O
S
B
O
Function
INT1
INT2
INT3
INT4
GND
INT3
GND
INT4
The surface mount product is packaged in an 8 mm x 4 mm Tape and Reel format per EIA-481 standard.
TOP SIDE VIEW
(INTO COMPONENT POCKET)
DIMENSIONS =
0.3 ± 0.05
(.01 ± .002)
4.0 ± 0.1
(.16 ± .004)
1.5 ± 0.1/-0
(.06 ± .004/-0)
DIA.
2.0 ± 0.05
(.08 ± .002)
R
MILLIMETERS
(INCHES)
1.75 ± 0.1
(.07 ± .004)
0.3
MAX.
(0.01)
0.76 ± 0.1
(.03 ± .004)
8.0 ± 0.3
(.31 ± .01)
1.52 ± 0.1
(.06 ± .004)
3.50 ± 0.05
(.14 ± .002)
1.18 ± 0.1
(0.05 ± 0.004)
4.0 ± 0.1
(.16 ± .004)
ORIENTATION
OF COMPONENT
IN POCKET
R 0.25 TYP.
(0.010)
BACKSIDE FACING UP
Reliable Electronic Solutions
Asia-Pacific:
TEL +886- (0)2 25624117 • FAX +886- (0)2 25624116
Europe:
TEL +41-41 768 5555 • FAX +41-41 768 5510
The Americas: TEL +1-951 781-5492 • FAX +1-951 781-5700
www.bourns.com
COPYRIGHT© 2005, BOURNS, INC. LITHO IN U.S.A. 08/04 e/IPA0411
2FAF-C10R REV. B, 03/05
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
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