BS67F3x0v120.pdf

Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
BS67F340/BS67F350/BS67F360
Revision: V1.20
Date: ������������
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Table of Contents
Features................................................................................................................. 7
CPU Features...............................................................................................................................7
Peripheral Features.......................................................................................................................8
General Description.............................................................................................. 9
Selection Table...................................................................................................... 9
Block Diagram..................................................................................................... 10
Pin Assignment................................................................................................... 10
Pin Descriptions................................................................................................. 15
Absolute Maximum Ratings............................................................................... 27
D.C. Characteristics............................................................................................ 28
A.C. Characteristics............................................................................................ 29
A/D Converter Characteristics........................................................................... 30
Temperature Sensor Electrical Characteristics............................................... 31
LVD/LVR Electrical Characteristics................................................................... 31
LCD Driver Electrical Characteristics............................................................... 32
Touch Key Electrical Characteristics................................................................ 32
Power-on Reset Characteristics........................................................................ 34
System Architecture........................................................................................... 35
Clocking and Pipelining...............................................................................................................35
Program Counter.........................................................................................................................36
Stack...........................................................................................................................................37
Arithmetic and Logic Unit – ALU.................................................................................................37
Flash Program Memory...................................................................................... 38
Structure......................................................................................................................................38
Special Vectors...........................................................................................................................38
Look-up Table..............................................................................................................................39
Table Program Example..............................................................................................................39
In Circuit Programming – ICP.....................................................................................................40
On-Chip Debug Support – OCDS...............................................................................................41
In Application Programming – IAP..............................................................................................41
Data Memory....................................................................................................... 53
Structure......................................................................................................................................53
Data Memory Addressing............................................................................................................54
General Purpose Data Memory..................................................................................................54
Special Purpose Data Memory...................................................................................................54
Rev. 1.20
2
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Special Function Register Description............................................................. 58
Indirect Addressing Registers − IAR0, IAR1, IAR2.....................................................................58
Memory Pointers − MP0, MP1H/MP1L, MP2H/MP2L.................................................................58
Program Memory Bank Pointer – PBP........................................................................................60
Accumulator − ACC.....................................................................................................................60
Program Counter Low Register − PCL........................................................................................60
Look-up Table Registers – TBLP, TBHP, TBLH..........................................................................60
Status Register − STATUS..........................................................................................................61
EEPROM Data Memory....................................................................................... 63
EEPROM Data Memory Structure..............................................................................................63
EEPROM Registers....................................................................................................................63
Reading Data from the EEPROM...............................................................................................65
Writing Data to the EEPROM......................................................................................................65
Write Protection...........................................................................................................................65
EEPROM Interrupt......................................................................................................................65
Programming Considerations......................................................................................................66
Oscillator............................................................................................................. 67
Oscillator Overview.....................................................................................................................67
System Clock Configurations......................................................................................................67
External Crystal/Ceramic Oscillator − HXT.................................................................................68
Internal High Speed RC Oscillator − HIRC.................................................................................69
External 32.768 kHz Crystal Oscillator − LXT.............................................................................69
Internal 32kHz Oscillator − LIRC.................................................................................................70
Operating Modes and System Clocks.............................................................. 71
System Clocks............................................................................................................................71
System Operation Modes............................................................................................................72
Control Registers........................................................................................................................73
Operating Mode Switching..........................................................................................................76
Standby Current Considerations.................................................................................................80
Wake-up......................................................................................................................................80
Watchdog Timer.................................................................................................. 81
Watchdog Timer Clock Source....................................................................................................81
Watchdog Timer Control Register...............................................................................................81
Watchdog Timer Operation.........................................................................................................82
Reset and Initialisation....................................................................................... 83
Reset Functions..........................................................................................................................83
Reset Initial Conditions...............................................................................................................87
Rev. 1.20
3
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Input/Output Ports.............................................................................................. 93
Pull-high Resistors......................................................................................................................94
Port A Wake-up...........................................................................................................................95
I/O Port Control Registers...........................................................................................................95
Pin-shared Functions..................................................................................................................95
I/O Pin Structures......................................................................................................................106
Programming Considerations....................................................................................................107
Timer Modules – TM......................................................................................... 107
Introduction...............................................................................................................................107
TM Operation............................................................................................................................108
TM Clock Source.......................................................................................................................108
TM Interrupts.............................................................................................................................108
TM External Pins.......................................................................................................................108
TM Input/Output Pin Selection..................................................................................................109
Programming Considerations.................................................................................................... 110
Compact Type TM – CTM................................................................................. 111
Compact TM Operation............................................................................................................. 111
Compact Type TM Register Description................................................................................... 112
Compact Type TM Operation Modes........................................................................................ 116
Standard Type TM – STM................................................................................. 122
Standard TM Operation.............................................................................................................122
Standard Type TM Register Description...................................................................................123
Standard Type TM Operation Modes........................................................................................127
Periodic Type TM – PTM................................................................................... 137
Periodic TM Operation..............................................................................................................137
Periodic Type TM Register Description.....................................................................................138
Periodic Type TM Operation Modes..........................................................................................142
Analog to Digital Converter............................................................................. 151
A/D Overview............................................................................................................................151
Registers Descriptions..............................................................................................................152
A/D Operation...........................................................................................................................158
A/D Reference Voltage..............................................................................................................159
A/D Input Pins...........................................................................................................................159
Conversion Rate and Timing Diagram......................................................................................159
Summary of A/D Conversion Steps...........................................................................................160
Programming Considerations....................................................................................................161
A/D Transfer Function...............................................................................................................161
A/D Programming Examples.....................................................................................................162
Rev. 1.20
4
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Serial Interface Module – SIM.......................................................................... 164
SPI Interface.............................................................................................................................164
SPI Registers............................................................................................................................165
SPI Communication..................................................................................................................168
I2C Interface..............................................................................................................................170
I2C Registers.............................................................................................................................171
UART Interface.................................................................................................. 180
UART External Pin....................................................................................................................181
UART Data Transfer Scheme...................................................................................................181
UART Status and Control Registers.........................................................................................181
Baud Rate Generator................................................................................................................187
UART Setup and Control..........................................................................................................188
UART Transmitter.....................................................................................................................189
UART Receiver.........................................................................................................................190
Managing Receiver Errors........................................................................................................192
UART Interrupt Structure..........................................................................................................193
UART Power Down and Wake-up.............................................................................................194
LCD Driver......................................................................................................... 195
LCD Memory.............................................................................................................................196
LCD Clock Source.....................................................................................................................198
LCD Register.............................................................................................................................198
LCD Voltage Source and Biasing..............................................................................................200
LCD Reset Function..................................................................................................................201
LCD Driver Output.....................................................................................................................202
Programming Considerations....................................................................................................205
Touch Key Function......................................................................................... 205
Touch Key Structure..................................................................................................................205
Touch Key Register Definition...................................................................................................207
Touch Key Operation.................................................................................................................214
Touch Key Interrupt...................................................................................................................220
Progrsmming Considerations....................................................................................................220
Low Voltage Detector – LVD............................................................................ 221
LVD Register.............................................................................................................................221
LVD Operation...........................................................................................................................222
Rev. 1.20
5
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Interrupts........................................................................................................... 223
Interrupt Registers.....................................................................................................................223
Interrupt Operation....................................................................................................................230
External Interrupt.......................................................................................................................231
Touch Key Interrupt...................................................................................................................232
UART Transfer Interrupt............................................................................................................232
A/D Converter Interrupt.............................................................................................................232
Multi-function Interrupt..............................................................................................................232
Time Base Interrupt...................................................................................................................233
Serial Interface Module Interrupt...............................................................................................235
LVD Interrupt.............................................................................................................................235
EEPROM Interrupt....................................................................................................................235
TM Interrupt...............................................................................................................................235
Interrupt Wake-up Function.......................................................................................................236
Programming Considerations....................................................................................................236
Application Circuits.......................................................................................... 237
Instruction Set Summary................................................................................. 238
Table Conventions.....................................................................................................................238
Extended Instruction Set...........................................................................................................240
Instruction Definition........................................................................................ 242
Extended Instruction Definition.................................................................................................251
Package Information........................................................................................ 258
48-pin LQFP (7mm × 7mm) Outline Dimensions......................................................................259
64-pin LQFP (7mm × 7mm) Outline Dimensions......................................................................260
Rev. 1.20
6
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Features
CPU Features
• Operating voltage
♦♦
fSYS= 4MHz: 2.2V~5.5V
♦♦
fSYS= 8MHz: 2.4V~5.5V
♦♦
fSYS= 12MHz: 2.7V~5.5V
♦♦
fSYS= 16MHz: 3.3V~5.5V
♦♦
fSYS= 20MHz: 4.5V~5.5V
• Up to 0.2μs instruction cycle with 20MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Oscillator type
♦♦
External High Speed Crystal – HXT
♦♦
Internal High Speed RC – HIRC
♦♦
External 32.768kHz Crystal – LXT
♦♦
Internal 32kHz RC – LIRC
• Fully integrated internal 8/12/16MHz oscillator requires no external components
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• All instructions executed in one to three instruction cycles
• Table read instructions
• 115 powerful instructions
• Up to 12-level subroutine nesting
• Bit manipulation instruction
Rev. 1.20
7
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Peripheral Features
• Program Memory: Up to 16K×16
• Data Memory: Up to 1024×8
• EEPROM Memory: 128×8
• Watchdog Timer function
• Up to 43 bidirectional I/O lines
• Two external interrupt lines shared with I/O pins
• Multiple Timer Modules for time measure, input capture, compare match output, PWM output
function or single pulse output function
• Serial Interfaces Module – SIM for SPI or I2C
• Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART
• LCD driver funciton with 1/3 bias – R-type & C-type bias
• Dual Time-Base functions for generation of fixed time interrupt signals
• 8-channel 12-bit resolution A/D converter
• Temperature Sensor
• In Application Programming function – IAP
• Low voltage reset function
• Low voltage detect function
• Flash program memory can be re-programmed up to 100,000 times
• Flash program memory data retention > 10 years
• EEPROM data memory can be re-programmed up to 1,000,000 times
• EEPROM data memory data retention > 10 years
• Wide range fo available package types
Rev. 1.20
8
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
General Description
The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture
microcontroller with fully integrated touch key functions. With all touch key functions provided
internally and with the convenience of Flash Memory multi-programming features, each device has
all the features to offer designers a reliable and easy means of implementing Touch Keyes within
their products applications.
The touch key functions are fully integrated completely eliminating the need for external
components. In addition to the flash program memory, other memory includes an area of RAM
Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data, etc. Protective features such as an internal Watchdog Timer and Low
Voltage Reset functions coupled with excellent noise immunity and ESD protection ensure that
reliable operation is maintained in hostile electrical environments.
These devices also include fully integrated low and high speed oscillators which are flexibly used for
different applications. The ability to operate and switch dynamically between a range of operating
modes using different clock sources gives users the ability to optimise microcontroller operation
and minimise power consumption. Easy communication with the outside world is provided using
the internal UART, I2C and SPI interfaces, while the inclusion of flexible I/O programming features,
Timer modules and many other features further enhance device functionality and flexibility.
The touch key device will find excellent use in a huge range of modern Touch Key product
applications such as instrumentation, household appliances, electronically controlled tools to name
but a few.
Selection Table
Most features are common to all devices. The main features distinguishing them are Memory
capacity, I/O count, A/D converter inputs, Timer Module features, Touch Module and key mumber,
stack capacity, LCD driver and package types. The following table summarises the main features of
each device.
Part No.
Program
Memory
Data
Memory
Data
EEPROM
I/O
External
Interrupt
A/D
Temp.
Sensor
Time
Base
BS67F340
4K×16
512×8
128×8
31
2
12-bit×8
√
2
BS67F350
8K×16
768×8
128×8
39
2
12-bit×8
√
2
BS67F360
16K×16
1024×8
128×8
43
2
12-bit×8
√
2
Part No.
Timer Module
Touch
Module
Touch
SIM UART
Key
LCD
Driver
Stacks
Package
BS67F340
10-bit CTM×2
10-bit PTM×1
16-bit STM×1
4
16
√
√
4×24
8
48LQFP
BS67F350
10-bit CTM×2
10-bit PTM×1
16-bit STM×1
5
20
√
√
4×32
8
48/64LQFP
BS67F360
10-bit CTM×2
10-bit PTM×1
16-bit STM×1
7
28
√
√
4×40
12
48/64LQFP
Note: As devices exist in more than one package format, the table reflects the situation for the package
with the most pins.
Rev. 1.20
9
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Block Diagram
Watchdog
Timer
Flash/EEPROM
Programming Circuitr�
EEPRO�
Data
�emor�
Flash
Program
�emor�
Low
Voltage
Detect
IAP
Reset
Circuit
Internal
HIRC/LIRC
Oscillators
Low
Voltage
Reset
RA� Data
�emor�
Time
Base
8-bit
RISC
�CU
Core
Interrupt
Controller
External HXT
Oscillator
External LXT
Oscillator
12-bit A/D
Converter
I/O
Timer
�odules
SI�
(SPI/I2C)
LCD
Driver
UART
Temperature
Sensor
Touch Ke�
�odules
Pin Assignment
PB3/RX/AN3
PB2/PTP0/PTP0I_0/TX/AN2
PB1/SCK/SCL/AN1
PB0/VREF/SDI/SDA/AN0
VDD
PA4/SDO/XT2
PA3/SCSB/XT1
VSS
PA0/SDO/OCDSDA
PA2/SCSB/OCDSCK
PLCD
VMAX
V1
PA1/CTP0/V2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
CO�0
CO�1
CO�2
CO�3
SEG23
SEG22
SEG21
SEG20
48 47 46 4� 44 43 42 41 40 39 38 37
36
1
3�
2
34
3
33
4
32
�
31
6
BS67F340/BS67V340
30
7
48 LQFP-A
29
8
28
9
27
10
26
11
2�
12
13 14 1� 16 17 18 19 20 21 22 23 24
PB4/PTP0B/PTP0I_1/AN4/KEY1
PB5/STCK0/AN5/KEY2
PB6/PTCK0/AN6/KEY3
PB7/INT1/AN7/KEY4
SEG0/PC0/KEY5
SEG1/PC1/KEY6
SEG2/PC2/KEY7
SEG3/PC3/KEY8
SEG4/PD4/KEY9
SEG5/PD5/KEY10
SEG6/PD6/KEY11
SEG7/PA7/KEY12
SEG8/PE4/KEY13
SEG9/PE5/CTCK1/KEY14
SEG10/PE6/CTP1/KEY15
SEG11/PE7/CTP1B/KEY16
SEG12/PE0
SEG13/PE1/OSC1
SEG14/PE2/STP0/STP0I_0/OSC2
SEG15/PE3/STP0B/STP0I_1
SEG16
SEG17
SEG18
SEG19
Rev. 1.20
10
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
PB3/RX/AN3
PB2/PTP0/PTP0I_0/TX/AN2
PB1/SCK/SCL/AN1
PB0/VREF/SDI/SDA/AN0
VDD
PA4/SDO/XT2
PA3/SCSB/XT1
VSS
PA0/SDO/OCDSDA
PA2/SCSB/OCDSCK
PLCD
VMAX
V1
PA1/CTP0/V2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
CO�0
CO�1
CO�2
CO�3
SEG27
SEG26
SEG2�
SEG24
48 47 46 4� 44 43 42 41 40 39 38 37
36
1
3�
2
34
3
33
4
32
�
31
6
BS67F350/BS67V350
30
7
48 LQFP-A
29
8
28
9
27
10
26
11
2�
12
13 14 1� 16 17 18 19 20 21 22 23 24
PB4/PTP0B/PTP0I_1/AN4/KEY1
PB5/STCK0/AN5/KEY2
PB6/PTCK0/AN6/KEY3
PB7/INT1/AN7/KEY4
SEG0/PD0/KEY13
SEG1/PD1/KEY14
SEG2/PD2/KEY15
SEG3/PD3/KEY16
SEG4/PD4/KEY17
SEG5/PD5/KEY18
SEG6/PD6/KEY19
SEG7/PA7/KEY20
SEG8/PE0
SEG9/PE1/OSC1
SEG10/PE2/STP0/STP0I_0/OSC2
SEG11/PE3/STP0B/STP0I_1
SEG12/PE4
SEG13/PE5/CTCK1
SEG14/PE6/CTP1
SEG15/PE7/CTP1B
SEG20
SEG21
SEG22
SEG23
Rev. 1.20
11
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
PB7/INT1/AN7/KEY4
PB6/PTCK0/AN6/KEY3
PB5/STCK0/AN5/KEY2
PB4/PTP0B/PTP0I_1/AN4/KEY1
PB3/RX/AN3
PB2/PTP0/PTP0I_0/TX/AN2
PB1/SCK/SCL/AN1
PB0/VREF/SDI/SDA/AN0
VDD
PA4/SDO/XT2
PA3/SCSB/XT1
VSS
PA0/SDO/OCDSDA
PA2/SCSB/OCDSCK
PLCD
VMAX
V1
PA1/CTP0/V2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
CO�0
CO�1
CO�2
CO�3
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG2�
SEG24
64 63 62 61 60 �9 �8 �7 �6 �� �4 �3 �2 �1 �0 49
1
48
2
47
3
46
4
4�
44
�
6
43
7
42
8
BS67F350/BS67V350
41
9
40
64 LQFP-A
10
39
11
38
12
37
13
36
3�
14
34
1�
33
16
171819 20212223242�262728 29303132
PC0/KEY5
PC1/KEY6
PC2/KEY7
PC3/KEY8
PC4/KEY9
PC5/KEY10
PC6/KEY11
PC7/KEY12
SEG0/PD0/KEY13
SEG1/PD1/KEY14
SEG2/PD2/KEY15
SEG3/PD3/KEY16
SEG4/PD4/KEY17
SEG5/PD5/KEY18
SEG6/PD6/KEY19
SEG7/PA7/KEY20
SEG8/PE0
SEG9/PE1/OSC1
SEG10/PE2/STP0/STP0I_0/OSC2
SEG11/PE3/STP0B/STP0I_1
SEG12/PE4
SEG13/PE5/CTCK1
SEG14/PE6/CTP1
SEG15/PE7/CTP1B
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
Rev. 1.20
12
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
PB3/RX/AN3
PB2/PTP0/PTP0I_0/TX/AN2
PB1/SCK/SCL/AN1
PB0/VREF/SDI/SDA/AN0
VDD
PA4/SDO/XT2
PA3/SCSB/XT1
VSS
PA0/SDO/OCDSDA
PA2/SCSB/OCDSCK
PLCD
VMAX
V1
PA1/CTP0/V2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
CO�0
CO�1
CO�2
CO�3
SEG3�
SEG34
SEG33
SEG32
48 47 46 4� 44 43 42 41 40 39 38 37
36
1
3�
2
34
3
33
4
32
�
31
6
BS67F360/BS67V360
30
7
48 LQFP-A
29
8
28
9
27
10
26
11
2�
12
13 14 1� 16 17 18 19 20 21 22 23 24
PB4/PTP0B/PTP0I_1/AN4/KEY1
PB5/STCK0/AN5/KEY2
PB6/PTCK0/AN6/KEY3
PB7/INT1/AN7/KEY4
SEG8/PD0/KEY13
SEG9/PD1/KEY14
SEG10/PD2/KEY15
SEG11/PD3/KEY16
SEG12/PD4/KEY17
SEG13/PD5/KEY18
SEG14/PD6/KEY19
SEG15/PA7/KEY20
SEG16/PE0/KEY21
SEG17/PE1/KEY22
SEG18/PE2/STP0/STP0I_0/KEY23
SEG19/PE3/STP0B/STP0I_1/KEY24
SEG20/PE4/KEY25
SEG21/PE5/CTCK1/KEY26
SEG22/PE6/CTP1/KEY27
SEG23/PE7/CTP1B/KEY28
SEG28/PF0/OSC1
SEG29/PF1/OSC2
SEG30/PF2
SEG31/PF3
Rev. 1.20
13
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
PB7/INT1/AN7/KEY4
PB6/PTCK0/AN6/KEY3
PB5/STCK0/AN5/KEY2
PB4/PTP0B/PTP0I_1/AN4/KEY1
PB3/RX/AN3
PB2/PTP0/PTP0I_0/TX/AN2
PB1/SCK/SCL/AN1
PB0/VREF/SDI/SDA/AN0
VDD
PA4/SDO/XT2
PA3/SCSB/XT1
VSS
PA0/SDO/OCDSDA
PA2/SCSB/OCDSCK
PLCD
VMAX
V1
PA1/CTP0/V2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
CO�0
CO�1
CO�2
CO�3
SEG39
SEG38
SEG37
SEG36
SEG3�
SEG34
SEG33
SEG32
64 63 62 61 60 �9 �8 �7 �6 �� �4 �3 �2 �1 �0 49
1
48
2
47
3
46
4
4�
�
44
6
43
42
7
8
41
BS67F360/BS67V360
9
40
64 LQFP-A
10
39
38
11
12
37
36
13
3�
14
34
1�
33
16
17 18 19 20 21 22 23 24 2� 26 27 28 29 30 31 32
SEG0/PC0/KEY5
SEG1/PC1/KEY6
SEG2/PC2/KEY7
SEG3/PC3/KEY8
SEG4/PC4/KEY9
SEG5/PC5/KEY10
SEG6/PC6/KEY11
SEG7/PC7/KEY12
SEG8/PD0/KEY13
SEG9/PD1/KEY14
SEG10/PD2/KEY15
SEG11/PD3/KEY16
SEG12/PD4/KEY17
SEG13/PD5/KEY18
SEG14/PD6/KEY19
SEG15/PA7/KEY20
SEG16/PE0/KEY21
SEG17/PE1/KEY22
SEG18/PE2/STP0/STP0I_0/KEY23
SEG19/PE3/STP0B/STP0I_1/KEY24
SEG20/PE4/KEY25
SEG21/PE5/CTCK1/KEY26
SEG22/PE6/CTP1/KEY27
SEG23/PE7/CTP1B/KEY28
SEG24
SEG2�
SEG26
SEG27
SEG28/PF0/OSC1
SEG29/PF1/OSC2
SEG30/PF2
SEG31/PF3
Note: The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the
BS67V3x0 device which is the OCDS EV chip for the BS67F3x0 device.
Rev. 1.20
14
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pin Descriptions
With the exception of the power pins and some relevant transformer control pins, all pins on these
devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O
function of the pins. However these Port pins are also shared with other function such as the Analog
to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table,
however the details behind how each pin is configured is contained in other sections of the datasheet.
BS67F340
Pad Name
PA0/SDO/ICPDA/OCDSDA
PA1/CTP0/V2
PA2/SCS/ICPCK/OCDSCK
PA3/SCS/XT1
PA4/SDO/XT2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
Rev. 1.20
Function
OPT
I/T
O/T
PA0
PAWU
PAPU
PAS0
ST
CMOS
Description
General purpose I/O. Register enabled pull-up
and wake-up.
SDO
PAS0
—
CMOS SPI data output
ICPDA
—
ST
CMOS ICP Data/Address pin
OCDSDA
—
ST
CMOS OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
CMOS CTM0 output
General purpose I/O. Register enabled pull-up
and wake-up.
CTP0
PAS0
—
V2
PAS0
—
AN
PA2
PAWU
PAPU
PAS0
ST
CMOS
SCS
PAS0
IFS
ST
CMOS SPI slave select
CMOS ICP Clock pin
LCD voltage pump
General purpose I/O. Register enabled pull-up
and wake-up.
ICPCK
—
ST
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
SCS
PAS0
IFS
ST
CMOS SPI slave select
XT1
PAS0
LXT
—
PA4
PAWU
PAPU
PAS1
ST
CMOS
CMOS SPI data output
OCDS Clock pin, for EV chip only.
General purpose I/O. Register enabled pull-up
and wake-up.
LXT oscillator pin
General purpose I/O. Register enabled pull-up
and wake-up.
SDO
PAS1
—
XT2
PAS1
—
LXT
PA5
PAWU
PAPU
PAS1
ST
CMOS
CTP0B
PAS1
—
CMOS CTM0 inverted output
C1
PAS1
—
AN
PA6
PAWU
PAPU
PAS1
ST
CMOS
CTCK0
PAS1
ST
—
CTM0 clock input
INT0
PAS1
INTEG
INTC0
ST
—
External Interrupt 0
C2
PAS1
—
AN
LCD voltage pump
15
LXT oscillator pin
General purpose I/O. Register enabled pull-up
and wake-up.
LCD voltage pump
General purpose I/O. Register enabled pull-up
and wake-up.
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PA7/KEY12/SEG7
PB0/SDI/SDA/VREF/AN0
PB1/SCK/SCL/AN1
PB2/PTPI/TX/PTP/AN2
PB3/RX/AN3
PB4/PTPI/PTPB/KEY1/
AN4
PB5/STCK/KEY2/AN5
PB6/PTCK/KEY3/AN6
PB7/INT1/KEY4/AN7
Rev. 1.20
Function
OPT
I/T
O/T
PA7
PAWU
PAPU
PAS1
Description
ST
CMOS
KEY12
PAS1
AN
—
Touch key input
SEG7
PAS1
—
AN
LCD segment output
PB0
PBPU
PBS0
ST
General purpose I/O. Register enabled pull-up
and wake-up.
CMOS General purpose I/O. Register enabled pull-up.
SDI
PBS0
ST
SDA
PBS0
ST
—
SPI data input
VREF
PBS0
—
AN
A/D Converter reference voltage output
AN0
PBS0
AN
—
A/D Converter analog input
PB1
PBPU
PBS0
ST
NMOS I2C data line
CMOS General purpose I/O. Register enabled pull-up.
SCK
PBS0
ST
CMOS SPI serial clock
SCL
PBS0
ST
NMOS I2C clock line
AN1
PBS0
AN
PB2
PBPU
PBS0
ST
PTPI
PBS0
IFS
ST
TX
PBS0
—
CMOS UART TX serial data output
CMOS PTM output
—
A/D Converter analog input
CMOS General purpose I/O. Register enabled pull-up.
—
PTM capture input
PTP
PBS0
—
AN2
PBS0
AN
PB3
PBPU
PBS0
ST
RX
PBS0
ST
—
UART RX serial data input
AN3
PBS0
AN
—
A/D Converter analog input
PB4
PBPU
PBS1
ST
PTPI
PBS1
IFS
ST
PTPB
PBS1
—
KEY1
PBS1
AN
—
Touch key input
AN4
PBS1
AN
—
A/D Converter analog input
PB5
PBPU
PBS1
ST
—
A/D Converter analog input
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
—
PTM capture input
CMOS PTM inverted output
CMOS General purpose I/O. Register enabled pull-up.
STM clock input
STCK
PBS1
ST
—
KEY2
PBS1
AN
—
Touch key input
AN5
PBS1
AN
—
A/D Converter analog input
PB6
PBPU
PBS1
ST
CMOS General purpose I/O. Register enabled pull-up.
PTM clock input
PTCK
PBS1
ST
—
KEY3
PBS1
AN
—
Touch key input
AN6
PBS1
AN
—
A/D Converter analog input
PB7
PBPU
PBS1
ST
INT1
PBS1
INTEG
INTC0
ST
—
External Interrupt 1
KEY4
PBS1
AN
—
Touch key input
AN7
PBS1
AN
—
A/D Converter analog input
CMOS General purpose I/O. Register enabled pull-up.
16
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PC0/KEY5/SEG0
PC1/KEY6/SEG1
PC2/KEY7/SEG2
PC3/KEY8/SEG3
PD4/KEY9/SEG4
PD5/KEY10/SEG5
PD6/KEY11/SEG6
PE0/SEG12
PE1/OSC1/SEG13
PE2/STPI/STP/OSC2/
SEG14
PE3/STPI/STPB/SEG15
Rev. 1.20
Function
OPT
I/T
PC0
PCPU
PCS0
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up.
KEY5
PCS0
AN
—
Touch key input
SEG0
PCS0
—
AN
LCD segment output
PC1
PCPU
PCS0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY6
PCS0
AN
—
Touch key input
SEG1
PCS0
—
AN
LCD segment output
PC2
PCPU
PCS0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY7
PCS0
AN
—
Touch key input
SEG2
PCS0
—
AN
LCD segment output
PC3
PCPU
PCS0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY8
PCS0
AN
—
Touch key input
SEG3
PCS0
—
AN
LCD segment output
PD4
PDPU
PDS1
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY9
PDS1
AN
—
Touch key input
SEG4
PDS1
—
AN
LCD segment output
PD5
PDPU
PDS1
ST
KEY10
PDS1
AN
—
Touch key input
SEG5
PDS1
—
AN
LCD segment output
PD6
PDPU
PDS1
ST
KEY11
PDS1
AN
—
Touch key input
SEG6
PDS1
—
AN
LCD segment output
PE0
PEPU
PES0
ST
SEG12
PES0
—
PE1
PEPU
PES0
ST
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
AN
LCD segment output
CMOS General purpose I/O. Register enabled pull-up.
OSC1
PES0
HXT
—
HXT oscillator pin
SEG13
PES0
—
AN
LCD segment output
PE2
PEPU
PES0
ST
STPI
PES0
IFS
ST
CMOS General purpose I/O. Register enabled pull-up.
—
STM capture input
STP
PES0
—
OSC2
PES0
—
CMOS STM output
HXT
HXT oscillator pin
SEG14
PES0
—
AN
LCD segment output
PE3
PEPU
PES0
ST
STPI
PES0
IFS
ST
STPB
PES0
—
SEG15
PES0
—
CMOS General purpose I/O. Register enabled pull-up.
—
STM capture input
CMOS STM inverted output
AN
17
LCD segment output
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PE4/KEY13/SEG8
PE5/CTCK1/KEY14/SEG9
PE6/CTP1/KEY15/SEG10
PE7/CTP1B/KEY16/
SEG11
Function
OPT
I/T
PE4
PEPU
PES1
O/T
Description
ST
KEY13
PES1
AN
—
Touch key input
SEG8
PES1
—
AN
LCD segment output
PE5
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CTCK1
PES1
ST
—
CTM1 clock input
KEY14
PES1
AN
—
Touch key input
SEG9
PES1
—
AN
LCD segment output
PE6
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CTP1
PES1
—
CMOS CTM1 output
KEY15
PES1
AN
—
Touch key input
SEG10
PES1
—
AN
LCD segment output
PE7
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CTP1B
PES1
—
CMOS CTM1 inverted output
KEY16
PES1
AN
—
Touch key input
SEG11
PES1
—
AN
LCD segment output
SEG16~SEG23
SEGn
LCDC0
—
AN
LCD segment output
COM0~COM3
COMn
LCDC0
—
AN
LCD common output
V1
V1
—
—
AO
LCD voltage ppump
PLCD
PLCD
—
PWR
—
LCD power supply
VMAX
VMAX
—
PWR
—
IC maximum voltage, connected to VDD, PLCD
or V1.
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
Note: I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
CO: Configuration option
PWR: Power
ST: Schmitt Trigger input
AN: Analog signal
CMOS: CMOS output
NMOS: NMOS output
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
Rev. 1.20
18
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
BS67F350
Pad Name
PA0/SDO/ICPDA/OCDSDA
PA1/CTP0/V2
PA2/SCS/ICPCK/OCDSCK
PA3/SCS/XT1
PA4/SDO/XT2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
PA7/KEY20/SEG7
Rev. 1.20
Function
OPT
I/T
O/T
PA0
PAWU
PAPU
PAS0
ST
CMOS
Description
General purpose I/O. Register enabled pull-up
and wake-up.
SDO
PAS0
—
CMOS SPI data output
ICPDA
—
ST
CMOS ICP Data/Address pin
OCDSDA
—
ST
CMOS OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
CMOS CTM0 output
General purpose I/O. Register enabled pull-up
and wake-up.
CTP0
PAS0
—
V2
PAS0
—
AN
PA2
PAWU
PAPU
PAS0
ST
CMOS
SCS
PAS0
IFS
ST
CMOS SPI slave select
CMOS ICP Clock pin
LCD voltage pump
General purpose I/O. Register enabled pull-up
and wake-up.
ICPCK
—
ST
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
SCS
PAS0
IFS
ST
CMOS SPI slave select
XT1
PAS0
LXT
—
PA4
PAWU
PAPU
PAS1
ST
CMOS
CMOS SPI data output
OCDS Clock pin, for EV chip only.
General purpose I/O. Register enabled pull-up
and wake-up.
LXT oscillator pin
General purpose I/O. Register enabled pull-up
and wake-up.
SDO
PAS1
—
XT2
PAS1
—
LXT
PA5
PAWU
PAPU
PAS1
ST
CMOS
CMOS CTM0 inverted output
LXT oscillator pin
General purpose I/O. Register enabled pull-up
and wake-up.
CTP0B
PAS1
—
C1
PAS1
—
AN
PA6
PAWU
PAPU
PAS1
ST
CMOS
CTCK0
PAS1
ST
—
CTM0 clock input
INT0
PAS1
INTEG
INTC0
ST
—
External Interrupt 0
C2
PAS1
—
AN
LCD voltage pump
PA7
PAWU
PAPU
PAS1
ST
CMOS
KEY20
PAS1
AN
—
Touch key input
SEG7
PAS1
—
AN
LCD segment output
19
LCD voltage pump
General purpose I/O. Register enabled pull-up
and wake-up.
General purpose I/O. Register enabled pull-up
and wake-up.
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PB0/SDI/SDA/VREF/AN0
PB1/SCK/SCL/AN1
PB2/PTPI/TX/PTP/AN2
PB3/RX/AN3
PB4/PTPI/PTPB/KEY1/AN4
PB5/STCK/KEY2/AN5
PB6/PTCK/KEY3/AN6
PB7/INT1/KEY4/AN7
PC0/KEY5
Rev. 1.20
Function
OPT
I/T
PB0
PBPU
PBS0
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up.
SDI
PBS0
ST
SDA
PBS0
ST
—
SPI data input
VREF
PBS0
—
AN
A/D Converter reference voltage output
AN0
PBS0
AN
—
A/D Converter analog input
PB1
PBPU
PBS0
ST
NMOS I2C data line
CMOS General purpose I/O. Register enabled pull-up.
SCK
PBS0
ST
CMOS SPI serial clock
SCL
PBS0
ST
NMOS I2C clock line
AN1
PBS0
AN
PB2
PBPU
PBS0
ST
PTPI
PBS0
IFS
ST
TX
PBS0
—
CMOS UART TX serial data output
PTP
PBS0
—
CMOS PTM output
AN2
PBS0
AN
PB3
PBPU
PBS0
ST
—
A/D Converter analog input
CMOS General purpose I/O. Register enabled pull-up.
—
—
PTM capture input
A/D Converter analog input
CMOS General purpose I/O. Register enabled pull-up.
RX
PBS0
ST
—
UART RX serial data input
AN3
PBS0
AN
—
A/D Converter analog input
PB4
PBPU
PBS1
ST
PTPI
PBS1
IFS
ST
PTPB
PBS1
—
KEY1
PBS1
AN
—
Touch key input
AN4
PBS1
AN
—
A/D Converter analog input
PB5
PBPU
PBS1
ST
STCK
PBS1
ST
CMOS General purpose I/O. Register enabled pull-up.
—
PTM capture input
CMOS PTM inverted output
CMOS General purpose I/O. Register enabled pull-up.
—
STM clock input
KEY2
PBS1
AN
—
Touch key input
AN5
PBS1
AN
—
A/D Converter analog input
PB6
PBPU
PBS1
ST
PTCK
PBS1
ST
CMOS General purpose I/O. Register enabled pull-up.
—
PTM clock input
KEY3
PBS1
AN
—
Touch key input
AN6
PBS1
AN
—
A/D Converter analog input
PB7
PBPU
PBS1
ST
INT1
PBS1
INTEG
INTC0
ST
CMOS General purpose I/O. Register enabled pull-up.
—
External Interrupt 1
KEY4
PBS1
AN
—
Touch key input
AN7
PBS1
AN
—
A/D Converter analog input
PC0
PCPU
PCS0
ST
KEY5
PCS0
AN
CMOS General purpose I/O. Register enabled pull-up.
—
20
Touch key input
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PC1/KEY6
PC2/KEY7
PC3/KEY8
PC4/KEY9
PC5/KEY10
PC6/KEY11
PC7/KEY12
PD0/KEY13/SEG0
PD1/KEY14/SEG1
PD2/KEY15/SEG2
PD3/KEY16/SEG3
PD4/KEY17/SEG4
PD5/KEY18/SEG5
PD6/KEY19/SEG6
Rev. 1.20
Function
OPT
I/T
PC1
PCPU
PCS0
O/T
Description
ST
KEY6
PCS0
AN
PC2
PCPU
PCS0
ST
KEY7
PCS0
AN
PC3
PCPU
PCS0
ST
KEY8
PCS0
AN
PC4
PCPU
PCS1
ST
KEY9
PCS1
AN
PC5
PCPU
PCS1
ST
KEY10
PCS1
AN
PC6
PCPU
PCS1
ST
KEY11
PCS1
AN
PC7
PCPU
PCS1
ST
KEY12
PCS1
AN
PD0
PDPU
PDS0
ST
KEY13
PDS0
AN
—
Touch key input
SEG0
PDS0
—
AN
LCD segment output
PD1
PDPU
PDS0
ST
KEY14
PDS0
AN
—
Touch key input
SEG1
PDS0
—
AN
LCD segment output
PD2
PDPU
PDS0
ST
KEY15
PDS0
AN
—
Touch key input
SEG2
PDS0
—
AN
LCD segment output
PD3
PDPU
PDS0
ST
KEY16
PDS0
AN
—
Touch key input
SEG3
PDS0
—
AN
LCD segment output
PD4
PDPU
PDS1
ST
KEY17
PDS1
AN
—
Touch key input
SEG4
PDS1
—
AN
LCD segment output
PD5
PDPU
PDS1
ST
KEY18
PDS1
AN
—
Touch key input
SEG5
PDS1
—
AN
LCD segment output
PD6
PDPU
PDS1
ST
KEY19
PDS1
AN
—
Touch key input
SEG6
PDS1
—
AN
LCD segment output
CMOS General purpose I/O. Register enabled pull-up.
—
Touch key input
CMOS General purpose I/O. Register enabled pull-up.
—
Touch key input
CMOS General purpose I/O. Register enabled pull-up.
—
Touch key input
CMOS General purpose I/O. Register enabled pull-up.
—
Touch key input
CMOS General purpose I/O. Register enabled pull-up.
—
Touch key input
CMOS General purpose I/O. Register enabled pull-up.
—
Touch key input
CMOS General purpose I/O. Register enabled pull-up.
—
Touch key input
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
21
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PE0/SEG8
PE1/OSC1/SEG9
PE2/STPI/STP/OSC2/
SEG10
PE3/STPI/STPB/SEG11
PE4/SEG12
PE5/CTCK1/SEG13
PE6/CTP1/SEG14
PE7/CTP1B/SEG15
Function
OPT
I/T
PE0
PEPU
PES0
O/T
Description
ST
SEG8
PES0
—
PE1
PEPU
PES0
ST
OSC1
PES0
HXT
—
HXT oscillator pin
SEG9
PES0
—
AN
LCD segment output
PE2
PEPU
PES0
ST
STPI
PES0
IFS
ST
CMOS General purpose I/O. Register enabled pull-up.
AN
LCD segment output
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
—
STM capture input
STP
PES0
—
OSC2
PES0
—
CMOS STM output
HXT
HXT oscillator pin
SEG10
PES0
—
AN
LCD segment output
PE3
PEPU
PES0
ST
STPI
PES0
IFS
ST
CMOS General purpose I/O. Register enabled pull-up.
—
STM capture input
STPB
PES0
—
SEG11
PES0
—
CMOS STM inverted output
PE4
PEPU
PES1
ST
SEG12
PES1
—
PE5
PEPU
PES1
ST
CTCK1
PES1
ST
—
CTM1 clock input
SEG13
PES1
—
AN
LCD segment output
PE6
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CTP1
PES1
—
CMOS CTM1 output
SEG14
PES1
—
PE7
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CMOS CTM1 inverted output
AN
LCD segment output
CMOS General purpose I/O. Register enabled pull-up.
AN
LCD segment output
CMOS General purpose I/O. Register enabled pull-up.
AN
LCD segment output
CTP1B
PES1
—
SEG15
PES1
—
AN
LCD segment output
SEG16~SEG31
SEGn
LCDC0
—
AN
LCD segment output
COM0~COM3
COMn
LCDC0
—
AN
LCD common output
V1
—
—
AO
LCD voltage ppump
PLCD
PLCD
—
PWR
—
LCD power supply
VMAX
VMAX
—
PWR
—
IC maximum voltage, connected to VDD, PLCD
or V1.
V1
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
Note: I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
CO: Configuration option PWR: Power
ST: Schmitt Trigger input
AN: Analog signal
CMOS: CMOS output NMOS: NMOS output
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
Rev. 1.20
22
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
BS67F360
Pad Name
PA0/SDO/ICPDA/OCDSDA
PA1/CTP0/V2
PA2/SCS/ICPCK/OCDSCK
PA3/SCS/XT1
PA4/SDO/XT2
PA5/CTP0B/C1
PA6/CTCK0/INT0/C2
PA7/KEY20/SEG15
Rev. 1.20
Function
OPT
I/T
O/T
Description
PA0
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up
and wake-up.
SDO
PAS0
—
CMOS SPI data output
ICPDA
—
ST
CMOS ICP Data/Address pin
OCDSDA
—
ST
CMOS OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
CMOS CTM0 output
General purpose I/O. Register enabled pull-up
and wake-up.
CTP0
PAS0
—
V2
PAS0
—
AN
PA2
PAWU
PAPU
PAS0
ST
CMOS
SCS
PAS0
IFS
ST
CMOS SPI slave select
CMOS ICP Clock pin
LCD voltage pump
General purpose I/O. Register enabled pull-up
and wake-up.
ICPCK
—
ST
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
SCS
PAS0
IFS
ST
CMOS SPI slave select
XT1
PAS0
LXT
—
PA4
PAWU
PAPU
PAS1
ST
CMOS
CMOS SPI data output
OCDS Clock pin, for EV chip only.
General purpose I/O. Register enabled pull-up
and wake-up.
LXT oscillator pin
General purpose I/O. Register enabled pull-up
and wake-up.
SDO
PAS1
—
XT2
PAS1
—
LXT
PA5
PAWU
PAPU
PAS1
ST
CMOS
CMOS CTM0 inverted output
LXT oscillator pin
General purpose I/O. Register enabled pull-up
and wake-up.
CTP0B
PAS1
—
C1
PAS1
—
AN
PA6
PAWU
PAPU
PAS1
ST
CMOS
CTCK0
PAS1
ST
—
CTM0 clock input
INT0
PAS1
INTEG
INTC0
ST
—
External Interrupt 0
C2
PAS1
—
AN
LCD voltage pump
PA7
PAWU
PAPU
PAS1
ST
CMOS
KEY20
PAS1
AN
—
Touch key input
SEG15
PAS1
—
AN
LCD segment output
23
LCD voltage pump
General purpose I/O. Register enabled pull-up
and wake-up.
General purpose I/O. Register enabled pull-up
and wake-up.
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PB0/SDI/SDA/VREF/AN0
PB1/SCK/SCL/AN1
PB2/PTPI/TX/PTP/AN2
PB3/RX/AN3
PB4/PTPI/PTPB/KEY1/AN4
PB5/STCK/KEY2/AN5
PB6/PTCK/KEY3/AN6
PB7/INT1/KEY4/AN7
PC0/KEY5/SEG0
Rev. 1.20
Function
OPT
I/T
PB0
PBPU
PBS0
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up.
SDI
PBS0
ST
SDA
PBS0
ST
—
SPI data input
VREF
PBS0
—
AN
A/D Converter reference voltage output
AN0
PBS0
AN
—
A/D Converter analog input
PB1
PBPU
PBS0
ST
NMOS I2C data line
CMOS General purpose I/O. Register enabled pull-up.
SCK
PBS0
ST
CMOS SPI serial clock
SCL
PBS0
ST
NMOS I2C clock line
AN1
PBS0
AN
PB2
PBPU
PBS0
ST
PTPI
PBS0
IFS
ST
TX
PBS0
—
CMOS UART TX serial data output
PTP
PBS0
—
CMOS PTM output
AN2
PBS0
AN
PB3
PBPU
PBS0
ST
—
A/D Converter analog input
CMOS General purpose I/O. Register enabled pull-up.
—
—
PTM capture input
A/D Converter analog input
CMOS General purpose I/O. Register enabled pull-up.
RX
PBS0
ST
—
UART RX serial data input
AN3
PBS0
AN
—
A/D Converter analog input
PB4
PBPU
PBS1
ST
PTPI
PBS1
IFS
ST
PTPB
PBS1
—
KEY1
PBS1
AN
—
Touch key input
AN4
PBS1
AN
—
A/D Converter analog input
PB5
PBPU
PBS1
ST
STCK
PBS1
ST
CMOS General purpose I/O. Register enabled pull-up.
—
PTM capture input
CMOS PTM inverted output
CMOS General purpose I/O. Register enabled pull-up.
—
STM clock input
KEY2
PBS1
AN
—
Touch key input
AN5
PBS1
AN
—
A/D Converter analog input
PB6
PBPU
PBS1
ST
PTCK
PBS1
ST
CMOS General purpose I/O. Register enabled pull-up.
—
PTM clock input
KEY3
PBS1
AN
—
Touch key input
AN6
PBS1
AN
—
A/D Converter analog input
PB7
PBPU
PBS1
ST
INT1
PBS1
INTEG
INTC0
ST
CMOS General purpose I/O. Register enabled pull-up.
—
External Interrupt 1
KEY4
PBS1
AN
—
Touch key input
AN7
PBS1
AN
—
A/D Converter analog input
PC0
PCPU
PCS0
ST
KEY5
PCS0
AN
—
Touch key input
SEG0
PCS0
—
AN
LCD segment output
24
CMOS General purpose I/O. Register enabled pull-up.
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PC1/KEY6/SEG1
PC2/KEY7/SEG2
PC3/KEY8/SEG3
PC4/KEY9/SEG4
PC5/KEY10/SEG5
PC6/KEY11/SEG6
PC7/KEY12/SEG7
PD0/KEY13/SEG8
PD1/KEY14/SEG9
PD2/KEY15/SEG10
PD3/KEY16/SEG11
PD4/KEY17/SEG12
Rev. 1.20
Function
OPT
I/T
PC1
PCPU
PCS0
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up.
KEY6
PCS0
AN
—
Touch key input
SEG1
PCS0
—
AN
LCD segment output
PC2
PCPU
PCS0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY7
PCS0
AN
—
Touch key input
SEG2
PCS0
—
AN
LCD segment output
PC3
PCPU
PCS0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY8
PCS0
AN
—
Touch key input
SEG3
PCS0
—
AN
LCD segment output
PC4
PCPU
PCS1
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY9
PCS1
AN
—
Touch key input
SEG4
PCS1
—
AN
LCD segment output
PC5
PCPU
PCS1
ST
KEY10
PCS1
AN
—
Touch key input
SEG5
PCS1
—
AN
LCD segment output
PC6
PCPU
PCS1
ST
KEY11
PCS1
AN
—
Touch key input
SEG6
PCS1
—
AN
LCD segment output
PC7
PCPU
PCS1
ST
KEY12
PCS1
AN
—
Touch key input
SEG7
PCS1
—
AN
LCD segment output
PD0
PDPU
PDS0
ST
KEY13
PDS0
AN
—
Touch key input
SEG8
PDS0
—
AN
LCD segment output
PD1
PDPU
PDS0
ST
KEY14
PDS0
AN
—
Touch key input
SEG9
PDS0
—
AN
LCD segment output
PD2
PDPU
PDS0
ST
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
KEY15
PDS0
AN
—
Touch key input
SEG10
PDS0
—
AN
LCD segment output
PD3
PDPU
PDS0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY16
PDS0
AN
—
Touch key input
SEG11
PDS0
—
AN
LCD segment output
PD4
PDPU
PDS1
ST
KEY17
PDS1
AN
—
Touch key input
SEG12
PDS1
—
AN
LCD segment output
25
CMOS General purpose I/O. Register enabled pull-up.
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PD5/KEY18/SEG13
PD6/KEY19/SEG14
PE0/KEY21/SEG16
PE1/KEY22/SEG17
PE2/STPI/STP/KEY23/
SEG18
PE3/STPI/STPB/KEY24/
SEG19
PE4/KEY25/SEG20
PE5/CTCK1/KEY26/SEG21
PE6/CTP1/KEY27/SEG22
PE7/CTP1B/KEY28/SEG23
Rev. 1.20
Function
OPT
I/T
PD5
PDPU
PDS1
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up.
KEY18
PDS1
AN
—
Touch key input
SEG13
PDS1
—
AN
LCD segment output
PD6
PDPU
PDS1
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY19
PDS1
AN
—
Touch key input
SEG14
PDS1
—
AN
LCD segment output
PE0
PEPU
PES0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY21
PES0
AN
—
Touch key input
SEG16
PES0
—
AN
LCD segment output
PE1
PEPU
PES0
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY22
PES0
AN
—
Touch key input
SEG17
PES0
—
AN
LCD segment output
PE2
PEPU
PES0
ST
STPI
PES0
IFS
ST
STP
PES0
—
CMOS General purpose I/O. Register enabled pull-up.
—
STM capture input
CMOS STM output
KEY23
PES0
AN
—
Touch key input
SEG18
PES0
—
AN
LCD segment output
PE3
PEPU
PES0
ST
STPI
PES0
IFS
ST
CMOS General purpose I/O. Register enabled pull-up.
—
STM capture input
STPB
PES0
—
KEY24
PES0
AN
CMOS STM inverted output
—
Touch key input
SEG19
PES0
—
AN
LCD segment output
PE4
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
KEY25
PES1
AN
—
Touch key input
SEG20
PES1
—
AN
LCD segment output
PE5
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CTCK1
PES1
ST
—
CTM1 clock input
KEY26
PES1
AN
—
Touch key input
SEG21
PES1
—
AN
LCD segment output
PE6
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CMOS CTM1 output
CTP1
PES1
—
KEY27
PES1
AN
—
Touch key input
SEG22
PES1
—
AN
LCD segment output
PE7
PEPU
PES1
ST
CMOS General purpose I/O. Register enabled pull-up.
CMOS CTM1 inverted output
CTP1B
PES1
—
KEY28
PES1
AN
—
Touch key input
SEG23
PES1
—
AN
LCD segment output
26
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Pad Name
PF0/OSC1/SEG28
PF1/OSC2/SEG29
PF2/SEG30
PF3/SEG31
Function
OPT
I/T
PF0
PFPU
PFS0
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up.
OSC1
PFS0
HXT
—
HXT oscillator pin
SEG28
PFS0
—
AN
LCD segment output
PF1
PFPU
PFS0
ST
CMOS General purpose I/O. Register enabled pull-up.
OSC2
PFS0
—
HXT
HXT oscillator pin
SEG29
PFS0
—
AN
LCD segment output
PF2
PFPU
PFS0
ST
SEG30
PFS0
—
PF3
PFPU
PFS0
ST
CMOS General purpose I/O. Register enabled pull-up.
AN
LCD segment output
CMOS General purpose I/O. Register enabled pull-up.
SEG31
PFS0
—
AN
LCD segment output
SEG24~SEG27,
SEG32~SEG39
SEGn
LCDC0
—
AN
LCD segment output
COM0~COM3
COMn
LCDC0
—
AN
LCD common output
V1
—
—
AO
LCD voltage ppump
PLCD
PLCD
—
PWR
—
LCD power supply
VMAX
VMAX
—
PWR
—
IC maximum voltage, connected to VDD, PLCD
or V1.
V1
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
Note: I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
CO: Configuration option PWR: Power
ST: Schmitt Trigger input
AN: Analog signal
CMOS: CMOS output NMOS: NMOS output
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
Absolute Maximum Ratings
Supply Voltage.................................................................................................... VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................... VSS−0.3V to VDD+0.3V
Storage Temperature....................................................................................................... -50˚C to 125˚C
Operating Temperature......................................................................................................-40˚C to 85˚C
IOH Total........................................................................................................................................ -80mA
IOL Total.........................................................................................................................................80mA
Total Power Dissipation.............................................................................................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute
Maximum Ratings” may cause substantial damage to these devices. Functional operation of
these devices at other conditions beyond those listed in the specification is not implied and
prolonged exposure to extreme conditions may affect devices reliability.
Rev. 1.20
27
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
D.C. Characteristics
Ta=25°C
Symbol
Parameter
Operating Voltage (HXT)
Test Conditions
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
—
5.5
V
fSYS=8MHz
2.4
—
5.5
V
— fSYS=12MHz
2.7
—
5.5
V
fSYS=16MHz
3.3
—
5.5
V
fSYS=20MHz
4.5
—
5.5
V
fSYS=8MHz
2.4
—
5.5
V
— fSYS=12MHz
2.7
—
5.5
V
fSYS=16MHz
VDD
Operating Voltage (HIRC)
Operating Current (HXT)
IDD
Operating Current (HIRC)
Conditions
VDD
3.3
—
5.5
V
3V fSYS=fH=4MHz
5V No load, all peripherals off
—
500
750
μA
—
1.0
1.5
mA
3V fSYS=fH=8MHz
5V No load, all peripherals off
—
1.0
1.5
mA
—
2.0
3.0
mA
3V fSYS=fH=12MHz
5V No load, all peripherals off
—
1.5
2.75
mA
—
3.0
4.5
mA
5V
fSYS=fH=16MHz
no load, all peripherals off
—
3.6
5.4
mA
5V
fSYS=fH=20MHz
no load, all peripherals off
—
4.3
6.45
mA
3V fSYS=fH=8MHz
5V No load, all peripherals off
—
0.8
1.2
mA
—
1.6
2.4
mA
3V fSYS=fH=12MHz
5V No load, all peripherals off
—
1.2
1.8
mA
—
2.4
3.6
mA
—
3.2
4.8
mA
fSYS=fH=16MHz
5V
no load, all peripherals off
Operating Current (LXT)
3V fSYS=fSUB=fLXT=32.768kHz
5V No load, all peripherals off
Operating Current (LIRC)
—
10
20
μA
—
30
50
μA
3V fSYS=fSUB=fLIRC=32kHz
5V No load, all peripherals off
—
10
20
μA
—
30
50
μA
Standby Current (IDLE0 Mode)
3V fSYS off, fSUB on, No load,
5V all peripherals off, WDT enabled
—
1.3
3.0
μA
—
2.4
5.0
μA
Standby Current (IDLE1 Mode)
3V fSYS=12MHz on, fSUB on, No load,
5V all peripherals off, WDT enabled
—
0.9
1.4
mA
—
1.4
2.1
mA
3V fSYS off, fSUB off, No load,
Standby Current (SLEEP Mode)
5V all peripherals off, WDT enabled
—
1.2
1.8
μA
—
1.8
2.7
μA
Input Low Voltage for I/O Ports
or Input Pins
5V
—
0
—
1.5
V
—
—
0
—
0.2VDD
V
VIH
Input High Voltage for I/O Ports
or Input Pins
5V
—
3.5
—
5.0
V
—
—
0.8VDD
—
VDD
V
IOL
Sink Current for I/O Port
17
34
—
mA
34
68
—
mA
-5.5
-11.0
—
mA
-11.0
-22.0
—
mA
ISTB
VIL
IOH
Source Current for I/O Port
RPH
Pull-high Resistance for I/O
Ports
Rev. 1.20
3V
5V
3V
5V
VOL=0.1VDD
VOH=0.9VDD
3V
—
20
60
100
kΩ
5V
—
10
30
50
kΩ
28
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
A.C. Characteristics
Ta=25°C
Symbol
Parameter
System Clock (HXT)
fSYS
System Clock (HIRC)
Test Condition
Condition
VDD
Typ.
Max. Unit
2.2V~5.5V fSYS=fHXT=4MHz
—
4
—
MHz
2.4V~5.5V fSYS=fHXT=8MHz
—
8
—
MHz
2.7V~5.5V fSYS=fHXT=12MHz
—
12
—
MHz
3.3V~5.5V fSYS=fHXT=16MHz
—
16
—
MHz
4.5V~5.5V fSYS=fHXT=20MHz
—
20
—
MHz
2.4V~5.5V fSYS=fHIRC=8MHz
—
8
—
MHz
2.7V~5.5V fSYS=fHIRC=12MHz
—
12
—
MHz
MHz
3.3V~5.5V fSYS=fHIRC=16MHz
—
16
—
System Clock (LXT)
2.2V~5.5V fSYS=fLXT=32.768kHz
—
32.768
—
kHz
System Clock (LIRC)
2.2V~5.5V fSYS=fLIRC=32kHz
—
32
—
kHz
Ta=25°C
Typ.2%
12
Typ.
MHz
+2%
Ta=0°C to 70°C
Typ.5%
12
Typ.
MHz
+5%
2.7V~5.5V Ta=0°C to 70°C
Typ.7%
12
Typ.
MHz
+7%
2.7V~5.5V Ta=-40°C to 85°C
Typ.10%
12
Typ.
MHz
+10%
3V
3V±0.1V
High Speed Internal RC oscillator
(HIRC)
(12MHz trim at VDD=3V)
3V
Ta=25°C
Typ.20%
8
Typ.
MHz
+20%
3V
Ta=25°C
Typ.20%
16
Typ.
MHz
+20%
5V
Ta=25°C
Typ.2%
12
Typ.
MHz
+2%
Ta=0°C to 70°C
Typ.5%
12
Typ.
MHz
+5%
2.7V~5.5V Ta=0°C to 70°C
Typ.7%
12
Typ.
MHz
+7%
2.7V~5.5V Ta=-40°C to 85°C
Typ.10%
12
Typ.
MHz
+10%
fHIRC
5V±0.1V
High Speed Internal RC oscillator
(HIRC)
(12MHz trim at VDD=5V)
fLIRC
Min.
Low Speed Internal RC Oscillator
(LIRC)
5V
Ta=25°C
Typ.20%
8
Typ.
MHz
+20%
5V
Ta=25°C
Typ.20%
16
Typ.
MHz
+20%
5V
Ta=25°C
Typ.10%
32
Typ.
kHz
+10%
Typ.40%
32
Typ.
kHz
+40%
2.2V~5.5V Ta= -40°C to 85°C
tTPI
CTPnI, STPI, PTPI Pin Minimum
Input Pulse Width
—
—
0.3
—
—
μs
tTCK
CTCKn, STCK, PTCK Pin Minimum
Input Pulse Width
—
—
0.3
—
—
μs
tINT
Interrupt Pin Minimum Input Pulse
Width
—
—
10
—
—
μs
Rev. 1.20
29
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
—
fSYS=fH=fHXT ~ fHXT/64
128
—
—
tHXT
—
fSYS=fH =fHIRC ~ fHIRC/64
16
—
—
tHIRC
—
fSYS=fSUB=fLXT
1024
—
—
tLXT
—
fSYS=fSUB=fLIRC
2
—
—
tLIRC
System Start-up Timer Period
(Wake-up from power down mode
and fSYS on)
—
fSYS=fH ~ fH/64,
fH=fHXT or fHIRC
2
—
—
tH
—
fSYS=fSUB=fLXT or fLIRC
tSUB
System Start-up Timer period
(SLOW mode → NORMAL mode)
(NORMAL mode → SLOW mode)
—
fHXT off → on (HXTF=1)
—
fHIRC off → on (HIRCF=1)
—
fLXT off → on (LXTF=1)
System Start-up Timer Period
(Wake-up from power down mode
and fSYS off)
tSST
Test Condition
VDD
2
—
—
1024
—
—
tHXT
16
—
—
tHIRC
1024
—
—
tLXT
System Start-up Timer Period
(WDT hardware reset)
—
—
0
—
—
tSYS
System Reset Delay Time
(Power-on reset,
LVR hardware reset,
LVRC/WDTC/RSTC software reset)
—
—
25
50
100
ms
System Reset Delay Time
(WDT Hardware Reset)
—
—
8.3
16.7
33.3
ms
tEERD
EEPROM Read Time
—
—
—
—
4
tSYS
tEEWR
EEPROM Write Time
—
—
—
2
4
ms
tRSTD
Note: tSYS= 1/fSYS
A/D Converter Characteristics
Operating Temperature: -40°C~85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
VDD
Operating Voltage
—
—
2.7
—
5.5
V
VADI
Input Voltage
—
—
0
—
VR\EF
V
VREF
Reference Voltage
—
—
2
—
VDD
V
VREF=VDD, tADCK=0.5μs or 10μs
—
—
±3
LSB
VREF=VDD, tADCK=0.5μs or 10μs
—
—
±4
LSB
—
1.0
2.0
mA
DNL
Differential Non-linearity
INL
Integral Non-linearity
IADC
Additional Current Consumption
for A/D Converter Enable
3V
5V
3V
5V
3V
5V
No load, tADCK =0.5μs
—
1.5
3.0
mA
—
AN≠Temperature sensor output
0.5
—
10
μs
—
AN≠Temperature sensor output
1
—
2
μs
tADCK
Clock Period
tADC
Conversion Time
(Including A/D Sample and Hold Time)
—
AN≠Temperature sensor output
—
16
—
tADCK
—
AN≠Temperature sensor output
—
56
—
tADCK
tON2ST
A/D Converter On-to-Start Time
—
—
4
—
—
μs
Rev. 1.20
30
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Temperature Sensor Electrical Characteristics
Ta=25°C, Operating Temperature: -40°C~85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
VDD
Conditions
—
—
VDD
Operating Voltage
VTSVREF
Temperature Sensor Reference 3V Ta=25°C, Trim @ VDD=3V
Voltage
5V K_VPTAT=0, K_REFO=0
CodeTS
tTSS
A/D Conversion Code Range
Temperature Sensor Turn on
Stable Time
Min. Typ. Max. Unit
2.7
—
5.5
Typ.
Typ.
2.01
-5%
+5%
V
V
3V Ta=25°C, VREF=VTSVREF, G5XEN=1,
5V AN ＝ Temperature sensor output
2050 2250 2500 LSB
3V Ta=90°C, VREF=VTSVREF, G5XEN=1,
5V AN ＝ Temperature sensor output
3500 3850 4090 LSB
3V Ta=-40°C, VREF=VTSVREF, G5XEN=1,
5V AN ＝ Temperature sensor output
570
720
965
LSB
—
—
5
μs
3V
—
5V
LVD/LVR Electrical Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
LVR Enable, voltage select 2.1V
VLVR
VLVD
Low Voltage Reset Voltage
Low Voltage Detector Voltage
VBG
Bandgap Reference Voltage
IOP
LVD/LVR Operating Current
tBGS
VBG Turn on Stable Time
tLVDS
LVDO Stable Time
2.1
LVR Enable, voltage select 2.55V Typ. 2.55 Typ.
—
LVR Enable, voltage select 3.15V - 5% 3.15 + 5%
—
LVR Enable, voltage select 3.8V
3.8
LVD Enable, voltage select 2.0V
2.0
LVD Enable, voltage select 2.2V
2.2
LVD Enable, voltage select 2.4V
2.4
LVD Enable, voltage select 2.7V
2.7
Typ.
+ 5%
V
LVD Enable, voltage select 4.0V
4.0
—
Typ.
Typ.
1.04
- 5%
+ 5%
V
LVD Enable, voltage select 3.0V
Typ.
- 5%
V
3.0
LVD Enable, voltage select 3.3V
3.3
LVD Enable, voltage select 3.6V
3.6
—
5V LVD/LVR Enable, VBGEN=0
—
20
25
μA
5V LVD/LVR Enable, VBGEN=1
—
25
30
μA
— No load
—
—
150
μs
For LVR enable, VBGEN=0,
—
LVD off→on
—
—
15
μs
For LVR disable, VBGEN=0,
LVD off→on
—
—
150
μs
—
tLVR
Minimum Low Voltage Width to Reset
—
—
120
240
480
μs
tLVD
Minimum Low Voltage Width to Interrupt
—
—
60
120
240
μs
Rev. 1.20
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May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCD Driver Electrical Characteristics
Ta=25°C
Symbol
Parameter
VIN
LCD Operating Voltage
Test Conditions
Conditions
—
R type, power supply from PLCD pin,
PLCD[3:0]=1xxxB
3.0
—
—
C type, power supply from PLCD pin
2.0
—
3.7
V
—
C type, power supply from V1 pin
3.0
—
5.5
V
—
C type, power supply from V2 pin
1.0
—
1.8
V
—
C type, power supply from VA
3.0
—
5.5
V
—
C type, power supply from VB
2.0
—
3.7
V
—
C type, power supply from VC
2.2
—
5.5
V
3V
RT=1170kΩ, VA=PLCD=VDD,
1/3 bias, no load
—
—
12.5
μA
—
—
25
μA
RT=225kΩ, VA=PLCD=VDD,
1/3 bias, no load
—
—
25
μA
—
—
50
μA
RT=60kΩ, VA=PLCD=VDD,
1/3 bias, no load
—
—
100
μA
—
—
160
μA
—
—
2
μA
—
—
2.6
μA
210
420
—
μA
5V
Additional Current Consumption
for LCD Driver enable (R type)
ILCD
3V
5V
3V
5V
ILCDOL
ILCDOH
Min. Typ. Max. Unit
VDD
Additional Current Consumption
for LCD Driver Enable (C type)
3V
LCD Common and Segment Sink
Current
3V
LCD Common and Segment
Source Current
3V
5V
5V
5V
No load, C type
VOL=0.1VDD
VOL=0.9VDD
5.5
V
350
700
—
μA
-80
-160
—
μA
-180 -360
—
μA
Touch Key Electrical Characteristics
Ta=25°C
Touch Key RC Oscillator 500kHz Mode Selected
Symbol
Parameter
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
IREFOSC
Only Reference Oscillator
Operating Current
Test Conditions
Conditions
VDD
3V
5V
3V
5V
3V
5V
*fSENOSC=500kHz
*fREFOSC=500kHz, MnTSS=0
*fREFOSC=500kHz, MnTSS=1
Min. Typ. Max. Unit
—
30
60
—
60
120
—
30
60
—
60
120
—
30
60
—
60
120
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator External
Capacitor
5V *fSENOSC=500kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal
Capacitor
5V *fREFOSC=500kHz
5
10
20
pF
fKEYOSC
Sensor (KEY) Oscillator Operating
Frequency
5V
*CEXT=7, 8, 9, 10, 11, 12, 13, 14,
15, … , 50pF
100
500 1000 kHz
fREFOSC
Reference Oscillator Operating
Frequency
5V
* CINT=7, 8, 9, 10, 11, 12, 13, 14,
15, … , 50pF
100
500 1000 kHz
Note: 1. fSENOSC=500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 500kHz.
2. fREFOSC=500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 500kHz.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Touch Key RC Oscillator 1000kHz Mode Selected
Symbol
Parameter
IKEYOSC
Only Sensor (KEY) Oscillator Operating
Current
IREFOSC
Only Reference Oscillator Operating
Current
Test Conditions
Conditions
VDD
3V
5V
3V
5V
3V
5V
*fSENOSC=1000kHz
*fREFOSC=1000kHz, MnTSS=0
*fREFOSC=1000kHz, MnTSS=1
Min. Typ. Max. Unit
—
40
80
—
80
160
—
40
80
—
80
160
—
40
80
—
80
160
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator External Capacitor
5V *fSENOSC=1000kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal Capacitor
5V *fREFOSC=1000kHz
5
10
20
pF
fKEYOSC
Sensor (KEY) Oscillator Operating
Frequency
5V
*CEXT=1, 2, 3, 4, 5, 6, 7, 8,
9, … , 50pF
150 1000 2000 kHz
fREFOSC
Reference Oscillator Operating Frequency
5V
* CINT=1, 2, 3, 4, 5, 6, 7, 8,
9, … , 50pF
150 1000 2000 kHz
Note: 1. fSENOSC=1000kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 1000kHz.
2. fREFOSC=1000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 1000kHz.
Touch Key RC Oscillator 1500kHz Mode Selected
Symbol
IKEYOSC
Parameter
Only Sensor (KEY) Oscillator Operating
Current
Test Conditions
VDD
3V
5V
3V
IREFOSC
Only Reference Oscillator Operating
Current
5V
3V
5V
CKEYOSC
Sensor (KEY) Oscillator External Capacitor
CREFOSC
Reference Oscillator Internal Capacitor
fKEYOSC
fREFOSC
3V
5V
3V
5V
Conditions
*fSENOSC=1500kHz
*fREFOSC=1500kHz, MnTSS=0
*fREFOSC=1500kHz, MnTSS=1
*fSENOSC=1500kHz
*fREFOSC=1500kHz
Min. Typ. Max. Unit
—
60
120
—
120
240
—
60
120
—
120
240
—
60
120
—
120
240
μA
μA
μA
4
8
16
pF
5
10
20
pF
4
8
16
pF
5
10
20
pF
Sensor (KEY) Oscillator Operating
Frequency
3V *CEXT=1, 2, 3, 4, 5, 6, 7, 8,
5V 9, … , 50pF
150 1500 3000 kHz
Reference Oscillator Operating Frequency
3V * CINT=1, 2, 3, 4, 5, 6, 7, 8,
5V 9, … , 50pF
150 1500 3000 kHz
150 1500 3000 kHz
150 1500 3000 kHz
Note: 1. fSENOSC=1500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 1500kHz.
2. fREFOSC=1500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 1500kHz.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Touch Key RC Oscillator 2000kHz mode selected
Symbol
Test Conditions
Parameter
IKEYOSC
Only Sensor (KEY) Oscillator Operating
Current
IREFOSC
Only Reference Oscillator Operating
Current
3V
*fSENOSC=2000kHz
5V
3V
*fREFOSC=2000kHz, MnTSS=0
5V
3V
*fREFOSC=2000kHz, MnTSS=1
5V
CKEYOSC
Sensor (KEY) Oscillator External Capacitor
Min. Typ. Max. Unit
Conditions
VDD
3V
*fSENOSC=2000kHz
5V
3V
—
80
160
—
160
320
—
80
160
—
160
320
μA
μA
—
80
160
—
160
320
4
8
16
pF
5
10
20
pF
4
8
16
pF
5
10
20
pF
μA
CREFOSC
Reference Oscillator Internal Capacitor
fKEYOSC
Sensor (KEY) Oscillator Operating
Frequency
3V *CEXT=1, 2, 3, 4, 5, 6, 7, 8,
5V 9, … , 50pF
150 2000 4000 kHz
Reference Oscillator Operating Frequency
3V * CINT=1, 2, 3, 4, 5, 6, 7, 8,
5V 9, … , 50pF
150 2000 4000 kHz
fREFOSC
*fREFOSC=2000kHz
5V
150 2000 4000 kHz
150 2000 4000 kHz
Note: 1. fSENOSC=2000kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 2000kHz.
2. fREFOSC=2000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 2000kHz.
Power-on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
—
—
—
100
mV
RRPOR
VDD Raising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to Ensure
Power-on Reset
—
—
1
—
—
ms
Rev. 1.20
34
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set
operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplified by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O and A/D control system with maximum reliability and flexibility. This makes these
devices suitable for low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided
into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented
at the beginning of the T1 clock during which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock
cycle forms one instruction cycle. Although the fetching and execution of instructions takes place
in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that
instructions are effectively executed in one instruction cycle. The exception to this are instructions
where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
   
 
  
System Clocking and Pipelining
Rev. 1.20
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May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
  
    
 Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a nonconsecutive Program Memory address. For the device whose memory capacity is greater than 8K
words the Program Memory address may be located in a certain program memory bank which is
selected by the program memory bank pointer bit, PMBP0. Only the lower 8 bits, known as the
Program Counter Low Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
Device
High Byte
Low Byte (PCL)
PC11~PC8
PC7~PC0
BS67F350
PC12~PC8
PC7~PC0
BS67F360
PBP0, PC12~PC8
PC7~PC0
BS67F340
Program Counter
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly; however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack has multiple levels and is neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
If the stack is overflow, the first Program Counter save in the stack will be lost.
Program Counter
Top of Stack
Stack Level 1
Stack Level 2
Stack
Pointer
Stack Level 3
Bottom of Stack
Stack Level N
:
:
:
Program �emor�
Note: N=8 for BS67F340/BS67F350 while N=12 for BS67F360.
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations
ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA
• Logic operations
AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA
• Rotation
RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC
• Increment and Decrement
INCA, INC, DECA, DEC
LINCA, LINC, LDECA, LDEC
• Branch decision
JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA
Rev. 1.20
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May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For these devices
series the Program Memory are Flash type, which means it can be programmed and re-programmed
a large number of times, allowing the user the convenience of code modification on the same
device. By using the appropriate programming tools, these Flash devices offer users the flexibility to
conveniently debug and develop their applications while also offering a means of field programming
and updating.
Device
Capacity
Banks
BS67F340
4K × 16
—
BS67F350
8K × 16
—
BS67F360
16K × 16
0~1
Structure
The Program Memory has a capacity of 4K×16 to 16K×16 bits. The Program Memory is addressed
by the Program Counter and also contains data, table information and interrupt entries. Table data,
which can be setup in any location within the Program Memory, is addressed by a separate table
pointer registers.
000H
BS67F340
BS67F350
BS67F360
Initialisation Vector
Initialisation Vector
Initialisation Vector
Interrupt Vectors
Interrupt Vectors
Interrupt Vectors
Look-up Table
Look-up Table
Look-up Table
16 bits
16 bits
004H
02CH
n00H
nFFH
FFFH
16 bits
1FFFH
2000H
Bank 1
3FFFH
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by these devices reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the “TABRD [m]” or “TABRDL [m]” instructions respectively when the memory [m] is located in
sector 0. If the memory [m] is located in other sectors except sector 0, the data can be retrieved from
the program memory using the corresponding extended table read instruction such as “LTABRD [m]”
or “LTABRDL [m]” respectively. When the instruction is executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified
in the instruction. The higher order table data byte from the Program Memory will be transferred to
the TBLH special register. Any unused bits in this transferred higher order byte will be read as “0”.
The accompanying diagram illustrates the addressing data flow of the look-up table.
A d d re s s
L a s t p a g e o r
T B H P R e g is te r
T B L P R e g is te r
D a ta
1 6 b its
R e g is te r T B L H
U s e r S e le c te d
R e g is te r
H ig h B y te
L o w B y te
Table Program Example
The accompanying example shows how the table pointer and table data is defined and retrieved from
the device. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is “0F00H” which refers to the start address of the
last page within the 4K Program Memory of the device. The table pointer low byte register is setup
here to have an initial value of “06H”. This will ensure that the first data read from the data table will
be at the Program Memory address “0F06H” or 6 locations after the start of the last page. Note that
the value for the table pointer is referenced to the first address of the present page pointed by the TBHP
register if the “TABRD [m]” instruction is being used. The high byte of the table data which in this
case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]
instruction is executed.
Because the TBLH register is a read/write register and can be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a ; to the last page or the page that tbhp pointed
mov a,0fh ; initialise high table pointer
movtbhp,a
:
tabrd tempreg1 ; transfers value in table referenced by table pointer, data at program
; memory address “0F06H” transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data, at program
; memory address “0F05H” transferred to tempreg2 and TBLH, in this
; example the data “1AH” is transferred to tempreg1 and data “0FH” to
; register tempreg2
:
org 0F00h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
In Circuit Programming – ICP
The provision of Flash type Program Memory provides the user with a means of convenient and
easy upgrades and modifications to their programs on the same device.
As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing
their circuit boards complete with a programmed or un-programmed microcontroller, and then
programming or upgrading the program at a later stage. This enables product manufacturers to easily
keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device.
Holtek Writer Pins
MCU Programming Pins
ICPDA
PA0
Programming Serial Data/Address
Pin Description
ICPCK
PA2
Programming Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
The Program Memory and EEPROM data memory can be programmed serially in-circuit using this
4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line
for the clock. Two additional lines are required for the power supply. The technical details regarding
the in-circuit programming of the device are beyond the scope of this document and will be supplied
in supplementary literature.
During the programming process, the user must take care of the ICPDA and ICPCK pins for data
and clock programming purposes to ensure that no other outputs are connected to these two pins.
Rev. 1.20
40
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
W r ite r C o n n e c to r
S ig n a ls
M C U
W r ite r _ V D D
V D D
IC P D A
P A 0
IC P C K
P A 2
W r ite r _ V S S
V S S
*
P r o g r a m m in g
P in s
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance
of * must be less than 1nF.
On-Chip Debug Support – OCDS
There is an EV chip named BS67V3x0 which is used to emulate the real MCU device named
BS67F3x0. The EV chip device also provides the “On-Chip Debug” function to debug the real MCU
device during development process. The EV chip and real MCU devices, BS67V3x0 and BS67F3x0,
are almost functional compatible except the “On-Chip Debug” function. Users can use the EV chip
device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins
to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output
pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for
debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real
MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared
with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For
more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for
8-bit MCU OCDS User’s Guide”.
Holtek e-Link Pins
EV Chip OCDS Pins
Pin Description
OCDSDA
OCDSDA
On-Chip Debug Support Data/Address input/output
OCDSCK
OCDSCK
On-Chip Debug Support Clock input
VDD
VDD
Power Supply
VSS
VSS
Ground
In Application Programming – IAP
These devices offer IAP function to update data or application program to flash ROM. Users can
define any ROM location for IAP, but there are some features which user must notice in using IAP
function. Note that the BS67F340 device supports the “Block Erase” function instead of the “Page
Erase” function.
BS67F340 Configurations
Rev. 1.20
BS67F350 Configurations
BS67F360 Configurations
Erase Block
256 words/block
Erase Page
32 words/page
Erase Page
64 words/page
Writing Word
4 words / time
Writing Word
32 words/time
Writing Word
64 words/time
Reading Word
1 word / time
Reading Word
1 word / time
Reading Word
1 word / time
41
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
In Application Programming Control Registers
The Address register, FARL and FARH, the Data registers, FD0L/FD0H, FD1L/FD1H, FD2L/FD2H
and FD3L/FD3H, and the Control registers, FC0, FC1 and FC2, are the corresponding Flash access
registers located in Data Memory sector 0 for IAP. If using the indirect addressing method to access
the FC0, FC1 and FC2 registers, all read and write operations to the registers must be performed
using the Indirect Addressing Register, IAR1 or IAR2, and the Memory Pointer pair, MP1L/MP1H
or MP2L/MP2H. Because the FC0, FC1 and FC2 control registers are located at the address of
50H~52H in Data Memory sector 0, the desired value ranged from 50H to 52H must first be written
into the MP1L or MP2L Memory Pointer low byte and the value “00H” must also be written into the
MP1H or MP2H Memory Pointer high byte.
Register Name
Bit
7
6
5
4
3
2
1
0
CFWEN FMOD2 FMOD1 FMOD0 FWPEN
FRD
FWT
FRDEN
FC1
D7
D6
D5
D4
D3
D2
D1
D0
FC2 (BS67F350/360)
—
—
—
—
—
—
—
CLWB
FARL
A7
A6
A5
A4
A3
A2
A1
A0
FARH (BS67F340)
—
—
—
—
A11
A10
A9
A8
A8
FC0
FARH (BS67F350)
—
—
—
A12
A11
A10
A9
FARH (BS67F360)
—
—
A13
A12
A11
A10
A9
A8
FD0L
D7
D6
D5
D4
D3
D2
D1
D0
FD0H
D15
D14
D13
D12
D11
D10
D9
D8
FD1L
D7
D6
D5
D4
D3
D2
D1
D0
FD1H
D15
D14
D13
D12
D11
D10
D9
D8
FD2L
D7
D6
D5
D4
D3
D2
D1
D0
FD2H
D15
D14
D13
D12
D11
D10
D9
D8
FD3L
D7
D6
D5
D4
D3
D2
D1
D0
FD3H
D15
D14
D13
D12
D11
D10
D9
D8
IAP Registers List
Rev. 1.20
42
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• FC0 Register
Bit
7
6
5
4
3
2
1
0
Name
CFWEN
FMOD2
FMOD1
FMOD0
FWPEN
FWT
FRDEN
FRD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
1
1
0
0
0
0
Bit 7CFWEN: Flash Memory Write enable control
0: Flash memory write function is disabled
1: Flash memory write function has been successfully enabled
When this bit is cleared to 0 by application program, the Flash memory write function
is disabled. Note that writing a “1” into this bit results in no action. This bit is used
to indicate that the Flash memory write function status. When this bit is set to 1 by
hardware, it means that the Flash memory write function is enabled successfully.
Otherwise, the Flash memory write function is disabled as the bit content is zero.
Bit 6~4FMOD2~FMOD0: Mode selection
000: Write program memory
001: Block/Page erase program memory
010: Reserved
011: Read program memory
10x: Reserved
110: FWEN mode – Flash memory Write function Enabled mode
111: Reserved
When these bits are set to “001”, the “Block erase” mode is selected for BS67F340
while the “Page erase” mode is selected for BS67F350/BS67F360.
Bit 3FWPEN: Flash memory Write Procedure Enable control
0: Disable
1: Enable
When this bit is set to 1 and the FMOD field is set to “110”, the IAP controller will
execute the “Flash memory write function enable” procedure. Once the Flash memory
write function is successfully enabled, it is not necessary to set the FWPEN bit any
more.
Bit 2FWT: Flash memory Write Initiate control
0: Do not initiate Flash memory write or Flash memory write process is completed
1: Initiate Flash memory write process
This bit is set by software and cleared by hardware when the Flash memory write
process is completed.
Bit 1FRDEN: Flash memory Read Enable control
0: Flash memory read disable
1: Flash memory read enable
Bit 0FRD: Flash memory Read Initiate control
0: Do not initiate Flash memory read or Flash memory read process is completed
1: Initiate Flash memory read process
This bit is set by software and cleared by hardware when the Flash memory read
process is completed.
Rev. 1.20
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May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• FC1 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Whole chip reset pattern
When user writes a specific value of “55H” to this register, it will generate a reset
signal to reset whole chip.
• FC2 Register – BS67F350/BS67F360
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
CLWB
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as 0
Bit 0CLWB: Flash memory Write Buffer Clear control
0: Do not initiate Write Buffer Clear process or Write Buffer Clear process is
completed
1: Initiate Write Buffer Clear process
This bit is set by software and cleared by hardware when the Write Buffer Clear
process is completed.
• FARL Register
Bit
7
6
5
4
3
2
1
0
Name
A7
A6
A5
A4
A3
A2
A1
A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Flash Memory Address bit 7 ~ bit 0
• FARH Register – BS67F340
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
A11
A10
A9
A8
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
3
2
1
0
Bit 7~4
Unimplemented, read as 0.
Bit 3~0
Flash Memory Address bit 11 ~ bit 8
• FARH Register – BS67F350
Rev. 1.20
Bit
7
6
5
4
Name
—
—
—
A12
A11
A10
A9
A8
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7~5
Unimplemented, read as 0.
Bit 4~0
Flash Memory Address bit 12 ~ bit 8
44
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• FARH Register – BS67F360
Bit
7
6
5
4
3
2
1
0
Name
—
—
A13
A12
A11
A10
A9
A8
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as 0.
Bit 5~0
Flash Memory Address bit 13 ~ bit 8
• FD0L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The first Flash Memory data bit 7 ~ bit 0
• FD0H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The first Flash Memory data bit 15 ~ bit 8
• FD1L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The second Flash Memory data bit 7 ~ bit 0
• FD1H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
The second Flash Memory data bit 15 ~ bit 8
• FD2L Register
Bit
6
5
4
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.20
7
The third Flash Memory data bit 7 ~ bit 0
45
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• FD2H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The third Flash Memory data bit 15 ~ bit 8
• FD3L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
The fourth Flash Memory data bit 7 ~ bit 0
• FD3H Register
Bit
7
6
5
4
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The fourth Flash Memory data bit 15 ~ bit 8
Flash Memory Write Function Enable Procedure
In order to allow users to change the Flash memory data through the IAP control registers, users
must first enable the Flash memory write operation by the following procedure:
1. Write “110” into the FMOD2~FMOD0 bits to select the FWEN mode.
2. Set the FWPEN bit to “1”. The step 1 and step 2 can be executed simultaneously.
3. The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written into the
FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively.
4. A counter with a time-out period of 300μs will be activated to allow users writing the correct
pattern data into the FD1L/FD1H ~ FD3L/FD3H register pairs. The counter clock is derived from
LIRC oscillator.
5. If the counter overflows or the pattern data is incorrect, the Flash memory write operation will
not be enabled and users must again repeat the above procedure. Then the FWPEN bit will
automatically be cleared to 0 by hardware.
6. If the pattern data is correct before the counter overflows, the Flash memory write operation will
be enabled and the FWPEN bit will automatically be cleared to 0 by hardware. The CFWEN bit
will also be set to 1 by hardware to indicate that the Flash memory write operation is successfully
enabled.
7. Once the Flash memory write operation is enabled, the user can change the Flash ROM data
through the Flash control register.
8. To disable the Flash memory write operation, the user can clear the CFWEN bit to 0.
Rev. 1.20
46
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Is counter
overflow ?
Flash Memory
Write Function
Enable Procedure
No
Yes
FWPEN=0
Set FMOD [2:0] =110 & FWPEN=1
→ Select FWEN mode & Start Flash write
Hardware activate a counter
Is pattern
correct ?
Wrtie the following pattern to Flash Data registers
FD1L= 00h , FD1H = 04h
FD2L= 0Dh , FD2H = 09h
FD3L= C3h , FD3H = 40h
No
Yes
CFWEN = 1
CFWEN=0
Success
Failed
END
Flash Memory Write Function Enable Procedure
Rev. 1.20
47
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Flash Memory Read/Write Procedure
After the Flash memory write function is successfully enabled through the preceding IAP procedure,
users must first erase the corresponding Flash memory block or page and then initiate the Flash
memory write operation. For the BS67F340 device the number of the block erase operation is
256 words per block, the available block erase address is only specified by FARH register and
the content in the FARL register is not used to specify the block address. For the BS67F350 and
BS67F360 devices the number of the page erase operation is 32 and 64 words per page respectively,
the available page erase address is specified by FARH register and the content of FARL [7:5] and
FARL [7:6] bit field respectively.
Erase Block
FARH [3:0]
FARL [7:0]
0
0000
xxxx xxxx
1
0001
xxxx xxxx
2
0010
xxxx xxxx
3
0011
xxxx xxxx
4
0100
xxxx xxxx
5
0101
xxxx xxxx
6
0110
xxxx xxxx
7
0111
xxxx xxxx
8
1000
xxxx xxxx
9
1001
xxxx xxxx
10
1010
xxxx xxxx
11
1011
xxxx xxxx
12
1100
xxxx xxxx
13
1101
xxxx xxxx
14
1110
xxxx xxxx
15
1111
xxxx xxxx
“x”: don’t care
BS67F340 Erase Block Number and Selection
Rev. 1.20
48
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Erase Page
FARH
FARL [7:5]
FARL [4:0]
0
0000 0000
000
x xxxx
1
0000 0000
001
x xxxx
2
0000 0000
010
x xxxx
3
0000 0000
011
x xxxx
4
0000 0000
100
x xxxx
5
0000 0000
101
x xxxx
6
0000 0000
110
x xxxx
7
0000 0000
111
x xxxx
8
0000 0001
000
x xxxx
9
0000 0001
001
x xxxx
:
:
:
:
:
:
:
:
126
0000 1111
110
x xxxx
127
0000 1111
111
x xxxx
128
0001 0000
000
x xxxx
129
0001 0000
001
x xxxx
:
:
:
:
:
:
:
:
254
0001 1111
110
x xxxx
255
0001 1111
111
x xxxx
“x”: don’t care
BS67F350 Erase Page Number and Selection
Erase Page
FARH
FARL [7:6]
0
0000 0000
00
FARL [5:0]
xx xxxx
1
0000 0000
01
xx xxxx
2
0000 0000
10
xx xxxx
3
0000 0000
11
xx xxxx
4
0000 0001
00
xx xxxx
5
0000 0001
01
xx xxxx
:
:
:
:
:
:
:
:
126
0001 1111
10
xx xxxx
127
0001 1111
11
xx xxxx
128
0010 0000
00
xx xxxx
129
0010 0000
01
xx xxxx
:
:
:
:
:
:
:
:
254
0011 1111
10
xx xxxx
255
0011 1111
11
xx xxxx
“x”: don’t care
BS67F350 Erase Page Number and Selection
Rev. 1.20
49
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Read
Flash �emor�
Set F�OD [2:0]=011
& FRDEN=1
Set Flash Address registers
FARH=xxh, FARL=xxh
Set FRD=1
No
FRD=0 ?
Yes
Read data value:
FD0L=xxh, FD0H=xxh
Read Finish ?
No
Yes
Clear FRDEN bit
END
Read Flash Memory Procedure
Rev. 1.20
50
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Write
Flash �emor�
Flash �emor�
Write Function
Enable Procedure
Set Block Erase address: FARH/FARL
Set F�OD [2:0]=001 & FWT=1
Select “Block Erase mode”
& Initiate write operation
No
FWT=0 ?
Yes
Set F�OD [2:0]=000
Select “Write Flash �ode”
Set Write starting address: FARH/FARL
Write data to data register:
FD0L/FD0H, FD1L/FD1H,
FD2L/FD2H, FD3L/FD3H,
Set FWT=1
No
FWT=0 ?
Yes
Write Finish ?
No
Yes
Clear CFWEN=0
END
Write Flash Memory Procedure – BS67F340
Rev. 1.20
51
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Write
Flash �emor�
Flash �emor�
Write Function
Enable Procedure
Set Page Erase address: FARH/FARL
Set F�OD [2:0]=001 & FWT=1
Select “Page Erase mode”
& Initiate write operation
No
FWT=0 ?
Yes
Set F�OD [2:0]=000
Select “Write Flash �ode”
Set Write starting address: FARH/FARL
Write data to data register: FD0L/FD0H
No
Page data
Write finish
Yes
Set FWT=1
No
FWT=0 ?
Yes
Write Finish ?
No
Yes
Clear CFWEN=0
END
Write Flash Memory Procedure – BS67F350/BS67F360
Note: When the FWT or FRD bit is set to 1, the MCU is stopped.
Rev. 1.20
52
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Data Memory
The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary
information is stored.
Divided into two types, the first of Data Memory is an area of RAM where special function registers
are located. These registers have fixed locations and are necessary for correct operation of the
device. Many of these registers can be read from and written to directly under program control,
however, some remain protected from user manipulation. The second area of Data Memory is
reserved for general purpose use. All locations within this area are read and write accessible under
program control.
Switching between the different Data Memory sectors is achieved by properly setting the Memory
Pointers to correct value.
Structure
The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide
Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data
Memory and the General Purpose Data Memory.
The address range of the Special Purpose Data Memory for the device is from 00H to 7FH. The
General Purpose Data Memory address range is from 80H to FFH except the LCD Display and
Touch Key Module Data Memory. The LCD Data Memory is located in sector 4 with a start address
of 00H. The Touch Key Modul Data Memory is located in sector 5 and sector 6 respectively with a
start address of 00H.
Device
Special Purpose
Data Memory
Located Sectors
Capacity
BS67F340
0, 1
BS67F350
BS67F360
0, 1
0, 1
General Purpose
Data Memory
LCD Display
Data Memory
Touch Key Module
Data Memory
Sector : Address
Sector : Address
Sector : Address
512×8
0: 80H~FFH
1: 80H~FFH
2: 80H~FFH
3: 80H~FFH
4: 00H~17H
5: 00H~1FH
6: 00H~1FH
768×8
0: 80H~FFH
1: 80H~FFH
:
5: 80H~FFH
4: 00H~1FH
5: 00H~27H
6: 00H~27H
1024×8
0: 80H~FFH
1: 80H~FFH
:
7: 80H~FFH
4: 00H~27H
5: 00H~37H
6: 00H~37H
Data Memory Summary
Rev. 1.20
53
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
00H
LCD Displa�
Data �emor�
(Sector 4)
Special Purpose
Data �emor�
(Sector 0 ~ Sector 1)
Touch Ke� �odule
Data �emor�
7FH
80H
(Sector �~Sector 6)
General Purpose
Data �emor�
(Sector 0 ~ Sector N)
FFH
Sector 0
Sector 1
Sector N
Note: N=3 for BS67F340;
N=5 for BS67F350;
N=7 for BS67F360;
Data Memory Structure
Data Memory Addressing
For these devices that support the extended instructions, there is no Bank Pointer for Data Memory.
The Bank Pointer, PBP, is only available for Program Memory. For Data Memory the desired Sector
is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected
sector is specified by the MP1L or MP2L register when using indirect addressing access.
Direct Addressing can be used in all sectors using the corresponding instruction which can address
all available data memory space. For the accessed data memory which is located in any data
memory sectors except sector 0, the extended instructions can be used to access the data memory
instead of using the indirect addressing access. The main difference between standard instructions
and extended instructions is that the data memory address “m” in the extended instructions can be
from 10 bits to 11 bits depending upon which device is selected, the high byte indicates a sector and
the low byte indicates a specific address.
General Purpose Data Memory
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user programing for both reading
and writing operations. By using the bit operation instructions individual bits can be set or reset
under program control giving the user a large range of flexibility for bit manipulation in the Data
Memory.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value “00H”.
Rev. 1.20
54
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
INTEG
SCC
HIRCC
HXTC
LXTC
LVDC
LVRC
WDTC
RSTC
PC
PCC
PCPU
PD
PDC
PDPU
MFI0
MFI1
MFI2
MFI3
ADRL
ADRH
ADCR0
ADCR1
PSCR0
TB0C
TB1C
SIMTOC
SIMC0
SIMC1
SIMD
SIMA/SIMC2
CTM0C0
CTM0C1
CTM0DL
CTM0DH
CTM0AL
CTM0AH
Sector 1
TKTMR
TKC0
TK16DL
TK16DH
TKC1
TKM016DL
TKM016DH
TKM0ROL
TKM0ROH
TKM0C0
TKM0C1
TKM0C2
TKM116DL
TKM116DH
TKM1ROL
TKM1ROH
TKM1C0
TKM1C1
TKM1C2
TKM216DL
TKM216DH
TKM2ROL
TKM2ROH
TKM2C0
TKM2C1
TKM2C2
TKM316DL
TKM316DH
TKM3ROL
TKM3ROH
TKM3C0
TKM3C1
TKM3C2
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
Sector 0
EEA
EED
PSCR1
LCDC0
LCDC1
PTMC0
PTMC1
PTMDL
PTMDH
PTMAL
PTMAH
PTMRPL
PTMRPH
FC0
FC1
Sector 1
EEC
IFS
PAS0
PAS1
PBS0
PBS1
PCS0
PDS1
PES0
PES1
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
STMRP
CTM1C0
CTM1C1
CTM1DL
CTM1DH
CTM1AL
CTM1AH
TSC0
TSC1
TSC2
TSC3
PE
PEC
PEPU
USR
UCR1
UCR2
TXR_RXR
BRG
7FH
: Unused, read as 00H
Speciap Purpose Data Memory Structure – BS67F340
Rev. 1.20
55
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
INTEG
SCC
HIRCC
HXTC
LXTC
LVDC
LVRC
WDTC
RSTC
PC
PCC
PCPU
PD
PDC
PDPU
MFI0
MFI1
MFI2
MFI3
ADRL
ADRH
ADCR0
ADCR1
PSCR0
TB0C
TB1C
SIMTOC
SIMC0
SIMC1
SIMD
SIMA/SIMC2
CTM0C0
CTM0C1
CTM0DL
CTM0DH
CTM0AL
CTM0AH
Sector 1
TKTMR
TKC0
TK16DL
TK16DH
TKC1
TKM016DL
TKM016DH
TKM0ROL
TKM0ROH
TKM0C0
TKM0C1
TKM0C2
TKM116DL
TKM116DH
TKM1ROL
TKM1ROH
TKM1C0
TKM1C1
TKM1C2
TKM216DL
TKM216DH
TKM2ROL
TKM2ROH
TKM2C0
TKM2C1
TKM2C2
TKM316DL
TKM316DH
TKM3ROL
TKM3ROH
TKM3C0
TKM3C1
TKM3C2
TKM416DL
TKM416DH
TKM4ROL
TKM4ROH
TKM4C0
TKM4C1
TKM4C2
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
Sector 0
EEA
EED
PSCR1
LCDC0
LCDC1
PTMC0
PTMC1
PTMDL
PTMDH
PTMAL
PTMAH
PTMRPL
PTMRPH
FC0
FC1
FC2
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
STMRP
CTM1C0
CTM1C1
CTM1DL
CTM1DH
CTM1AL
CTM1AH
TSC0
TSC1
TSC2
TSC3
Sector 1
EEC
IFS
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PE
PEC
PEPU
USR
UCR1
UCR2
TXR_RXR
BRG
7FH
: Unused, read as 00H
Speciap Purpose Data Memory Structure – BS67F350
Rev. 1.20
56
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
PBP
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
INTEG
SCC
HIRCC
HXTC
LXTC
LVDC
LVRC
WDTC
RSTC
PC
PCC
PCPU
PD
PDC
PDPU
MFI0
MFI1
MFI2
MFI3
ADRL
ADRH
ADCR0
ADCR1
PSCR0
TB0C
TB1C
SIMTOC
SIMC0
SIMC1
SIMD
SIMA/SIMC2
CTM0C0
CTM0C1
CTM0DL
CTM0DH
CTM0AL
CTM0AH
Sector 1
TKTMR
TKC0
TK16DL
TK16DH
TKC1
TKM016DL
TKM016DH
TKM0ROL
TKM0ROH
TKM0C0
TKM0C1
TKM0C2
TKM116DL
TKM116DH
TKM1ROL
TKM1ROH
TKM1C0
TKM1C1
TKM1C2
TKM216DL
TKM216DH
TKM2ROL
TKM2ROH
TKM2C0
TKM2C1
TKM2C2
TKM316DL
TKM316DH
TKM3ROL
TKM3ROH
TKM3C0
TKM3C1
TKM3C2
TKM416DL
TKM416DH
TKM4ROL
TKM4ROH
TKM4C0
TKM4C1
TKM4C2
TKM516DL
TKM516DH
TKM5ROL
TKM5ROH
TKM5C0
TKM5C1
TKM5C2
TKM616DL
TKM616DH
TKM6ROL
TKM6ROH
TKM6C0
TKM6C1
TKM6C2
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
Sector 0
EEA
EED
PSCR1
LCDC0
LCDC1
PTMC0
PTMC1
PTMDL
PTMDH
PTMAL
PTMAH
PTMRPL
PTMRPH
FC0
FC1
FC2
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
STMRP
CTM1C0
CTM1C1
CTM1DL
CTM1DH
CTM1AL
CTM1AH
TSC0
TSC1
TSC2
TSC3
Sector 1
EEC
IFS
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PFS0
PE
PEC
PEPU
PF
PFC
PFPU
USR
UCR1
UCR2
TXR_RXR
BRG
7FH
: Unused, read as 00H
Speciap Purpose Data Memory Structure – BS67F360
Rev. 1.20
57
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section.
However, several registers require a separate description in this section.
Indirect Addressing Registers − IAR0, IAR1, IAR2
The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal
RAM register space, do not actually physically exist as normal registers. The method of indirect
addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory
Pointers, in contrast to direct memory addressing, where the actual memory address is specified.
Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to
these registers but rather to the memory location specified by their corresponding Memory Pointers,
MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data
only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2
register together with MP2L/MP2H register pair can access data from any Data Memory sector. As
the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing
Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in
no operation.
Memory Pointers − MP0, MP1H/MP1L, MP2H/MP2L
Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These
Memory Pointers are physically implemented in the Data Memory and can be manipulated in the
same way as normal registers providing a convenient way with which to address and track data.
When any operation to the relevant Indirect Addressing Registers is carried out, the actual address
that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0,
together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while
MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data
from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can
be used in all data sectors using the corresponding instruction which can address all available data
memory space.
Indirect Addressing Program Example
Example 1
data .section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org 00h
start:
mov a,04h;
mov block,a
mov a,offset adres1 ;
mov mp0,a ;
loop:
clr IAR0 ;
inc mp0;
sdz block;
jmp loop
continue:
:
Rev. 1.20
setup size of block
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by MP0
increment memory pointer
check if last memory location has been cleared
58
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Example 2
data .section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ‘code’
org 00h
start:
mov a,04h;
mov block,a
mov a,01h;
mov mp1h,a
mov a,offset adres1 ;
mov mp1l,a ;
loop:
clr IAR1 ;
inc mp1l ;
sdz block;
jmp loop
continue:
:
setup size of block
setup the memory sector
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by MP1L
increment memory pointer MP1L
check if last memory location has been cleared
The important point to note here is that in the example shown above, no reference is made to specific
RAM addresses.
Direct Addressing Program Example using extended instructions
data .section ‘data’
temp db ?
code .section at 0 code
org 00h
start:
lmov
a,[m]; move [m] data to acc
lsuba, [m+1] ; compare [m] and [m+1] data
snz
c; [m]>[m+1]?
jmp continue; no
lmov
a,[m]; yes, exchange [m] and [m+1] data
movtemp,a
lmova,[m+1]
lmov[m],a
mova,temp
lmov[m+1],a
continue:
:
Note: Here “m” is a data memory address located in any data memory sectors. For example,
m=1F0H, it indicates address 0F0H in Sector 1.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Program Memory Bank Pointer – PBP
For the BS67F360 device the Program Memory is divided into several banks. Selecting the required
Program Memory area is achieved using the Program Memory Bank Pointer, PBP. The PBP register
should be properly configured before the device executes the “Branch” operation using the “JMP”
or “CALL” instruction. After that a jump to a non-consecutive Program Memory address which is
located in a certain bank selected by the program memory bank pointer bits will occur.
PBP Register – BS67F360
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
PBP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~1D7~D1: General data bits and can be read or written.
Bit 0PBP0: Program Memory Bank Point bit 0
0: Bank 0
1: Bank 1
Accumulator − ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register − PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location
where the table data is located. Their value must be setup before any table read commands are
executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Status Register − STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/
logical operation and system management flags are used to record the status and operation of the
microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
• SC is the result of the “XOR” operation which is performed by the OV flag and the MSB of the
current instruction operation result.
• CZ is the operational result of different flags for different instuctions. Refer to register definitions
for more details.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
SC
CZ
TO
PDF
OV
Z
AC
C
R/W
R
R
R
R
R/W
R/W
R/W
R/W
POR
x
x
0
0
x
x
x
x
“x”: unknown
Bit 7SC: The result of the “XOR” operation which is performed by the OV flag and the
MSB of the instruction operation result.
Bit 6CZ: The the operational result of different flags for different instuctions.
For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag.
For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the “AND” operation
result which is performed by the previous operation CZ flag and current operation zero
flag. For other instructions, the CZ flag willl not be affected.
Bit 5TO: Watchdog Time-out flag
0: After power up ow executing the “CLR WDT” or “HALT” instruction
1: A watchdog time-out occurred
Bit 4PDF: Power down flag
0: After power up ow executing the “CLR WDT” instruction
1: By executing the “HALT” instructin
Bit 3OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa
Bit 2Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles, in addition, or no borrow
from the high nibble into the low nibble in substraction
Bit 0C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
The “C” flag is also affected by a rotate through carry instruction.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
EEPROM Data Memory
These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for
Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form
of re-programmable memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are made
available to the designer. The availability of EEPROM storage allows information such as product
identification numbers, calibration values, specific user data, system setup data or other product
information to be stored directly within the product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced to a very trivial affair.
Device
Capacity
Address
128×8
00H ~ 7FH
BS67F340
BS67F350
BS67F360
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is 128×8 bits for the series of devices. Unlike the Program
Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory
space and is therefore not directly addressable in the same way as the other types of memory. Read
and Write operations to the EEPROM are carried out in single byte operations using an address and
data register in sector 0 and a single control register in sector 1.
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in sector 0, they can be directly accessed in the same was as any other
Special Function Register. The EEC register, however, being located in sector 1, can be read from
or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect
Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H
in sector 1, the Memory Pointer low byte register, MP1L or MP2L, must first be set to the value
40H and the Memory Pointer high byte register, MP1H or MP2H, set to the value, 01H, before any
operations on the EEC register are executed.
Bit
Register
Name
7
6
5
4
3
2
1
0
EEA
—
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
EEPROM Registers List
EEA Register
Bit
7
6
5
4
3
2
1
0
Name
—
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as 0.
Bit 6~0EEA6~EEA0: Data EEPROM address bit 6 ~ bit0
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0D7~D0: Data EEPROM data bit 7~bit0
EEC Register
Bit
7
6
5
4
3
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as 0.
Bit 3WREN: Data EEPROM write enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2WR: EEPROM write control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1RDEN: Data EEPROM read enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0RD: EEPROM read control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The
WR and RD can not be set to “1” at the same time.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM
To write data to the EEPROM, the EEPROM address of the data to be written must first be placed
in the EEA register and the data placed in the EED register. Then the write enable bit, WREN,
in the EEC register must first be set high to enable the write function. After this, the WR bit in
the EEC register must be immediately set high to initiate a write cycle. These two instructions
must be executed consecutively. The global interrupt bit EMI should also first be cleared before
implementing any write operations, and then set again after the write cycle has started. Note that
setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the
EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to
microcontroller system clock, a certain time will elapse before the data will have been written into
the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the
WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates,
the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the
data has been written to the EEPROM. The application program can therefore poll the WR bit to
determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered on, the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset
to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control register
is located in sector 1, this adds a further measure of protection against spurious write operations.
During normal program operation, ensuring that the Write Enable bit in the control register is
cleared will safeguard against incorrect write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However, as
the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic
by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory
Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1
where the EEPROM control register exist. Although certainly not necessary, consideration might be
given in the application program to the checking of the validity of new write data by a simple read
back process. When writing data the WR bit must be set high immediately after the WREN bit has
been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also
be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that
the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is
totally complete. Otherwise, the EEPROM read or write operation will fail.
Programming Example
Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, 040H
MOV MP1L, A
MOV A, 01H
MOV MP1H, A
SET IAR1.1
SET IAR1.0
BACK:
SZ IAR1.0
JMP BACK
CLR IAR1
CLR MP1H
MOV A, EED
MOV READ_DATA, A
; user defined address
; setup memory pointer low byte MP1L
; MP1L points to EEC register
; setup Memory Pointer high byte MP1H
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM write
; move read data to register
Writing Data to the EEPROM – polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA
MOV EED, A
MOV A, 040H
MOV MP1L, A
MOV A, 01H
MOV MP1H, A
CLR EMI
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ IAR1.2
JMP BACK
CLR IAR1
CLR MP1H
Rev. 1.20
; user defined address
; user defined data
; setup memory pointer low byte MP1L
; MP1L points to EEC register
; setup Memory Pointer high byte MP1H
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM write
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Oscillator
Various oscillator types offer the user a wide range of functions according to their various application
requirements. The flexible features of the oscillator functions ensure that the best optimisation can
be achieved in terms of speed and power saving. Oscillator selections and operation are selected
through a combination of application program and relevant control registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external
components as well as fully integrated internal oscillators, requiring no external components, are
provided to form a wide range of both fast and slow system oscillators. All oscillator options are
selected through register programming. The higher frequency oscillators provide higher performance
but carry with it the disadvantage of higher power requirements, while the opposite is of course true
for the lower frequency oscillators. With the capability of dynamically switching between fast and
slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature
especially important in power sensitive portable applications.
Name
Frequency
Pins
External High Speed Crystal
Type
HXT
400kHz~20MHz
OSC1/OSC2
Internal High Speed RC
HIRC
8/12/16MHz
—
External Low Speed Crystal
LXT
32.768kHz
XT1/XT2
Internal Low Speed RC
LIRC
32kHz
—
Oscillator Types
System Clock Configurations
There are four methods of generating the system clock, two high speed oscillators for all devices
and two low speed oscillators. The high speed oscillator is the external crystal/ceramic oscillator,
HXT, and the internal 8/12/16MHz RC oscillator, HIRC. The two low speed oscillators are the
internal 32kHz RC oscillator, LIRC, and the external 32.768 kHz crystal oscillator, LXT. Selecting
whether the low or high speed oscillator is used as the system oscillator is implemented using the
CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected.
The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC
register while for the high speed oscillator the source clock is selected by the FHS bit in the SCC
register. The frequency of the slow speed or high speed system clock is determined using the
CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one
high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection
for either the high or low speed oscillator.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
fH
High Speed
Oscillation
HIRCEN
HIRC
HXTEN
HXT
FHS
fH/2
fH/4
fH/8
Prescaler
fH
fSYS
fH/16
fH/32
fH/64
Low Speed
Oscillation
FSS
CKS2~CKS0
LXTEN
LXT
fSUB
fSUB
fLIRC
LIRC
fLIRC
System Clock Configurations
External Crystal/Ceramic Oscillator − HXT
The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the
default oscillator clock source after power on. For most crystal oscillator configurations, the simple
connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer’s specification.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
     Crystal/Resonator Oscillator
HXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0 pF
0 pF
8MHz
0 pF
0 pF
4MHz
0 pF
0 pF
1MHz
100 pF
100 pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Internal High Speed RC Oscillator − HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 8/12/16 MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 3V or 5V and at a temperature
of 25°C degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 2%. Note
that if this internal system clock option is selected, as it requires no external pins for its operation, I/
O pins are free for use as normal I/O pins.
External 32.768 kHz Crystal Oscillator − LXT
The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices,
which is selected via a software control bit, FSS. This clock source has a fixed frequency of
32.768kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The
external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to
provide oscillation. For applications where precise frequencies are essential, these components may
be required to provide frequency compensation due to different crystal manufacturing tolerances.
After the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated
with the LXT oscillator waiting for it to start-up.
When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. However, in many microcontroller applications it may
be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or
IDLE Mode. To do this, another clock, independent of the system clock, must be provided.
However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary
to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be
selected in consultation with the crystal or resonator manufacturer’s specification. The external
parallel feedback resistor, Rp, is required.
The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator
or as I/O or other pin-shared functional pins.
• If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O
or other pin-shared functional pins.
• If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to
the XT1/XT2 pins.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
‚   
­ €
  ‚  External LXT Oscillator
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the Speed-Up Mode and the Low-Power
Mode. The mode selection is executed using the LXTSP bit in the LXTC register.
LXTSP
LXT Operating Mode
0
Low-Power
1
Speed-Up
When the LXTSP bit is set to high, the LXT Quick Start Mode will be enabled. In the Speed-Up
Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has
fully powered up, it can be placed into the Low-Power Mode by clearing the LXTSP bit to zero and
the oscillator will continue to run but with reduced current consumption. It is important to note that
the LXT operating mode switching must be properly controlled before the LXT oscillator clock is
selected as the system clock source. Once the LXT oscillator clock is selected as the system clock
source using the CKS bit field and FSS bit in the SCC register, the LXT oscillator operating mode
can not be changed.
It should be note that no matter what condition the LXTSP is set to the LXT oscillator will always
function normally. The only difference is that it will take more time to start up if in the Low Power
Mode.
Internal 32kHz Oscillator − LIRC
The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is
selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency
of 32 kHz at 5V, requiring no external components for its implementation. Device trimming during
the manufacturing process and the inclusion of internal frequency compensation circuits are used
to ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of
25˚C degrees, the fixed oscillation frequency of 32 kHz will have a tolerance within 10%.
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Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided these devices with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
Each device has different clock sources for both the CPU and peripheral function operation. By
providing the user with a wide range of clock selections using register programming, a clock system
can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source,
and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is
sourced from an HXT or HIRC oscillator, selected via configuring the FHS bit in the SCC register.
The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected
then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in
the SCC register. The other choice, which is a divided version of the high speed system oscillator
has a range of fH/2~fH/64.
fH
High Speed
Oscillation
HIRCEN
HXTEN
FHS
fH/2
fH/4
HIRC
fH/8
Prescaler
fH
HXT
fSYS
fH/16
fH/32
fH/64
FSS
LXTEN
CKS2~CKS0
LXT
fSUB
LIRC
fSUB
fLIRC
fSYS
fSYS/4
Low Speed
Oscillation
fPSC0
fSUB
Prescaler 0
Time Base 0
TB0 [2:0]
CLKSEL0[1:0]
fSYS
fSYS/4
fPSC1
fSUB
Prescaler 1
Time Base 1
TB1 [2:0]
CLKSEL1[1:0]
fLIRC
fLIRC
WDT
LVR
Device Clock Configurations
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation can be
stopped to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for
peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit.
System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP,
IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve
power.
Operation
Mode
CPU
NORMAL
On
SLOW
On
Register Setting
FHIDEN FSIDEN CKS2~CKS0
x
x
x
000~110
x
IDLE0
Off
0
1
IDLE1
Off
1
1
IDLE2
Off
1
0
SLEEP
Off
0
0
fSYS
fH
fH~fH/64
On
111
fSUB
000~110
Off
111
On
xxx
On
000~110
On
111
Off
xxx
Off
fSUB
fLIRC
On
On
On
On
Off
On
On
On
On
On
On
Off
On
Off
Off
On/Off
(1)
(2)
On
Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable
bit in the SLOW mode.
2. The fLIRC clock will be switched on since the WDT function is always enabled.
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by one of the high speed oscillators.
This mode operates allowing the microcontroller to operate normally with a clock source will come
from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator
will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by
the CKS2~CKS0 bits in the SCC register.Although a high speed oscillator is used, running the
microcontroller at a divided clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the
LIRC or LXT oscillator.
SLEEP Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and
FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. However the fLIRC clock still
continues to operate since the WDT function is always enabled.
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IDLE0 Mode
The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in
the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the
CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral
functions.
IDLE1 Mode
The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU
will be switched off but both the high and low speed oscillators will be turned on to provide a clock
source to keep some peripheral functions operational.
IDLE2 Mode
The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU
will be switched off but the high speed oscillator will be turned on to provide a clock source to keep
some peripheral functions operational.
Control Registers
The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the
corresponding oscillator configurations.
Bit
Register
Name
7
6
5
4
3
2
1
0
SCC
CKS2
CKS1
CKS0
—
FHS
FSS
FHIDEN
FSIDEN
HIRCC
—
—
—
—
HIRC1
HIRC0
HIRCF
HIRCEN
HXTC
—
—
—
—
—
HXTM
HXTF
HXTEN
LXTC
—
—
—
—
—
LXTSP
LXTF
LXTEN
2
1
0
System Operating Mode Control Registers List
SCC Register
Bit
7
6
5
4
3
Name
CKS2
CKS1
R/W
R/W
R/W
CKS0
—
FHS
FSS
FHIDEN
FSIDEN
R/W
—
R/W
R/W
R/W
POR
0
0
R/W
0
—
0
0
0
0
Bit 7~5CKS2~CKS0: System clock selection
000: fH
001: fH/2
010: fH/4
011: fH/8
100: fH/16
101: fH/32
110: fH/64
111: fSUB
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source directly derived from fH or fSUB, a divided version
of the high speed system oscillator can also be chosen as the system clock source.
Bit 4
Unimplemented, read as 0.
Bit 3FHS: High Frequency clock selection
0: HIRC
1: HXT
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit 2FSS: Low Frequency clock selection
0: LIRC
1: LXT
Bit 1FHIDEN: High Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the high speed oscillator is activated or stopped
when the CPU is switched off by executing an “HALT” instruction.
Bit 0FSIDEN: Low Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the low speed oscillator is activated or stopped
when the CPU is switched off by executing an “HALT” instruction. The LIRC
oscillator is controlled by this bit together with the WDT function enable control when
the LIRC is selected to be the low speed oscillator clock source or the WDT function
is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the
LIRC oscillator will also be enabled.
HIRCC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
HIRC1
HIRC0
HIRCF
HIRCEN
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
1
Bit 7~2
Unimplemented, read as 0.
Bit 3~2HIRC1~HIRC0: HIRC frequency selection
00: 8 MHz
01: 12 MHz
10: 16 MHz
11: 8 MHz
When the HIRC oscillator is enabled or the HIRC frequency selection is changed
by application program, the clock frequency will automatically be changed after the
HIRCF flag is set to 1.
Bit 1HIRCF: HIRC oscillator stable flag
0: HIRC unstable
1: HIRC stable
This bit is used to indicate whether the HIRC oscillator is stable or not. When the
HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection
is changed by application program, the HIRCF bit will first be cleared to 0 and then
set to 1 after the HIRC oscillator is stable.
Bit 0HIRCEN: HIRC oscillator enable control
0: Disable
1: Enable
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HXTC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
HXTM
HXTF
HXTEN
R/W
—
—
—
—
—
R/W
R
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Unimplemented, read as 0.
Bit 2HXTM: HXT mode selection
0: HXT frequency ≤ 10 MHz
1: HXT frequency >10 MHz
This bit is used to select the HXT oscillator operating mode. Note that this bit must
be properly configured before the HXT is enabled. When the HXTEN bit is set to 1 to
enable the HXT oscillator, it is invalid to change the value of this bit.
Bit 1HXTF: HXT oscillator stable flag
0: HXT unstable
1: HXT stable
This bit is used to indicate whether the HXT oscillator is stable or not. When the
HXTEN bit is set to 1 to enable the HXT oscillator, the HXTF bit will first be cleared
to 0 and then set to 1 after the HXT oscillator is stable.
Bit 0HXTEN: HXT oscillator enable control
0: Disable
1: Enable
LXTC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
LXTSP
LXTF
LXTEN
R/W
—
—
—
—
—
RW
R
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Unimplemented, read as 0.
Bit 2LXTSP: LXT oscillator speed-up control
0: Disable – Low power
1: Enable – Speed up
This bit is used to control whether the LXT oscillator is operating in the low power
or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate
quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator
will consume less power but take longer time to stablise. It is important to note that
this bit can not be changed after the LXT oscillator is selected as the system clock
source using the CKS2~CKS0 and FSS bits in the SCC register.
Bit 1LXTF: LXT oscillator stable flag
0: LXT unstable
1: LXT stable
This bit is used to indicate whether the LXT oscillator is stable or not. When the
LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared
to 0 and then set to 1 after the LXT oscillator is stable.
Bit 0LXTEN: LXT oscillator enable control
0: Disable
1: Enable
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Operating Mode Switching
These devices can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using
the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes
to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is
executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the
condition of the FHIDEN and FSIDEN bits in the SCC register.
NORMAL
fSYS=fH~fH/64
fH on
CPU run
fSYS on
fSUB on
SLOW
fSYS=fSUB
fSUB on
CPU run
fSYS on
fH on/off
SLEEP
HALT instruction executed
CPU stop
FHIDEN=0
FSIDEN=0
fH off
fSUB off
IDLE0
HALT instruction executed
CPU stop
FHIDEN=0
FSIDEN=1
fH off
fSUB on
IDLE2
HALT instruction executed
CPU stop
FHIDEN=1
FSIDEN=0
fH on
fSUB off
Rev. 1.20
IDLE1
HALT instruction executed
CPU stop
FHIDEN=1
FSIDEN=1
fH on
fSUB on
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by set the
CKS2~CKS0 bits to “111” in the SCC register. This will then use the low speed system oscillator
which will consume less power. Users may decide to do this for certain operations which do not
require high performance and can subsequently reduce power consumption.
The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC
register and therefore requires this oscillator to be stable before full mode switching occurs.
NORMAL Mode
CKS2~CKS0 = 111
SLOW Mode
FHIDEN=0, FSIDEN=0
HALT instruction is executed
SLEEP Mode
FHIDEN=0, FSIDEN=1
HALT instruction is executed
IDLE0 Mode
FHIDEN=1, FSIDEN=1
HALT instruction is executed
IDLE1 Mode
FHIDEN=1, FSIDEN=0
HALT instruction is executed
IDLE2 Mode
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
SLOW Mode to NORMAL Mode Switching
In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the
NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to “000” ~“110” and then the system
clock will respectively be switched to fH~ fH/64.
However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is
monitored using the HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register. The
time duration required for the high speed system oscillator stabilization is specified in the A.C.
characteristics.
SLOW Mode
CKS2~CKS0 = 000~110
NORMAL Mode
FHIDEN=0, FSIDEN=0
HALT instruction is executed
SLEEP Mode
FHIDEN=0, FSIDEN=1
HALT instruction is executed
IDLE0 Mode
FHIDEN=1, FSIDEN=1
HALT instruction is executed
IDLE1 Mode
FHIDEN=1, FSIDEN=0
HALT instruction is executed
IDLE2 Mode
Entering the SLEEP Mode
There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT”
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to “0”. In this mode all the clocks and functions will be switched off except the WDT function.
When this instruction is executed under the conditions described above, the following will occur:
• The system clock will be stopped and the application program will stop at the "HALT"
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the FHIDEN bit in the SCC register equal to “0” and the
FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be stopped and the application program will stop at the “HALT” instruction, but
the fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to “1”. When this instruction is executed under the conditions described above, the following
will occur:
• The fH and fSUB clocks will be on but the application program will stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
Entering the IDLE2 Mode
There is only one way for the device to enter the IDLE2 Mode and that is to execute the “HALT”
instruction in the application program with the FHIDEN bit in the SCC register equal to “1” and the
FSIDEN bit in the SCC register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be on but the fSUB clock will be off and the application program will stop at the
“HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by
the circuit designer if the power consumption is to be minimised. Special attention must be made
to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed
high or low level as any floating input pins could create internal oscillations and result in increased
current consumption. This also applies to devices which have different package types, as there may
be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high
resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.
These should be placed in a condition in which minimum current is drawn or connected only to
external circuits that do not draw current, such as other CMOS inputs. Also note that additional
standby current will also be required if the LIRC oscillator has enabled.
In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock
source is derived from the high speed oscillator, the additional standby current will also be perhaps
in the order of several hundred micro-amps.
Wake-up
To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the
CPU will be switched off. However, when the device is woken up again, it will take a considerable
time for the original system oscillator to restart, stablise and allow normal operation to resume.
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
When the device executes the “HALT” instruction, the PDF flag will be set to 1. The PDF flag will
be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer
instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated
and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up
that only resets the Program Counter and Stack Pointer, other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the “HALT” instruction. In this situation, the interrupt which woke up the device will
not be immediately serviced, but wukk rather be serviced later when the related interrupt is finally
enabled or when a stack level becomes free. The other situation is where the related interrupt is
enabled and the stack is not full, in which case the regular interrupt response takes place. If an
interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of
the related interrupt will be disabled.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal RC oscillator, fLIRC. The LIRC internal
oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary
with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided
by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0
bits in the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register controls the overall operation of the Watchdog Timer.
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3WE4~WE0: WDT function enable control
10101 or 01010: Enabled
Other values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the
WRF bit in the RSTFC register will be set to 1.
Bit 2~0WS2~WS0: WDT time-out period selection
000: 28/fLIRC
001: 210/fLIRC
010: 212/fLIRC
011: 214/fLIRC
100: 215/fLIRC
101: 216/fLIRC
110: 217/fLIRC
111: 218/fLIRC
These three bits determine the division ratio of the watchdog timer source clock,
which in turn determines the time-out period.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
RSTFC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
“x”: unknown
Bit 7~4
Unimplemented, read as “0”
Bit 3RSTF: Reset control register software reset flag
Described elsewhere.
Bit 2LVRF: LVR function reset flag
Described elsewhere.
Bit 1LRF: LVR control register software reset flag
Described elsewhere.
Bit 0WRF: WDT control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the WDT control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear instruction will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to
the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register
to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will
be enabled when the WE4~WE0 bits are set to a value of 01010B or 10101B. If the WE4~WE0 bits
are set to any other values, other than 01010B and 10101B, it will reset the device after 2~3 fLIRC
clock cycles. After power on these bits will have a value of 01010B.
WE4 ~ WE0 Bits
WDT Function
10101B or 01010B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value except 01010B and 10101B written into the
WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is
via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single “CLR WDT” instruction to clear the WDT contents.
The maximum time out period is when the 218 division ratio is selected. As an example, with a 32
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
second for the 218 division ratio and a minimum timeout of 7.8ms for the 28 division ration.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
WDTC WE4~WE0 bits
Register
Reset MCU
CLR
“HALT”Instruction
“CLR WDT”Instruction
LIRC
fLIRC
8-stage Divider
fLIRC/28
WS2~WS0
(fLIRC/28 ~ fLIRC/218)
WDT Prescaler
8-to-1 MUX
WDT Time-out
(28/fLIRC ~ 218/fLIRC)
Watchdog timer
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR,
where a full reset is implemented in situations where the power supply voltage falls below a
certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the
microcontroller. All types of reset operations result in different register conditions being setup.
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally.
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
VDD
Power-on Reset
tRSTD
SST Time-out
Note: tRSTD is power-on delay with typical time=50 ms
Power-On Reset Timing Chart
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Internal Reset Control
There is an internal reset control register, RSTC, which is used to provide a reset when the device
operates abnormally due to the environmental noise interference. If the content of the RSTC register
is set to any value other than 01010101B or 10101010B, it will reset the device after 2~3 fLIRC clock
cycles. After power on the register will have a value of 01010101B.
RSTC7 ~ RSTC0 Bits
Reset Function
01010101B
No operation
10101010B
No operation
Any other value
Reset MCU
Internal Reset Function Control
• RSTC Register
Bit
7
6
5
4
3
2
1
0
Name
RSTC7
RSTC6
RSTC5
RSTC4
RSTC3
RSTC2
RSTC1
RSTC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0RSTC7~RSTC0: Reset function control
01010101: No operation
10101010: No operation
Other values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the
RSTF bit in the RSTFC register will be set to 1.
• RSTFC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
“x”: unknown
Bit 7~4
Unimplemented, read as “0”
Bit 3RSTF: Reset control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the RSTC control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Bit 2LVRF: LVR function reset flag
Described elsewhere.
Bit 1LRF: LVR control register software reset flag
Described elsewhere.
Bit 0WRF: WDT control register software reset flag
Described elsewhere.
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Low Voltage Reset — LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage
of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery,
the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will
also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~ VLVR must exist for a time greater than that specified by tLVR in the LVD/LVR characteristics.
If the low supply voltage state does not exceed this value, the LVR will ignore the low supply
voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS
bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which may perhaps occur
due to adverse environmental conditions such as noise, the LVR will reset the device after 2~3 fLIRC
clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power
on the register will have the value of 01010101B. Note that the LVR function will be automatically
disabled when the device enters the power down mode.
LVR
tRSTD + tSST
Internal Reset
Note: tRSTD is power-on delay with typical time=50 ms
Low Voltage Reset Timing Chart
• LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0LVS7~LVS0: LVR voltage select
01010101: 2.1V
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
Other values: Generates a MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the four defined
LVR voltage value above, an MCU reset will generated. The reset operation will be
activated after 2~3 fLIRC clock cycles. In this situation the register contents will remain
the same after such a reset occurs.
Any register value, other than the four defined register values above, will also result
in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC
clock cycles. However in this situation the register contents will be reset to the POR
value.
Rev. 1.20
85
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• RSTFC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
“x”: unknown
Bit 7~4
Unimplemented, read as “0”
Bit 3RSTF: Reset control register software reset flag
Described elsewhere.
Bit 2LVRF: LVR function reset flag
0: Not occurred
1: Occurred
This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit
can only be cleared to 0 by the application program.
Bit 1LRF: LVR control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the LVRC control register contains any undefined LVR voltage
register values. This in effect acts like a software-reset function. Note that this bit can
only be cleared to 0 by the application program.
Bit 0WRF: WDT control register software reset flag
Described elsewhere.
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as the hardware Low Voltage
Reset except that the Watchdog time-out flag TO will be set to “1”.
WDT Time-out
tRSTD + tSST
Internal Reset
Note: tRSTD is power-on delay with typical time=16.7 ms
WDT Time-out Reset during NORMAL Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for
tSST details.
WDT Time-out
tSST
Internal Reset
WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart
Rev. 1.20
86
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
0
0
Power-on reset
Reset Function
u
u
LVR reset during NORMAL or SLOW Mode operation
1
u
WDT time-out reset during NORMAL or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
“u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Program Counter
Reset Function
Reset to zero
Interrupts
All interrupts will be disabled
WDT, Time Base
Clear after reset, WDT begins counting
Timer Modules
Timer Modules will be turned off
Input/Output Ports
I/O ports will be setup as inputs
Stack pointer
Stack pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects the microcontroller internal registers.
Rev. 1.20
87
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
BS67F340
BS67F350
BS67F360
Reset
(Power On)
IAR0
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
LVR Reset
WDT Time-out
WDT Time-out
(Normal Operation) (Normal Operation) (IDLE or SLEEP)*
MP0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
IAR1
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP1H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
●
---- xxxx
---- uuuu
---- uuuu
---- uuuu
---x xxxx
---u uuuu
---u uuuu
---u uuuu
TBHP
●
TBHP
●
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
●
xx00 xxxx
uuuu uuuu
xx1u uuuu
uu11 uuuu
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
●
●
---- 0x00
---- u1uu
---- uuuu
---- uuuu
INTC0
●
●
●
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PA
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PB
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBPU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTEG
●
●
●
---- 0000
---- 0000
---- 0000
---- uuuu
SCC
●
●
●
000- 0000
000- 0000
000- 0000
uuu- uuuu
HIRCC
●
●
●
---- 0001
---- 0001
---- 0001
---- uuuu
---- -uuu
STATUS
●
●
IAR2
●
●
MP2L
●
MP2H
RSTFC
PBP
HXTC
●
●
●
---- -000
---- -001
---- -001
LXTC
●
●
●
---- -000
---- -000
---- -000
---- -uuu
LVDC
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
LVRC
●
●
●
0101 0101
0101 0101
0101 0101
uuuu uuuu
WDTC
●
●
●
0101 0011
0101 0011
0101 0011
uuuu uuuu
RSTC
●
●
●
0101 0101
0101 0101
0101 0101
uuuu uuuu
PC
●
---- 1111
---- 1111
---- 1111
---- uuuu
1111 1111
1111 1111
1111 1111
uuuu uuuu
---- 1111
---- 1111
---- 1111
---- uuuu
1111 1111
1111 1111
uuuu uuuu
PC
PCC
●
PCC
PCPU
Rev. 1.20
●
●
1111 1111
---- 0000
---- 0000
---- 0000
---- uuuu
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
-111 ----
-111 ----
-111 ----
-uuu ----
●
PCPU
PD
●
●
●
88
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
PDC
Reset
(Power On)
●
●
-111 1111
-111 ----
-111 ----
-111 ----
-uuu ----
●
●
-111 1111
-111 1111
-111 1111
-uuu uuuu
-000 ----
-000 ----
-000 ----
-uuu ----
●
●
-000 0000
-000 0000
-000 0000
-uuu uuuu
●
PDC
PDPU
BS67F360
PD
BS67F350
BS67F340
Register
●
PDPU
LVR Reset
WDT Time-out
WDT Time-out
(Normal Operation) (Normal Operation) (IDLE or SLEEP)*
-111 1111
-111 1111
-uuu uuuu
MFI0
●
●
●
--00 --00
--00 --00
--00 --00
--uu --uu
MFI1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFI2
●
●
●
-000 -000
-000 -000
-000 -000
-uuu -uuu
MFI3
●
●
●
--00 --00
--00 --00
--00 --00
--uu --uu
ADRL (ADRFS=0)
●
●
●
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRL (ADRFS=1)
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ADRH (ADRFS=0)
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ADRH (ADRFS=1)
●
●
●
---- xxxx
---- uuuu
---- uuuu
---- uuuu
ADCR0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADCR1
●
●
●
0-00 -000
0-00 -000
0-00 -000
u-uu -uuu
PSCR0
●
●
●
---- --00
---- --00
---- --00
---- --uu
TB0C
●
●
●
0--- -000
0--- -000
0--- -000
u--- -uuu
TB1C
●
●
●
0--- -000
0--- -000
0--- -000
u--- -uuu
SIMTOC
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
SIMC0
●
●
●
111- 0000
111- 0000
111- 0000
uuu- uuuu
SIMC1
●
●
●
1000 0001
1000 0001
1000 0001
uuuu uuuu
SIMD
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIMA/SIMC2
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0C0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0C1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0DH
●
●
●
---- --00
---- --00
---- --00
---- --uu
CTM0AL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0AH
●
●
●
---- --00
---- --00
---- --00
---- --uu
EEA
●
●
●
-000 0000
-000 0000
-000 0000
-uuu uuuu
EED
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PSCR1
●
●
●
---- --00
---- --00
---- --00
---- --uu
LCDC0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
LCDC1
●
●
●
000- 0000
000- 0000
000- 0000
uuu- uuuu
PTMC0
●
●
●
0000 0---
0000 0---
0000 0---
uuuu u---
PTMC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTMDL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTMDH
●
●
●
---- --00
---- --00
---- --00
---- --uu
PTMAL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTMAH
●
●
●
---- --00
---- --00
---- --00
---- --uu
PTMRPL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTMRPH
●
●
●
---- --00
---- --00
---- --00
---- --uu
FC0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.20
89
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
FARL
●
FARH
●
FARH
BS67F360
FC2
BS67F350
BS67F340
Register
Reset
(Power On)
●
●
---- ---0
---- ---0
---- ---0
---- ---u
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
---- 0000
---- 0000
---- 0000
---- uuuu
---0 0000
---0 0000
---0 0000
---u uuuu
●
--00 0000
--00 0000
--00 0000
--uu uuuu
●
FARH
LVR Reset
WDT Time-out
WDT Time-out
(Normal Operation) (Normal Operation) (IDLE or SLEEP)*
FD0L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD0H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD1L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD1H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD2L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD2H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD3L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD3H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMC0
●
●
●
0000 0---
0000 0---
0000 0---
uuuu u---
STMC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMDL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMDH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMAL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMAH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMRP
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1C0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1C1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1DH
●
●
●
---- --00
---- --00
---- --00
---- --uu
CTM1AL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1AH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TSC0
●
●
●
010- ----
010- ----
010- ----
uuu- ----
TSC1
●
●
●
000- ----
000- ----
000- ----
uuu- ----
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TSC2
TSC3
●
●
●
--0- ----
--0- ----
--0- ----
--u- ----
PE
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEPU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PF
●
- - - - 1111
- - - - 1111
- - - - 1111
---- uuuu
PFC
●
- - - - 1111
- - - - 1111
- - - - 1111
---- uuuu
PFPU
●
---- 0000
---- 0000
---- 0000
---- uuuu
USR
●
●
●
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
uuuu uuuu
UCR1
●
●
●
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
UCR2
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TXR_RXR
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRG
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TKTMR
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKC0
●
●
●
0000 0-00
0000 0-00
0000 0-00
uuuu u-uu
TK16DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.20
90
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
BS67F340
BS67F350
BS67F360
Reset
(Power On)
TK16DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKC1
●
●
●
0 0 0 0 0 0 11
0 0 0 0 0 0 11
0 0 0 0 0 0 11
uuuu uuuu
TKM016DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM016DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM0ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
Register
LVR Reset
WDT Time-out
WDT Time-out
(Normal Operation) (Normal Operation) (IDLE or SLEEP)*
TKM0ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM0C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM0C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM0C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM116DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM116DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM1ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM1ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM1C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM1C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM1C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM216DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM216DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM2ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM2ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM2C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM2C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM2C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM316DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM316DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM3ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM3ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM3C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM3C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM3C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM416DL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM416DH
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM4ROL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM4ROH
●
●
---- --00
---- --00
---- --00
---- --uu
TKM4C0
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM4C1
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM4C2
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM516DL
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM516DH
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM5ROL
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM5ROH
●
---- --00
---- --00
---- --00
---- --uu
TKM5C0
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM5C1
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM5C2
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
Rev. 1.20
91
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
BS67F360
BS67F350
BS67F340
Reset
(Power On)
TKM616DL
●
0000 0000
0000 0000
0000 0000
Register
LVR Reset
WDT Time-out
WDT Time-out
(Normal Operation) (Normal Operation) (IDLE or SLEEP)*
uuuu uuuu
TKM616DH
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM6ROL
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM6ROH
●
---- --00
---- --00
---- --00
---- --uu
TKM6C0
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM6C1
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM6C2
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
EEC
●
●
●
---- 0000
---- 0000
---- 0000
---- uuuu
IFS
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
PAS0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAS1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PBS0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PBS1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PCS0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PCS1
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PDS0
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PDS1
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
PES0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PES1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PFS0
Note: “u” stands for unchanged
“x” stands for “unknown”
“-“ stands for unimplemented
Rev. 1.20
92
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
These devices provide bidirectional input/output lines labeled with port names PA~PF. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
PC
PCC
PCPU
PD
PDC
PDPU
PE
PEC
PEPU
PA7
PAC7
PAPU7
PAWU7
PB7
PBC7
PBPU7
—
—
—
—
—
—
PE7
PEC7
PEPU7
PA6
PAC6
PAPU6
PAWU6
PB6
PBC6
PBPU6
—
—
—
PD6
PDC6
PDPU6
PE6
PEC6
PEPU6
PA5
PAC5
PAPU5
PAWU5
PB5
PBC5
PBPU5
—
—
—
PD5
PDC5
PDPU5
PE5
PEC5
PEPU5
PA4
PAC4
PAPU4
PAWU4
PB4
PBC4
PBPU4
—
—
—
PD4
PDC4
PDPU4
PE4
PEC4
PEPU4
PA3
PAC3
PAPU3
PAWU3
PB3
PBC3
PBPU3
PC3
PCC3
PCPU3
—
—
—
PE3
PEC3
PEPU3
PA2
PAC2
PAPU2
PAWU2
PB2
PBC2
PBPU2
PC2
PCC2
PCPU2
—
—
—
PE2
PEC2
PEPU2
PA1
PAC1
PAPU1
PAWU1
PB1
PBC1
PBPU1
PC1
PCC1
PCPU1
—
—
—
PE1
PEC1
PEPU1
PA0
PAC0
PAPU0
PAWU0
PB0
PBC0
PBPU0
PC0
PCC0
PCPU0
—
—
—
PE0
PEC0
PEPU0
I/O Registers List – BS67F340
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
PC
PCC
PCPU
PD
PDC
PDPU
PE
PEC
PEPU
PA7
PAC7
PAPU7
PAWU7
PB7
PBC7
PBPU7
PC7
PCC7
PCPU7
—
—
—
PE7
PEC7
PEPU7
PA6
PAC6
PAPU6
PAWU6
PB6
PBC6
PBPU6
PC6
PCC6
PCPU6
PD6
PDC6
PDPU6
PE6
PEC6
PEPU6
PA5
PAC5
PAPU5
PAWU5
PB5
PBC5
PBPU5
PC5
PCC5
PCPU5
PD5
PDC5
PDPU5
PE5
PEC5
PEPU5
PA4
PAC4
PAPU4
PAWU4
PB4
PBC4
PBPU4
PC4
PCC4
PCPU4
PD4
PDC4
PDPU4
PE4
PEC4
PEPU4
PA3
PAC3
PAPU3
PAWU3
PB3
PBC3
PBPU3
PC3
PCC3
PCPU3
PD3
PDC3
PDPU3
PE3
PEC3
PEPU3
PA2
PAC2
PAPU2
PAWU2
PB2
PBC2
PBPU2
PC2
PCC2
PCPU2
PD2
PDC2
PDPU2
PE2
PEC2
PEPU2
PA1
PAC1
PAPU1
PAWU1
PB1
PBC1
PBPU1
PC1
PCC1
PCPU1
PD1
PDC1
PDPU1
PE1
PEC1
PEPU1
PA0
PAC0
PAPU0
PAWU0
PB0
PBC0
PBPU0
PC0
PCC0
PCPU0
PD0
PDC0
PDPU0
PE0
PEC0
PEPU0
I/O Registers List – BS67F350
Rev. 1.20
93
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PAWU0
PB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PBC
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PD
—
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDC
—
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
—
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PE
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PEC
PEC7
PEC6
PEC5
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU
PEPU7
PEPU6
PEPU5
PEPU4
PEPU3
PEPU2
PEPU1
PEPU0
PF
—
—
—
—
PF3
PF2
PF1
PF0
PFC
—
—
—
—
PFC3
PFC2
PFC1
PFC0
PFPU
—
—
—
—
PFPU3
PFPU2
PFPU1
PFPU0
I/O Registers List – BS67F360
“—”: Unimplemented, read as “0”.
PAWUn: Port A Pin wake-up function control
0: Disable
1: Enable
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: I/O Pin pull-high function control
0: Disable
1: Enable
PAn/PBn/PCn/PDn/PEn/PFn: I/O Port Data bit
0: Data 0
1: Data 1
PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O Pin type selection
0: Output
1: Input
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using the relevant pull-high control registers and are implemented
using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant
pull-high control register only when the pin-shared functional pin is selected as an input or NMOS
output. Otherwise, the pull-high resistors can not be enabled.
Rev. 1.20
94
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register. Note that the wake-up function can be controlled by the wake-up control
registers only when the pin-shared functional pin is selected as general purpose input/output and the
MCU enters the Power down mode.
I/O Port Control Registers
Each Port has its own control register, known as PAC~PFC, which controls the input/output
configuration. With this control register, each I/O pin with or without pull-high resistors can be
reconfigured dynamically under software control. For the I/O pin to function as an input, the
corresponding bit of the control register must be written as a “1”. This will then allow the logic state
of the input pin to be directly read by instructions. When the corresponding bit of the control register
is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an
output, instructions can still be used to read the output register.
However, it should be noted that the program will in fact only read the status of the output data latch
and not the actual logic status of the output pin.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the
desired function of the multi-function I/O pins is selected by a series of registers via the application
program control.
Pin-shared Function Selection Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes. Each device includes Port “x” output function Selection
register “n”, labeled as PxSn, and Input Function Selection register, labeled as IFS, which can select
the desired functions of the multi-function pin-shared pins.
When the pin-shared input function is selected to be used, the corresponding input and output
functions selection should be properly managed. For example, if the I2C SDA line is used, the
corresponding output pin-shared function should be configured as the SDI/SDA function by
configuring the PxSn register and the SDA signal intput should be properly selected using the IFS
register. However, if the external interrupt function is selected to be used, the relevant output pinshared function should be selected as an I/O function and the interrupt input signal should be selected.
The most important point to note is to make sure that the desired pin-shared function is properly
selected and also deselected. To select the desired pin-shared function, the pin-shared function
should first be correctly selected using the corresponding pin-shared control register. After that the
corresponding peripheral functional setting should be configured and then the peripheral function
can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be
disabled and then the corresponding pin-shared function control register can be modified to select
other pin-shared functions.
Rev. 1.20
95
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Register
Name
Bit
7
6
5
4
3
2
1
0
PAS0
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
PAS1
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
PBS0
PBS07
PBS06
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
PBS1
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
PCS0
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
PDS1
—
—
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
PES0
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
PES1
PES17
PES16
PES15
PES14
PES13
PES12
PES11
PES10
IFS
—
—
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
Pin-shared Function Selection Registers List – BS67F340
Bit
Register
Name
7
6
5
4
3
2
1
0
PAS0
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
PAS1
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
PBS0
PBS07
PBS06
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
PBS1
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
PCS0
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
PCS1
PCS17
PCS16
PCS15
PCS14
PCS13
PCS12
PCS11
PCS10
PDS0
PDS07
PDS06
PDS05
PDS04
PDS03
PDS02
PDS01
PDS00
PDS1
—
—
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
PES0
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
PES1
PES17
PES16
PES15
PES14
PES13
PES12
PES11
PES10
IFS
—
—
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
Pin-shared Function Selection Registers List – BS67F350
Bit
Register
Name
7
6
5
4
3
2
1
0
PAS0
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
PAS1
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
PBS0
PBS07
PBS06
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
PBS1
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
PCS0
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
PCS1
PCS17
PCS16
PCS15
PCS14
PCS13
PCS12
PCS11
PCS10
PDS0
PDS07
PDS06
PDS05
PDS04
PDS03
PDS02
PDS01
PDS00
PDS1
—
—
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
PES0
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
PES1
PES17
PES16
PES15
PES14
PES13
PES12
PES11
PES10
PFS0
PFS07
PFS06
PFS05
PFS04
PFS03
PFS02
PFS01
PFS00
IFS
—
—
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
Pin-shared Function Selection Registers List – BS67F360
Rev. 1.20
96
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PAS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PAS07~PAS06: PA3 pin function selection
00/11: PA3
01: SCS
10: XT1
Bit 5~4PAS05~PAS04: PA2 pin function selection
00/10/11: PA2
01: SCS
Bit 3~2PAS03~PAS02: PA1 pin function selection
00/10: PA1
01: CTP0
11: V2
Bit 1~0PAS01~PAS00: PA0 pin function selection
00/10/11: PA0
01: SDO
• PAS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PAS17~PAS16: PA7 pin function selection
PAS1[7:6]
BS67F340
BS67F350
BS67F360
00
PA7
PA7
PA7
01
PA7
PA7
PA7
10
KEY12
KEY20
KEY20
11
SEG7
SEG7
SEG15
Bit 5~4PAS15~PAS14: PA6 pin function selection
00/01/10: PA6/CTCK0/INT0
11: C2
Bit 3~2PAS13~PAS12: PA5 pin function selection
00/10: PA5
01: CTP0B
11: C1
Bit 1~0PAS11~PAS10: PA4 pin function selection
00/11: PA4
01: SDO
10: XT2
Rev. 1.20
97
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PBS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PBS07
PBS06
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PBS07~PBS06: PB3 pin function selection
00/10: PB3/INT0
01: RX
11: AN3
Bit 5~4PBS05~PBS04: PB2 pin function selection
00: PB2/PTPI
01: TX
10: PTP
11: AN2
Bit 3~2PBS03~PBS02: PB1 pin function selection
00/10: PB1
01: SCK/SCL
11: AN1
Bit 1~0PBS01~PBS00: PB0 pin function selection
00: PB0
01: SDI/SDA
10: VREF
11: AN0
• PBS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PBS17~PBS16: PB7 pin function selection
00/01: PB7/INT1
10: KEY4
11: AN7
Bit 5~4PBS15~PBS14: PB6 pin function selection
00/01: PB6/PTCK
10: KEY3
11: AN6
Bit 3~2PBS13~PBS12: PB5 pin function selection
00/01: PB5/STCK
10: KEY2
11: AN5
Bit 1~0PBS11~PBS10: PB4 pin function selection
00: PB4/PTPI
01: PTPB
10: KEY1
11: AN4
Rev. 1.20
98
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PCS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PCS07~PCS06: PC3 pin function selection
PCS0[7:6]
BS67F340
BS67F350
BS67F360
00
PC3
PC3
PC3
01
PC3
PC3
PC3
10
KEY8
KEY8
KEY8
11
SEG3
PC3
SEG3
Bit 5~4PCS05~PCS04: PC2 pin function selection
PCS0[5:4]
BS67F340
BS67F350
BS67F360
00
PC2
PC2
PC2
01
PC2
PC2
PC2
10
KEY7
KEY7
KEY7
11
SEG2
PC2
SEG2
Bit 3~2PCS03~PCS02: PC1 pin function selection
PCS0[3:2]
BS67F340
BS67F350
BS67F360
00
PC1
PC1
PC1
01
PC1
PC1
PC1
10
KEY6
KEY6
KEY6
11
SEG1
PC1
SEG1
Bit 1~0PCS01~PCS00: PC0 pin function selection
Rev. 1.20
PCS0[1:0]
BS67F340
BS67F350
BS67F360
00
PC0
PC0
PC0
01
PC0
PC0
PC0
10
KEY5
KEY5
KEY5
11
SEG0
PC0
SEG0
99
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PCS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PCS17
PCS16
PCS15
PCS14
PCS13
PCS12
PCS11
PCS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PCS17~PCS16: PC7 pin function selection
PCS1[7:6]
BS67F340
BS67F350
BS67F360
00
—
PC7
PC7
01
—
PC7
PC7
10
—
KEY12
KEY12
11
—
PC7
SEG7
Bit 5~4PCS15~PCS14: PC6 pin function selection
PCS1[5:4]
BS67F340
BS67F350
BS67F360
00
—
PC6
PC6
01
—
PC6
PC6
10
—
KEY11
KEY11
11
—
PC6
SEG6
Bit 3~2PCS13~PCS12: PC5 pin function selection
PCS1[3:2]
BS67F340
BS67F350
BS67F360
00
—
PC5
PC5
01
—
PC5
PC5
10
—
KEY10
KEY10
11
—
PC5
SEG5
Bit 1~0PCS11~PCS10: PC4 pin function selection
Rev. 1.20
PCS1[1:0]
BS67F340
BS67F350
BS67F360
00
—
PC4
PC4
01
—
PC4
PC4
10
—
KEY9
KEY9
11
—
PC4
SEG4
100
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PDS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PDS07
PDS06
PDS05
PDS04
PDS03
PDS02
PDS01
PDS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PDS07~PDS06: PD3 pin function selection
PDS0[7:6]
BS67F340
BS67F350
BS67F360
00
—
PD3
PD3
01
—
PD3
PD3
10
—
KEY16
KEY16
11
—
SEG3
SEG11
Bit 5~4PDS05~PDS04: PD2 pin function selection
PDS0[5:4]
BS67F340
BS67F350
BS67F360
00
—
PD2
PD2
01
—
PD2
PD2
10
—
KEY15
KEY15
11
—
SEG2
SEG10
Bit 3~2PDS03~PDS02: PD1 pin function selection
PDS0[3:2]
BS67F340
BS67F350
BS67F360
00
—
PD1
PD1
01
—
PD1
PD1
10
—
KEY14
KEY14
11
—
SEG1
SEG9
Bit 1~0PDS01~PDS00: PD0 pin function selection
Rev. 1.20
PDS0[1:0]
BS67F340
BS67F350
BS67F360
00
—
PD0
PD0
01
—
PD0
PD0
10
—
KEY13
KEY13
11
—
SEG0
SEG8
101
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PDS1 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
“—” Unimplemented, read as 0
Bit 5~4PDS15~PDS14: PD6 pin function selection
PDS1[5:4]
BS67F340
BS67F350
BS67F360
00
PD6
PD6
PD6
01
PD6
PD6
PD6
10
KEY11
KEY19
KEY19
11
SEG6
SEG6
SEG14
Bit 3~2PDS13~PDS12: PD5 pin function selection
PDS1[3:2]
BS67F340
BS67F350
BS67F360
PD5
00
PD5
PD5
01
PD5
PD5
PD5
10
KEY10
KEY18
KEY18
11
SEG5
SEG5
SEG13
Bit 1~0PDS11~PDS10: PD4 pin function selection
Rev. 1.20
PDS1[1:0]
BS67F340
BS67F350
BS67F360
00
PD4
PD4
PD4
01
PD4
PD4
PD4
10
KEY9
KEY17
KEY17
11
SEG4
SEG4
SEG12
102
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PES0 Register
Bit
7
6
5
4
3
2
1
0
Name
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PES07~PES06: PE3 pin function selection
PES0[7:6]
BS67F340
BS67F350
BS67F360
00
PE3/STPI
PE3/STPI
PE3/STPI
01
STPB
STPB
STPB
10
PE3/STPI
PE3/STPI
KEY24
11
SEG15
SEG11
SEG19
Bit 5~4PES05~PES04: PE2 pin function selection
PES0[5:4]
BS67F340
BS67F350
BS67F360
00
PE2/STPI
PE2/STPI
PE2/STPI
01
STP
STP
STP
10
OSC2
OSC2
KEY23
11
SEG14
SEG10
SEG18
Bit 3~2PES03~PES02: PE1 pin function selection
PES0[3:2]
BS67F340
BS67F350
BS67F360
00
PE1
PE1
PE1
01
PE1
PE1
PE1
10
OSC1
OSC1
KEY22
11
SEG13
SEG9
SEG17
Bit 1~0PES01~PES00: PE0 pin function selection
Rev. 1.20
PES0[1:0]
BS67F340
BS67F350
BS67F360
00
PE0
PE0
PE0
01
PE0
PE0
PE0
10
PE0
PE0
KEY21
11
SEG12
SEG8
SEG16
103
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PES1 Register
Bit
7
6
5
4
3
2
1
0
Name
PES17
PES16
PES15
PES14
PES13
PES12
PES11
PES10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PES17~PES16: PE7 pin function selection
PES1[7:6]
BS67F340
BS67F350
00
PE7
PE7
BS67F360
PE7
01
CTP1B
CTP1B
CTP1B
10
KEY16
PE7
KEY28
11
SEG11
SEG15
SEG23
Bit 5~4PES15~PES14: PE6 pin function selection
PES1[5:4]
BS67F340
BS67F350
00
PE6
PE6
BS67F360
PE6
01
CTP1
CTP1
CTP1
10
KEY15
PE6
KEY27
11
SEG10
SEG14
SEG22
Bit 3~2PES13~PES12: PE5 pin function selection
PES1[3:2]
BS67F340
BS67F350
BS67F360
00
PE5/CTCK1
PE5/CTCK1
PE5/CTCK1
01
PE5/CTCK1
PE5/CTCK1
PE5/CTCK1
10
KEY14
PE5/CTCK1
KEY26
11
SEG9
SEG13
SEG21
Bit 1~0PES11~PES10: PE4 pin function selection
Rev. 1.20
PES1[1:0]
BS67F340
BS67F350
BS67F360
00
PE4
PE4
PE4
01
PE4
PE4
PE4
10
KEY13
PE4
KEY25
11
SEG8
SEG12
SEG20
104
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• PFS0 Register – BS67F360
Bit
7
6
5
4
3
2
1
0
Name
PFS07
PFS06
PFS05
PFS04
PFS03
PFS02
PFS01
PFS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PFS07~PFS06: PF3 pin function selection
00/01/10: PF3
11: SEG31
Bit 5~4PFS05~PFS04: PF2 pin function selection
00/01/10: PF2
11: SEG30
Bit 3~2PFS03~PFS02: PF1 pin function selection
00/01: PF1
10: OSC2
11: SEG29
Bit 1~0PFS01~PFS00: PF0 pin function selection
00/01: PF0
10: OSC1
11: SEG28
• IFS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
“—” Unimplemented, read as 0
Bit 5~4IFS5~IFS4: SCS input source pin selection
00/10: PA2
01/11: PA3
Bit 3~2IFS3~IFS2: PTPI input source pin selection
00/10: PB2
01/11: PB4
Bit 1~0IFS1~IFS0: STPI input source pin selection
00/01: PE2
01/11: PE3
Rev. 1.20
105
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
 
     Generic Input/Output Structure
 €  
 ­
­
   
A/D Input/Output Structure
Rev. 1.20
106
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Programming Considerations
Within the user program, one of the things first to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set to high. This means that all I/O pins will be
defaulted to an input state, the level of which depends on the other connected circuitry and whether
pull-high selections have been chosen. If the port control registers are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated
port data registers are first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct values into the appropriate port control register or
by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i”
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Timer Modules – TM
One of the most fundamental functions in any microcontroller devices is the ability to control and
measure time. To implement time related functions the device includes several Timer Modules,
generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
interrupts. The addition of input and output pins for each TM ensures that users are provided with
timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Compact, Standard and Periodic TM sections.
Introduction
These devices contain four TMs and each individual TM can be categorised as a certain type,
namely Compact Type TM, Standard Type TM or Periodic Type TM. Although similar in nature,
the different TM types vary in their feature complexity. The common features to all of the Compact,
Standard and Periodic TMs will be described in this section and the detailed operation regarding
each of the TM types will be described in separate sections. The main features and differences
between the three types of TMs are summarised in the accompanying table.
CTM
STM
PTM
Timer/Counter
TM Function
√
√
√
Input Capture
—
√
√
Compare Match Output
√
√
√
PWM Channels
1
1
1
Single Pulse Output
—
1
1
Edge
Edge
Edge
Duty or Period
Duty or Period
Duty or Period
PWM Alignment
PWM Adjustment Period & Duty
TM Function Summary
Rev. 1.20
107
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TM Operation
The different types of TM offer a diverse range of functions, from simple timing operations to PWM
signal generation. The key to understanding how the TM operates is to see it in terms of a free
running count-up counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running count-up counter has the same value as the pre-programmed
comparator, known as a compare match situation, a TM interrupt signal will be generated which
can clear the counter and perhaps also change the condition of the TM output pin. The internal TM
counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources. The
selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn
control registers, where “x” stands for C, S or P type TM and “n” stands for the specific TM serial
number. For STM and PTM there is no serial number “n” in the relevant pin or control bits since
there is only one STM and PTM respectively in the series of devices, The clock source can be a ratio
of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCKn
pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external
clock source for event counting.
TM Interrupts
The Compact, Standard or Periodic type TM has two internal interrupt, one for each of the internal
comparator A or comparator P, which generate a TM interrupt when a compare match condition
occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the
state of the TM output pin.
TM External Pins
Each of the TMs, irrespective of what type, has one or two TM input pins, with the label xTCKn and
xTPnI respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is
selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows
an external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either
a rising or falling active edge. The STCK and PTCK pins are also used as the external trigger input
pin in single pulse output mode for the STM and PTM respectively.
The other xTM input pin, STPI or PTPI, is the capture input whose active edge can be a rising edge,
a falling edge or both rising and falling edges and the active edge transition type is selected using
the STIO1~STIO0 or PTIO1~PTIO0 bits in the STMC1 or PTMC1 register respectively. There is
another capture input, PTCK, for PTM capture input mode, which can be used as the external trigger
input source except the PTPI pin.
The TMs each have two output pins, xTPn and xTPnB. The xTPnB is the inverted signal of the
xTPn output. The TM output pins can be selected using the corresponding pin-shared function
selection bits described in the Pin-shared Function section. When the TM is in the Compare Match
Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle
when a compare match situation occurs. The external xTPn or xTPnB output pin is also the pin
where the TM generates the PWM output waveform. As the TM output pins are pin-shared with
other functions, the TM output function must first be setup using relevant pin-shared function
selection register.
Rev. 1.20
108
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Device
BS67F340
BS67F350
BS67F360
CTM
STM
PTM
Input
Output
Input
Output
Input
Output
CTCK0
CTCK1
CTP0, CTP0B
CTP1, CTP1B
STCK, STPI
STP, STPB
PTCK, PTPI
PTP, PTPB
TM External Pins
TM Input/Output Pin Selection
Selecting to have a TM input/output or whether to retain its other shared function is implemented
using the relevant pin-shared function selection registers, with the corresponding selection bits in
each pin-shared function register corresponding to a TM input/output pin. Configuring the selection
bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared
function selection are described in the pin-shared function section.
CTCKn
CT�n
CCR output
CTPn
CTPnB
CTM Function Pin Control Block Diagram – n=0 or 1
STCK
CCR capture input
STPI
ST�
CCR output
STP
STPB
STM Function Pin Control Block Diagram
PTCK
CCR capture input
PTPI
PT�
CCR output
PTP
PTPB
PTM Function Pin Control Block Diagram
Rev. 1.20
109
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low
and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be
accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in
a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its
related low byte only takes place when a write or read operation to its corresponding high byte is
executed.
As the CCRA and CCRP registers are implemented in the way shown in the following diagram and
accessing these register pairs is carried out in a specific way as described above, it is recommended
to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named xTMnAL
and PTMRPL, using the following access procedures. Accessing the CCRA or CCRB low byte
registers without following these access procedures will result in unpredictable values.
xT�n Counter Register (Read onl�)
xT�nDL
xTMnDH
8-bit Buffer
xT�nAL
xTMnAH
xTMn CCRA Register (Read/Write)
PT�RPL
PTMRPH
PTM CCRP Register (Read/Write)
Data Bus
The following steps show the read and write procedures:
• Writing Data to CCRA or CCRP
♦♦
Step 1. Write data to Low Byte xTMnAL or PTMRPL
–– note that here data is only written to the 8-bit buffer.
♦♦
Step 2. Write data to High Byte xTMnAH or PTMRPH
–– here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA or CCRP
Rev. 1.20
♦♦
Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMRPH
–– here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦
Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMRPL
–– this step reads data from the 8-bit buffer.
110
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Compact Type TM – CTM
Although the simplest form of the TM types, the Compact TM type still contains three operating
modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The
Compact TM can also be controlled with an external input pin and can drive two external output pin.
Device
CTM Core
CTM Input Pin
CTM Output Pin
Note
BS67F340
BS67F350
BS67F360
10-bit CTM
(CTM0, CTM1)
CTCK0, CTCK1
CTP0, CTP0B
CTP1, CTP1B
n=0 ~ 1
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fSUB
3-bit Comparator P
001
b7~b9
011
10-bit Count-up Counter
100
101
111
CTnON
CTnPAU
Counter Clear
0
1
CTnCCLR
b0~b9
10-bit Comparator A
CT�nPF Interrupt
CTnOC
010
110
CTCKn
Comparator P �atch
000
Comparator A �atch
Output
Control
Polarit�
Control
Pin
Control
CTn�1� CTn�0
CTnIO1� CTnIO0
CTnPOL
PxSn
CTPn
CTPnB
CT�nAF Interrupt
CTnCK2~CTnCK0
CCRA
Compact Type TM Block Diagram – n=0 or 1
Compact TM Operation
The Compact TM core is a 10-bit count-up counter which is driven by a user selectable internal or
external clock source. There are also two internal comparators with the names, Comparator A and
Comparator P. These comparators will compare the value in the counter with CCRP and CCRA
registers. The CCRP is three-bit wide whose value is compared with the highest three bits in the
counter while the CCRA is ten-bit wide and therefore compares with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the CTnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Compact
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
Rev. 1.20
111
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Compact Type TM Register Description
Overall operation of the Compact TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes and as well as the three CCRP bits.
Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CTMnC0
CTnPAU CTnCK2 CTnCK1 CTnCK0
CTnON
CTnRP2 CTnRP1
CTMnC1
CTnM1
CTnM0
CTnIO1
CTnIO0
CTnOC
CTnPOL CTnDPX CTnCCLR
CTnRP0
CTMnDL
D7
D6
D5
D4
D3
D2
D1
D0
CTMnDH
—
—
—
—
—
—
D9
D8
CTMnAL
D7
D6
D5
D4
D3
D2
D1
D0
CTMnAH
—
—
—
—
—
—
D9
D8
10-bit Compact TM Registers List – n=0 or 1
CTMnDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
CTMn Counter Low Byte Register bit 7 ~ bit 0
CTMn 10-bit Counter bit 7 ~ bit 0
CTMnDH Register
Bit
7
6
5
4
3
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
CTMn Counter High Byte Register bit 1 ~ bit 0
CTMn 10-bit Counter bit 9 ~ bit 8
CTMnAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.20
CTMn CCRA Low Byte Register bit 7 ~ bit 0
CTMn 10-bit CCRA bit 7 ~ bit 0
112
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
CTMnAH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
CTMn CCRA High Byte Register bit 1 ~ bit 0
CTMn 10-bit CCRA bit 9 ~ bit 8
CTMnC0 Register
Bit
7
6
5
4
3
2
1
0
Name
CTnPAU
CTnCK2
CTnCK1
CTnCK0
CTnON
CTnRP2
CTnRP1
CTnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7CTnPAU: CTMn Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the CTMn will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4CTnCK2~CTnCK0: Select CTMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: CTCKn rising edge clock
111: CTCKn falling edge clock
These three bits are used to select the clock source for the CTMn. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which
can be found in the oscillator section.
Bit 3CTnON: CTMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the CTMn. Setting the bit high enables
the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero
will stop the counter from counting and turn off the CTMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the CTMn is in
the Compare Match Output Mode then the CTMn output pin will be reset to its initial
condition, as specified by the CTnOC bit, when the CTnON bit changes from low to
high.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit 2~0CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn Counter
bit 9 ~ bit 7
000: 1024 CTMn clocks
001: 128 CTMn clocks
010: 256 CTMn clocks
011: 384 CTMn clocks
100: 512 CTMn clocks
101: 640 CTMn clocks
110: 768 CTMn clocks
111: 896 CTMn clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter’s highest three bits. The result of this
comparison can be selected to clear the internal counter if the CTnCCLR bit is set to
zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
CTMnC1 Register
Bit
7
6
5
4
3
Name
CTnM1
CTnM0
CTnIO1
CTnIO0
CTnOC
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
CTnPOL CTnDPX CTnCCLR
Bit 7~6CTnM1~CTnM0: Select CTMn Operating Mode
00: Compare Match Output Mode
01: Undefined
10: PWM Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the CTMn. To ensure reliable
operation the CTMn should be switched off before any changes are made to the
CTnM1 and CTnM0 bits. In the Timer/Counter Mode, the CTMn output pin control
will be disabled.
Bit 5~4CTnIO1~CTnIO0: Select CTMn external pin (CTPn) function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Undefined
Timer/Counter Mode
Unused
These two bits are used to determine how the CTMn output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the CTMn is running.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the
CTMn output pin changes state when a compare match occurs from the Comparator A.
The CTMn output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the CTMn
output pin should be setup using the CTnOC bit in the CTMnC1 register. Note that
the output level requested by the CTnIO1 and CTnIO0 bits must be different from the
initial value setup using the CTnOC bit otherwise no change will occur on the CTMn
output pin when a compare match occurs. After the CTMn output pin changes state,
it can be reset to its initial level by changing the level of the CTnON bit from low to
high.
In the PWM Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output
pin changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to only change the
values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched off.
Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed
when the CTMn is running.
Bit 3CTnOC: CTPn Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode
0: Active low
1: Active high
This is the output control bit for the CTMn output pin. Its operation depends upon
whether CTMn is being used in the Compare Match Output Mode or in the PWM
Mode. It has no effect if the CTMn is in the Timer/Counter Mode. In the Compare
Match Output Mode it determines the logic level of the CTMn output pin before a
compare match occurs. In the PWM Mode it determines if the PWM signal is active
high or active low.
Bit 2CTnPOL: CTPn Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the CTPn output pin. When the bit is set high the
CTMn output pin will be inverted and not inverted when the bit is zero. It has no effect
if the TM is in the Timer/Counter Mode.
Bit 1CTnDPX: CTMn PWM duty/period control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0CTnCCLR: CTMn Counter Clear condition selection
0: CTMn Comparator P match
1: CTMn Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the CTnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The CTnCCLR bit is not
used in the PWM Mode.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Compact Type TM Operation Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Mode or Timer/Counter Mode. The operating mode is selected using the CTnM1 and CTnM0
bits in the CTMnC1 register.
Compare Match Output Mode
To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register, should be set to “00”
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the CTnCCLR bit is low, there are two ways in which the counter can
be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP
bits are all zero which allows the counter to overflow. Here both CTMnAF and CTMnPF interrupt
request flags for the Comparator A and Comparator P respectively, will both be generated.
If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the CTMnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
CTnCCLR is high no CTMnPF interrupt request flag will be generated. If the CCRA bits are all
zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here
the CTMnAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the CTMn output pin will change
state. The CTMn output pin condition however only changes state when a CTMnAF interrupt
request flag is generated after a compare match occurs from Comparator A. The CTMnPF interrupt
request flag, generated from a compare match occurs from Comparator P, will have no effect on
the CTMn output pin. The way in which the CTMn output pin changes state are determined by
the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register. The CTMn output pin can
be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present
condition when a compare match occurs from Comparator A. The initial condition of the CTMn
output pin, which is setup after the CTnON bit changes from low to high, is setup using the CTnOC
bit. Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
Counter overflow
CCRP=0
0x3FF
CTnCCLR = 0; CTnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
CTnON
CTnPAU
CTnPOL
CCRP Int. flag
CTMnPF
CCRA Int. flag
CTMnAF
CTMn O/P Pin
Output pin set to
initial Level Low
if CTnOC=0
Output not affected by CTMnAF
flag. Remains High until reset by
CTnON bit
Output Toggle with
CTMnAF flag
Here CTnIO [1:0] = 11
Toggle Output select
Note CTnIO [1:0] = 10
Active High Output select
Output Inverts
when CTnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – CTnCCLR=0
Note: 1. With CTnCCLR=0, a Comparator P match will clear the counter
2. The CTMn output pin controlled only by CTMnAF flag
3. The output pin is reset to its initial state by CTnON bit rising edge
4. n=0 or 1
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
CTnCCLR = 1; CTnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
CTnON
CTnPAU
CTnPOL
No CTMnAF flag
generated on
CCRA overflow
CCRA Int. flag
CTMnAF
CCRP Int. flag
CTMnPF
CTMn
O/P Pin
CTMnPF not
generated
Output pin set to
initial Level Low
if CTnOC=0
Output does
not change
Output not affected by
CTMnAF flag. Remains High
until reset by CTnON bit
Output Toggle with
CTMnAF flag
Here CTnIO [1:0] = 11
Toggle Output select
Note CTnIO [1:0] = 10
Active High Output select
Output Inverts
when CTnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – CTnCCLR=1
Note: 1. With CTnCCLR=1, a Comparator A match will clear the counter
2. The CTMn output pin is controlled only by CTMnAF flag
3. The CTMn output pin is reset to initial state by CTnON rising edge
4. The CTMnPF flags is not generated when CTnCCLR=1
5. n=0 or 1
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Timer/Counter Mode
To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
CTMn output pin is not used. Therefore the above description and Timing Diagrams for the
Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not
used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 10
respectively. The PWM function within the CTMn is useful for applications which require functions
such as motor control, heating control, illumination control etc. By providing a signal of fixed
frequency but of varying duty cycle on the CTMn output pin, a square wave AC waveform can be
generated with varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the CTnCCLR bit has no effect on the PWM
operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the CTnDPX bit in the CTMnC1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The CTnOC bit in the CTMnC1 register is used
to select the required polarity of the PWM waveform while the two CTnIO1 and CTnIO0 bits are
used to enable the PWM output or to force the TM output pin to a fixed high or low level. The
CTnPOL bit is used to reverse the polarity of the PWM output waveform.
• 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=0
CCRP
001b
010b
011b
100b
101b
110b
111b
000b
Period
128
256
384
512
640
768
896
1024
Duty
CCRA
If fSYS=16MHz, CTMn clock source is fSYS/4, CCRP=2 and CCRA=128,
The CTMn PWM output frequency=(fSYS/4)/256=fSYS/1024=15.625kHz,
duty=128/256=50%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=1
CCRP
001b
010b
011b
100b
Period
Duty
101b
110b
111b
000b
768
896
1024
CCRA
128
256
384
512
640
The PWM output period is determined by the CCRA register value together with the CTMn clock
while the PWM duty cycle is defined by the CCRP register value.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
CTnDPX = 0; CTnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
CTnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
CTnON bit low
Time
CTnON
CTnPAU
CTnPOL
CCRA Int. flag
CTMnAF
CCRP Int. flag
CTMnPF
CTMn O/P Pin
(CTnOC=1)
CTMn O/P Pin
(CTnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when CTnPOL = 1
PWM Output Mode – CTnDXP=0
Note: 1. Here CTnDPX=0 – Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues even when CTnIO1, CTnIO0=00 or 01
4. The CTnCCLR bit has no influence on PWM operation
5. n=0 or 1
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
CTnDPX = 1; CTnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
CTnON returns high
CCRA
Pause Resume
CCRP
Counter Stop if
CTnON bit low
Time
CTnON
CTnPAU
CTnPOL
CCRP Int.
flag CTMnPF
CCRA Int.
flag CTMnAF
CTMn O/P
Pin (CTnOC=1)
CTMn O/P
Pin (CTnOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when CTnPOL = 1
PWM Output Mode – CTnDXP=1
Note: 1. Here CTnDPX=1 – Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when CTnIO [1:0]=00 or 01
4. The CTnCCLR bit has no influence on PWM operation
5. n=0 or 1
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Standard Type TM – STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can
also be controlled with two external input pins and can drive two external output pin.
Device
STM Core
STM Input Pin
STM Output Pin
BS67F340
BS67F350
BS67F360
16-bit STM
STCK, STPI
STP, STPB
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fSUB
8-bit Comparator P
001
ST�PF Interrupt
STOC
b8~b1�
010
011
16-bit Count-up Counter
100
101
110
STCK
Comparator P �atch
000
STON
STPAU
16-bit Comparator A
0
1
STCCLR
b0~b1�
111
STCK2~STCK0
Counter Clear
Output
Control
Polarit�
Control
Pin
Control
ST�1� ST�0
STIO1� STIO0
STPOL
PxSn
Comparator A �atch
STP
STPB
ST�AF Interrupt
STIO1� STIO0
Edge
Detector
CCRA
STPI
Standard Type TM Block Diagram
Standard TM Operation
The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by
a user selectable internal or external clock source. There are also two internal comparators with the
names, Comparator A and Comparator P. These comparators will compare the value in the counter
with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the
with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all
counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the STON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a STM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. The STMRP register is used to store the 8-bit CCRP value. The
remaining two registers are control registers which setup the different operating and control modes.
Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
STMC0
STPAU
STCK2
STCK1
STCK0
STON
—
—
—
STMC1
STM1
STM0
STIO1
STIO0
STOC
STPOL
STDPX
STCCLR
Bit2
Bit1
Bit0
STMDL
D7
D6
D5
D4
D3
D2
D1
D0
STMDH
D15
D14
D13
D12
D11
D10
D9
D8
STMAL
D7
D6
D5
D4
D3
D2
D1
D0
STMAH
D15
D14
D13
D12
D11
D10
D9
D8
STMRP
STRP7
STRP6
STRP5
STRP4
STRP3
STRP2
STRP1
STRP0
16-bit Standard TM Registers List
STMDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
STM Counter Low Byte Register bit 7 ~ bit 0
STM 16-bit Counter bit 7 ~ bit 0
STMDH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
STM Counter High Byte Register bit 7 ~ bit 0
STM 16-bit Counter bit 15 ~ bit 8
STMAL Register
Bit
7
6
5
4
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
STM CCRA Low Byte Register bit 7 ~ bit 0
STM 16-bit CCRA bit 7 ~ bit 0
STMAH Register
Bit
6
5
4
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.20
7
STM CCRA High Byte Register bit 7 ~ bit 0
STM 16-bit CCRA bit 15 ~ bit 8
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
STMC0 Register
Bit
7
6
5
4
3
2
1
0
Name
STPAU
STCK2
STCK1
STCK0
STON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7STPAU: STM Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the STM will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4STCK2~STCK0: Select STM Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: STCK rising edge clock
111: STCK falling edge clock
These three bits are used to select the clock source for the STM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fSUB are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3STON: STM Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the STM. Setting the bit high enables
the counter to run while clearing the bit disables the STM. Clearing this bit to zero
will stop the counter from counting and turn off the STM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the STM is in
the Compare Match Output Mode then the STM output pin will be reset to its initial
condition, as specified by the STOC bit, when the STON bit changes from low to high.
Bit 2~0
Rev. 1.20
Unimplemented, read as “0”
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
STMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
STM1
STM0
STIO1
STIO0
STOC
STPOL
STDPX
STCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6STM1~STM0: Select STM Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the STM. To ensure reliable operation
the STM should be switched off before any changes are made to the STM1 and STM0
bits. In the Timer/Counter Mode, the STM output pin control will be disabled.
Bit 5~4STIO1~STIO0: Select STM external pin (STP or STPI) function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single Pulse Output
Capture Input Mode
00: Input capture at rising edge of STPI
01: Input capture at falling edge of STPI
10: Input capture at rising/falling edge of STPI
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the STM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the STM is running.
In the Compare Match Output Mode, the STIO1 and STIO0 bits determine how the
STM output pin changes state when a compare match occurs from the Comparator
A. The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the STM output
pin should be setup using the STOC bit in the STMC1 register. Note that the output
level requested by the STIO1 and STIO0 bits must be different from the initial value
setup using the STOC bit otherwise no change will occur on the STM output pin when
a compare match occurs. After the STM output pin changes state, it can be reset to its
initial level by changing the level of the STON bit from low to high.
In the PWM Mode, the STIO1 and STIO0 bits determine how the STM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to only change the
values of the STIO1 and STIO0 bits only after the STM has been switched off.
Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed
when the STM is running.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit 3STOC: STM STP Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the STM output pin. Its operation depends upon
whether STM is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the STM
output pin before a compare match occurs. In the PWM Mode/Single Pulse Output
Mode it determines if the PWM signal is active high or active low.
Bit 2STPOL: STM STP Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the STP output pin. When the bit is set high the STM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
STM is in the Timer/Counter Mode.
Bit 1STDPX: STM PWM duty/period control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0STCCLR: STM Counter Clear condition selection
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the STCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
STMRP Register
Bit
7
6
5
4
3
2
1
0
Name
STRP7
STRP6
STRP5
STRP4
STRP3
STRP2
STRP1
STRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter
bit15~bit8
Comparator P match period =
0: 65536 STM clocks
1~255: (1~255) × 256 STM clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the STCCLR bit is set to
zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Standard Type TM Operation Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the STM1 and STM0 bits in the STMC1 register.
Compare Match Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the STM output pin, will change
state. The STM output pin condition however only changes state when a STMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STM
output pin. The way in which the STM output pin changes state are determined by the condition of
the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the
STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the STM output pin, which is setup after
the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and
STIO0 bits are zero then no pin change will take place.
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
Counter overflow
CCRP=0
0xFFFF
STCCLR = 0; STM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
STON
STPAU
STPOL
CCRP Int.
flag STMPF
CCRA Int.
flag STMAF
STM O/P Pin
Output pin set to
initial Level Low
if STOC=0
Output not affected by STMAF
flag. Remains High until reset by
STON bit
Output Toggle with
STMAF flag
Here STIO [1:0] = 11
Toggle Output select
Note STIO [1:0] = 10
Active High Output select
Output Inverts
when STPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – STCCLR=0
Note: 1. With STCCLR=0 a Comparator P match will clear the counter
2. The STMn output pin is controlled only by the STMAF flag
3. The output pin is reset to itsinitial state by a STON bit rising edge
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
STCCLR = 1; STM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0xFFFF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
STON
STPAU
STPOL
No STMAF flag
generated on
CCRA overflow
CCRA Int.
flag STMAF
CCRP Int.
flag STMPF
STM O/P Pin
STMPF not
generated
Output pin set to
initial Level Low
if STOC=0
Output does
not change
Output Toggle with
STMAF flag
Here STIO [1:0] = 11
Toggle Output select
Output not affected by
STMAF flag. Remains High
until reset by STON bit
Note STIO [1:0] = 10
Active High Output select
Output Inverts
when STPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode –STCCLR=1
Note: 1. With STCCLR=1 a Comparator A match will clear the counter
2. The STM output pin is controlled only by the STMAF flag
3. The output pin is reset to its initial state by a STON bit rising edge
4. A STMPF flag is not generated when STCCLR=1
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Timer/Counter Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM
output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively
and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within
the STM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty
cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to
select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to
enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit
is used to reverse the polarity of the PWM output waveform.
• 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0
CCRP
1~255
0
Period
CCRPx256
65536
Duty
CCRA
If fSYS=16MHz, STM clock source is fSYS/4, CCRP=2 and CCRA=128,
The STM PWM output frequency=(fSYS/4) / (2×256)=fSYS/2048=7.8125 kHz, duty=128/(2×256)= 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1
CCRP
1~255
Period
0
CCRA
Duty
CCRPx256
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is
equal to 0.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
STDPX = 0; STM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
STON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
STON bit low
Time
STON
STPAU
STPOL
CCRA Int.
flag STMAF
CCRP Int.
flag STMPF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when STPOL = 1
PWM Output Mode – STDXP=0
Note: 1. Here STDPX=0 – Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when STIO [1:0]=00 or 01
4. The STCCLR bit has no influence on PWM operation
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
STDPX = 1; STM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
STON returns high
CCRA
Pause Resume
CCRP
Counter Stop if
STON bit low
Time
STON
STPAU
STPOL
CCRP Int.
flag STMPF
CCRA Int.
flag STMAF
STM O/P
Pin (STOC=1)
STM O/P
Pin (STOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when STPOL = 1
PWM Output Mode – STDXP=1
Note: 1. Here STDPX=1 – Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when STIO [1:0]=00 or 01
4. The STCCLR bit has no influence on PWM operation
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Single Pulse Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively
and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode,
as the name suggests, will generate a single shot pulse on the STM output pin.
The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the STON bit
can also be made to automatically change from low to high using the external STCK pin, which will
in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The STON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
STON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the STON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter
can only be reset back to zero when the STON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in
this Mode.
S/W Command
SET“STON”
or
STCK Pin
Transition
CCRA
Leading Edge
CCRA
Trailing Edge
STON bit
0à1
STON bit
1à0
S/W Command
CLR“STON”
or
CCRA Compare
Match
STP Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
STM [1:0] = 10 ; STIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
STON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
STON
Software
Trigger
Auto. set by
STCK pin
Cleared by
CCRA match
STCK pin
Software
Trigger
Software
Trigger
Software
Clear
Software
Trigger
STCK pin
Trigger
STPAU
STPOL
No CCRP Interrupts
generated
CCRP Int. Flag
STMPF
CCRA Int. Flag
STMAF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
Output Inverts
when STPOL = 1
Pulse Width
set by CCRA
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse triggered by the STCK pin or by setting the STON bit high
4. A STCK pin active edge will automatically set the STON bit high.
5. In the Single Pulse Mode, STIO [1:0] must be set to “11” and can not be changed.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Capture Input Mode
To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal
is supplied on the STPI pin, whose active edge can be a rising edge, a falling edge or both rising
and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in
the STMC1 register. The counter is started when the STON bit changes from low to high which is
initiated using the application program.
When the required edge transition appears on the STPI pin the present value in the counter will be
latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur
on the STPI pin the counter will continue to free run until the STON bit changes from high to low.
When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP
value can be used to control the maximum counter value. When a CCRP compare match occurs
from Comparator P, a STM interrupt will also be generated. Counting the number of overflow
interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1
and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or
both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take
place irrespective of what happens on the STPI pin, however it must be noted that the counter will
continue to run. The STCCLR and STDPX bits are not used in this Mode.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
STM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
STON
STPAU
Active
edge
Active
edge
Active edge
STM capture
pin STPI
CCRA Int. Flag
STMAF
CCRP Int. Flag
STMPF
CCRA
Value
STIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. STnM [1:0]=01 and active edge set by the STIO [1:0] bits
2. A STM Capture input pin active edge transfers the counter value to CCRA
3. STCCLR bit not used
4. No output function -- STOC and STPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Periodic Type TM – PTM
The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
also be controlled with two external input pins and can drive two external output pin.
Device
PTM Core
PTM Input Pin
PTM Output Pin
BS67F340
BS67F350
BS67F360
10-bit PTM
PTCK, PTPI
PTP, PTPB
CCRP
10-bit Comparator P
fSYS/4
fSYS
fH/16
fH/64
fSUB
fSUB
Comparator P �atch
PT�PF Interrupt
000
001
PTOC
b0~b9
010
011
10-bit Count-up Counter
100
101
110
PTCK
PTON
PTPAU
10-bit Comparator A
CCRA
Output
Control
Polarit�
Control
Pin
Control
PT�1� PT�0
PTIO1� PTIO0
PTPOL
PxSn
0
1
PTCCLR
b0~b9
111
PTCK2~PTCK0
Counter Clear
Comparator A �atch
PTIO1� PTIO0
PTCAPTS
Edge
Detector
0
1
PTP
PTPB
PT�AF Interrupt
IFS
Pin
Control
PTPI
Periodic Type TM Block Diagram
Periodic TM Operation
The size of Periodic TM is 16-bit wide and its core is a 10-bit count-up counter which is driven by
a user selectable internal or external clock source. There are also two internal comparators with the
names, Comparator A and Comparator P. These comparators will compare the value in the counter
with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is
respectively compared with all counter bits.
The only way of changing the value of the 10-bit counter using the application program is to
clear the counter by changing the PTON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pins. All operating setup conditions
are selected using relevant internal registers.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Periodic Type TM Register Description
Overall operation of the Periodic TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which
setup the different operating and control modes.
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTMC0
PTPAU
PTCK2
PTCK1
PTCK0
PTON
—
—
—
PTMC1
PTM1
PTM0
PTIO1
PTIO0
PTOC
PTMDL
D7
D6
D5
D4
D3
D2
D1
PTMDH
—
—
—
—
—
—
D9
D8
PTMAL
D7
D6
D5
D4
D3
D2
D1
D0
PTPOL PTCAPTS PTCCLR
D0
PTMAH
—
—
—
—
—
—
D9
D8
PTMRPL
PTRP7
PTRP6
PTRP5
PTRP4
PTnRP3
PTRP2
PTRP1
PTRP0
PTMRPH
—
—
—
—
—
—
PTRP9
PTRP8
Periodic TM Registers List
PTMDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTM Counter Low Byte Register bit 7 ~ bit 0
PTM 10-bit Counter bit 7 ~ bit 0
PTMDH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
PTM Counter High Byte Register bit 1 ~ bit 0
PTM 10-bit Counter bit 9 ~ bit 8
PTMAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.20
PTM CCRA Low Byte Register bit 7 ~ bit 0
PTM 10-bit CCRA bit 7 ~ bit 0
138
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
PTMAH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
PTM CCRA High Byte Register bit 1 ~ bit 0
PTM 10-bit CCRA bit 9 ~ bit 8
PTMRPL Register
Bit
7
6
5
4
3
2
1
0
Name
PTnRP7
PTnRP6
PTnRP5
PTnRP4
PTnRP3
PTnRP2
PTnRP1
PTnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0PTRP7~PTRP0: PTM CCRP Low Byte Register bit 7 ~ bit 0
PTM 10-bit CCRP bit 7 ~ bit 0
PTMRPH Register
Bit
7
6
5
4
3
Name
—
—
—
—
—
—
PTnRP9
PTnRP8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
1
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0PTRP9~PTRP8: PTM CCRP High Byte Register bit 1 ~ bit 0
PTM 10-bit CCRP bit 9 ~ bit 8
PTMC0 Register
Bit
7
6
5
4
3
2
Name
PTPAU
PTCK2
PTCK1
PTCK0
PTON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7PTPAU: PTM Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the PTM will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit 6~4PTCK2~PTCK0: Select PTM Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: PTCK rising edge clock
111: PTCK falling edge clock
These three bits are used to select the clock source for the PTM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fSUB are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3PTON: PTM Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the PTM. Setting the bit high enables
the counter to run while clearing the bit disables the PTM. Clearing this bit to zero
will stop the counter from counting and turn off the PTM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the PTM is in
the Compare Match Output Mode then the PTM output pin will be reset to its initial
condition, as specified by the PTOC bit, when the PTON bit changes from low to high.
Bit 2~0
Unimplemented, read as “0”
PTMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
PTM1
PTM0
PTIO1
PTIO0
PTOC
PTPOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PTCAPTS PTCCLR
Bit 7~6PTM1~PTM0: Select PTM Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the PTM. To ensure reliable operation
the PTM should be switched off before any changes are made to the PTM1 and PTM0
bits. In the Timer/Counter Mode, the PTM output pin control will be disabled.
Bit 5~4PTIO1~PTIO0: Select PTM external pin PTP or PTPI function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single Pulse Output
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Capture Input Mode
00: Input capture at rising edge of PTPI or PTCK
01: Input capture at falling edge of PTPI or PTCK
10: Input capture at rising/falling edge of PTPI or PTCK
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the PTM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the PTM is running.
In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the
PTM output pin changes state when a compare match occurs from the Comparator A.
The PTM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the PTM output
pin should be setup using the PTOC bit in the PTMC1 register. Note that the output
level requested by the PTIO1 and PTIO0 bits must be different from the initial value
setup using the PTOC bit otherwise no change will occur on the PTM output pin when
a compare match occurs. After the PTM output pin changes state, it can be reset to its
initial level by changing the level of the PTON bit from low to high.
In the PWM Mode, the PTIO1 and PTIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PTM output function
is modified by changing these two bits. It is necessary to only change the values of the
PTIO1 and PTIO0 bits only after the PTM has been switched off. Unpredictable PWM
outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is running.
Bit 3PTOC: PTM PTP Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the PTM output pin. Its operation depends upon
whether PTM is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the PTM
output pin before a compare match occurs. In the PWM Mode/Single Pulse Output
Mode it determines if the PWM signal is active high or active low.
Bit 2PTPOL: PTM PTP Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the PTP output pin. When the bit is set high the PTM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
PTM is in the Timer/Counter Mode.
Bit 1PTCAPTS: PTM Capture Triiger Source selection
0: From PTPI pin
1: From PTCK pin
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit 0PTCCLR: PTM Counter Clear condition selection
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the PTCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
Periodic Type TM Operation Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register.
Compare Match Output Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the PTM output pin will change
state. The PTM output pin condition however only changes state when a PTMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM
output pin. The way in which the PTM output pin changes state are determined by the condition of
the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the
PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after
the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and
PTIO0 bits are zero then no pin change will take place.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
Counter overflow
CCRP=0
0x3FF
PTCCLR = 0; PTM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
PTON
PTPAU
PTPOL
CCRP Int. Flag
PTMPF
CCRA Int. Flag
PTMAF
PTM
O/P Pin
Output pin set to
initial Level Low
if PTOC=0
Output not affected by
PTMAF flag. Remains High
until reset by PTON bit
Output Toggle with
PTMAF flag
Here PTIO [1:0] = 11
Toggle Output select
Note PTIO [1:0] = 10
Active High Output select
Output Inverts
when PTPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode - PTCCLR=0
Note: 1. With PTCCLR=0, a Comparator P match will clear the counter
2. The PTM output pin is controlled only by the PTMAF flag
3. The output pin is reset to its initial state by a PTON bit rising edge
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
PTCCLR = 1; PTM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
PTON
PTPAU
PTPOL
No PTMAF flag
generated on
CCRA overflow
CCRA Int. Flag
PTMAF
CCRP Int. Flag
PTMPF
PTM
O/P Pin
PTMPF not
generated
Output pin set to
initial Level Low
if PTOC=0
Output does
not change
Output Toggle with
PTMAF flag
Here PTIO [1:0] = 11
Toggle Output select
Output not affected by PTMAF
flag. Remains High until reset
by PTON bit
Note PTIO [1:0] = 10
Active High Output select
Output Inverts
when PTPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode - PTCCLR=1
Note: 1. With PTCCLR=1, a Comparator A match will clear the counter
2. The PTM output pin is controlled only by the PTMAF flag
3. The output pin is reset to its initial state by a PTON bit rising edge
4. A PTMPF flag is not generated when PTCCLR =1
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Timer/Counter Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM
output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the PTM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively
and also the PTIO1 and PTIO0 bits should be set to 10 respectively. The PWM function within
the PTM is useful for applications which require functions such as motor control, heating control,
illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the
PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the PTCCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore
be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to
select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to
enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit
is used to reverse the polarity of the PWM output waveform.
• 16-bit PTM, PWM Mode
Period
Duty
CCRP=0
CCRP=1~65535
65536
1~65535
CCRA
If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128,
The PTM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%,
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
PTM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
PTON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
PTON bit low
Time
PTON
PTPAU
PTPOL
CCRA Int. Flag
PTMAF
CCRP Int. Flag
PTMPF
PTM O/P Pin
(PTOC=1)
PTM O/P Pin
(PTOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
When PTPOL = 1
PWM Mode
Note: 1. The counter is cleared by CCRP.
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PTIO [1:0]=00 or 01
4. The PTCCLR bit has no influence on PWM operation
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Single Pulse Output Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively
and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode,
as the name suggests, will generate a single shot pulse on the PTM output pin.
The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the PTON bit
can also be made to automatically change from low to high using the external PTCK pin, which will
in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The PTON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
PTON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PTON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter
can only be reset back to zero when the PTON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR is not used in this Mode.
S/W Command
SET“PTON”
or
PTCK Pin
Transition
CCRA
Leading Edge
CCRA
Trailing Edge
PTON bit
0à1
PTON bit
1à0
S/W Command
CLR“PTON”
or
CCRA Compare
Match
PTP Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
PTM [1:0] = 10 ; PTIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
PTON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
PTON
Software
Trigger
Auto. set by
PTCK pin
Cleared by
CCRA match
PTCK pin
Software
Trigger
Software
Trigger
Software
Clear
Software
Trigger
PTCK pin
Trigger
PTPAU
PTPOL
No CCRP Interrupts
generated
CCRP Int. Flag
PTMPF
CCRA Int. Flag
PTMAF
PTM O/P Pin
(PTOC=1)
PTM O/P Pin
(PTOC=0)
Pulse Width
set by CCRA
Output Inverts
when PTPOL = 1
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse triggered by the PTCK pin or by setting the PTON bit high
4. A PTCK pin active edge will automatically set the PTON bit high.
5. In the Single Pulse Mode, PTIO [1:0] must be set to “11” and can not be changed.
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Capture Input Mode
To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the PTPI or PTCK pin, selected by the PTCAPTS bit in the PTMC1 register. The input
pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active
edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter
is started when the PTON bit changes from low to high which is initiated using the application
program.
When the required edge transition appears on the PTPI or PTCK pin the present value in the counter
will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events
occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes
from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this
way the CCRP value can be used to control the maximum counter value. When a CCRP compare
match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of
overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths.
The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising
edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture
operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be
noted that the counter will continue to run.
As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the
Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin
may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not
used in this Mode.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Counter Value
PTM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
PTON
PTPAU
Active
edge
Active
edge
Active edge
PTM capture pin
PTPI or PTCK
CCRA Int. Flag
PTMAF
CCRP Int. Flag
PTMPF
CCRA
Value
PTIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. PTM [1:0]=01 and active edge set by the PTIO [1:0] bits
2. A PTM Capture input pin active edge transfers the counter value to CCRA
3. PTCCLR bit not used
4. No output function – PTOC and PTPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Overview
These devices contain a multi-channel analog to digital converter which can directly interface to
external analog signals, such as that from sensors or other control signals and convert these signals
directly into a 12-bit digital value. It also can convert the internal signals, such as the Temperature
semsor output or Temperature sensor reference voltage, into a 12-bit digital value. The external or
internal analog signal to be converted is determined by the ACS3~ACS0 bits together with the TSE
and BGMEN bits. When the external analog signal is to be converted, the corresponding pin-shared
control bits should first be properly configured and then desired external channel input should be
selected using the ACS3~ACS0 bits.
This A/D converter also includes a temperature sensor circuitry which contains a temperature
sensor, operational amplifiers and an internal reference voltage. The temperature sensor will detect
the temperature and output a voltage proportional to the temperature. The output voltage can be
amplified by the OPA and then converted to an 12-bit digital data using the A/D converter.
The accompanying block diagram shows the internal structure of the A/D converter with temperature
sensor together with its associated registers and control bits.
Rev. 1.20
Device
External Input Channels
Internal Signal
A/D Channel Select Bits
BS67F340
BS67F350
BS67F360
8: AN0~AN7
2: VTSO, VTSVREF
ACS3~ACS0
TSE, BGMEN
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VDD
fSYS
÷ 2N
ADCK2~ADCK0
Pin-shared
Selection ACS3~SACS0
(N=0~7)
ADCEN
TSCLK_S1~TSCLK_S0
A/D Clock
AN0
AN1
1xxxB
ADRL
A/D Converter
AN7
VSS
TSE
1xxxB
VTSVREF
ATM
START
IDLE_CONV
VTSO
A/D Converter
Reference Voltage
OP2EN
VPTAT
Temp.
Sensor
BGMEN
ADRFS
ADBZ
BGMEN
TSE
A/D Data
Registers
ADRH
VTSO
OPA2
VTSVREF
VDD
Gain=4 or 5
G5XEN
BIAS
VPTAT
VBG
Pin-shared
Selection
VREFP_EXT
VREF
OP1EN
VTSVRI
VTSVREF
OPA1
VDD
VREFS
Gain=1.675 or 1
K_VPTAT
K_REFO
A/D Converter with Temperature Sensor Diagram
Registers Descriptions
Overall operation of the A/D converter with Temperature sensor is controlled using eight registers.
A read only register pair exists to store the A/D Converter data 12-bit value. Two registers, ADCR0
and ADCR1, are the control registers which setup the operating and control function of the A/D
converter. The remaining four registers are the temperature sensor control registers which select
the temperature sensor signal to be converted and the reference voltage source together with the
temperature sensor conversion clock cycles.
Register Name
ADRL (ADRFS=0)
Bit
7
6
5
4
3
2
1
0
D3
D2
D1
D0
—
—
—
—
ADRL (ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
ADRH (ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
ADRH (ADRFS=1)
—
—
—
—
D11
D10
D9
D8
ADCR0
START
ADBZ
ADCR1
ATM
—
ADCEN
ADRFS ACS3
IDLE_CONV VREFS
ACS2
ACS1
ACS0
—
ADCK2
ADCK1
ADCK0
TSC0
BGMEN
G5XEN
K_REFO
—
—
—
—
—
TSC1
TSE
OP2EN
OP1EN
—
—
—
—
—
TSC2
VREFP_EXT
BIAS
D5
D4
D3
D2
TSC3
—
—
K_VPTAT
—
—
—
TSCLK_S1 TSCLK_S0
—
—
A/D Converter with Temperature Sensor Registers List
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
A/D Converter Data Registers – ADRL, ADRH
As these devices contain an internal 12-bit A/D converter, it requires two data registers to store the
converted value. These are a high byte register, known as ADRH, and a low byte register, known
as ADRL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any
unused bits will be read as zero. Note that the A/D data register contents can only be read in the A/
D conversion completion interrupt service subroutine when the Auto-conversion mode is enabled by
setting the ATM bit in the ADCR1 register to 1. The A/D data registers contents will be cleared to
zero if the A/D converter is disabled.
ADRFS
0
1
ADRH
7
6
D11 D10
0
0
ADRL
5
4
3
2
1
0
7
6
5
4
3
2
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Converter Data Registers
A/D Converter Control Registers – ADCR0, ADCR1
To control the function and operation of the A/D converter, two control registers known as
ADCR0 and ADCR1 are provided. These 8-bit registers define functions such as the selection of
which analog channel is connected to the internal A/D converter, the digitised data format, the A/
D clock source as well as controlling the start function and monitoring the A/D converter busy
status. As these devices contain only one actual analog to digital converter hardware circuit, each
of the external and internal analog signals must be routed to the converter. The ACS3~ACS0 bits
in the ADCR0 register and the TSE and BGMEN bits in the TSC1 and TSC0 registers are used to
determine that the specific external channel input or relevant internal temperature sensor signal is
selected to be converted. If the internal temperature sensor analog signal is selected to be converted,
the ACS3~ACS0 bits should be set as “1xxx” together with proper configurations of TSE and
BGMEN bits.
TSE
BGMEN
ACS3~ACS0
Input Signals
Description
0
x
x000~x111
AN0~AN7
External channel analog input
1
0
1xxx
VTSO
Temperature Sensor output voltage
1
1
1xxx
VTSVREF
Temperature Sensor reference voltage
A/D Converter Input Signal Selection
The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog
inputs for the A/D converter input and which pins are not to be used as the A/D converter input.
When the pin is selected to be an A/D input, its original function whether it is an I/O or other pinshared function will be removed. In addition, any internal pull-high resistor connected to the pin will
be automatically removed if the pin is selected to be an A/D converter input.
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• ADCR0 Register
Bit
7
6
5
4
3
2
1
0
Name
START
ADBZ
ADCEN
ADRFS
ACS3
ACS2
ACS1
ACS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7START: Start the A/D Conversion
0→1→0: Start
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
Bit 6ADBZ: A/D Converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to 0 after the A/D conversion is complete.
Bit 5ADCEN: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set to one to enable
the A/D converter. If the bit is set low, then the A/D converter will be switched off
reducing the device power consumption. When the A/D converter function is disabled,
the contents of the A/D data register pair known as ADRH and ADRL will be cleared
to zero.
Bit 4ADRFS: A/D conversion data format select
0: A/D converter data format → ADRH=D [11:4]; ADRL=D [3:0]
1: A/D converter data format → ADRH=D [11:8]; ADRL=D [7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Bit 3~0ACS3~ACS0: A/D converter analog input signal select
0000: External AN0 input
0001: External AN1 input
0010: External AN2 input
0011: External AN3 input
0100: External AN4 input
0101: External AN5 input
0110: External AN6 input
0111: External AN7 input
1xxx: Internal signal from temperature sensor – temperature output voltage or
reference voltage
The “1xxx” selection is only available when the TSE bit is set to 1. To select the
internal temperature sensor signal to be converted, these bits must be set as “1xxx”
when the TSE bit is set to 1. Otherwise, these bits are used to select the external ANn
channel input without the regard of the ACS3 value if the TSE bit is cleared to 0.
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• ADCR1 Register
Bit
7
6
5
4
3
2
1
0
Name
ATM
—
IDLE_CONV
VREFS
—
ADCK2
ADCK1
ADCK0
R/W
R/W
—
R/W
R/W
—
R/W
R/W
R/W
POR
0
—
0
0
—
0
0
0
Bit 7ATM: A/D auto-conversion mode enable control
0: Disable
1: Enable
When this bit is set to 1, the A/D converter will continuously perform the data
conversion after the current conversion is complete without configuring the “START”
bit by application program. Note that the A/D conversion data can only be read in the
A/D conversion completion interrupt service subroutine when the A/D auto-conversion
mode is enabled.
Bit 6
Unimplemented, read as “0”
Bit 5IDLE_CONV: CPU idle conversion mode enable control
0: Disable
1: Enable
When this bit is set to 1, the A/D conversion with CPU idle mode will be enabled. The
CPU will not operate when the A/D converter is operating with the IDLE_CONV bit
being set to 1 until the conversion is completed.
Bit 4VREFS: A/D converter reference voltage select
0: Internal A/D converter power
1: VREF pin
This bit is used to select the A/D converter reference voltage and only available when
the VREFP_EXT bit in the TSC2 regoster is set to 1. It is recommended to keep the
VREFP_EXT bit low when the internal temperature sensor signal is selected to be
converted.
Bit 3
Unimplemented, read as “0”
Bit 2~0ADCK2~ADCK0: A/D conversion clock source select
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: fSYS/128
These bits are used to select the clock source for the A/D converter. It is recommended
that the A/D conversion clock frequency should be in the range from 500 kHz
to 1MHz by properly configuring the ADCK2~ADCK0 bits when the internal
temperature sensor signal is selected to be converted as temperature sensor enabled.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
• TSC0 Register
Bit
7
6
5
4
3
2
1
0
Name
BGMEN
G5XEN
K_REFO
—
—
—
—
—
R/W
R/W
R/W
R/W
—
—
—
—
—
POR
0
1
0
—
—
—
—
—
Bit 7BGMEN: Temperature sensor reference voltage output function enable control
0: Disable
1: Enable
This bit controls the internal temperature sensor reference voltage output function
and is only available when the TSE bit is set to 1. The internal temperature sensor
reference voltage can be converted when the TSE and BGMEN bits are set to 1 and
the ACS bit field is set to “1xxx”. However, the internal temperature sensor output
voltage will be converted if the TSE bit is set to 1 and the BGMEN bit is cleared to 0
together with ACS bit field equal to “1xxx”.
Bit 6G5XEN: OPA2 gain select
0: Gain=4
1: Gain=5
This bit controls the OPA2 gain selection. This bit should be properly selected for
different temperature range applications to avoid the saturated code.
Bit 5K_REFO: OPA1 gain select
0: Gain=1.675
1: Gain=1
This bit is used to select the OPA1 gain to determine the temperature sensor reference
voltage output value.
Bit 4~0
Unimplemented, read as “0”
• TSC1 Register
Bit
7
6
5
4
3
2
1
0
Name
TSE
OP2EN
OP1EN
—
—
—
—
—
R/W
R/W
R/W
R/W
—
—
—
—
—
POR
0
0
0
—
—
—
—
—
Bit 7TSE: Temperature sensor circuitry enable control
0: Disable
1: Enable
This bit controls the internal temperature sensor circuitry. When the temperature sensor
is enabled by setting the TSE bit to 1, a time named as tTSS should be allowed for the
temperature sensor circuit to stabilise before implementing relevant temperature sensor
operation.
Bit 6OP2EN: Temperature sensor OPA2 enable control
0: Disable
1: Enable
Bit 5OP1EN: Temperature sensor OPA1 enable control
0: Disable
1: Enable
Bit 4~0
Rev. 1.20
Unimplemented, read as “0”
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• TSC2 Register
Bit
7
6
5
4
3
2
Name
VREFP_EXT
BIAS
D5
D4
D3
D2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
TSCLK_S1 TSCLK_S0
Bit 7VREFP_EXT: A/D converter positive reference voltage select
0: Temperature reference voltage – VTSVREF
1: Determined by VREFS bit
This bit is used to select the A/D converter positive reference voltage. When this bit
is set to 1, the A/D converter reference voltage is determines by the VREFS bit in the
ADCR1 register. However, this bit should be set low to select the VTSVREF voltage as
the A/D converter reference voltage together with proper configurations of the OPA2
input signal and gain.
Bit 6BIAS: OPA2 bias voltage select
0: VTSVREF
1: Internal A/D converter power
Bit 5~2D5~D2: Data bits for internal used
These bits should be kept low and can not be changed.
Bit 1~0TSCLK_S1~TSCLK_S0: Temperature sensor clock source tTSCLK select
00: tTSCLK=tADCK/4
01: tTSCLK=tADCK/8
1x: tTSCLK=tADCK/16
The temperature sensor signal conversion time can be ontained using the equation:
Temperature sensor signal conversion time=(5*N+1+16) * tADCK
In the above equation “N” represents the divided ratio, 4, 8 or 16, which is determined
by the TSCLK_S1 and TSCLK_S0 bits.
• TSC3Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
K_VPTAT
—
—
—
—
—
R/W
—
—
R/W
—
—
—
—
—
POR
—
—
0
—
—
—
—
—
Bit 7~6
Unimplemented, read as “0”
Bit 5K_VPTAT: OPA1 input voltage select
0: VBG
1: VPTAT
This bit is used to select the OPA1 input voltage to obtain the internal temperature
sensor reference voltage.
Bit 4~0
Rev. 1.20
Unimplemented, read as “0”
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A/D Operation
The START bit in the ADCR0 register is used to start the AD conversion. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be
initiated.
The ADBZ bit in the ADCR0 register is used to indicate whether the analog to digital conversion
process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an
A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be
cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an internal interrupt signal will be generated. This
A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt
address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the
ADBZ bit in the ADCR0 register to check whether it has been cleared as an alternative method of
detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the
system clock fSYS and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D
clock source speed that can be selected. As the recommended range of permissible A/D clock period,
tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, as the
system clock operates at a frequency of 8MHz, the ADCK2~ADCK0 bits should not be set to 000,
001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period
which may result in inaccurate A/D conversion values. Refer to the following table for examples,
where values marked with an asterisk * show where, depending upon the device, special care must
be taken, as the values may be less than the specified minimum A/D Clock Period.
However, the recommended A/D clock period is from 1μs to 2μs if the input signal to be converted
is the temperature sensor output voltage or reference voltage.
A/D Clock Period (tADCK)
fSYS
ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0]
= 000
= 001
= 010
= 011
= 100
= 101
= 110
= 111
(fSYS)
(fSYS/2)
(fSYS/4)
(fSYS/8)
(fSYS/16)
(fSYS/32)
(fSYS/64)
(fSYS/128)
1MHz
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
2MHz
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
128μs *
64μs *
4MHz
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
8MHz
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
12MHz
83ns *
167ns *
333ns *
667ns
1.33μs
2.67μs
5.33μs
10.67μs *
16MHz
62.5ns *
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
20MHz
50ns *
100ns *
200ns *
400ns *
800ns
1.6μs
3.2μs
6.4μs
A/D Clock Period Examples for External Analog Inputs
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADCEN bit in the ADCR0 register. This bit must be set high to power on the A/D converter.
When the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay,
as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be
consumed. In power conscious applications it is therefore recommended that the ADCEN is set low
to reduce power consumption when the A/D converter function is not being used.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
A/D Reference Voltage
The reference voltage supply to the A/D Converter can be supplied from the positive power supply
pin, VDD, an external reference source supplied on pin VREF or an internal temperature sensor
reference voltage VTSVREF. The internal temperature sensor reference voltage can be derived from the
intenal VBG or VPTAT voltage selected using the K_VPTAT bit in the TSC3 register and then amplified
through a programmable gain amplifier except the one sourced from VDD. The PGA gain can be
equal to 1.675 or 1 selected by the K_REFO bit in the TSC0 register. As the VREF pin is pin-shared
with other functions, when the VREF pin is selected as the reference voltage supply pin, the VREF
pin-shared function control bits should first be properly configured to disable other pin-shared
functions.
A/D Input Pins
All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions.
The corresponding pin-shared function selection bits in the PxS0 and PxS1 registers, determine
whether the external input pins are setup as A/D converter analog channel inputs or whether they
have other functions. If the corresponding pin is setup to be an A/D converter analog channel input,
the original pin functions will be disabled. In this way, pins can be changed under program control
to change their function between A/D inputs and other functions. All pull-high resistors, which are
setup through register programming, will be automatically disconnected if the pins are setup as A/D
inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register
to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input,
the status of the port control register will be overridden.
The A/D converter has its own reference voltage pin, VREF. However, the reference voltage can
also be supplied from the power supply pin or an internal temperature sensor circuit, a choice which
is made through the VREFP_EXT and VREFS bits in the TSC2 and ADCR1 register respectively.
Note that the analog input signal values must not be allowed to exceed the value of the selected A/D
reference voltage.
Conversion Rate and Timing Diagram
A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D
clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is
defined as tADC are necessary. However, an A/D conversion for an internal temperature sensor signal
will take a total of 56 A/D clock cycles.
Maximum single A/D conversion rate=A/D clock period/16 (External channel input signal)
Maximum single A/D conversion rate=A/D clock period/56 (Internal Temperature sensor signal)
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
tON2ST
ADCEN
off
on
off
A/D sampling time
tADS
A/D sampling time
tADS
Start of A/D conversion
Start of A/D conversion
on
START
ADBZ
ACS[3:0]
(TSE=0)
End of A/D
conversion
x011B
A/D channel
switch
End of A/D
conversion
x010B
tADC
A/D conversion time
Start of A/D conversion
x000B
tADC
A/D conversion time
x001B
tADC
A/D conversion time
A/D Conversion Timing – External Channel Input
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by properly programming the ADCK2~ADCK0 bits in
the ADCR1 register.
• Step 2
Enable the A/D converter by setting the ADCEN bit in the ADCR0 register to one.
• Step 3
Select which signal is to be connected to the internal A/D converter by correctly configuring the
ACS3~ACS0 bits
If the TSE bit is 0 and ACS3~ACS0 bits are equal to x000~x111, then an external channel input
is selected.
If the TSE bit is 1 and ACS3~ACS0 bits are equal to 1xxx, then the relevant internal temperature
sensor signal is selected.
• Step 4
Select the reference voltgage source by configuring the K_VPTAT, K_REFO and VREFS bits.
• Step 5
Select the A/D converter output data format by configuring the ADRFS bit.
• Step 6
If A/D conversion interrupt is used, the interrupt control registers must be correctly configured
to ensure the A/D interrupt function is active. The master interrupt bontrol bit, EMI, and the A/D
conversion interrupt control bit, ADE, must both be set high in advance.
• Step 7
The A/D conversion procedure can now be initialized by setting the START bit from low to high
and then low again.
• Step 8
If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion
process is complete, the ADBZ flag will go low and then the output data can be read from ADRH
and ADRL registers.
Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit
in the ADCR0 register is used, the interrupt enable step above can be omitted. However, the
interrupt method must be used to check for the end of the conversion process and obtain the
corresponding digital output data if the auto-conversion mode is enabled.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by setting bit ADCEN low in the ADCR
register. When this happens, the internal A/D converter circuits will not consume power irrespective
of what analog voltage is applied to their input lines. If the A/D converter input lines are used as
normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may
lead to some increase in power consumption.
A/D Transfer Function
As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the reference voltage, this gives a single bit
analog input value of reference voltage value divided by 4096.
1 LSB=VREF ÷ 4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage=A/D output digital value × VREF ÷ 4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VREF level.
    
 
      Ideal A/D Transfer Function
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A/D Programming Examples
The following two programming examples illustrate how to setup and implement an A/D
conversion. In the first example, the method of polling the ADBZ bit in the ADCR register is used to
detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is
used to determine when the conversion is complete.
Example: using an ADBZ polling method to detect the end of conversion
clr ADE;
set VREFP_EXT ;
mov a,03H;
mov ADCR1,a ;
set ADCEN
mov a,03H ;
mov PBS0,a
mov a,20H
mov ADCR0,a ;
:
start_conversion:
clr START ;
set START ;
clr START ;
:
polling_EOC:
sz ADBZ ;
jmp polling_EOC ;
:
mov a,ADRL ;
mov ADRL_buffer,a ;
mov a,ADRH ;
mov ADRH_buffer,a ;
:
jmp start_conversion ;
Rev. 1.20
disable ADC interrupt
deselect the temperature sensor reference voltage
select fSYS/8 as A/D clock and A/D internal power supply
as reference voltage
setup PBS0 to configure pin AN0
enable and connect AN0 channel to A/D converter
high pulse on start bit to initiate conversion
reset A/D
start A/D
poll the ADCR0 register ADBZ bit to detect end of A/D conversion
continue polling
read
save
read
save
low byte conversion result value
result to user defined register
high byte conversion result value
result to user defined register
start next A/D conversion
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Example: using the interrupt method to detect the end of conversion
clr ADE;
set VREFP_EXT ;
mov a,03H;
mov ADCR1,a ;
set ADCEN
mov a,03H ;
mov PBS0,a
mov a,20H
mov ADCR0,a ;
:
Start_conversion:
clr START ;
set START ;
clr START ;
clr ADF ;
set ADE;
set EMI ;
:
:
ADC_ISR: ;
mov acc_stack,a ;
mov a,STATUS
mov status_stack,a ;
:
mov a, ADRL ;
mov ADRL_buffer,a ;
mov a, ADRH ;
mov ADRH_buffer,a ;
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ;
mov a,acc_stack ;
reti
Rev. 1.20
disable ADC interrupt
deselect the temperature sensor reference voltage
select fSYS/8 as A/D clock and A/D internal power supply
as reference voltage
setup PBS0 to configure pin AN0
enable and connect AN0 channel to A/D converter
high pulse on START bit to initiate conversion
reset A/D
start A/D
clear ADC interrupt request flag
enable ADC interrupt
enable global interrupt
ADC interrupt service routine
save ACC to user defined memory
save STATUS to user defined memory
read
save
read
save
low byte conversion result value
result to user defined register
high byte conversion result value
result to user defined register
restore STATUS from user defined memory
restore ACC from user defined memory
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Serial Interface Module – SIM
These devices contain a Serial Interface Module, which includes both the four-line SPI interface or
two-line I2C interface types, to allow an easy method of communication with external peripheral
hardware. Having relatively simple communication protocols, these serial interface types allow
the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or
EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the
SIM interface functional pins must first be selected using the corresponding pin-shared function
selection bits. As both interface types share the same pins and registers, the choice of whether the
SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in
the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pullhigh control registers when the SIM function is enabled and the corresponding pins are used as SIM
input pins.
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the devices can be
either master or slave. Although the SPI interface specification can control multiple slave devices
from a single master, these devices provided only one SCS pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pin to select the slave devices.
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data
Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins
are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first
be selected by configuring the pin-shared function selection bits and setting the correct bits in the
SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or
enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected
to the SPI interface is carried out in a slave/master mode with all data transfer initiations being
implemented by the master. The Master also controls the clock signal. As the device only contains
a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set
CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state.
The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN and
SIMEN.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
SPI Master/Slave Connection

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SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These are
the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only
used by the I2C interface.
Bit
Register
Name
7
6
5
4
SIMC0
SIM2
SIM1
SIM0
—
SIMC2
D7
D6
CKPOLB
CKEG
MLS
SIMD
D7
D6
D5
D4
D3
3
2
1
0
SIMEN
SIMICF
CSEN
WCOL
TRF
D2
D1
D0
SIMDEB1 SIMDEB0
SPI Registers List
SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2
register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used
by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable
function and to set the data transmission clock frequency. Register SIMC2 is used for other control
functions such as LSB/MSB selection, write collision flag, etc.
SIMC0 Register
Bit
7
6
5
4
Name
SIM2
SIM1
SIM0
—
3
R/W
R/W
R/W
R/W
—
R/W
POR
1
1
1
—
0
2
1
0
SIMEN
SIMICF
R/W
R/W
R/W
0
0
0
SIMDEB1 SIMDEB0
Bit 7~5SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS /4
001: SPI master mode; SPI clock is fSYS /16
010: SPI master mode; SPI clock is fSYS /64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock but
can also be chosen to be sourced from CTM0. If the SPI Slave Mode is selected then
the clock will be supplied by an external Master device.
Bit 4
Unimplemented, read as “0”
Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection
Described elsewhere.
Bit 1SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I2C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I2C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0SIMICF: SIM SPI slave mode Incomplete Transfer Flag
0: SIM SPI slave mode incomplete condition not occurred
1: SIM SPI slave mode incomplete condition occured
This bit is only available when the SIM is configured to operate in an SPI slave mode.
If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set
to 1 but the SCS line is pulled high by the external master device before the SPI data
transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF
bit. When this condition occurs, the corresponding interrupt will occur if the interrupt
function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set
to 1 by software application program.
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SIMC2 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Undefined bits
These bits can be read or written by the application program.
Bit 5CKPOLB: SPI clock line base condition selection
0: The SCK line will be high when the clock is inactive.
1: The SCK line will be low when the clock is inactive.
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4CKEG: SPI SCK clock active edge type selection
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive. The CKEG bit determines active clock
edge type which depends upon the condition of CKPOLB bit.
Bit 3MLS: SPI data shift order
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Bit 2CSEN: SPI SCS pin control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the
SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the
bit is high, the SCS pin will be enabled and used as a select pin.
Bit 1WCOL: SPI write collision flag
0: No collision
1: Collision
The WCOL flag is used to detect whether a data collision has occurred or not. If this
bit is high, it means that data has been attempted to be written to the SIMD register
duting a data transfer operation. This writing operation will be ignored if data is being
transferred. This bit can be cleared by the application program.
Bit 0TRF: SPI Transmit/Receive complete flag
0: SPI data is being transferred
1: SPI data transfer is completed
The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when
an SPI data transfer is completed, but must cleared to 0 by the application program. It
can be used to generate an interrupt.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the TRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into
the SIMD register. The master should output a SCS signal to enable the slave devices before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG
bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal
for various configurations of the CKPOLB and CKEG bits.
The SPI will continue to function even in the IDLE Mode.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Master/Slave Bus Connection
I2C interface Operation
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I2C bus is identified by a unique address which
will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For these devices, which only
operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
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The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses
the system clock to in effect add a debounce time to the external clock to reduce the possibility
of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be
chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there
exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C
Standard or Fast mode operation, users must take care of the selected system clock frequency and
the configured debounce time to match the criterion shown in the following table.
I2C Debounce Time Selection
I2C Standard Mode (100kHz)
I2C Fast Mode (400kHz)
No Devounce
fSYS > 2 MHz
fSYS > 5 MHz
2 system clock debounce
fSYS > 4 MHz
fSYS > 10 MHz
4 system clock debounce
fSYS > 8 MHz
fSYS > 20 MHz
I C Minimum fSYS Frequency
2
I2C Registers
There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA, and one
data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store
the data being transmitted and received on the I2C bus. Before the microcontroller writes data to
the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is
received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission
or reception of data from the I2C bus must be made via the SIMD register.
Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN
and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface.
Bit
Register
Name
7
SIMC0
SIMC1
6
5
SIM2
SIM1
SIM0
—
HCF
HAAS
HBB
HTX
TXAK
SRW
SIMA
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
D0
SIMD
D7
D6
D5
D4
D3
D2
D1
D0
SIMTOC
4
3
2
SIMDEB1 SIMDEB0
1
0
SIMEN
SIMICF
IAMWU
RXAK
SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
I2C Registers List
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the
device can read it from the SIMD register. Any transmission or reception of data from the I2C bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
SIMA Register
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is
the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register
define the device slave address. Bit 0 is not defined.
When a master device, which is connected to the I2C bus, sends out an address, which matches the
slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is
the same register address as SIMC2 which is used by the SPI interface.
Bit
7
6
5
4
3
2
1
0
Name
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
Bit 7~1IICA6~IICA0: I2C slave address
IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0
Bit 0
Undefined bit
The bit can be read or written by the application program.
There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0
is used to control the enable/disable function and to set the data transmission clock frequency.The
SIMC1 register contains the relevant flags which are used to indicate the I2C communication status.
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SIMC0 Register
Bit
7
6
5
4
Name
SIM2
SIM1
SIM0
—
3
R/W
R/W
R/W
R/W
—
R/W
POR
1
1
1
—
0
2
1
0
SIMEN
SIMICF
R/W
R/W
R/W
0
0
0
SIMDEB1 SIMDEB0
Bit 7~5SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS /4
001: SPI master mode; SPI clock is fSYS /16
010: SPI master mode; SPI clock is fSYS /64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock but
can also be chosen to be sourced from TM0. If the SPI Slave Mode is selected then the
clock will be supplied by an external Master device.
Bit 4
Unimplemented, read as “0”
Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection
00: No debounce
01: 2 system clock debounce
1x: 4 system clock debounce
Bit 1SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I2C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I2C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0SIMICF: SIM SPI slave mode Incomplete Transfer Flag
Described elsewhere.
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SIMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
HCF
HAAS
HBB
HTX
TXAK
SRW
IAMWU
RXAK
R/W
R
R
R
R/W
R/W
R/W
R/W
R
POR
1
0
0
0
0
0
0
1
Bit 7HCF: I C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
2
Bit 6HAAS: I2C Bus data transfer completion flag
0: Not address match
1: Address match
The HAAS flag is the address match flag. This flag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match then
this bit will be high, if there is no match then the flag will be low.
Bit 5HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy
which will occur when a START signal is detected. The flag will be set to “0” when
the bus is free which will occur when a STOP signal is detected.
Bit 4HTX: I2C slave device transmitter/receiver selection
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3TXAK: I2C bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave does not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits
of data, this bit will be transmitted to the bus on the 9th clock from the slave device.
The slave device must always set TXAK bit to “0” before further data is received.
Bit 2SRW: I2C slave read/write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus. When the
transmitted address and slave address is match, that is when the HAAS flag is set high,
the slave device will check the SRW flag to determine whether it should be in transmit
mode or receive mode. If the SRW flag is high, the master is requesting to read data
from the bus, so the slave device should be in transmit mode. When the SRW flag
is zero, the master will write data to the bus, therefore the slave device should be in
receive mode to read this data.
Bit 1IAMWU: I2C Address Match Wake-Up control
0: Disable
1: Enable – must be cleared by the application program after wake-up
This bit should be set to 1 to enable the I2C address match wake up from the SLEEP
or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or
IDLE mode to enable the I2C address match wake up, then this bit must be cleared by
the application program after wake-up to ensure correction device operation.
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Bit 0RXAK: I2C bus receive acknowledge flag
0: Slave receives acknowledge flag
1: Slave does not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it
means that a acknowledge signal has been received at the 9th clock, after 8 bits of data
have been transmitted. When the slave device in the transmit mode, the slave device
checks the RXAK flag to determine if the master receiver wishes to receive the next
byte. The slave transmitter will therefore continue sending out data until the RXAK
flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow
the master to send a STOP signal to release the I2C Bus.
I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of
data on the bus. The first seven bits of the data will be the slave address with the first bit being the
MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the
SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service
routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine
whether the interrupt source originates from an address match, 8-bit data transfer completion or
I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been
transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in
the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or
receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise
the bus, the following are steps to achieve this:
• Step 1
Set the SIM2~SIM0 bits to “110” and SIMEN bit to “1” in the SIMC0 register to enable the I2C
bus.
• Step 2
Write the slave address of the device to the I2C bus address register SIMA.
• Step 3
Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to
enable the SIM interrupt and Multi-function interrupt.
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I2C Bus Initialisation Flow Chart
I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the slave device. This START signal will be detected by all devices connected to the I2C bus. When
detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
I2C Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the
read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then
transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the
status flag HAAS when the addresses match.
As an I2C bus interrupt can come from three sources, when the program enters the interrupt
subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source has
come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out
occurrence. When a slave address is matched, the devices must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a dummy
read from the SIMD register to release the SCL line.
I2C Bus Read/Write Signal
The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the
I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to
be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes
to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as
a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I2C
bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
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I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. The
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the HAAS flag is high, the addresses have matched and the slave
device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag
is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register
should be set to “1”. If the SRW flag is low, then the microcontroller slave device should be setup as
a receiver and the HTX bit in the SIMC1 register should be set to “0”.
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before
it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master
to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD
register. If setup as a transmitter, the slave device must first write the data to be transmitted into the
SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD
register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the SIMC1 register to determine if it is to send another data byte, if not then it will release the
SDA line and await the receipt of a STOP signal from the master.
€

€

­
         ­ Note: *When a slave address is matched, the devices must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a
dummy read from the SIMD register to release the SCL line.
I2C Communication Timing Diagram
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     
            I2C Bus ISR Flow Chart
I2C Time-out Control
In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out
function is provided. If the clock source connected to the I2C bus is not received for a while, then the
I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to
count on an I2C bus “START” & “address match”condition, and is cleared by an SCL falling edge.
Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period
specified by the SIMTOC register, then a time-out condition will occur. The time-out function will
stop when an I2C “STOP” condition occurs.
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S ta rt
S C L
S R W
S la v e A d d r e s s
0
1
S D A
1
1
0
1
0
A C K
1
0
I2 C t i m e - o u t
c o u n te r s ta rt
S to p
S C L
1
0
0
1
0
1
0
0
S D A
I2 C t im e - o u t c o u n t e r r e s e t
o n S C L n e g a tiv e tr a n s itio n
I2C Time-out
When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will
be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has
occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector.
When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset
into the following condition:
Register
After I2C Time-out
SIMD, SIMA, SIMC0
No change
SIMC1
Reset to POR condition
I C Register after Time-out
2
The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections
which can be selected using the SIMTOS bits in the SIMTOC register. The time-out duration is
calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from
about 1ms to 64ms.
SIMTOC Register
Bit
Name
7
6
5
4
3
2
1
0
SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7SIMTOEN: SIM I C Time-out control
0: Disable
1: Enable
2
Bit 6SIMTOF: SIM I2C Time-out flag
0: No time-out occurred
1: Time-out occurred
Bit 5~0SIMTOS5~SIMTOS0: SIM I2C Time-out period selection
I2C Time-out clock source is fSUB/32
32
I2C Time-out period is equal to (SIMTOS [5:0] + 1) ×
fSUB
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UART Interface
These devices contain an integrated full-duplex asynchronous serial communications UART
interface that enables communication with external devices that contain a serial interface. The
UART function has many features and can transmit and receive data serially by transferring a frame
of data with eight or nine data bits per transmission as well as being able to detect errors when the
data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt
which can be used to indicate when a reception occurs or when a transmission terminates.
The integrated UART function contains the following features:
• Full-duplex, asynchronous communication
• 8 or 9 bits character length
• Even, odd or no parity options
• One or two stop bits
• Baud rate generator with 8-bit prescaler
• Parity, framing, noise and overrun error detection
• Support for interrupt on address detect (last character bit=1)
• Separately enabled transmitter and receiver
• 2-byte Deep FIFO Receive Data Buffer
• RX pin wake-up function
• Transmit and receive interrupts
• Interrupts can be initialized by the following conditions:
♦♦
Transmitter Empty
♦♦
Transmitter Idle
♦♦
Receiver Full
♦♦
Receiver Overrun
♦♦
Address Mode Detect
Transmitter Shift Register (TSR)
�SB ………………………… LSB
TX Pin
TX Register (TXR)
RX Pin
Receiver Shift Register (RSR)
�SB ………………………… LSB
RX Register (RXR)
Buffer
Baud Rate
Generator
fSYS
Data to be transmitted
Data received
�CU Data Bus
UART Data Transfer Block Diagram
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UART External Pin
To communicate with an external serial interface, the internal UART has two external pins known
as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The
TX and RX pin function should first be selected by the corresponding pin-shared function selection
register before the UART function is used. Along with the UARTEN bit, the TXEN and RXEN bits,
if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX
output and RX input conditions and disable any pull-high resistor option which may exist on the
TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TXEN or
RXEN bit, the TX or RX pin will be set to a floating state. At this time whether the internal pullhigh resistor is connected to the TX or RX pin or not is determined by the corresponding I/O pullhigh function control bit.
UART Data Transfer Scheme
The above diagram shows the overall data transfer structure arrangement for the UART interface.
The actual data to be transmitted from the MCU is first transferred to the TXR register by the
application program. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only
the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped
and is therefore inaccessible to the application program.
Data to be received by the UART is accepted on the external RX pin, from where it is shifted in,
LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When
the shift register is full, the data will then be transferred from the shift register to the internal RXR
register, where it is buffered and can be manipulated by the application program. Only the TXR
register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is
therefore inaccessible to the application program.
It should be noted that the actual register for data transmission and reception, although referred to
in the text, and in application programs, as separate TXR and RXR registers, only exists as a single
shared register in the Data Memory. This shared register known as the TXR_RXR register is used
for both data transmission and data reception.
UART Status and Control Registers
There are five control registers associated with the UART function. The USR, UCR1 and UCR2
registers control the overall function of the UART, while the BRG register controls the Baud rate.
The actual data to be transmitted and received on the serial interface is managed through the TXR_
RXR data registers.
TXR_RXR Register
The TXR_RXR register is the data register which is used to store the data to be transmitted on the
TX pin or being received from the RX pin.
Bit
7
6
5
4
3
2
1
0
Name
TXRX7
TXRX6
TXRX5
TXRX4
TXRX3
TXRX2
TXRX1
TXRX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bits
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
USR Register
The USR register is the status register for the UART, which can be read by the program to
determine the present status of the UART. All flags within the USR register are read only and further
explanations are given below.
Bit
7
6
5
4
3
2
1
0
Name
PERR
NF
FERR
OERR
RIDLE
RXIF
TIDLE
TXIF
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
1
0
1
1
Bit 7PERR: Parity error flag
0: No parity error is detected
1: Parity error is detected
The PERR flag is the parity error flag. When this read only flag is “0”, it indicates a
parity error has not been detected. When the flag is “1”, it indicates that the parity of
the received word is incorrect. This error flag is applicable only if Parity mode (odd or
even) is selected. The flag can also be cleared by a software sequence which involves
a read to the status register USR followed by an access to the RXR data register.
Bit 6NF: Noise flag
0: No noise is detected
1: Noise is detected
The NF flag is the noise flag. When this read only flag is “0”, it indicates no noise
condition. When the flag is “1”, it indicates that the UART has detected noise on the
receiver input. The NF flag is set during the same cycle as the RXIF flag but will not
be set in the case of as overrun. The NF flag can be cleared by a software sequence
which will involve a read to the status register USR followed by an access to the RXR
data register.
Bit 5FERR: Framing error flag
0: No framing error is detected
1: Framing error is detected
The FERR flag is the framing error flag. When this read only flag is “0”, it indicates
that there is no framing error. When the flag is “1”, it indicates that a framing error
has been detected for the current character. The flag can also be cleared by a software
sequence which will involve a read to the status register USR followed by an access to
the RXR data register.
Bit 4OERR: Overrun error flag
0: No overrun error is detected
1: Overrun error is detected
The OERR flag is the overrun error flag which indicates when the receiver buffer has
overflowed. When this read only flag is “0”, it indicates that there is no overrun error.
When the flag is “1”, it indicates that an overrun error occurs which will inhibit further
transfers to the RXR receive data register. The flag is cleared by a software sequence,
which is a read to the status register USR followed by an access to the RXR data
register.
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Bit 3RIDLE: Receiver status
0: data reception is in progress (data being received)
1: no data reception is in progress (receiver is idle)
The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates
that the receiver is between the initial detection of the start bit and the completion of
the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the
completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1”
indicating that the UART receiver is idle and the RX pin stays in logic high condition.
Bit 2RXIF: Receive RXR data register status
0: RXR data register is empty
1: RXR data register has available data
The RXIF flag is the receive data register status flag. When this read only flag is “0”,
it indicates that the RXR read data register is empty. When the flag is “1”, it indicates
that the RXR read data register contains new data. When the contents of the shift
register are transferred to the RXR register, an interrupt is generated if RIE=1 in the
UCR2 register. If one or more errors are detected in the received word, the appropriate
receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The
RXIF flag is cleared when the USR register is read with RXIF set, followed by a read
from the RXR register, and if the RXR register has no data available.
Bit 1TIDLE: Transmission status
0: data transmission is in progress (data being transmitted)
1: no data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only
flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1”
when the TXIF flag is “1” and when there is no transmit data or break character being
transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state
in logic high condition. The TIDLE flag is cleared by reading the USR register with
TIDLE set and then writing to the TXR register. The flag is not generated when a data
character or a break is queued and ready to be sent.
Bit 0TXIF: Transmit TXR data register status
0: character is not transferred to the transmit shift register
1: character has transferred to the transmit shift register (TXR data register is empty)
The TXIF flag is the transmit data register empty flag. When this read only flag is “0”,
it indicates that the character is not transferred to the transmitter shift register. When
the flag is “1”, it indicates that the transmitter shift register has received a character
from the TXR data register. The TXIF flag is cleared by reading the UART status
register (USR) with TXIF set and then writing to the TXR data register. Note that
when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data
register is not yet full.
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UCR1 Register
The UCR1 register together with the UCR2 register are the UART control registers that are used
to set the various options for the UART function such as overall on/off control, parity control, data
transfer bit length, etc. Further explanation on each of the bits is given below.
Bit
7
6
5
4
3
2
1
0
Name
UARTEN
BNO
PREN
PRT
STOPS
TXBRK
RX8
TX8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
POR
0
0
0
0
0
0
x
0
“x”: unknown
Bit 7UARTEN: UART function enable control
0: Disable UART; TX and RX pins are in a floating state.
1: Enable UART; TX and RX pins function as UART pins
The UARTEN bit is the UART enable bit. When this bit is equal to “0”, the UART
will be disabled and the RX pin as well as the TX pin will be set in a floating state.
When the bit is equal to “1”, the UART will be enabled and the TX and RX pins will
function as defined by the TXEN and RXEN enable control bits. When the UART
is disabled, it will empty the buffer so any character remaining in the buffer will be
discarded. In addition, the value of the baud rate counter will be reset. If the UART
is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK,
RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and
RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will
remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending
transmissions and receptions will be terminated and the module will be reset as defined
above. When the UART is re-enabled, it will restart in the same configuration.
Bit 6BNO: Number of data transfer bits selection
0: 8-bit data transfer
1: 9-bit data transfer
This bit is used to select the data length format, which can have a choice of either
8-bit or 9-bit format. When this bit is equal to “1”, a 9-bit data length format will be
selected. If the bit is equal to “0”, then an 8-bit data length format will be selected. If
9-bit data length format is selected, then bits RX8 and TX8 will be used to store the
9th bit of the received and transmitted data respectively.
Bit 5PREN: Parity function enable control
0: Parity function is disabled
1: Parity function is enabled
This bit is the parity function enable bit. When this bit is equal to 1, the parity function
will be enabled. If the bit is equal to 0, then the parity function will be disabled.
Bit 4PRT: Parity type selection bit
0: Even parity for parity generator
1: Odd parity for parity generator
This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will
be selected. If the bit is equal to 0, then even parity type will be selected.
Bit 3STOPS: Number of stop bits selection
0: One stop bit format is used
1: Two stop bits format is used
This bit determines if one or two stop bits are to be used. When this bit is equal to “1”,
two stop bits format are used. If the bit is equal to “0”, then only one stop bit format is
used.
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Bit 2TXBRK: Transmit break character
0: No break character is transmitted
1: Break characters transmit
The TXBRK bit is the Transmit Break Character bit. When this bit is equal to “0”,
there are no break characters and the TX pin operats normally. When the bit is equal to
“1”, there are transmit break characters and the transmitter will send logic zeros. When
this bit is equal to “1”, after the buffered data has been transmitted, the transmitter
output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset.
Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only)
This bit is only used if 9-bit data transfers are used, in which case this bit location will
store the 9th bit of the received data known as RX8. The BNO bit is used to determine
whether data transfes are in 8-bit or 9-bit format.
Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only)
This bit is only used if 9-bit data transfers are used, in which case this bit location
will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to
determine whether data transfes are in 8-bit or 9-bit format.
UCR2 Register
The UCR2 register is the second of the UART control registers and serves several purposes. One
of its main functions is to control the basic enable/disable operation if the UART Transmitter and
Receiver as well as enabling the various UART interrupt sources. The register also serves to control
the baud rate speed, receiver wake-up function enable and the address detect function enable.
Further explanation on each of the bits is given below.
Bit
7
6
5
4
3
2
1
0
Name
TXEN
RXEN
BRGH
ADDEN
WAKE
RIE
TIIE
TEIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7TXEN: UART Transmitter enable control
0: UART Transmitter is disabled
1: UART Transmitter is enabled
The TXEN bit is the Transmitter Enable Bit. When this bit is equal to “0”, the
transmitter will be disabled with any pending data transmissions being aborted. In
addition the buffers will be reset. In this situation the TX pin will be set in a floating
state. If the TXEN bit is equal to “1” and the UARTEN bit is also equal to 1, the
transmitter will be enabled and the TX pin will be controlled by the UART. Clearing
the TXEN bit during a transmission will cause the data transmission to be aborted and
will reset the transmitter. If this situation occurs, the TX pin will be set in a floating
state.
Bit 6RXEN: UART Receiver enable control
0: UART Receiver is disabled
1: UART Receiver is enabled
The RXEN bit is the Receiver Enable Bit. When this bit is equal to “0”, the receiver
will be disabled with any pending data receptions being aborted. In addition the
receiver buffers will be reset. In this situation the RX pin will be set in a floating state.
If the RXEN bit is equal to “1” and the UARTEN bit is also equal to 1, the receiver
will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN
bit during a reception will cause the data reception to be aborted and will reset the
receiver. If this situation occurs, the RX pin will be set in a floating state.
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Bit 5BRGH: Baud Rate speed selection
0: Low speed baud rate
1: High speed baud rate
The bit named BRGH selects the high or low speed mode of the Baud Rate Generator.
This bit, together with the value placed in the baud rate register, BRG, controls the
baud rate of the UART. If the bit is equal to 0, the low speed mode is selected.
Bit 4ADDEN: Address detect function enable control
0: Address detection function is disabled
1: Address detection function is enabled
The bit named ADDEN is the address detection function enable control bit. When this
bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th
bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8
if BNO=1, has a value of “1”, then the received word will be identified as an address,
rather than data. If the corresponding interrupt is enabled, an interrupt request will be
generated each time the received word has the address bit set, which is the 8th or 9th
bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th
bit of the received word is “0” with the address detection function being enabled, an
interrupt will not be generated and the received data will be discarded.
Bit 3WAKE: RX pin falling edge wake-up function enable control
0: RX pin wake-up function is disabled
1: RX pin wake-up function is enabled
The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and
the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the
device. If this bit is equal to 0 and the device is in IDLE or SLEEP mode, any edge
transitions on the RX pin will not wake up the device.
Bit 2RIE: Receiver interrupt enable control
0: Receiver related interrupt is disabled
1: Receiver related interrupt is enabled
The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the
receiver overrun flag OERR or received data available flag RXIF is set, the UART
interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request
flag will not be influenced by the condition of the OERR or RXIF flags.
Bit 1TIIE: Transmitter Idle interrupt enable control
0: Transmitter idle interrupt is disabled
1: Transmitter idle interrupt is enabled
The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and
when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the
UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt
request flag will not be influenced by the condition of the TIDLE flag.
Bit 0TEIE: Transmitter Empty interrupt enable control
0: Transmitter empty interrupt is disabled
1: Transmitter empty interrupt is enabled
The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and
when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the
UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt
request flag will not be influenced by the condition of the TXIF flag.
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Baud Rate Generator
To setup the speed of the serial data communication, the UART function contains its own dedicated
baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the
period of which is determined by two factors. The first of these is the value placed in the BRG
register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH
bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which
in turn determines the formula that is used to calculate the baud rate. The value in the BRG register,
N, which is used in the following baud rate calculation formula determines the division factor. Note
that N is the decimal value placed in the BRG register and has a range of between 0 and 255.
UCR2 BRGH Bit
0
1
Baud Rate (BR)
fSYS
[64(N+1)]
fSYS
[16(N+1)]
By programming the BRGH bit which allows selection of the related formula and programming the
required value in the BRG register, the required baud rate can be setup. Note that because the actual
baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error
associated between the actual and requested value. The following example shows how the BRG
register value N and the error value can be calculated.
BRG Register
Bit
7
6
5
4
3
2
1
0
Name
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
Bit 7~0BRG7~BRG0: Baud Rate values
By programming the BRGH bit in the UCR2 register which allows selection of the
related formula described above and programming the required value in the BRG
register, the required baud rate can be setup.
Calculating the Baud Rate and Error Values
For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the
actual baud rate and the error value for a desired baud rate of 4800.
fSYS
[64(N+1)]
From the above table the desired baud rate BR=
Re-arranging this equation gives N=
fSYS
(BR×64)
-1
4000000
Giving a value for N=
-1=12.0208
(4800×64)
To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives
4000000
an actual or calculated baud rate value of BR=
=4808
[64(12+1)]
4808-4800
Therefore the error is equal to
=0.16%
4800
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
UART Setup and Control
For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ,
format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity
is supported by the UART hardware and can be setup to be even, odd or no parity. For the most
common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used
as the default setting, which is the setting at power-on. The number of data bits and stop bits, along
with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in
the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit
baud rate generator, while the data is transmitted and received LSB first. Although the transmitter
and receiver of the UART are functionally independent, they both use the same data format and baud
rate. In all cases stop bits will be used for data transmission.
Enabling/Disabling the UART Interface
The basic on/off function of the internal UART function is controlled using the UARTEN bit in the
UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act
as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX
pin, then it will default to a logic high value.
Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be in a floating
state. When the UART function is disabled, the buffer will be reset to an empty condition, at the
same time discarding any remaining residual data. Disabling the UART will also reset the enable
control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR
and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits
in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1
register is cleared while the UART is active, then all pending transmissions and receptions will be
immediately suspended and the UART will be reset to a condition as defined above. If the UART is
then subsequently re-enabled, it will restart again in the same configuration.
Data, Parity and Stop Bit Selection
The format of the data to be transferred is composed of various factors such as data bit length,
parity on/off, parity type, address bits and the number of stop bits. These factors are determined by
the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits
which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN
bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to
be used. The following table shows various formats for data transmission. The address detect mode
control bit identifies the frame as an address character. The number of stop bits, which can be either
one or two, is independent of the data length.
Start Bit
Data Bits
Address Bits
Parity Bit
Stop Bit
Example of 8-bit Data Formats
1
8
0
0
1
1
7
0
1
1
1
7
1
0
1
Example of 9-bit Data Formats
1
9
0
0
1
1
8
0
1
1
1
8
1
0
1
Transmitter Receiver Data Format
The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data
formats.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
UART Transmitter
Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1
register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which
is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the
Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the
transmit data register, which is known as the TXR register. The data to be transmitted is loaded
into this TXR register by the application program. The TSR register is not written to with new data
until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been
transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It
should be noted that the TSR register, unlike many other registers, is not directly mapped into the
Data Memory area and as such is not available to the application program for direct read/write
operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but
the data will not be transmitted until the TXR register has been loaded with data and the baud rate
generator has defined a shift clock source. However, the transmission can also be initiated by first
loading data into the TXR register, after which the TXEN bit can be set. When a transmission of
data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in
an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission
will immediately cease and the transmitter will be reset. The TX output pin will be in a floating
state.
Transmitting Data
When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with
the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the
internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been
selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a
data transfer can be summarized as follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a
UART transmitter pin.
• Access the USR register and write the data that is to be transmitted into the TXR register. Note
that this step will clear the TXIF bit.
This sequence of events can now be repeated to send additional data. It should be noted that when
TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is
always achieved using the following software sequence:
1. A USR register access
2. A TXR register write execution
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is
empty and that other data can now be written into the TXR register without overwriting the previous
data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission,
a write instruction to the TXR register will place the data into the TXR register, which will be
copied to the shift register at the end of the present transmission. When there is no data transmission
in progress, a write instruction to the TXR register will place the data directly into the shift register,
resulting in the commencement of data transmission, and the TXIF bit being immediately set. When
a frame transmission is complete, which happens after stop bits are sent or after the break frame, the
TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used:
1. A USR register access
2. A TXR register write execution
Note that both the TXIF and TIDLE bits are cleared by the same software sequence.
Transmitting Break
If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break
character transmission consists of a start bit, followed by 13xN “0” bits, where N=1, 2, etc. If a
break character is to be transmitted, then the TXBRK bit must be first set by the application program
and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually
kept at a logic high level, then the transmitter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the
last break character and subsequently send out one or two stop bits. The automatic logic high at the
end of the last break character will ensure that the start bit of the next frame is recognized.
UART Receiver
The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming
the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In
this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the
receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which
is received on the RX external input pin is sent to the data recovery block. The data recovery block
operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the
baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the
receive data register, if the register is empty. The data which is received on the external RX input pin
is sampled three times by a majority detect circuit to determine the logic level that has been placed
onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly
mapped into the Data Memory area and as such is not available to the application program for direct
read/write operations.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep
FIFO data buffer, where two bytes can be held in the FIFO while the 3rd byte can continue to be
received. Note that the application program must ensure that the data is read from RXR before the
3rd byte has been completely shifted in, otherwise the 3rd byte will be discarded and an overrun error
OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as
follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART
receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received, the following sequence of events will occur:
• The RXIF bit in the USR register will be set then RXR register has data available, at least one
more character can be read.
• When the contents of the shift register have been transferred to the RXR register and if the RIE
bit is set, then an interrupt will be generated.
• If during reception, a frame error, noise error, parity error or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
1. A USR register access
2. A RXR register read execution
Receiving Break
Any break character received by the UART will be managed as a framing error. The receiver will
count and expect a certain number of bit times as specified by the values programmed into the BNO
and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as
complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR
is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the
RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit,
the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid
stop bit before looking for the next start bit. The receiver will not make the assumption that the
break condition on the line is the next start bit. A break is regarded as a character that contains only
zeros with the FERR flag set. The break character will be loaded into the buffer and no further data
will be received until stop bits are received. It should be noted that the RIDLE read only flag will go
high when the stop bits have not yet been received. The reception of a break character on the UART
registers will result in the following:
• The framing error flag, FERR, will be set.
• The receive data register, RXR, will be cleared.
• The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit and
the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE
flag, will have a zero value. In between the reception of a stop bit and the detection of the next start
bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
Receiver Interrupt
The read only receive interrupt flag, RXIF, in the USR register is set by an edge generated by the
receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift
Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if
RIE=1.
Managing Receiver Errors
Several types of reception errors can occur within the UART module, the following section describes
the various types and how they are managed by the UART.
Overrun Error – OERR
The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in
the FIFO register, while a 3th byte can continue to be received. Before the 3th byte has been entirely
shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag
OERR will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
• The OERR flag in the USR register will be set.
• The RXR contents will not be lost.
• The shift register will be overwritten.
• An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the USR register followed by a read to the RXR
register.
Noise Error – NF
Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is
detected within a frame, the following will occur:
• The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit.
• Data will be transferred from the shift register to the RXR register.
• No interrupt will be generated. However this bit rises at the same time as the RXIF bit which
itself generates an interrupt.
Note that the NF flag is reset by a USR register read operation followed by an RXR register read
operation.
Framing Error – FERR
The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of
stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERR flag will be
set. The FERR flag is buffered along with the received data and is cleared in any reset.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Parity Error – PERR
The read only parity error flag, PERR, in the USR register, is set if the parity of the received word
is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the
parity type, odd or even, is selected. The read only PERR flag is buffered along with the received
data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buffered
along with the corresponding word and should be read before reading the data word.
UART Interrupt Structure
Several individual UART conditions can generate a UART interrupt. When these conditions exist,
a low pulse will be generated to get the attention of the microcontroller. These conditions are a
transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address
detect and an RX pin wake-up. When any of these conditions are created, if its corresponding
interrupt control is enabled and the stack is not full, the program will jump to its corresponding
interrupt vector where it can be serviced before returning to the main program. Four of these
conditions have the corresponding USR register flags which will generate a UART interrupt if its
associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable control bits, while the two receiver interrupt
conditions have a shared enable control bit. These enable bits can be used to mask out individual
UART interrupt sources.
The address detect condition, which is also a UART interrupt source, does not have an associated
flag, but will generate a UART interrupt when an address detect condition occurs if its function
is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a
UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the
microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin, if the
WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt
occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for
the oscillator to restart and stabilize before the system resumes normal operation.
Note that the USR register flags are read only and cannot be cleared or set by the application
program, neither will they be cleared when the program jumps to the corresponding interrupt
servicing routine, as is the case for some of the other interrupts. The flags will be cleared
automatically when certain actions are taken by the UART, the details of which are given in the
UART register section. The overall UART interrupt can be disabled or enabled by the related
interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether
the interrupt requested by the UART module is masked out or allowed.
USR Register
UCR2 Register
Transmitter Empt� Flag
TXIF
TEIE
Transmitter Idle Flag
TIDLE
TIIE
1
RIE
OR
Receiver Data Available
RXIF
WAKE
0
1
Receiver Overrun Flag
OERR
RX Pin
Wake-up
0
ADDEN
URE
0
1
EMI
0
1
Interrupt signal
to �CU
1
0
1
0
0
UART Interrupt
Request Flag
URF
0
1
RX7 if BNO=0
RX8 if BNO=1
1
UCR2 Register
UART Interrupt Structure
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Address Detect Mode
Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this
special function. If this bit is set to 1, then an additional qualifier will be placed on the generation
of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit
is equal to 1, then when the data is available, an interrupt will only be generated, if the highest
received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the
microcontroller must also be enabled for correct interrupt generation. The highest address bit is the
9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received
word will be defined as an address rather than data. A Data Available interrupt will be generated
every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive
Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last
but status. The address detection and parity functions are mutually exclusive functions. Therefore, if
the address detect function is enabled, then to ensure correct operation, the parity function should be
disabled by resetting the parity function enable bit PREN to zero.
ADDEN
0
1
Bit 9 if BNO=1
Bit 8 if BNO=0
UART Interrupt Generated
0
√
1
√
0
X
1
√
ADDEN Bit Function
UART Power Down and Wake-up
When the MCU system clock is switched off, the UART will cease to function. If the MCU executes
the “HALT” instruction and switches off the system clock while a transmission is still in progress,
then the transmission will be paused until the UART clock source derived from the microcontroller
is activated. In a similar way, if the MCU executes the “HALT” instruction and switches off the
system clock while receiving data, then the reception of data will likewise be paused. When the
MCU enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2, transmit and receive
registers, as well as the BRG register will not be affected. It is recommended to make sure first that
the UART data transmission or reception has been finished before the microcontroller enters the
IDLE or SLEEP mode.
The UART function contains a receiver RX pin wake-up function, which is enabled or disabled
by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the
receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the
IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the MCU from the IDLE0
or SLEEP Mode. Note that as it takes certain system clock cycles after a wake-up, before normal
microcontroller operation resumes, any data received during this time on the RX pin will be ignored.
For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global
interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must be set. If the EMI and URE
bits are not set then only a wake up event will occur and no interrupt will be generated. Note also
that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes,
the UART interrupt will not be generated until after this time has elapsed.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCD Driver
For large volume applications, which incorporate an LCD in their design, the use of a custom
display rather than a more expensive character based display reduces costs significantly. However,
the corresponding COM and SEG signals required, which vary in both amplitude and time, to drive
such a custom display require many special considerations for proper LCD operation to occur.
These devices all contain an LCD Driver function, which with their internal LCD signal generating
circuitry and various options, will automatically generate these time and amplitude varying signals
to provide a means of direct driving and easy interfacing to a range of custom LCDs.
Device
Duty
Bias
Bias Type
Wave Type
BS67F340
BS67F350
BS67F360
1/4
1/3
R or C
A or B
LCD Selections
VMAX
0.1uF
V1
C2
VA=V1=3*VIN
Charge
Pump
0.1uF
VB=PLCD=2*VIN
VC=V2=1/3*VIN
V2
V1
VIN
Charge
Pump
VA=V1=VIN
VB=PLCD=2/3*VIN
VB=PLCD=VIN
0.1uF
C2
V1
0.1uF
0.1uF
C1
0.1uF
0.1uF
Charge
Pump
VDD or V1
PLCD
C1
C2
VC=V2=1/2*VIN
VMAX
PLCD
VIN
C1
VA=V1=3/2*VIN
VDD or V1
VMAX
VDD or V1
PLCD
VC=V2=VIN
V2
V2
VIN
0.1uF
0.1uF
Power Suppl� from pin PLCD
Power Suppl� from pin V1
Power Suppl� from pin V2
Note:ThepinVMAXmustbeconnectedtothemaximumvoltagetopreventfromthepadleakage.
C Type Bias External Power Supply Configuration – 1/3 Bias
VMAX
PLCD
V1
VMAX
PLCD
0.1uF
VDD
VIN
VA=V1=VIN
VDD
VIN
VC=V2=1/2*VIN
V2
VA=V1=3*VIN
VB=PLCD=VIN
V1
Charge
Pump
0.1uF
VB=PLCD=2*VIN
V2
VREFIN
VIN
VC=V2=VIN
V2
0.1uF
0.1uF
0.1uF
Power Suppl� from VA
0.1uF
0.1uF
Charge
Pump
0.1uF
C2
V1
VA=V1=3/2*VIN
VDD or V1
C1
C2
0.1uF
VB=PLCD=2/3*VIN
VC=V2=1/3*VIN
PLCD
0.1uF
0.1uF
0.1uF
V1
Charge
Pump
VMAX
C1
C1
C2
V1
Power Suppl� from VB
Power Suppl� from VC
Note:ThepinVMAXmustbeconnectedtothemaximumvoltagetopreventfromthepadleakage.
C Type Bias Internal Power Supply Configuration – 1/3 Bias
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PLCD
VIN
VA control
VA
Quick charging control
QCT
VB
VC
LCDEN
Note: When the R type LCD is disabled� the DC path will be switched.
CO�n
QT
QT: Quick charging time determined b� QCT [2:0]
R Type Bias Configuration – 1/3 Bias
LCD Memory
An area of Data Memory is especially reserved for use for the LCD display data. This data area
is known as the LCD Memory. Any data written here will be automatically read by the internal
display driver circuits, which will in turn automatically generate the necessary LCD driving signals.
Therefore any data written into this Memory will be immediately reflected into the actual display
connected to the microcontroller.
As the LCD Memory addresses overlap those of the General Purpose Data Memory, it is stored in its
own independent Sector 4 area. The Data Memory sector to be used is chosen by using the Memory
Pointer high byte register, which is a special function register in the Data Memory, with the name,
MP1H or MP2H. To access the LCD Memory therefore requires first that Sector 4 is selected by
writing a value of 04H to the MP1H or MP2H register. After this, the memory can then be accessed
by using indirect addressing through the use of Memory Pointer low byte, MP1L or MP2L. With
Sector 4 selected, then using MP1L or MP2L to read or write to the memory area, starting with
address “00H” for all the devices, will result in operations to the LCD Memory. Directly addressing
the LCD Display Memory can be applicable using the extended instructions for the full range
address access.
The accompanying LCD Memory Map diagrams shows how the internal LCD Memory is mapped
to the Segments and Commons of the display for the devices.
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b3 b2 b1 b0
00H
SEG 0
01H
SEG 1
02H
SEG 2
03H
SEG 3
14H
SEG 20
15H
SEG 21
16H
SEG 22
17H
SEG 23
CO� 0
CO� 1
CO� 2
CO� 3
24 SEG x 4 COM
BS67F340 LCD Memory Map
b3 b2 b1 b0
00H
SEG 0
01H
SEG 1
02H
SEG 2
03H
SEG 3
1CH
SEG 28
1DH
SEG 29
1EH
SEG 30
1FH
SEG 31
CO� 0
CO� 1
CO� 2
CO� 3
32 SEG x 4 COM
BS67F350 LCD Memory Map
b3 b2 b1 b0
00H
SEG 0
01H
SEG 1
02H
SEG 2
03H
SEG 3
24H
SEG 36
25H
SEG 37
26H
SEG 38
27H
SEG 39
CO� 0
CO� 1
CO� 2
CO� 3
40 SEG x 4 COM
BS67F360 LCD Memory Map
Rev. 1.20
197
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCD Clock Source
The LCD clock source is the internal clock signal, fSUB, divided by 8 using an internal divider
circuit. The fSUB internal clock is supplied by either the LIRC or LXT oscillator, the choice of which
is determined by a software control bit. For proper LCD operation, this arrangement is provided to
generate an ideal LCD clock source frequency of 4 kHz.
LCD Register
There are control registers, named as LCDC0 and LCDC1, in the Data Memory which is used to
control the various setup features of the LCD Driver.
Various bits in this registers control functions such as LCD wave type, bias type, supply power
selection, total bias resistor selection together with the overall LCD enable and disable control. The
LCDEN bit in the LCDC0 register, which provides the overall LCD enable/disable function, will
only be effective when the device is in the NOAMRL, SLOW or IDLE Mode. If the device is in
the SLEEP Mode then the display will always be disabled. Bits, RSEL2 ~ RSEL0, in the LCDC0
register select the internal total bias resistors to supply the LCD panel with the proper bias current.
A choice to best match the LCD panel used in the application can be selected also to minimise
bias current. The TYPE bit in the LCDC0 register is used to select whether Type A or Type B LCD
waveform signals are used. The RCT bit in the same register is used to select whether R Type or C
Type LCD bias is used. The LCDP1 and LCDP0 bits are used to select that the LCD supply power
comes from either the external pin or internal power supply for C type bias application.
The PLCD3~PLCD0 bits in the LCDC1 register are used to select the VA voltage for R type bias
circuitry. The QCT2~QCT0 bits in the same register are used to determine the quick charge time
period.
Register
Name
Bit
7
6
5
4
3
2
1
0
LCDC0
TYPE
RCT
LCDP1
LCDP0
RSEL2
RSEL1
RSEL0
LCDEN
LCDC1
QCT2
QCT1
QCT0
—
PLCD3
PLCD2
PLCD1
PLCD0
LCD Registers List
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCDC0 Register
Bit
7
6
5
4
3
2
1
0
Name
TYPE
RCT
LCDP1
LCDP0
RSEL2
RSEL1
RSEL0
LCDEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7TYPE: LCD waveform type selection
0: Type A
1: Type B
Bit 6RCT: LCD bias type selection
0: R type
1: C type
Bit 5~4LCDP1~LCDP0: C type bias LCD power supply selection
00: From external pin PLCD, V1 or V2
01: From internal reference voltage VREFIN supplied to VC
10: From internal voltage VDD supplied to VB
11: From internal voltage VDD supplied to VA
The VREFIN is an internal reference voltage with an approximate level of 1.08V.
Bit 3~1RSEL2~RSEL0: R type total bias resistors selection
000: 1170 kΩ
001: 225 kΩ
010: 60 kΩ
011: Quick charging mode – switching between 60 kΩ and 1170 kΩ
1xx: Quick charging mode – switching between 60 kΩ and 225 kΩ
The device provides the low power quick charging mode for R type LCD display. In
quick charging mode the LCD will provide more bias current at the beginning of each
COMn phase as LCD display refreshes and then provide less bias current to reduce the
bias current consumption in the remaining time duration in the same COMn phase.
Bit 0LCDEN: LCD Enable control
0: Disable
1: Enable
In the NORMAL, SLOW or IDLE mode, the LCD on/off function can be controlled
by this bit. However, in the SLEEP mode, the LCD function is always switched off.
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCDC1 Register
Bit
7
6
5
4
3
2
1
0
Name
QCT2
QCT1
QCT0
—
PLCD3
PLCD2
PLCD1
PLCD0
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
POR
0
0
0
—
0
0
0
0
Bit 7~5QCT2~QCT0: R type quick charging time selection
000: 1 tSUB
001: 2 tSUB
010: 3 tSUB
011: 4 tSUB
100: 5 tSUB
101: 6 tSUB
110: 7 tSUB
111: 8 tSUB
The tSUB is the period of the LCD clock source fSUB, i.e., 1/fSUB.
Bit 4
Unimplemented, read as “0”
Bit 3~0PLCD3~PLCD0: R type bias supply voltage selection for VA
0000: 8/16 × PLCD
0001: 9/16 × PLCD
0010: 10/16 × PLCD
0011: 11/16 × PLCD
0100: 12/16 × PLCD
0101: 13/16 × PLCD
0110: 14/16 × PLCD
0111: 15/16 × PLCD
1xxx: PLCD
Note that the VA voltage level has to be equal to or greater than 2.1V.
LCD Voltage Source and Biasing
The time and amplitude varying signals generated by the LCD Driver function require the generation
of several voltage levels for their operation. The devices can have either R type or C type biasing
selected via a software control bit named RCT. Selecting the C type biasing will enable an internal
charge pump circuitry.
R Type Biasing
For R type biasing an external LCD voltage source must be supplied on pin PLCD to generate the
internal biasing voltages. This could be the microcontroller power supply VDD or some other voltage
source equal to or less than VDD. For the R type 1/3 bias scheme, four voltage levels VSS, VA, VB and
VC are utilised. The voltage VA is selected by the PLCD 3~PLCD0 bits to be equal to a specific ratio
of VPLCD varying from 8/16 VPLCD to VPLCD. The voltage VB is equal to VA×2/3 while the voltage VC is
equal to VA×1/3.
Different values of internal bias resistors can be selected using the RSEL2~RESEL0 bits in the
LCDC0 register. This along with the voltage on pin PLCD will determine the bias current. The
VMAX pin should be connected to the VDD pin since the available maximum voltage applied to the
PLCD pin is equal to VDD. Note that no external capacitors or resistors are required to be connected
if R type biasing is used.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
C Type Biasing
For C type biasing the LCD voltage source can be supplied on the external pin PLCD, V1 or V2
or derived from the internal voltage source to generate the required biasing voltages. The C type
bias voltage source is selected using the LCDP1 and LCDP0 bits in the LCDC0 register. The C
type biasing scheme uses an internal charge pump circuit can generate voltages higher than what
is supplied on PLCD or V2. This feature is useful in applications where the microcontroller supply
voltage is less than the supply voltage required by the LCD. Additional charge pump capacitors must
also be connected between pins C1 and C2 to generate the necessary voltage levels.
For C type 1/3 bias external power supply scheme, the LCD power can be supplied on PLCD, V1
or V2 pin. However, the LCD power is internally supplied on VA, VB or VC for C type 1/3 bias
internal power supply scheme. Four internally generated voltage levels VSS, VA, VB and VC are
utilised. These bias voltages have different levels depending upon different LCD power supply
schemes.
LCD Power Supply
External Power Supply
Internal Power Supply
VA voltage
VB voltage
VC voltage
VIN on V1
VIN
2/3 × VIN
1/3 × VIN
VIN on PLCD
3/2 × VIN
VIN
1/2 × VIN
VIN on V2
3 × VIN
2 × VIN
VIN
VDD on VA
VDD
2/3 × VDD
1/3 × VDD
VDD on VB
3/2 × VDD
VDD
1/2 × VDD
VREFIN on VC
3 × VREFIN
2 × VREFIN
VREFIN
C Type Bias Power Supply Scheme
The connection to the VMAX pin depends upon the LCD power supply scheme. It is extremely
important to ensure that these charge pump generated internal voltages do not exceed the maximum
VDD voltage of 5.5V.
Condition
VMAX Connection
VDD > VIN × 1.5
Connect VMAX to VDD
Otherwise
Connect VMAX to V1
C Type Bias VMAX Pin Connection
LCD Reset Function
The LCD has an internal reset function that is an OR function of the inverted LCDEN bit in the
LCDC0 register and the SLEEP function. When the LCDEN bit is set to 1 to enable the LCD driver
function before the device enters the SLEEP mode, the LCD function will be reset after the device
enters the SLEEP mode. Clearing the LCDEN bit to zero will also reset the LCD function.
SLEEP Mode
LCDEN
LCD Reset
COM & SEG Voltage Level
Off
1
No
Normal Operation
Off
0
Yes
Low
On
x
Yes
Low
“x”: Don’t care
LCDReset Function
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCD Driver Output
The number of COM and SEG outputs supplied by the LCD driver, as well as its biasing and wave
type selections, are dependent upon how the LCD control bits are programmed. The Bias Type,
whether C or R type is also selected by a software control bit.
The nature of Liquid Crystal Displays require that only AC voltages can be applied to their pixels
as the application of DC voltages to LCD pixels may cause permanent damage. For this reason the
relative contrast of an LCD display is controlled by the actual RMS voltage applied to each pixel,
which is equal to the RMS value of the voltage on the COM pin minus the voltage applied to the
SEG pin. This differential RMS voltage must be greater than the LCD saturation voltage for the
pixel to be on and less than the threshold voltage for the pixel to be off.
The requirement to limit the DC voltage to zero and to control as many pixels as possible with
a minimum number of connections requires that both a time and amplitude signal is generated
and applied to the application LCD. These time and amplitude varying signals are automatically
generated by the LCD driver circuits in the microcontroller. What is known as the duty determines
the number of common lines used, which are also known as backplanes or COMs. The duty, which
is to have a value of 1/4 and which equates to a COM number of 4, therefore defines the number
of time divisions within each LCD signal frame. Two types of signal generation are also provided,
known as Type A and Type B, the required type is selected via the TYPE bit in the LCDC0 register.
Type B offers lower frequency signals, however, lower frequencies may introduce flickering and
influence display clarity.
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCD Display Off Mode
VA
VB
VC
VSS
CO�0 ~ CO�3
VA
VB
VC
VSS
All sengment outputs
Normal Operation Mode
1 Frame
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
CO�0
CO�1
CO�2
CO�3
All segments are OFF
COM0 side segments are ON
COM1 side segments are ON
COM2 side segments are ON
COM3 side segments are ON
COM0,1 side segments are ON
COM0,2 side segments are ON
COM0,3 side segments are ON
(other combinations are omitted)
VA
VB
VC
VSS
All sengments are ON
LCD Driver Output – Type A, 1/4 duty, 1/3 bias
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCD Display Off Mode
VA
VB
VC
VSS
CO�0 ~ CO�3
VA
VB
VC
VSS
All sengment outputs
Normal Operation Mode
1 Frame
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
VA
VB
VC
VSS
CO�0
CO�1
CO�2
CO�3
All segments are OFF
COM0 side segments are ON
COM1 side segments are ON
COM2 side segments are ON
COM3 side segments are ON
COM0,1 side segments are ON
COM0,2 side segments are ON
COM0,3 side segments are ON
(other combinations are omitted)
VA
VB
VC
VSS
All sengments are ON
LCD Driver Output – Type B, 1/4 duty, 1/3 bias
Rev. 1.20
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Programming Considerations
Certain precautions must be taken when programming the LCD. One of these is to ensure that
the LCD Memory is properly initialised after the microcontroller is powered on. Like the General
Purpose Data Memory, the contents of the LCD Memory are in an unknown condition after power-on.
As the contents of the LCD Memory will be mapped into the actual display, it is important to
initialise this memory area into a known condition soon after applying power to obtain a proper
display pattern.
Consideration must also be given to the capacitive load of the actual LCD used in the application.
As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly
capacitive in nature, it is important that this is not excessive, a point that is particularly true in the
case of the COM lines which may be connected to many LCD pixels. The accompanying diagram
depicts the equivalent circuit of the LCD.
One additional consideration that must be taken into account is what happens when the
microcontroller enters the IDLE or SLOW Mode. The LCDEN control bit in the LCDC0 register
permits the display to be powered off to reduce power consumption. If this bit is zero, the driving
signals to the display will cease, producing a blank display pattern but reducing any power
consumption associated with the LCD.
After Power-on, note that as the LCDEN bit will be cleared to zero, the display function will be
disabled.
LCD Panel Equivalent Circuit
Touch Key Function
Each device provides multiple touch key functions. The touch key function is fully integrated and
requires no external components, allowing touch key functions to be implemented by the simple
manipulation of internal registers.
Touch Key Structure
The touch keys are pin shared with the I/O pins, with the desired function chosen via the pin-shared
selection register bit. Keys are organised into several groups, with each group known as a module
and having a module number, M0 to Mn. Each module is a fully independent set of four Touch Keys
and each Touch Key has its own oscillator. Each module contains its own control logic circuits and
register set. Examination of the register names will reveal the module number it is referring to.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Device
Total Key Number
BS67F360
Touch Key Module
Touch Key
M0
KEY1~KEY4
28
BS67F350
20
BS67F340
16
M1
KEY5~KEY8
M2
KEY9~KEY12
M3
KEY13~KEY16
M4
KEY17~KEY20
M5
KEY21~KEY24
M6
KEY25~KEY28
M0
KEY1~KEY4
M1
KEY5~KEY8
M2
KEY9~KEY12
M3
KEY13~KEY16
M4
KEY17~KEY20
M0
KEY1~KEY4
M1
KEY5~KEY8
M2
KEY9~KEY12
M3
KEY13~KEY16
Touch Key Structure
Ke�
KEY 1
OSC
TKMn16DH / TKMn16DL
( to Data �emor� Sector �)
Ke�
KEY 2
OSC
�ux .
Filter
�ultifrequenc�
16-bit C/F Counter
TKCFOV
Ke�
KEY 3
OSC
MnDFEN
Ke�
KEY 4
OSC
TKMnROH / TKMnROL
( from Data �emor� Sector 6)
TK�nC2
�nTSS
fSYS/4
Reference Oscillator
Filter
TKT�R
�
U
X
8-bit Time Slot Counter
�-bit unit period counter
TKRCOV
�odule 0
�odule n
16-bit C/F Counter
Value
(Sector �)
TKT�R
8-bit Time Slot Counter
Preload Register
fSYS
fSYS/2
fSYS/4
fSYS/8
Reference Osc.
Capacitor Value
(Sector 6)
Overflow
�
U
X
16-bit Counter
TK16OV
TK16DL / TK16DH
TK16S1~
TK16S0
Touch Ke�
Data �emor�
Note: The structure contained in the dash line is identical for each touch key module which contains four touch
keys.
Touch Key Function Block Diagram
Rev. 1.20
206
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Touch Key Register Definition
Each touch key module, which contains four touch key functions, has its own suite registers. The
following table shows the register set for each touch key module. The Mn within the register name
refers to the Touch Key module number. The series of devices has up to seven Touch Key Modules
dependent upon the selected device.
Name
Description
TKTMR
Touch key time slot 8-bit counter proload register
TKC0
Touch key function Control register 0
TKC1
Touch key function Control register 1
TK16DL
Touch key function 16-bit counter low byte
TK16DH
Touch key function 16-bit counter high byte
TKMn16DL
Touch key module n 16-bit C/F counter low byte
TKMn16DH
Touch key module n 16-bit C/F counter high byte
TKMnROL
Touch key module n reference oscillator capacitor select low byte
TKMnROH
Touch key module n reference oscillator capacitor select high byte
TKMnC0
Touch key module n Control register 0
TKMnC1
Touch key module n Control register 1
TKMnC2
Touch key module n Control register 2
Touch Key Module Registers List
Register
Name
TKTMR
TKC0
Bit
7
6
D7
D6
TKRAMC TKRCOV
5
D5
TKST
4
3
2
D4
D3
D2
D1
D0
—
TKMOD
TKBUSY
TKCFOV TK16OV
1
0
TKC1
D7
D6
D5
TSCS
TK16S1
TK16S0
TKFS1
TKFS0
TK16DL
D7
D6
D5
D4
D3
D2
D1
D0
TK16DH
D15
D14
D13
D12
D11
D10
D9
D8
TKMn16DL
D7
D6
D5
D4
D3
D2
D1
D0
TKMn16DH
D15
D14
D13
D12
D11
D10
D9
D8
TKMnROL
D7
D6
D5
D4
D3
D2
D1
D0
TKMnROH
—
—
—
—
—
—
D9
D8
TKMnC0
—
—
MnDFEN
D4
MnROEN MnKOEN MnK4EN MnK3EN MnK2EN MnK1EN
TKMnC1
MnTSS
—
TKMnC2
MnSK31
MnSK30
MnSK21
MnSK20
MnSOFC MnSOF2 MnSOF1 MnSOF0
MnSK11
MnSK10
MnSK01
MnSK00
Touch Key Function Registers List
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TKTMR Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Touch key time slot 8-bit counter proload register
The touch key time slot counter proload register is used to determine the touch key
time slot overflow time. The time slot unit period is obtained by a 5-bit counter and
equal to 32 time slot clock cycles. Therefore, the time slot counter overflow time is
equal to the following equation shown.
Time slot counter overflow time=(256 - TKTMR[7:0]) × 32tTSC, where tTSC is the time
slot counter clock.
TKC0 Register
Bit
Name
7
6
TKRAMC TKRCOV
5
4
3
2
1
0
TKST
TKCFOV
TK16OV
—
TKMOD
TKBUSY
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
POR
0
0
0
0
0
—
0
0
Bit 7TKRAMC: Touch key Data RAM access control
0: Accessed by MCU
1: Accessed by Touch key module
This bit determines that the touch key RAM is used by the MCU or touch key
module. However, the touch key module will have the priority to access the touch
key RAM when the touch key module operates in the auto scan mode, i.e., the TKST
bit state is changed from 0 to 1 when the TKMOD bit is set low. After the touch key
auto scan operation is completed, i.e., the TKBUSY bit state is changed from 1 to 0,
the touch key RAM access will be controlled by the TKRAMC bit. Therefore, it is
recommended to set the TKRAMC bit to 1 when the touch key module operates in the
auto scan mode. Otherwise, the contents of the touch key RAM may be modified as
this RAM space is configured by the touch key module followed by the MCU access.
Bit 6TKRCOV: Touch key time slot counter overflow flag
0: No overflow occurs
1: Overflow occurs
This bit can be accessed by application programs. When this bit is set by touch key
time slot counter overflow, the corrrespondingn touch key interrupt request flag will be
set. However, if this bit is set by application programs, the touch key interrupt request
flag will not be affected.
In auto scan mode, if the time slot counter overflows but the touch key auto scan
operation is not completed, the TKRCOV bit will not be set. At this time, the touch
key module n 16-bit C/F counter, touch key function 16-bit counter and 5-bit time
slot unit period counter will be automatically cleared but the 8-bit time slot counter
will be reloaded from the 8-bit time slot counter preload register. When the touch
key auto scan operation is completed, the TKRCOV bit and the Touch Key Interrupt
request flag, TKMF, will be set and all modules key and reference oscillators will
automatically stop. The touch key modules 16-bit C/F counter, touch key function
16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter will be
automatically switched off.
In manual scan mode, if the time slot counter overflows, the TKRCOV bit and the
Touch Key Interrupt request flag, TKMF, will be set and all modules key and reference
oscillators will automatically stop. The touch key module 16-bit C/F counter, touch
key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot
counter will be automatically switched off.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit 5TKST: Touch key detection Start control
0: Stopped or no operation
0→1: Start detection
In all modules the touch key module 16-bit C/F counter, touch key function 16-bit
counter and 5-bit time slot unit period counter will automatically be cleared when this
bit is cleared to zero. However, the 8-bit programmable time slot counter will not be
cleared. When this bit is changed from low to high, the touch key module 16-bit C/F
counter, touch key function 16-bit counter, 5-bit time slot unie period counter and 8-bit
time slot counter will be switched on together with the key and reference oscillators to
drive the corresponding counters.
Bit 4TKCFOV: Touch key module 16-bit C/F counter overflow flag
0: No overflow occurs
1: Overflow occurs
This bit is set by touch key module 16-bit C/F counter overflow and must be cleared to
0 by application programs.
Bit 3TK16OV: Touch key function 16-bit counter overflow flag
0: No overflow occurs
1: Overflow occurs
This bit is set by touch key function 16-bit counter overflow and must be cleared to 0
by application programs.
Bit 2
Unimplemented, read as “0”
Bit 1TKMOD: Touch key scan mode select
0: Auto scan mode
1: Manual scan mode
In manual scan mode the reference oscillator capacitor value should be properly
configured before the scan operation begins and the touch key module 16-bit C/F
counter value should be read after the scan operation finishes by application program.
In auto scan mode the data movement which is described above is implemented by
hardware. The individual reference oscillator capacitor value and 16-bit C/F counter
content for all scanned keys will be read from and written into a dedicated Touch
Key Data Memory area. In auto scan mode the keys to be scaned can be arranged in a
specific sequence which is determined by the MnSK3[1:0] ~ MnSK0[1:0] bits in the
TKMnC2 register. The scan operation will not be stopped until all arranged keys are
scanned.
Bit 0TKBUSY: Touch key scan operation busy flag
0: Not busy – no scan operation is executed or scan operation is complete
1: Busy – scan operation is executing
This bit indicates whether the touch key scan operation is executing or not. It is set to
1 when the TKST bit is set high to start the scan operation and cleared to 0 when the
touch key time slot counter overflows.
Rev. 1.20
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TKC1 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
TSCS
TK16S1
TK16S0
TKFS1
TKFS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
1
1
Bit 7~5D7~D5: Data bits for test only
These bits are used for test purpose only and must be kept as “000” for normal
operations.
Bit 4TSCS: Touch key time slot counter select
0: Each touch key module uses its own time slot counter
1: All touch key modules use Module 0 time slot counter
Bit 3~2TK16S1~TK16S0: Touch key function 16-bit counter clock source select
00: fSYS
01: fSYS/2
10: fSYS/4
11: fSYS/8
Bit 1~0TKFS1~TKFS0: Touch key oscillator and Reference oscillator frequency select
00: 500 kHz
01: 1000 kHz
10: 1500 kHz
11: 2000 kHz
TK16DH/TK16DL – Touch Key Function 16-bit Counter Register Pair
Register
Bit
TK16DH
7
6
5
4
3
TK16DL
2
0
7
6
5
4
3
2
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
D15 D14 D13 D12 D11 D10
1
This register pair is used to store the touch key function 16-bit counter value. This 16-bit counter can
be used to calibrate the reference or key oscillator frequency. When the touch key time slot counter
overflows in the manual scan mode, this 16-bit counter will be stopped and the counter content will
be unchanged. However, this 16-bit counter content will be cleared to zero at the end of the time slot 0,
slot 1 and slot 2 but kept unchanged at the end of the time slot 3 in the auto scan mode. This register
pair will be cleared to zero when the TKST bit is set low.
TKMn16DH/TKMn16DL – Touch Key Module n 16-bit C/F Counter Register Pair
Register
Bit
Name
TKMn16DH
7
6
5
4
3
TKMn16DL
2
D15 D14 D13 D12 D11 D10
1
0
7
6
5
4
3
2
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register pair is used to store the touch key module n 16-bit C/F counter value. This 16-bit C/
F counter will be stopped and the counter content will be kept unchanged when the touch key time
slot counter overflows in the manual scan mode. However, this 16-bit C/F counter content will be
cleared to zero at the end of the time slot 0, slot 1 and slot 2 but kept unchanged at the end of the
time slot 3 when the auto scan mode is selected. This register pair will be cleared to zero when the
TKST bit is set low.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TKMnROH/TKMnROL – Touch Key Module n Reference Oscillator Capacitor Select
Register Pair
Register
TKMnROH
TKMnROL
Bit
7
6
5
4
3
2
Name
—
—
—
—
—
—
R/W
—
—
—
—
—
—
POR
—
—
—
—
—
—
1
0
7
6
5
4
3
2
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
This register pair is used to store the touch key module n reference oscillator capacitor value. This
register pair will be loaded with the corresponding next time slot capacitor value from the dedicated
touch key data memory at the end of the current time slot when the auto scan mode is selected.
TKMn [9:0] × 50pF
The reference oscillator internal capacitor value=
.
1024
TKMnC0 Register
Bit
7
6
5
4
Name
—
—
MnDFEN
D4
3
2
MnSOFC MnSOF2
1
0
MnSOF1
MnSOF0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5MnDFEN: Touch key module n multi-frequency control
0: Disable
1: Enable
This bit is used to control the touch key oscillator frequency doubling function. When
this bit is set to 1, the key oscillator frequency will be doubled.
Bit 4D4: Data bit for test only
The bit is used for test purpose only and must be kept as “0” for normal operations.
Bit 3MnSOFC: Touch key module n C-to-F oscillator frequency hopping function control select
0: Controlled by the MnSOF2~MnSOF0
1: Controlled by hardware circuit
This bit is used to select the touch key oscillator frequency hopping function control
method. When this bit is set to 1, the key oscillator frequency hopping function is
controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value.
Bit 2~0MnSOF2~MnSOF0: Touch key module n Reference and Key oscillators hopping
frequency select
000: fHOP0 – Min. hopping frequency
001: fHOP1
010: fHOP2
011: fHOP3
100: fHOP4 – Selected touch key oscillator frequency
101: fHOP5
110: fHOP6
111: fHOP7 – Max. hopping frequency
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TKMnC1 Register
Bit
7
6
Name
MnTSS
—
5
4
R/W
R/W
—
R/W
R/W
POR
0
—
0
0
3
2
1
0
MnK3EN
MnK2EN
MnK1EN
R/W
R/W
R/W
R/W
0
0
0
0
MnROEN MnKOEN MnK4EN
Bit 7MnTSS: Touch key module n time slot counter clock source select
0: Touch key module n reference oscillator
1: fSYS/4
Bit 6
Unimplemented, read as “0”
Bit 5MnROEN: Touch key module n Reference oscillator enable control
0: Disable
1: Enable
This bit is used to enable the touch key module n reference oscillator. In auto scan
mode the reference oscillator will automatically be enabled by setting the MnROEN
bit high when the TKST bit is set from low to high if the reference oscillator is
selected as the time slot clock source. The combination of the MnTSS, TSCS and
MnK4EN~MnK1EN bits determines whether the reference oscillator is used or
not. When the TKBUSY bit is changed from high to low, the MnROEN bit will
automatically be set low to disable the reference oscillator.
In manual scan mode the reference oscillator should first be enabled before setting the
TKST bit from low to high if the reference oscillator is selected to be used and will be
disabled when the TKBUSY bit is changed from high to low.
Bit 4MnKOEN: Touch key module n Key oscillator enable control
0: Disable
1: Enable
This bit is used to enable the touch key module n key oscillator. In auto scan mode the
key oscillator will automatically be enabled by setting the MnKOEN bit high when the
TKST bit is set form low to high. When the TKBUSY bit is changed from high to low,
the MnKOEN bit will automatically be set low to disable the key oscillator.
In manual scan mode the key oscillator shoule first be enabled before setting the TKST
bit from low to high if the relevant key is enabled to be scanned and will be disabled
when the TKBUSY bit is changed from high to low.
Bit 3MnK4EN: Touch key module n Key 4 enable control
0: Disable
1: Enable
Bit 2MnK3EN: Touch key module n Key 3 enable control
0: Disable
1: Enable
Bit 1MnK2EN: Touch key module n Key 2 enable control
0: Disable
1: Enable
Bit 0MnK1EN: Touch key module n Key 1 enable control
0: Disable
1: Enable
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TKMnC2 Register
Bit
7
6
5
4
3
2
1
0
Name
MnSK31
MnSK30
MnSK21
MnSK20
MnSK11
MnSK10
MnSK01
MnSK00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
0
0
1
0
0
Bit 7~6MnSK31~MnSK30: Touch key module n time slot 3 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 3 and only available in
the auto scan mode.
Bit 5~4MnSK21~MnSK20: Touch key module n time slot 2 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 2 and only available in
the auto scan mode.
Bit 3~2MnSK11~MnSK10: Touch key module n time slot 1 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 1 and only available in
the auto scan mode.
Bit 1~0MnSK01~MnSK00: Touch key module n time slot 0 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 0 in the auto scan mode
or used as the multiplexer for scan key select in the manual mode.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Touch Key Operation
When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase.
By using this capacitance variation to change slightly the frequency of the internal sense oscillator,
touch actions can be sensed by measuring these frequency changes. Using an internal programmable
divider the reference clock is used to generate a fixed time period. By counting a number of
generated clock cycles from the sense oscillator during this fixed time period touch key actions can
be determined.
TKST
MnKOEN
MnROEN
Hardware set to “0”
KEY OSC CLK
Reference OSC CLK
fCFT�CK Enable
fCFT�CK (MnDFEN=0)
fCFT�CK (MnDFEN=0)
TKBUSY
TKRCOV
Set Touch Ke� interrupt request flag
Touch Key Mamual Scan Mode Timing Diagram
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Each touch key module contains four touch key inputs which are shared logical I/O pins, and the
desired function is selected using register Bits. Each touch key has its own independent sense
oscillator. There are therefore four sense oscillators within each touch key module.
During this reference clock fixed interval, the number of clock cycles generated by the sense
oscillator is measured, and it is this value that is used to determine if a touch action has been made
or not. At the end of the fixed reference clock time interval a Touch Key interrupt signal will be
generated in the manual scan mode.
Using the TSCS bit in the TKC1 register can select the module 0 time slot counter as the time
slot counter for all modules. All modules use the same started signal, TKST, in the TKC0 register.
The touch key module 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter in
all modules will be automatically cleared when the TKST bit is cleared to zero, but the 8-Bit
programmable time slot counter will not be cleared. The overflow time is setup by user. When the
TKST bit changes from low to high, the 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period
counter and 8-bit time slot timer counter will be automatically switched on.
The key oscillator and reference oscillator in all modules will be automatically stopped and the 16bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter
will be automatically switched off when the time slot counter overflows. The clock source for
the time slot counter is sourced from the reference oscillator or fSYS/4 which is selected using the
MnTSS bit in the TKMnC1 register. The reference oscillator and key oscillator will be enabled by
setting the MnROEN bit and MnKOEN bits in the TKMnC1 register.
When the time slot counter in all the touch key modules or in the touch key module 0 overflows,
an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are
enabled.
Each touch key module consists of four touch keys, KEY1 ~ KEY4 are contained in module 0,
KEY5 ~ KEY8 are contained in module 1, KEY9 ~ KEY12 are contained in module 2, etc. Each
touch key module has an identical structure.
Auto Scan Mode
There are two scan modes contained for the touch key function. The auto scan mode can minisize
the load of the application programs and improve the touch key scan operation performance. The
auto scan mode and manual scan mode are selected using the TKMOD bit in the TKC0 register.
When the TKMOD bit is set low, the auto scan mode is selcted to scan the keys in each module in a
specific sequence determined by the MnSK3[1:0]~MnSK0[1:0] in the TKMnC2 register.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Ke� Auto Scan C�cle
TKST
Time slot 0
Time slot 1
�odule 0
Time slot 1
Time slot 2
Time slot 2
Time slot 3
Time slot 3
Time slot 0
Time slot 1
Time slot 1
�odule 1
Time slot 2
Time slot 2
Time slot 3
Time slot 3
Time slot 0
Time slot 1
�odule n
Time slot 1
Time slot 2
Time slot 2
Time slot 3
Time slot 3
TKBUSY
Cleared b� software
TKRCOV
Touch Ke� Data
�emor� Access
: Set Touch Ke� interrupt request flag
: Read 2N bytes from Touch Key Data Memory to TKMnROH/TKMnTROL registers
: Write 2N bytes from TKMn16DH/TKMn16DL registers to Touch Ke� Data �emor�
N = Touch Key Module Number; n = Module Serial Number
Touch Key Auto Scan Mode Timing Diagram
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
In the auto scan mode the key oscillator and reference oscillator will automatically be enabled when
the TKST bit is set from low to high and disabled automatically when the TKBUSY bit changes from
high to low. When the TKST bit is set from low to high in the auto scan mode, the first reference
oscillator internal capacitor value will be read from a specific location of the dedicated touch key
data memory and loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit
C/F counter value will be written into the last location of the corresponding touch key module data
memory. After this the selected key will be scanned in time slot 0. At the end of the time slot 0 key
scan operation, the reference oscillator internal capacitor value for the next selected key will be read
from the touch key data memory and loaded into the the next TKMnROH/TKMnROL registers.
Then the 16-bit C/F counter value of the current scanned key will be written into the corresponding
touch key data memory. The whole auto scan operation will sequentially be carried out in the above
specific way from time slot 0 to time slot 3. After four keys are scanned, the TKRCOV bit will be
set high and the TKBUSY bit will be set low. At the end of the auto scan mode, the first reference
oscillator internal capacitor value will again be read from the touch key data memory and loaded
into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value will
again be written into the relevant touch key data memory.
Touch Key Data Memory
The device provides two dedicated Data Memory area for the touch key auto scan mode. One area
is used to store the 16-bit C/F counter values of the touch key module 0~n and located in Data
Memory Sector 5. The other area is used to store the reference oscillator internal capacitor values of
the touch key module 0~n and located in Data Memory Sector 6.
16-bit C/F counter value
(Sector 5)
Ref. OSC Capacitor value
(Sector 6)
00H
TKM016DL_K1
TKM0ROL_K1
01H
TKM016DH_K1
TKM0ROH_K1
02H
TKM016DL_K2
TKM016DH_K2
TKM016DL_K3
TKM0ROL_K2
Module 0
TKM016DH_K3
Touch Key Circuit
TKM016DL_K4
TKM0ROL_K4
TKM0ROH_K4
TKM116DL_K1
TKM1ROL_K1
TKM116DH_K1
TKM1ROH_K1
TKM116DL_K2
TKMnROL / TKMnROH
TKM116DL_K3
Step 1
TKM1ROL_K2
Module 1
TKM116DH_K3
Step 2
16-bit C/F counter
TKM1ROL_K3
TKM1ROH_K3
TKM116DL_K4
TKM1ROL_K4
TKM1ROH_K4
TKM216DL_K1
TKM2ROL_K1
TKM216DH_K1
TKM2ROH_K1
TKM216DL_K2
TKM216DL_K3
TKM2ROL_K2
Module 2
TKM216DH_K3
TKM2ROH_K2
TKM2ROL_K3
TKM2ROH_K3
TKM216DL_K4
TKM2ROL_K4
TKM216DH_K4
TKM2ROH_K4
TKM316DL_K1
TKM3ROL_K1
TKM316DH_K1
TKM3ROH_K1
TKM316DL_K2
TKM316DH_K2
TKM316DL_K3
TKM316DH_K3
xxH
TKM1ROH_K2
TKM116DH_K4
TKM216DH_K2
TKMn16DL / TKMn16DH
TKM0ROL_K3
TKM0ROH_K3
TKM016DH_K4
TKM116DH_K2
10-bit Ref. OSC capacitor
TKM0ROH_K2
TKM3ROL_K2
Module n
TKM3ROH_K2
TKM3ROL_K3
TKM3ROH_K3
TKM316DL_K4
TKM3ROL_K4
TKM316DH_K4
TKM3ROH_K4
Touch Key Data Memory Map
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Touch Key Data Memory
Device
Sector : Address
5: 00H~1FH
6: 00H~1FH
5: 00H~27H
6: 00H~27H
5: 00H~37H
6: 00H~37H
BS67F340
BS67F350
BS67F360
Touch Key Data Memory Summary
Touch Key Scan Operation Flow Chart
Start
Write Ref. OSC Capacitor
to TKMnROH/TKMnROL
Touch Ke� �anual Scan Operation Start
1
Set Start bit TKST 0
Busy flag TKBUSY=1
Initiate Time Slot &
16-bit C/F Counter
All Time Slot &
16-bit C/F Counter
Start to count
Time Slot &
16-bit C/F Counter
Keep counting
TKRCOV=0
All Time Slot
Counter overflow ?
TKRCOV=1
Touch ke� bus� flag
TKBUSY=0
Generate Interrupt
request flag
Read C/F counter from
TKMn16DH/TKMn16DL
Touch ke� scan end
0
Set TKST bit 1
End
Touch Key Manual Scan Mode Flow Chart – TKMOD=1, TSCS=0
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Start
Write Ref. OSC internal
Capacitor value
to Data �emor� (Sector 6 )
Touch Ke� Auto Scan Operation Start
1
Set Start bit TKST 0
Busy flag TKBUSY=1
Load Ref. OSC internal
Capacitor value from
Data �emor� (Sector 6 )
Store C/F counter value to
Data �emor� (Sector � )
Touch ke� bus� flag
TKBUSY=0
Initiate Time Slot &
16-bit C/F Counter
TKRCOV = 1
Generate Interrupt
request flag
All Time Slot counter &
16-bit C/F counter
Start to count
Touch ke� scan end
0
Set TKST bit 1
Time Slot &
16-bit C/F Counter
Keep counting
No
All Time Slot
Counter overflow ?
Read C/F counter value from
Data �emor� (Sector �)
Yes
All ke� scan finish ?
No
Change next ke�
End
Yes
Touch Key Auto Scan Mode Flow Chart – TKMOD=0, TSCS=0
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Touch Key Interrupt
The touch key only has single interrupt, when the time slot counter in all the touch key modules or
in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys
mentioned here are the keys which are enabled. The 16-bit C/F counter, 16-bit counter, 5-bit time
slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared.
The TKCFOV flag which is the 16-bit C/F counter overflow flag will go high when any of the Touch
Key Module 16-bit C/F counter overflows. As this flag will not be automatically cleared, it has to be
cleared by the application program.
The TK16OV flag which is the 16-bit counter overflow flag will go high when the 16-bit counter
overflows. As this flag will not be automatically cleared, it has to be cleared by the application
program. More details regarding the touch key interrupt is located in the interrupt section of the
datasheet.
Progrsmming Considerations
After the relevant registers are setup, the touch key detection process is initiated the changing the
TKST Bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV
flag which is the time slot counter flag will go high when the counter overflows. When this happens
an interrupt signal will be generated.
When the external touch key size and layout are defined, their related capacitances will then
determine the sensor oscillator frequency.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Low Voltage Detector – LVD
Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
The Low Voltage Detector also has the capability of generating an interrupt signal.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which
a low voltage condition will be determined. A low voltage condition is indicated when the LVDO
bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage
value. The LVDEN bit is used to control the overall on/off function of the low voltage detector.
Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the
internal low voltage detector circuits. As the low voltage detector will consume a certain amount of
power, it may be desirable to switch off the circuit when not in use, an important consideration in
power sensitive battery powered applications.
LVDC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
LVDO
LVDEN
VBGEN
VLVD2
VLVD1
VLVD0
R/W
—
—
R
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Uunimplemented, read as “0”
Bit 5LVDO: LVD output flag
0: No Low Voltage Detected
1: Low Voltage Detected
Bit 4LVDEN: Low Voltage Detector Enable control
0: Disable
1: Enable
Bit 3VBGEN: Bandgap Voltage Output Enable control
0: Disable
1: Enable
Bit 2~0VLVD2~VLVD0: LVD Voltage selection
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be
set high indicating a low power supply voltage condition. The Low Voltage Detector function is
supplied by a reference voltage which will be automatically enabled. When the device is powered
down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low
Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the
LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that
of VLVD, there may be multiple bit LVDO transitions.
LVD Operation
The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling
the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been
set high by a low voltage condition. When the device is powered down the Low Voltage Detector
will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set,
causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the
device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up
function is not required then the LVF flag should be first set high before the device enters the SLEEP
or IDLE Mode.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. These devices contain several external
interrupt and internal interrupts functions. The external interrupts are generated by the action of
the external INT0 and INT1 pins, while the internal interrupts are generated by various internal
functions such as the TMs, Time Base, LVD, EEPROM, SIM, UART and the A/D converter, etc.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the
accompanying table. The number of registers depends upon the device chosen but fall into three
categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second
is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG
register to setup the external interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual interrupts as well
as interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an “E” for enable/disable bit or “F” for request flag.
Function
Enable Bit
Request Flag
Notes
EMI
—
—
INTn Pins
INTnE
INTnF
n=0 ~ 1
Touch Key
Global
TKME
TKMF
—
UART
URE
URF
—
Multi-function
MFnE
MFnF
n=0 ~ 3
A/D Converter
ADE
ADF
—
Time Base
TBnE
TBnF
n=0 ~ 1
LVD
LVE
LVF
—
EEPROM write operation
DEE
DEF
—
SIM
SIME
SIMF
—
CTMnPE
CTMnPF
CTMnAE
CTMnAF
PTMPE
PTMPF
PTMAE
PTMAF
STMPE
STMPF
STMAE
STMAF
CTM
PTM
STM
n=0 ~ 1
—
—
Interrupt Register Bit Naming Conventions
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Bit
Register
Name
7
INTEG
—
—
INTC0
—
TKMF
INTC1
ADF
MF1F
INTC2
MF3F
TB1F
MFI0
—
—
CTM0AF CTM0PF
CTM1AF CTM1PF
6
5
4
3
2
1
0
—
—
INT1S1
INT1S0
INT0S1
INT0S0
INT1F
INT0F
TKME
INT1E
INT0E
EMI
MF0F
URF
ADE
MF1E
MF0E
URE
TB0F
MF2F
MF3E
TB1E
TB0E
MF2E
—
—
CTM0AE CTM0PE
CTM1AE CTM1PE
MFI1
STMAF
STMPF
STMAE
STMPE
MFI2
—
SIMF
PTMAF
PTMPF
—
SIME
PTMAE
PTMPE
MFI3
—
—
DEF
LVF
—
—
DEE
LVE
Interrupt Registers List
INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3~2INT1S1~INT1S0: Interrupt edge control for INT1 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 1~0INT0S1~INT0S0: Interrupt edge control for INT0 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
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INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
TKMF
INT1F
INT0F
TKME
INT1E
INT0E
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6TKMF: Touch key interrupt request flag
0: no request
1: interrupt request
Bit 5INT1F: INT1 interrupt request flag
0: no request
1: interrupt request
Bit 4INT0F: INT0 interrupt request flag
0: no request
1: interrupt request
Bit 3TKME: Touch key interrupt control
0: Disable
1: Enable
Bit 2INT1E: INT1 interrupt control
0: Disable
1: Enable
Bit 1INT0E: INT0 interrupt control
0: Disable
1: Enable
Bit 0EMI: Global interrupt control
0: Disable
1: Enable
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INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
ADF
MF1F
MF0F
URF
ADE
MF1E
MF0E
URE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7ADF: A/D Converter interrupt request flag
0: no request
1: interrupt request
Bit 6MF1F: Multi-function 1 interrupt request flag
0: no request
1: interrupt request
Bit 5MF0F: Multi-function 0 interrupt request flag
0: no request
1: interrupt request
Bit 4URF: UART transfer interrupt request flag
0: no request
1: interrupt request
Bit 3ADE: A/D Converter interrupt control
0: Disable
1: Enable
Bit 2MF1E: Multi-function 1 interrupt control
0: Disable
1: Enable
Bit 1MF0E: Multi-function 0 interrupt control
0: Disable
1: Enable
Bit 0URE: UART transfer interrupt control
0: Disable
1: Enable
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INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
MF3F
TB1F
TB0F
MF2F
MF3E
TB1E
TB0E
MF2E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
1
0
Bit 7MF3F: Multi-function 3 interrupt request flag
0: no request
1: interrupt request
Bit 6TB1F: Time Base 1 interrupt request flag
0: no request
1: interrupt request
Bit 5TB0F: Time Base 0 interrupt request flag
0: no request
1: interrupt request
Bit 4MF2F: Multi-function 2 interrupt request flag
0: no request
1: interrupt request
Bit 3MF3E: Multi-function 3 interrupt control
0: Disable
1: Enable
Bit 2TB1E: Time Base 1 interrupt control
0: Disable
1: Enable
Bit 1TB0E: Time Base 0 interrupt control
0: Disable
1: Enable
Bit 0MF2E: Multi-function 2 interrupt control
0: Disable
1: Enable
MFI0 Register
Bit
7
6
5
4
3
2
Name
—
—
CTM0AF
CTM0PF
—
—
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
CTM0AE CTM0PE
Unimplemented, read as “0”
Bit 5CTM0AF: CTM0 Comparator A match Interrupt request flag
0: no request
1: interrupt request
Bit 4CTM0PF: CTM0 Comparator P match Interrupt request flag
0: no request
1: interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1CTM0AE: CTM0 Comparator A match Interrupt control
0: disable
1: enable
Bit 0CTM0PE: CTM0 Comparator P match Interrupt control
0: disable
1: enable
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MFI1 Register
Bit
7
6
5
4
3
2
Name
STMAF
STMPF
CTM1AF
CTM1PF
STMAE
STMPE
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
CTM1AE CTM1PE
Bit 7STMAF: STM Comparator A match Interrupt request flag
0: no request
1: interrupt request
Bit 6STMPF: STM Comparator P match Interrupt request flag
0: no request
1: interrupt request
Bit 5CTM1AF: CTM1 Comparator A match Interrupt request flag
0: no request
1: interrupt request
Bit 4CTM1PF: CTM1 Comparator P match Interrupt request flag
0: no request
1: interrupt request
Bit 3STMAE: STM Comparator A match Interrupt control
0: disable
1: enable
Bit 2STMPE: STM Comparator P match Interrupt control
0: disable
1: enable
Bit 1CTM1AE: CTM1 Comparator A match Interrupt control
0: disable
1: enable
Bit 0CTM1PE: CTM1 Comparator P match Interrupt control
0: disable
1: enable
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
MFI2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
SIMF
PTM1AF
PTM1PF
—
SIME
PTM1AE
PTM1PE
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
—
0
0
0
—
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6SIMF: SIM Interrupt request flag
0: no request
1: interrupt request
Bit 5PTMAF: PTM Comparator A match Interrupt request flag
0: no request
1: interrupt request
Bit 4PTMPF: PTM Comparator P match Interrupt request flag
0: no request
1: interrupt request
Bit 3
Unimplemented, read as “0”
Bit 2SIME: SIM Interrupt control
0: disable
1: enable
Bit 1PTMAE: PTM Comparator A match Interrupt control
0: disable
1: enable
Bit 0PTMPE: PTM Comparator P match Interrupt control
0: disable
1: enable
MFI3 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
DEF
LVF
—
—
DEE
LVE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 7DEF: Data EEPROM Interrupt request flag
0: no request
1: interrupt request
Bit 4LVF: LVD Interrupt request flag
0: no request
1: interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1DEE: Data EEPROM Interrupt control
0: disable
1: enable
Bit 0LVE: LVD Interrupt control
0: disable
1: enable
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/D
conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag
actually generates a program jump to the relevant interrupt vector is determined by the condition of
the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector;
if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be
generated and the program will not jump to the relevant interrupt vector. The global interrupt enable
bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a JMP which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a RETI, which retrieves the original Program Counter address from the
stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI
bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Legend
xxF
Request Flag, no auto reset in ISR
xxF
Request Flag, auto reset in ISR
xxE
Enable Bits
Interrupts contained within
Multi-Function Interrupts
CTM0 P
CTM0PF
CTM0PE
CTM0 A
CTM0AF
CTM0AE
CTM1 P
CTM1PF
CTM1PE
CTM1 A
CTM1AF
CTM1AE
STM P
STMPF
STMPE
STM A
STMAF
STMAE
PTM P
PTMPF
PTMPE
PTM A
PTMAF
PTMAE
SIM
SIMF
SIME
LVD
LVF
LVE
EEPROM
DEF
DEE
EMI auto disabled in ISR
Interrupt
Name
Request
Flags
Enable
Bits
Master
Enable
INT0 Pin
INT0F
INT0E
EMI
INT1 Pin
INT1F
INT1E
EMI
08H
Touch Key
TKMF
TKME
EMI
0CH
UART
URF
URE
EMI
10H
M. Funct. 0
MF0F
MF0E
EMI
14H
M. Funct. 1
MF1F
MF1E
EMI
18H
A/D
ADF
ADE
EMI
1CH
M. Funct. 2
MF2F
MF2E
EMI
20H
Time Base 0
TB0F
TB0E
EMI
24H
Time Base 1
TB1F
TB1E
EMI
28H
M. Funct. 3
MF3F
MF3E
EMI
2CH
Vector Priority
High
04H
Low
Interrupt Scheme
External Interrupt
The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external
interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set,
which will occur when a transition, whose type is chosen by the edge select bits, appears on the
external interrupt pins. To allow the program to branch to its respective interrupt vector address,
the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E,
must first be set. Additionally the correct interrupt edge type must be selected using the INTEG
register to enable the external interrupt function and to choose the trigger edge type. As the external
interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if
their external interrupt enable bit in the corresponding interrupt register has been set and the external
interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also
be setup as an input by setting the corresponding bit in the port control register. When the interrupt
is enabled, the stack is not full and the correct transition type appears on the external interrupt pin,
a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the
external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the
external interrupt pins will remain valid even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Touch Key Interrupt
For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the Touch Key interrupt
enable TKME must be first set. An actual Touch Key interrupt will take place when the Touch Key
request flag, TKMF, is set, a situation that will occur when the time slot counter overflows. When
the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs,
a subroutine call to the relevant touch key interrupt vector, will take place. When the interrupt is
serviced, the Touch Key interrupt request flag, TKMF, will be automatically reset and the EMI Bit
will be automatically cleared to disable other interrupts.
UART Transfer Interrupt
The UART Transfer Interrupt is controlled by several UART transfer conditions. When one of these
conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller.
These conditions are a transmitter data register empty, transmitter idle, receiver data available,
receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and UART Interrupt
enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of the
conditions described above occurs, a subroutine call to the UART Interrupt vector, will take place.
When the interrupt is serviced, the UART Interrupt flag, URF, will be automatically cleared. The
EMI bit will also be automatically cleared to disable other interrupts.
A/D Converter Interrupt
The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D
Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is
set, which occurs when the A/D conversion process finishes. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit,
ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion
process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the
interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI
bit will also be automatically cleared to disable other interrupts.
Multi-function Interrupt
Within the device there are up to four Multi-function interrupts. Unlike the other independent
interrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM interrupts, LVD interrupt, EEPROM write operation interrupt and
SIM interface interrupts.
A Multi-function interrupt request will take place when any of the Multi-function interrupt request
flags MFnF are set. The Multi-function interrupt flags will be set when any of their included
functions generate an interrupt request flag. To allow the program to branch to its respective interrupt
vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one
of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of
the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts.
However, it must be noted that, although the Multi-function Interrupt request flags will be
automatically reset when the interrupt is serviced, the request flags from the original source of
the Multi-function interrupts will not be automatically reset and must be manually reset by the
application program.
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Time Base Interrupt
The function of the Time Base Interrupt is to provide regular time signal in the form of an internal
interrupt. It is controlled by the overflow signal from its internal timer. When this happens its
interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt
vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be
set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine
call to its respective vector location will take place. When the interrupt is serviced, the interrupt
request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other
interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its
clock source, fPSC0 or fPSC1, originates from the internal clock source fSYS, fSYS/4 or fSUB and then
passes through a divider, the division ratio of which is selected by programming the appropriate bits
in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock
source which in turn controls the Time Base interrupt period is selected using the CLKSEL0[1:0]
and CLKSEL1[1:0] bits in the PSCR0 and PSCR1 register respectively.
fSYS
fSYS/4
fSUB
M
U
X
fPSC0
Prescaler 0
TB0ON
fPSC0/28 ~ fPSC0/215
M
U
X
TB0[2:0]
CLKSEL0[1:0]
fSYS
fSYS/4
fSUB
M
U
X
fPSC1
Time Base 0 Interrupt
Prescaler 1
fPSC1/28 ~ fPSC1/215
M
U
X
TB1ON
CLKSEL1[1:0]
Time Base 1 Interrupt
TB1[2:0]
Time Base Interrupts
PSCR0 Register
Bit
7
6
5
4
3
2
Name
—
—
—
—
—
—
1
0
CLKSEL01 CLKSEL00
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
1
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0CLKSEL01~CLKSEL00: Prescaler 0 clock source selection
00: fSYS
01: fSYS/4
1x: fSUB
PSCR1 Register
Bit
7
6
5
4
3
2
Name
—
—
—
—
—
—
CLKSEL11 CLKSEL10
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0CLKSEL11~CLKSEL10: Prescaler 1 clock source selection
00: fSYS
01: fSYS/4
1x: fSUB
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TB0C Register
Bit
7
6
5
4
3
2
1
0
Name
TB0ON
—
—
—
—
TB02
TB01
TB00
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7TB0ON: Time Base 0 Enable Control
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as “0”
Bit 2~0TB02~TB00: Time Base 0 time-out period selection
000: 28/fPSC
001: 29/fPSC
010: 210/fPSC
011: 211/fPSC
100: 212/fPSC
101: 213/fPSC
110: 214/fPSC
111: 215/fPSC
TB1C Register
Bit
7
6
5
4
3
2
1
0
Name
TB1ON
—
—
—
—
TB12
TB11
TB10
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7TB1ON: Time Base 1 Enable Control
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as “0”
Bit 2~0TB12~TB10: Time Base 1 time-out period selection
000: 28/fPSC
001: 29/fPSC
010: 210/fPSC
011: 211/fPSC
100: 212/fPSC
101: 213/fPSC
110: 214/fPSC
111: 215/fPSC
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Serial Interface Module Interrupt
The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the
Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request
flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM
interface, an I2C slave address match or I2C bus time-out occurrence. To allow the program to
branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial
Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bit must first be set. When
the interrupt is enabled, the stack is not full and any of the above described situations occurs, a
subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial
Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts,
however only the Multi-function interrupt request flag will be also automatically cleared. As the
SIMF flag will not be automatically cleared, it has to be cleared by the application program.
LVD Interrupt
The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD
Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs
when the Low Voltage Detector function detects a low power supply voltage. To allow the program
to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage
Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When
the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to
the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function
interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically
cleared, it has to be cleared by the application program.
EEPROM Interrupt
The EEPROM Write Interrupt is contained within the Multi-function Interrupt. An EEPROM
Write Interrupt request will take place when the EEPROM Write Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, EEPROM Write Interrupt enable bit,
DEE, and associated Multi-function interrupt enable bit must first be set. When the interrupt is
enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective
Multi-function Interrupt vector will take place. When the EEPROM Write Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function
interrupt request flag will be automatically cleared. As the DEF flag will not be automatically
cleared, it has to be cleared by the application program.
TM Interrupt
The Compact, Standard and Periodic TMs have two interrupts, one comes from the comparator A
match situation and the other comes from the comparator P match situation. All of the TM interrupts
are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt
request flags and two enable control bits. A TM interrupt request will take place when any of the
TM request flags are set, a situation which occurs when a TM comparator P or A match situation
happens.
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To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE,
must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match
situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take
place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other
interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low
to high and is independent of whether the interrupt is enabled or not. Therefore, even though these
devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as
external edge transitions on the external interrupt pins, a low power supply voltage or comparator
input change may cause their respective interrupt flag to be set high and consequently generate
an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an
interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be
set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect
on the interrupt wake-up function.
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be
automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
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Application Circuits
A/D
KEY1
SPI/I2C
RX
KEYx
I/O
XT1
TX
Analog Signals
Communication Device
RS_DIR
32768Hz
RS488 Transceiver
XT2
OSC1
S�stem Cr�stal
CO�0~CO�3
SEGx
OSC2
VDD
T�
PWM / Capture
VDD
0.1µF
10µF
T�
Buzzer
VSS
I/O
Control Device
BS67F3x0
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one Bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
Bit from where it can be examined and the necessary serial Bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual Bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data Bits.
Bit Operations
The ability to provide single Bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port Bit programming where
individual Bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].
i" instructions respectively. The feature removes the need for programmers to first read the 8-Bit
output port, manipulate the input data to ensure that other Bits are not changed and then output the
port with the correct new data. This read-modify-write process is taken care of automatically when
these Bit operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The instructions related to the data memory access in the following table can be used when the
desired data memory is located in Data Memory sector 0.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract immediate data from ACC with Carry
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1
1Note
1Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,x
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
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Mnemonic
Description
Cycles Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2Note
2Note
2Note
None
None
None
2Note
None
1
1Note
1Note
1
1Note
1
1
None
None
None
TO, PDF
None
None
TO, PDF
Bit Operation
CLR [m].i
SET [m].i
Branch Operation
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m]
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if Data Memory is not zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
Table Read Operation
TABRD [m] Read table (specific page) to TBLH and Data Memory
TABRDL [m] Read table (last page) to TBLH and Data Memory
ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
ITABRDL [m]
Data Memory
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
SWAP [m]
SWAPA [m]
HALT
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if
no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT” instruction the TO and PDF flags may be affected by the execution status. The TO
and PDF flags are cleared after the “CLR WDT” instructions is executed. Otherwise the TO and PDF
flags remain unchanged.
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Extended Instruction Set
The extended instructions are used to support the full range address access for the data memory.
When the accessed data memory is located in any data memory sections except sector 0, the
extended instruction can be used to access the data memory instead of using the indirect addressing
access to improve the CPU firmware performance.
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
2
2Note
2
2Note
2
2Note
2
2Note
2Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
2
2
2
2Note
2Note
2Note
2Note
2
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
2
2Note
2
2Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
2
2Note
2
2Note
2
2Note
2
2Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
2
2Note
None
None
Clear bit of Data Memory
Set bit of Data Memory
2Note
2Note
None
None
Arithmetic
LADD A,[m]
LADDM A,[m]
LADC A,[m]
LADCM A,[m]
LSUB A,[m]
LSUBM A,[m]
LSBC A,[m]
LSBCM A,[m]
LDAA [m]
Logic Operation
LAND A,[m]
LOR A,[m]
LXOR A,[m]
LANDM A,[m]
LORM A,[m]
LXORM A,[m]
LCPL [m]
LCPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
LINCA [m]
LINC [m]
LDECA [m]
LDEC [m]
Rotate
LRRA [m]
LRR [m]
LRRCA [m]
LRRC [m]
LRLA [m]
LRL [m]
LRLCA [m]
LRLC [m]
Data Move
LMOV A,[m]
LMOV [m],A
Bit Operation
LCLR [m].i
LSET [m].i
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Mnemonic
Description
Cycles Flag Affected
Branch
LSZ [m]
LSZA [m]
LSNZ [m]
LSZ [m].i
LSNZ [m].i
LSIZ [m]
LSDZ [m]
LSIZA [m]
LSDZA [m]
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if Data Memory is not zero
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
None
None
None
None
None
None
None
None
None
3Note
3Note
3Note
None
None
None
3Note
None
2Note
2Note
2Note
2
None
None
None
None
Table Read
LTABRD [m] Read table to TBLH and Data Memory
LTABRDL [m] Read table (last page) to TBLH and Data Memory
LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
LITABRDL [m]
Data Memory
Miscellaneous
LCLR [m]
LSET [m]
LSWAP [m]
LSWAPA [m]
Clear Data Memory
Set Data Memory
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles
are required, if no skip takes place two cycles is required.
2. Any extended instruction which changes the contents of the PCL register will also require three cycles for
execution.
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Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C, SC
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
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CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
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DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
Rev. 1.20
246
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
Rev. 1.20
247
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
Rev. 1.20
248
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
SBC A, x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC with Carry
The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC - [m] - C
OV, Z, AC, C, SC, CZ
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
Rev. 1.20
249
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SNZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m]≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
Rev. 1.20
250
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C, SC, CZ
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.20
251
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
TABRD [m]
Description
Operation
Affected flag(s)
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
ITABRD [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
ITABRDL [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.20
252
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Extended Instruction Definition
The extended instructions are used to directly access the data stored in any data memory sections.
LADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
LADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
LADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
LADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
LAND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
LANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
LCLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
LCLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
Rev. 1.20
Add Data Memory to ACC
253
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LCPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
LCPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
LDAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
LDEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
LDECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
LINC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
LINCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
Rev. 1.20
254
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LMOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
LMOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
LOR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
LORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
LRL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
LRLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
LRLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
LRLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
Rev. 1.20
255
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LRR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
LRRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
LRRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
LRRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
LSBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
LSBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
Rev. 1.20
256
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LSDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
LSDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
LSET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
LSET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
LSIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
LSIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
LSNZ [m].i
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LSNZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m] ≠ 0
None
LSUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
LSUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
LSWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
LSWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
LSZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
LSZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
LSZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
LTABRD [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LTABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LITABRD [m]
Description
Operation
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
Affected flag(s)
None
LITABRDL [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LXOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
LXORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
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Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
48-pin LQFP (7mm × 7mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.020 BSC
—
D2
0.170
—
0.205
E2
0.079
—
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.20
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.50 BSC
—
5.21
D2
4.31
—
E2
2.00
—
—
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
261
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BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
64-pin LQFP (7mm × 7mm) Outline Dimensions
Symbol
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.20
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.40 BSC
—
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
262
May 15, 2015
BS67F340/BS67F350/BS67F360
Enhanced Touch A/D 8-Bit Flash MCU with LCD Driver
Copyright© 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.20
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