C5515 Overview Presentation 4Q2010.pdf

Ultra-Low Power TMS320C5515 DSP
Overview
C5000 Ultra Low Power DSPs
Agenda
• C5515 Device Overview
• C5515 Architecture
• C5515 Peripherals
• C5515 Instructions
• 3rd Party Network
Embedded processing portfolio
TI Embedded Processors
Microcontrollers (MCUs)
16-bit ultralow power
MCUs
32-bit
real-time
MCUs
MSP430™
C2000™
Delfino ™
Piccolo ™
Up to
25 MHz
Flash
1 KB to 256 KB
Analog I/O, ADC
LCD, USB, RF
Measurement,
Sensing, General
Purpose
$0.25 to $9.00
ARM®-Ba sed Processors
32-bit ARM
Cortex™-M3
MCUs
Stellaris
®
AR M® Cortex™-M3
ARM
Cortex-A8
MPUs
Sitara™
AR M® Cortex™-A8
& ARM9
300MHz to
Up to
>1GHz
100 MHz
Flash, RAM
Flash
Cache,
16 KB to 512 KB
64 KB to 256 KB
RAM, ROM
USB, ENET
USB, CAN,
PWM, ADC,
MAC+PHY
CAN,
2
PCIe,
EMAC
CAN, SPI, I C
ADC, PWM, SPI
Motor Control,
Connectivity, Security, Industrial computing,
POS & portable
Digital Power,
Motion Control, HMI,
Lighting, Ren. Enrgy Industrial Automation
data terminals
$5.00 to $20.00
$1.50 to $20.00
$1.00 to $8.00
40MHz to
300 MHz
Digital Signal Processors (DSPs)
C6000
DSP &
DSP+ARM
C6000™
DaVinci™
OMAP™
300MHz to
>1GHz
+Accelerator
Cache
RAM, ROM
16-bit Ultra
Low power
DSPs
C6000™
C5000™
24.000
MMACS
Up to 300 MHz
+Accelerator
Up to 320KB RAM
Up to 128KB ROM
Cache
SRIO, EMAC
USB, ENET,
USB, ADC
DMA, PCIe
PCIe, SATA, SPI
McBSP, SPI, I2C
Video, Audio,
Telecom test & meas.,
Audio, Voice
Voice, Security, media gateways, base
Conferencing
Medical, Biometrics
stations
$5.00 to $200.00
$3.00 to $10.00
$40 to $200. 00
Software & Dev. Tools
MPUs – Microprocessors
Multi core
DSP
Ultra Low Power C5000 DSP Summary
•
C5504/05/14/15 is the industry’s lowest power (< 0.15mW/MHz)
DSP family
•
•
•
Energy efficient audio/voice processing
Completely C-programmable and no assembly required
Comprehensive ecosystem to accelerate time to market
–
–
–
–
Fully functional development platforms including specific end equipment
System Development Kits
Low cost eZdsp tools for simple application development
Production-quality software with code examples for specific application
designs
Large and well established 3rd Party network
Four new C5000™ lowest power DSPs
offer longer battery life at reduced
system cost
Ultra Low power C5000™ DSP Roadmap
Enable innovation with industry’s lowest power
Increased performance/ optimized power
Production
C55 Next
Dev elopment
Sampling
C55x family:
19 devices
Latest generation
industry's
lowest power 16-bit DSP family
Performance up to 300MHz
Pow er consumption <0.15mW/MHz
C5504/05
150 MHz
C5505
•120 MHz
•USB 2.0
•FFT
•LCD
C5502
C5510
200 MHz
C5503/
C5506/
C5507/
C5509
C5402
100/160
MHz
1st generation low
pow er 16-bit DSP
Performance up to
160MHz
Large on-chip memory
FFT coprocessor
USB2.0 w ith PHY integration
LDO Integration
• 200 MHz
C5416
C55 Next
120/160
MHz
C5504
C5501
C5000
C5514/C5515
• 120 MHz
•USB 2.0
•FFT
•LCD
•LDOs
300 MHz
C54x family:
19 devices
C5401
•120 MHz
• USB 2.0
300 MHz
Very small package (QFP or BGA)
50 MHz
2009
2010
2011
C5504/05/14/15 Value Proposition
Industry’s Lowest Power DSP
Best combination of standby and active power
Enables longer battery life for portable devices
High integration of peripherals
and increased memory
Reduces system cost and enables intuitive
user interface
• Standby mode <0.15mW
• Active mode < 0.15mW/MHz
• Dynamic Voltage &
Frequency Scaling
• On-chip FFT hardware
acceleration
• Up to 320KB memory
• Integrated LDOs, Power Mgmt
• High speed USB 2.0 w/PHY
• LCD controller and ADC
• MMC/SD, I2S, SPI, I2C
• RTC, Watchdog timer
Extensive development resources
and pin-to-pin compatible devices
Provide customers with great design support
and flexibility
$49
$79
C5515 Evaluation
Module $395
eZdsp USB Stick
7
C5504/05/14/5 Block Diagram and Deltas
I/O: - 1.8V, 2.5V, 2.8V, 3.3V
- Separate I/O supplies for EMIF and serial interface
Asynchronous LCD interface supporting LCD displays w ith memorymapped interface - MPU68, MPU80, MPUXX, and Hitachi HD44780U
4ch 10-bit SAR ADC: Conversion rate 32 clock cycles @ 2MHz
FFT
I2S
I2S
4
8
4
SARAM
192/256
KB
LCD
ROM
128 KB
GPIO
32KHz
PLL
DARAM
64 KB
4
8
13
8
USB 2.0
slave
10-Bit
SAR
Mem ory
INT
JTAG
DSP Core
2
3 LDOs
4 4-Ch.
DMA
C55x™
16
4
3 Timers
MMC/SD
GPIO
I2S
MMC/SD
EMIF/
NAND,
m SDRAM
2
SPI
C5515 – additional Features to C5514
320-KB On- Chip Memory:
64-KB DARA M, 256-KB SARA M
1024-point FFT Coprocessor
6
UART
Peripherals
60
– Low Pow er FFT HWA
– Four serial busses offering combinations of I2S, UART,
SPI, MMC/SD, and GPIO
– High speed USB2.0
– Multi- master and Slave I2 C w ith 7 or 10-bit addressing modes
– Three 32-bit timers w ith w atchdog functionality
– Four 4-Channel DMAs
4
– Low pow er PLL (0.7mA) w ith 32KHz crystal oscillator
– 16-bit EMIF w ith asynchronous SRAM, NAND
(w ith 4-bit ECC) and SDRA M
– Real-time clock w ith 32-KHz crystal input, separate pow er
– Integrated LDOs for CPU and USB analog
GPIO
Mem ory
– 256-KB On- Chip Memory: 64-KB DARA M, 192-KB SARA M
– 128-KB ROM
6
Peripheral Bus
– 1.05V @ 60/75MHz, 1.3V @ 100/120MHz, 1.4V @ 150MHz (C5504/05 only)
– Dy namic Voltage and Frequency Scaling
RTC
Package: 196-pin 10x10mm BGA with 0.65mm pitch
I2C
Core
– Dual MAC, C55x CPU w ith JTAG disable option
I2S
C5514/5 – additional features to C5504/5
7
7
C5504/05/14/15 DSP Feature Comparison
Not recomm
ended
Sam
pling
Now
Software
Integrated
Compatibility Peripherals
Memory
CoProcessor
Integrated
Power Mgmt
For new designs
Pin to Pin Compatible
™
OMAP
VC5504
OMAP3503
C55x DSP
VC5505
C55x DSP
Peripherals
LCD I/F
256KB
320 KB
1 ANA LDO
FFT CoP
1 ANA LDO
SAR ADC
Rev “A”
™
OMAP
C5504A
OMAP3503
Pin to Pin Compatible
Sam pling Now
OMAP™C5505A
OMAP3503
C55x DSP
ARM
C55x DSP
Cortex-A8
600 MHz
C5514A
C55x DSP
C5515A
C55x DSP
Peripherals
LCD I/F
Peripherals
SAR ADC
1 ANA LDO
SDRAM I/F
320 KB
SDRAM I/F
FFT CoP
LCD I/F
320KB
SDRAM I/F
1 ANA LDO
3 LDOs
Power Mgmt
256KB
SDRAM I/F
SAR ADC
In Production
256KB
FFT CoP
3 LDOs
Power Mgmt
Security Options available with secure ROM and secure bootloader
C5515 Device Nomenclature
C5504/C5505/14/15 Extensive Power Modes
Industry’s Lowest Power 16-bit DSP
• Active Power Mode
– 75% DMAC + 25% ADD typical data
• 0.15mW/MHz @ 1.05V, 0.22mW/MHz @1.3V
• Standby Power Modes
– With SARAM retention mode
• 0.15mW @ 1.05V, 0.28mW @ 1.3V
– With DARAM retention mode
• 0.23mW @ 1.05V, 0.40mW @ 1.3V
– With SARAM and DARAM active mode
• 0.26mW @ 1.05V, 0.44mW @ 1.3V
• “RTC only” Low Power mode
– New in C5504/05/14/15 (Rev A silicon)
TMS320C55xx power numbers comparison
Based on 75% DMAC + 25% ADD Test Case
C5501/02
Device
Production
C5509A, C5507,
C5503
Power Consumption
Sam pling
200 MHz @ 1.6V
0.96m W/MHz
300 MHz @ 1.26V
1m W/MHz
C5510A
200 MHz @ 1.6V
0.9m W/MHz
In Development
C5509A, C5507,
C5503
Future
144 MHz @ 1.35V
C5509A, C5507, 0.69m W/MHz
C5506, C5503
108 MHz @ 1.2V
0.54m W/MHz
C55X4/5*
C55X4/5
120 MHz @ 1.3V
0.22m W/MHz
~4x improvement in power consumption
60 MHz @ 1.05V
0.15m W/MHz
* Based on DSP PLL at 100 MHz; DSP at 1.3 C Vdd; Room Temp (25 °C), CLOCK_OUT
disabled, 75% DMAC + 25% ADD (high data switching)
Performance
Energy efficiency of FFT HWA
FFT w ith HWA
CPU (Scale)
HWA VS. CPU
FFT + BR
Cycles
Energy/
FFT
(nJ/FFT)
x Times
Faster
(Scale)
x Times
Energy
Efficient
(Scale)
Complex
FFT
FFT + BR
Cycles
Energy/
FFT
(nJ/FFT)
8 pt
92+38 =130
23.6
196+95 = 291
95.1
2.2
4.0
16 pt
115+55 = 170
32.1
344+117=461
157.1
2.7
4.9
32 pt
234 +87 =321
69.5
609+139=748
269.9
2.3
3.9
64 pt
285+151 =436
98.5
1194+211=1405
531.7
3.2
5.4
128 pt
633+279 =912
219.2
2499+299=2798
1090.4
3.1
5.0
256 pt
1133+535=1668
407.2
5404+543=5947
2354.2
3.6
5.8
512 pt
2693+1047=3740
939.7
11829+907=12736
5097.5
3.4
5.4
1024 pt
5244+2071=7315
1836.2
25934+1783=27717
11097.9
3.8
6.0
FFT HWA is 4 ~ 6x more energy efficient and 2.2 ~ 3.8x faster
Note:
1.
BR = Bit-Reverse Operation
2.
Power measurement Condition: at room temp only, all peripherals are clock gated, measured at Vddc
C5504A/05A improvements from VC5504/05 – 1/2
• Power up sequencing (Core first and then I/O) is not
required in the C5504A/C5505A.
• SAR reset bit (bit2) of the PRCR register(0x1C05) has
been added.
• “Divide-by-4” added to the PLL output divider.
• mSDRAM Support
– Available in C5504A/C5505A, was not available in VC5504/VC5505.
• DMA Double Buffering Capability
– Not possible to support double buffering (ping-pong buffer) in
VC5504/VC5505. DMA needs to be configured by CPU at every new DMA.
This could cause data loss at high transfer data rate.
– A ping-pong buffer has been added in C5504A/C5505A.
C5504A/05A improvements from VC5504/05 – 2/2
• Word/Byte swap issue (Advisory 1.4.1)
–
–
–
–
DPORT word swap remov ed
Endianess of EMIF changed to big endian (hardcoded)
Endianess of MMC/SD changed to big endian (software controllable)
Endianess of USB DMA changed to big endian (hardcoded)
• RTC positive compensation did not work for compensation values that are
multiples of 10 (Advisory 1.4.2). This has been fixed in C5504A/C5505A.
• Invalid I2S OUERRFL Error Report at First Frame has been fixed (Advisory
1.4.3).
• DMA in H/W Sync Mode, Auto Reload Bit Overrides Enable Bit has been fixed
(Advisory 1.4.6).
• DMA: Hardware Event can trigger DMA data transfer in S/W control mode has
been fixed (Advisory 1.4.7).
Note: The advisories mentioned above are with reference to the VC5505/04
Errata (SPRZ281A).
Tools, Software and Support
Get to Market Fast with
Best-in-Class Tools and Development Platforms
Code Composer
Studio™ IDE
Free CCS v4 with
XDS100 emulator
Allows designers of
all experience levels
to move quickly
through application
development
• Design
• Code and build
• Debug
• Analyze
• Tune
• Eclipse based
Evaluation Modules
System
Development Kits
Simple Application
Development Board
eZDSP5505 $49
eZDSP5515 $79
Solving the Problem
from the Sensors
• Medical Development Kit
Fully Featured EVM
C5515 EVM $395
ECG
Digital Stethoscope
Pulse Oximeter
• Fingerprint Biometrics
Development Kit $79
Extensive Support: Wiki, E2E Forums, On-line community
http://tiexpressdsp.com/index.php/C5000
http://e2e.ti.com/support/dsp/tms320c5000_pow er-efficient_dsps/default.aspx
Begin development today with C5515 EVM
Hardware
Connectivity
• TMS320C5515 fixed point low power DSP
• TLV320AIC3204 Stereo codec
• Analog front end connectors
• Integrated NAND/NOR/mSDRAM
•USB 2.0 slave port high speed
• Real-time pow er monitoring circuit
•SD/MMC, I2C, SPI, I2S, UART
• OLED color LCD display (128x128 pixels)
•Two expansion connectors
• I2C and SPI EEPROMs
• 10 user defined push button switches
•Stereo line in (2) /out (1), headphone out (1)
and microphone in (L/R)
• Embedded JTAG emulation via mini USB
interface and external JTAG emulation interface
•CE-ATA connector
•External oscillator socket
• Battery Holder (For 2 AAA, not included)
Software
• Chip Support Library
• Code Composer Studio IDE™ Rev 3.3
Documentation
• Quick Start Installation Guide
•Technical Reference Manual
• Schematics
Evaluation capability of
C55X4/5 low power DSP
Several memory options
Embedded emulation on
board though A-mini B
USB cable to save cost
Common platform for
ECG, Digital Stethoscope
& Pulse Oximeter Medical
Development Kits
•BT/Chipcon connector
Order Information
•Part Num ber:
TMDXEVM5515
• Price: $395
• Available now
Blue: Improvements in TMDXEVM5515 compared to TMDXEVM5505
eZdsp5505 USB stick development tool
Expansion
Connector
LED 18 Signals
AIC3204
SAR ADC i/ps
VC5505 DSP
To PC
or
Laptop
USB
Connector
TMS320VC5505 DSP
On-board emulation
Integrated audio codec
Audio line out/line in
connectors
• Extension connector
(UART/SPI/I2S/I2C/GPIO)
• Simple form factor plugs
into any USB host port
• Simplifies development
tools setup by eliminating
power and interface cables
•
•
•
•
XDS100
JTAG
emulator
GPIOs
Stereo Headphone
In
Out
EEPROM
(64kB)
Begin development today with eZdsp tool
Community
Hardware
• Online community
• Code examples with
software
• Promotions for example
contribution
• TMS320VC5505 fixed
point low power DSP
• TLV320AIC3204 stereo
codec
• I2C EEPROM (64kB)
• Embedded XDS100
JTAG emulation
• Expansion connector
Software
• Chip support library
• Code Composer Studio IDE™
rev 4.0
Documentation
• Quick Start Installation Guide
• Technical Reference Manual
• Schematics
• code.google.com/p/c5505-ezdsp
Sample demos
Evaluation capability of
VC5504/05 low power DSP
Embedded XDS100
emulation
Online community
•
•
•
Audio tone gen
Digital Filtering
Music/Audio special Efx
Order information
• Part Number:
TMDX5505eZdsp
• Price: $49
• Order entry open: NOW
C5515 eZdsp USB Stick Development Tool
USB 2.0
Slave Port
JTAG
USB
Connector
XDS100
JTAG
emulator
Color
LEDs
LCD
Screen
GPIO Push
Buttons
Bluetooth®/
Chipcon
Expansion
C5515 DSP
NOR Flash
Expansion
Connector
60 Signals
AIC3204
Codec
•
•
•
•
•
•
•
•
•
•
•
Micro-SD Stereo Headphone
(bottom)
In
Out
TMS320C5515 DSP
On-board emulation
Integrated audio codec
Audio line out/line in
connectors
USB 2.0 Slave Port
Micro-SD Slot
4 MByte NOR Flash
Extension connectors
(UART/SPI/I2S/I2C/GPIO/SD)
Simple form factor plugs
into any USB host port
Simplifies development
tools setup by eliminating
power and interface cables
$79
C5505/04/15/14 CSL
• Benefits of CSL
–
–
–
–
–
Peripherals ease of use
Shortened development time
Portability
Hardware abstraction
Standardization and compatibility among devices
• Two Layers of Abstraction
– CSL Register Level
– CSL Function Level
• Reference for Customer Driver Development
– All source code for CSL is open to customers
– Most of CSL is written in C
• CCS 3.3 and CCS 4.0 Compatible
– Examples are provided for CCS4.x and CCS3.3
• http://processors.wiki.ti.com/index.php/Chip_Support_Library
C5505/04/15/14 CSL Architecture
USER
TASK 1
USER
TASK 2
CSL API
DMA
RTC
SPI
…
USB
Function Level
DMAr
RTCr
SPIr
…
USBr
Register Level
C5505/04/15/14 Hardware
Configuration Functions
Csl_ files
Register & Bit Definitions
Cslr_ files
What is included in C5505/15 CSL
• Release Notes
• Peripheral Drivers with Source Code
– DAT, DMA, EMIF, GPIO, GPT, I2C, I2S, INTC, LCD, MMC/SD, NAND, PLL,
RTC, SAR, SPI, UART, USB, WDT
• C5505/15 CSL Pre-built library and header files
• APIs documentation
• Example Code for all peripherals including Project Files for CCS 4.x
and CCS3.3
• Example Application Code Using CSL
– USB Mass Storage Class on SD card
– USB Audio Class
– FAT16/32 on SD card
Online Community
• Where can I get support?
• C5515 Product Page
– DSP Datasheets, User’s Guides, App Notes, Simulation Models, Videos
– http://focus.ti.com/docs/prod/folders/print/tms320c5515.html
• Spectrum Digital C5515 Support Site
– Quick Start Guide, Technical Reference, Schematics, Layout, GEL Files
– http://support.spectrumdigital.com
• TI E2E™ Forums
– Browse, Search, Subscribe to existing posts
– Free support from engineers and expert users
– http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/default.aspx
• TI Embedded Processors Wiki
– Growing documentation, User contribution
– http://processors.wiki.ti.com/index.php/Category:C5000
C5505/15 Architecture
C54x vs C55x Architecture
16-bit data busses
B Bus (Coefficient)
C Bus
D Bus
D Registers Interconnect
ACC Buss
Shifter
MAC-0
MAC-1
40-Bit ALU
16-Bit ALU
Splittable
AC0
AC1
AC2
AC3
Three
Address Generators
Y
X
CC
DR0
DR1
DR2
DR3
Resources
on C54x
Added to
C55x
BAB
DAB
FAB
CAB
EAB
E Bus
XAR0
XAR1
XAR2
XAR3
XAR4
XAR5
XAR6
XAR7
XCDP
XDP
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
CDP
-
F Bus
5 Address Busses
24-bit
C55x Core Rev 2 Architectural Overview
C5501/02/03/06/07/09A/10
Data Read busses BB (16-bits) , CB (16-bits), DB (16-bits)
Data Read Address busses BAB, CAB, DAB (3x24)
Program Address bus PAB (24)
PROGRAM FLOW
Prog.
Read bus
PB
DATA FLOW
Program Counter
Instruction Buffer
Queue
(64x8 bit)
RET A
32
Auxiliary Registers[0:7]
Data Registers [0:3]
Coefficient Dat a Pointer
Smem/Xmem
48 bits
Status Registers
Program Flow
Ymem
Cmem
Pipeline Protection Unit
Interrupts
Data Write Address busses EAB, FAB (2x24)
Data Write busses EB, FB (2x16)
MAC
AC0 AC1 AC2 AC3
40 bit ALU
Prog Address Gen
Instruction Decoder
Controller
2nd
1st
instruc
instruc
tion
tion
MAC
shifter
Transition Regs.
Bit Operations
ALU 16-bit
C55x Core Rev 3 Improvements
(C5505/04/15/14)
Data Read busses BB (32-bits) , CB (16-bits), DB (16-bits)
Data Read Address busses BAB, CAB, DAB (3x24)
Program Address bus PAB (24)
PROGRAM FLOW
Prog.
Read bus
PB
DATA FLOW
Program Counter
Instruction Buffer
Queue
(128x8 bit)
RET A
32
Auxiliary Registers[0:7]
Data Registers [0:3]
Coefficient Dat a Pointer
Smem/Xmem 23-bit
64 bits
Status Registers
Program Flow
Ymem 23-bit
Cmem 23-bit
Pipeline Protection Unit
Interrupts
Data Write Address busses EAB, FAB (2x24)
Data Write busses EB, FB (2x16)
MAC
AC0 AC1 AC2 AC3
40 bit ALU
Prog Address Gen
Instruction Decoder
Controller
2nd
1st
instruc
instruc
tion
tion
MAC
shifter
Transition Regs.
Bit Operations
ALU 16-bit
C55x Rev3 Instruction Buffer Unit
Program Read Bus (PB) (32)
Improved Code Density
Instruction Buffer Queue
(128x8 bit)
Lower Powe r
64 bits
Instruction Decoder Controller
2nd instruction
PU
AU
DU
Explicit & "Soft-Dual" 48, 56, and 64-bit parallel
instructions
Program fetched in packets of 32-bits from memory
Inner loops buffered, pre-decode
Support global and local repeat block
Higher Performance
1st instruction
Automatically scalable instruction word 8, 16, 24, 32, 40, and 64-bit instruction formats
Predicated instructions
Program memory byte addressable
Protected pipeline
Independent 4 byte packet fetched every cycle (if
zero wait states)
Determines parallelism and dispatches execution to
three processing units
Two instructions in parallel can be executed per
clock cycle
Predictive branching intelligence enables faster
processing
C55x Program Flow Unit
Data-read data buses CB, DB (16 bits of data each)
Program-read address bus PAB (24 bit address each)
Increased Efficiency
Program Counter
IU
LCRPC
Prog Address Gen
Status Registers
Program Flow
Pipeline Protection Unit
Interrupts
Data-write data buses EB, FB (16 bits of data each)
Program memory byte addressable
Interruptible block and single repeats (2
block, 1 single)
Conditional execution instructions(except
goto, switch, trap, call, repeat, intr, return,
blockrepeat, and reset.)
Reduction in Programming Complexity
Protected pipeline
Higher Performance
1 x 32-bit, 4 x 16-bit data busses
(3R, 2W)
6 x 24 bit address busses
1 x 32 bit program bus
C55x Address Data Flow Unit
Data-read data buses (3)
(16-bits of data each)
Data-read address buses (3) (23-bit address each)
8 23-bit Address Registers
4 16-bit Data Registers
23-bit Coefficient Data Pointer
Sme m/Xme m 23-bit
Lower Power
Increased Efficiency
Yme m 23-bit
Cmem 23-bit
ALU 16-bit
Data-write data buses EB, FB (16 bits of data each)
Data-write address buses (2) (23-bit address each)
One generic 16-bit ALU with shifting capabilities allow
simpler arithmetic operations to be performed outside
multiply unit
No alignment constraint on data page and circular
buffers
8 23-bit address registers (AR[7:0])
4 generic temporary registers (T[3:0]) 23-bit dedicated
address generation arithmetic units
3 independent circular buffers
Interruptible block and single repeats (2 block, 1
single)
Conditional execution instructions
C55x Data Computation Unit
Data-read data buses or operand from data registers
32-bit
16-bit
16-bit
MAC
MAC
Lower Power
AC0
AC1
AC2
AC3
Higher Performance
40 bit ALU
40-bit
shifter
Transition Regs.
Bit Operations
Data-write data buses EB, FB (16 bits of data)
Parallelism minimizes cycle count per task
Program memory byte addressable
Protected pipeline
32-bit B Bus provides fourth independent value for
dual MAC and other instructions
Four 40-bit generic (Accumulator) Registers
Single cycle 17x17 dual MAC hardware
40-bit ALU, splitable to 2 x “16-bit” ALU
Rounding option for multiply and store instructions
(2 rounding modes)
Barrel shifter (extended range -32/+31)
Saturation range control
C55x Pipeline
Pab
Ram pb
Ftch
Dec
Adr
Ac1
Ac2
Read
Ex
Write
Pipeline Stage description:
Fetch:
Read four bytes from program memory via PB, and load the four bytes into the instruction buffer
queue.
This prefetch is an independent operation from the execution pipeline.
1: Decode : Read up to six bytes from the instruction buffer queue.
Decode an instruction pair or a single instruction.
Dispatch instructions to the program flow unit (P unit),
the address-data flow unit (A unit), and the data computation unit (D unit).
2: Address : Compute data-space address(es) in the data-address generation unit (DAGEN).
Modify pointers and repeat counters as required.
Compute the program-space addresses for PC-relative branching instructions.
3: Access 1 Send addresses for read operands on BAB, CAB, and DAB.
4: Access 2 One cycle for memory access
5: Read
Transfer an operand or operands to the CPU via CB (Ymem operand),
DB (Smem or Xmem operand), CB and DB (Lmem operand), and BB (Cmem operand).
Generate address(es) for operand write(s) and send them on EAB and FAB.
Evaluate conditional operators
6: Execute Execute data processing instructions that are executed in the A unit and the D unit.
Store result of computation into registers.
7: Write
Data sent to memory / memory mapped accesses
Memory Map
Start Byt e
Address
( Hex)
Start
Word
Address
(H ex)
Mem ory Bank
Size In
Bytes
000000h
000000h
Mem ory Map ped R egisters
192 bytes
0000C0h
000060h
DARAM0
002000h
001000h
DARAM1
8K – 192
bytes
8K bytes
004000h
002000h
DARAM2
8K bytes
006000h
003000h
DARAM3
8K bytes
008000h
004000h
DARAM4
8K bytes
00A000h
005000h
DARAM5
8K bytes
00C000h
006000h
DARAM6
8K bytes
00E000h
007000h
DARAM7
8K bytes
010000h
008000h
SAR AM 0
8K bytes
012000h
009000h
SAR AM 1
8K bytes
014000h
00A000h
SAR AM 2
8K bytes
016000h
00B000h
SAR AM 3
8K bytes
018000h
00C000h
SAR AM 4
8K bytes
01A000h
00D000h
SAR AM 5
8K bytes
01C000h
00E000h
SAR AM 6
8K bytes
01E000h
00F000h
SAR AM 7
8K bytes
020000h
010000h
SAR AM 8
8K bytes
022000h
011000h
SAR AM 9
8K bytes
024000h
012000h
SAR AM10
8K bytes
026000h
013000h
SAR AM11
8K bytes
028000h
014000h
SAR AM12
8K bytes
02A000h
015000h
SAR AM13
8K bytes
02C000h
016000h
SAR AM14
8K bytes
02E000h
0170 00h
SAR AM15
8K bytes
030000h
018000h
SAR AM16
8K bytes
032000h
019000h
SAR AM17
8K bytes
034000h
01A000h
SAR AM18
8K bytes
036000h
01B000h
SAR AM19
8K bytes
038000h
01C000h
SAR AM20
8K bytes
03A000h
01D000h
SAR AM21
8K bytes
03C000h
01E000h
SAR AM22
8K byt es
03E000h
01F000h
SAR AM23
8K bytes
040000h
020000h
SAR AM24
8K bytes
042000h
021000h
SAR AM25
8K bytes
044000h
022000h
SAR AM26
8K bytes
046000h
023000h
SAR AM27
8K bytes
048000h
024000h
SAR AM28
8K bytes
04A000h
025000h
SAR AM29
8K bytes
04C000h
026000 h
SAR AM30
8K bytes
04E000h
027000h
SAR AM31
8K bytes
050000h
028000h
800000h
400000h
C00000h
600000h
E 00000h
700000h
F00000h
780000h
FE 0000h
7F 0000h
E xt er na l SD RA M Me mor y
CS 0/1
Ext er n al Asy nc hr on ous
Me mo ry CS 2
Ext er n al Asy nc hr on ous
Me mo ry CS 3
Ext er n al Asy nc hr on ous
Me mo ry CS 4
Ext e rn al Asy nc h ron ous
Me mo ry CS 5
S ARO M0
7.6875M
byt es
FE 8000h
7F 4000h
S ARO M1
32K byte s
FF 0000h
7F 8000h
S ARO M2
32K byte s
FF 8000h
7F C000h
S ARO M3
32K byte s
4M byt es
2M byt es
1M byt es
896K byt es
32K byte s
Parallel Execution: Operators
• Add the following instruction pairs
to add more computational power
and flexibility with the D-Unit.
ALU || MAC
SHIFT || MAC
ALU || SHIFT
MAC || MAC
• Relax soft dual parallelism rules in
the DAGEN. Allow:
Smem_R || Lmem_W
Lmem_R || Smem_W
Smem_RW || Smem_R
Smem_RW || Smem_W
X
X
X
X
X
X
Parallel Execution: Busses
Bus connections to registers/operators in three main units
Note: C55x Rev. 3 has KAB2 & KDB2 buses for transport of
constants to A & D from I ⇒ KAB1||KAB2 & KDB1||KDB2
C55x Rev 3.0 Speed-up in Typical Algorithms
32-bit
B bus
16-bit complex
vector mpy
32-bit extended
precision vector
mpy
16-bit real
vector mpy
16-bit real
vector dot
product
parallel
store
64-bit
dispatch
C55x
Benchmark
rev 2.0 rev 3.0
3N
2N
4N
3N
1.5N
1N
1N
0.5N
C5505/15 Peripherals
Power Management
•
3 LDOs:
–
–
–
Core LDO (1.05 or 1.3V) with min shutdown
current of 180mA
POR and SAR LDO (1.3V) with min shutdown
current of 4mA
USB Analog (1.3V) LDO with min shutdown
current of 18mA
•
DSP Core LDO can be shutdown by software.
•
DSP Core LDO can be enabled by RTC alarm
or external WAKEUP pin.
12/13/2010
TI Proprietary - NDA Confidential
40
C5505 Parallel Interface
mSDR
Async
60
NAND
External
Parallel Bus
GPIO
12/13/2010
TI Proprietary - NDA Confidential
C5505 External Interface:
Asynchronous:
21-bit address with A[20:13] individually selectable as
GPIO. Each GPIO supports interrupt capabilities and pulldowns
16-bit data
2 Chip Selects
Programmable cycle timing for each chip select
NAND:
8 and 16-bit data bus width
1-bit ECC for 8-bit NAND Flash
4-bit ECC for 8 and 16-bit NAND Flash
4 NAND Chip Selects
Programmable cycle timing for each chip select
Mobile SDRAM (mSDR):
Supports 2 and 3 CAS Latencies
Supports 1, 2, and 4 internal banks
Supports 256, 512, 1024, and 2048-word page sizes
Supports 4 and 8 burst lengths
41
C5505 Serial Busses
GPIO
6
MMC/SD
I2S
GPIO
6
MMC/SD
I2S
I2 C
2
Two Serial Interface Busses:
Serial 0:
6 pins of MMC/SD
4 pins of I2S and 2 GPIO
6 pins GPIO
Serial 1:
6 pins of MMC/SD
4 pins of I2S and 2 GPIO
6 pins GPIO
I2S
Bidirectional clock and frame sync. One output and one input
data lines.
8, 10, 12, 16, 20, 24, or 32-bit MSB-first, left justified
transfers
Programmable clock and frame sync polarities
Overrun and underrun error detection
Loopback mode
Data packing modes into a 32-bit word
MMC/SD
• IIC:
Supports a Multimedia Card (MMC), a Secure Digital
7-bit or 10-bit addressing
Memory Card (SD), or a Secure Digital I/O Card (SDIO)
Multi-Master and slave mode
The capability to use either the MMC/SD protocol or the SPI
Up to 400Kbits
protocol
Programmable frequency for the operation of the MMC/SD
controller
Programmable frequency for the clock that controls the
timing of transfers between the MMC/SD controller and the
memory card.
12/13/2010
TI Proprietary - NDA Confidential
42
C5505 Serial Busses (cont.)
GPIO
SPI
6
7
13
21 13
LCD
LCD Bridge :
• Supports single panel mode display with size from 16 to 1024 pixels, total video frame up to 1024 x
1024
• Supports passive (STN) with 16, 256, or 3375 colors or 15 grayscale level for monochrome screen
• Supports active (TFT) with up to 4096 colors active
• Supports up to 16-bits per pixel
• If less than 8-bits per pixel, then the other 8-bits are available for UART, I2S, SPI, and GPIO.
8
8
GPIO
UART
4
8
I2S
I2S
SPI
4
SPI:
Programmable data size: 1-32
bits
Programmable frame length:
1-4096 words
Programmable CS to data
delay: 0-3 clocks
Programmable clock and CS
polarities
Frame and/or word interrupts
Loopback mode
12/13/2010
TI Proprietary - NDA Confidential
UART:
16-bit FIFO, 1, 4, 8, or 16 byte selectable receiver FIFO
trigger level for autoflow control and DMA
Programmable auto-rts and auto-cts for autoflow control
Frequency pre-scale values from 0 to 65,535 to generate
appropriate baud rates
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
False start bit detection
Line break generation and detection
Loopback controls for communications link fault isolation
Break, parity, o verrun, and framing error simulation
Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)
43
DMA Controller
• 4 independent DMAs with 4 Channels each
–
–
–
–
–
–
2 channels actively transferring at a given time
Round robin arbitration scheme between all channels of a DMA controller
Auto increment source and destination
Peripheral generate DMA events that dictate when the DMA can transfer
1, 2, 4, 8, 16, or 32 FIFO depth per channel
Ping-Pong Buffering
10-bit SAR A/D
•
Features:
– 4 channel 10-bit Successive Approximation Converter
– Measure battery voltage, internal analog voltage, and volume control by measuring
across a potentiometer.
–
4-Wire Resistive Touch Screen coordinate pair measurement.
–
General purpose outputs (drive high or drive low (except for GPAIN0 which only
drives low)
–
General purpose voltage measurement
–
Continuous and single cycle conversion modes
–
–
Interrupt driven or polling conversion
Internal configurable bandgap reference voltages of 1V or 0.8V
–
Software controlled power down
–
Individually configurable general purpose outputs that drive high or low
–
Conversion rate 32 clock cycles with a 2MHz clock
12/13/2010
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45
C55x FFT Hardware Coprocessor
•
Support 8 to 1024-point real- and
complex-valued FFT ’s
•
Internal twiddle factor generator for
optimal use of memory bandwidth and
more efficient programming.
•
Basic and software -driven auto-scaling
feature provides good precision vs. cycle
count trade -off.
•
Single-stage and double-stage modes
enable to compute one or two stages in
one pass, and thus to better handle odd
power of two FFT widths.
•
A programmable scaled or not -scaled
butterfly operation (default is scaled).
•
The capability to do FFT or Inverse FFT
(default is FFT).
12/13/2010
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46
Watchdog Timer
•
The purpose of Watchdog timer is to prevent system from locking up if the software becomes trapped in
loops with no controlled exit.
•
The watchdog timer requires a special service sequence to be executed periodically. Without this
periodic servicing, the watchdog timer counter reaches zero and times out.
•
The watchdog output can be selected to be connected to the local hardware reset, NMI (non-maskable
interrupt), timer interrupt, or not connected. This allows maximum flexibility for utilizing the watchdog as
required by the particular application.
•
The watchdog timer consists of a 16 bit counter and a 16-bit pre-scalar, and supports up to 32 bit
dynamic range. Out of reset, the watchdog is disabled by default, this allows a flexible period of time for
code to be loaded into the on-chip memory.
•
Once the watchdog is enabled, it can not be disabled by software, but can be disabled by watchdog
time-out and hardware reset. A special key sequence is provided to prevent watchdog from being
accidentally serviced while the software is trapped in a dead loop or in some other software failures.
12/13/2010
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47
Real Time Clock (RTC)
•
Allows implementation of clock and calendar
functions
• 100 year calendar up to 2099
• Count milliseconds, seconds, minutes,
hours, days, day of the week, date month,
and year with leap year compensation
• BCD representation of time calendar and
alarm
• 24-hour clock
• Every millisecond, second, minute, hour, or
day alarm interrupt
• Alarm interrupt: precise time of day
12/13/2010
TI Proprietary - NDA Confidential
•
Support external 32K oscillator
•
Time compensation registers
•
Millisecond time correction/round-up
•
Separate power supply, allows DSP core to be
completely powered down while RTC keeps
track of time.
•
Wakes up DSP LDO upon fixed alarm,
periodic alarm, or external interrupt
48
I2S
•
Up to 4 2-ch I2S ports with the following features:
•
Full-duplex (transmit and receive) dual-channel communication for each I2S module
•
Double buffered data registers that allow for continuous data stream
•
Most significant bit (MSB) - first data transfers
•
I2S/Left-justified and DSP data format with a data delay of 1 or 2 bits
•
Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits
•
Ability to sign-extend received data samples for easy use in signal processing algorithms
•
Packing mode to transmit/receive multiple samples of data before interrupting CPU or DMA
•
Programmable polarity for both frame synchronization and bit clocks
•
Digital loopback of data from transmit to receive register(s) for application code debug
•
Stereo (in I2S/Left-justified or DSP data formats) or mono (in DSP data format) mode.
•
Programmable divider for serial data clock (bit-clock) generation when I2S module is used as the
master device
•
Programmable divider for frame sync generation when I2S module is used as the master device
•
Detection of over-run, under-run, and frame-sync error conditions
12/13/2010
TI Proprietary - NDA Confidential
49
I2C
•
Compliance of Philips I2C specification (reference to Philips I2C specification v2.1)
•
Byte format transfer
•
7-bit or 10-bit addressing modes
•
Multi-master transmitter/slave receiver mode
•
Multi-master receiver/slave transmitter mode
•
Free data format
•
I2C data transfer rate of from 10kbps up to 400kbps (Philips I2C rate)
•
Has one read and one write DMA event that can be used by the DMA
•
Module operates from 6.7MHz to 13.3MHz
12/13/2010
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50
MMC/SD
•
2 ports, each one supporting a MultiMediaCard (MMC) or Secure Digital Memory Card (SD card).
•
A programmable frequency of the clock that controls the timing of transfers between the MMC/SD
Controller and memory card.
•
256 bit Read/Write FIFO to lower system overhead.
•
Signaling to support DMA transfers
•
50 MHz maximum clock to SD (spec. V1.1)
12/13/2010
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51
LCD Bridge
•
LCD Interface Display Driver
– support a variety of MPU-like interface requirements which are commonly used in low-end LCD
character displays.
– support the signal function and timing requirements for the most prevalent parallel LCD display
interface standards – MPU68, MPU80, MPUXX, and Hitachi HD44780U.
•
LCD Raster Controller
– Support raster-type LCD displays that require a constant flow of data at a ~70 Hz Frame rate.
– Displays supported: passive and active color, and passive and active monochrome
– Passive STN mode allows a total of 3375 possible colors, allowing any 16, 256 or 3375 colors to
be displayed in each frame, as well as 15 grayscale levels for monochrome screens
– Active TFT mode allows 4096 possible colors, in the 16 BPP mode, up to 64K possible colors
– Screen size from 16x16 up to 1024x1024 pixels
– Frame, line and pixel clocks, AC-bias drive signal
– 4, 8, 12 and 16 bit-per-pixel display modes and dithering mode
12/13/2010
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52
USB 2.0 Slave
•
Supports USB 2.0 peripheral at speeds HS (480 Mb/s) and FS (12 Mb/s)
•
Supports all modes of transfers (control, bulk, interrupt)
•
Supports 4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
•
Supports USB Session Resume (SRP) and Host Negotiation (HNP)
•
Includes a 4K endpoint FIFO RAM, and supports programmable FIFO sizes
•
Includes a DMA sub-module that supports 4 TX and 4 RX channels of CPPI 3.0 DMAs
•
The DMA interfaces to the system bus through a CBA 3.0 VBUSP master port using incrementing
addressing mode and up to 64 byte burst size
•
Includes RNDIS mode for accelerating RNDIS type protocols using short packet termination over
USB
12/13/2010
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53
Bootloader
C5505 Bootloader
Supports System Initialization from non-encrypted and encrypted content utilizing a 64-bit device ID and 64-bit manufacturer key from:
•
•
External Parallel Bus:
–
NAND
• non-encrypted
• encrypted
–
NOR
• non-encrypted
• encrypted
Serial Bus:
–
–
–
–
–
SPI EEPROM
• non-encrypted
• encrypted
I2C EEPROM
• non-encrypted
• encrypted
MMC/SD with FAT16/32
• encrypted
UART
• encrypted
USB
• Encrypted
12/13/2010
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55
C5505 Unsecure Boot Table
Word
Content
1
Boot Si g n at ur e (16 -bits )
Valid Data Entries
0x0 9 AA, 0 x09 5A
2 :3
En tr y P oint ( 32 -b its)
Byte a dd re ss to beg in e xec ut io n
4
Reg is te r Co nfigur a ti on Coun t (16 -bits , N = c ount )
1 to 2 16 - 1
Fir st reg ist e r add re ss followed b y ad dr es s conten ts o r 0 xFFF F
followed b y del ay coun t
.. .
4 +2N
La s t reg ist er add r es s followed by conten t s o r 0 xFFF F followed
b y de lay coun t
5 +2N
Word Count ( size) o f fir s t dat a block (16 -bits )
S ize is the n umbe r o f v alid (n o n -pad ) d a ta wor d s i n blo ck
M = (s iz e + 2) rou n de d u p to n eares t m u lti p le o f 4
6 :7
(+2N)
Dest inat ion add re s s to loa d the fi rs t s o ur ce b lock ( 32 -bits )
8 +2N
Fir s t w o rd of fir st d a ta b lock (16 -b its )
5+2N +
M
La s t wo r d o f fi rs t dat a blo ck , often pa d d a ta (pad de d to 8-b yt e
bo u nd ar y)
1 to 216 -1
16 -bit w or d ad dr ess
(0x00006 0 to 0 x0 97 FFF)
.. .
.. .
X
Word Count ( size) o f fir s t dat a block (16 -bits )
S ize is the n umbe r o f v alid (n o n -pad ) d a ta wor d s i n blo ck
N' = (siz e + 2) rou n de d u p to n eares t m u lti p le o f 4
1 to 2 16 -1
X+1
Dest inat ion add re s s to loa d the l as t s o urc e blo ck (32 -bit s)
16 -bit w or d ad dr ess
(0x00006 0 to 0 x097 FFF)
X+3
Fir s t w o rd of la s t dat a blo ck
.. .
X+N'
La s t wo rd o f la st d a ta blo ck , us u a lly pa d data ( pad d ed t o 8 by te b ou n d a ry )
X+N '+1
Zer o w o rd. N ote t h at if mor e th an one s o ur ce blo ck wa s r e ad ,
wo rd X+N ' sho wn a bov e wo u ld be th e la s t w ord of the las t
s our ce b lock . Eac h blo ck w o u ld hav e the for mat s h ow n in the
s ha de d ent ries.
0x0000
Secure Bootload vs ROM code
• Secure Bootload
–
–
–
–
–
–
Field upgrades through USB Secure bootload.
No additional costs.
No minimum volume.
Encrypted code can be bound to a specific device.
Simple JTAG disability b y grounding JTAG pins in the board, under the package.
Used by customers in MP3 players since 2000.
• ROM Code
– Fast start-up, no need to boot.
– Field upgrade possible by patching ROM routines and bootloading encrypted code. Adds extra level of indirection
on ROM routines.
– JTAG must be disabled at factory to protect contents.
Instruction Set
Addressing Modes
• Absolute:
– k16: 16-bit unsigned constant *abs(#k16)
– k23: 23-bit unsigned constant *(#k23)
– I/O: 16-bit unsigned constant *port(#k16)
• Direct: uses DP, SP
– Paging scheme with base pointer
XDP = #0
T2 = @(AC0_L)
• Indirect:
–
–
–
–
Smem: single word (16-bit) access
Lmem: long-word (32-bitss) access
Xmem and Ymem: rwo simultaneous single word access using C and D bus
Cmem: single word access using B-Bus
Indirect Addressing (single access)
•
Smem addressing options:
*ARn
*ARn+
*ARn*+ARn
*-ARn
*(ARn + AR0)
*(ARn - AR0)
*(ARn + T0), *(ARn + T1)
*(ARn - T0), *(ARn - T1)
*ARn(AR0)
*ARn(T0), *ARn(T1)
*(ARn + AR0B)
*(ARn - AR0B)
*(ARn + T0B)
*(ARn - T0B)
*ARn(#k16)
*+ARn(#k16)
post ARn = ARn + 1
post ARn = ARn - 1
pre ARn = ARn + 1
pre ARn = ARn - 1
post ARn = ARn + AR0
post ARn = ARn - AR0
post ARn = ARn + T0
post ARn = ARn - T0
post ARn =
post ARn =
post ARn =
post ARn =
ARn
ARn
ARn
ARn
+ AR0 bit reversed
- AR0 bit rev ersed
+ T0 bit reversed
- T0 bit rev ersed
pre ARn = ARn + k16
Cmem options:
*CDP
*CDP+
*CDP*CDP(#k16)
*+CDP(#k16)
post CDP = CDP + 1
post CDP = CDP - 1
post CDP = CDP + k16
pre CDP = CDP + k16
Indirect Addressing (dual/triple access)
• Xmem and Ymem options:
*ARn
*ARn+
*ARn*(ARn + AR0)
*(ARn - AR0)
*(ARn + T0), *(ARn + T1)
*(ARn - T0), *(ARn - T1)
*ARn(AR0)
*ARn(T0), *ARn(T1)
•
post ARn = ARn + 1
post ARn = ARn - 1
post ARn = ARn + AR0
post ARn = ARn - AR0
post ARn = ARn + T0
post ARn = ARn - T0
Cmem options:
*CDP
*CDP+
*CDP*(CDP + AR0)
*(CDP + T0)
post CDP = CDP + 1
post CDP = CDP - 1
post CDP = CDP + AR0
post CDP = CDP + T0
Circular Addressing
Buffe r must be alinged to a power of two greater than size:
2buffer_size > buffe r_start_address
Stack
• Two pointers: decrement before push
– SP: data stack
– SSP: system stack
• Program Flow Registers:
– PC: Program counter
– RETA: Return Address Register, used in Fast-Return
– CFCT: Control-Flow Context Register, used in Fast-Return
• Stack options:
– Dual 16-bit stack with Fast-Return:
• RETA and CFCT used for fast return
• Independent SP and SSP
RST:
.ivec
_MAIN0, USE_RETA
– Dual 16-bit stack with Slow-Return:
• RETA and CFCT are not used
• Independent SP and SSP
– 32-bit stack with Slow-Return:
• RETA and CFCT are not used
• Linked SP and SSP
C55x Rev 3 New Instructions
•
LMS:
lms (Xmem,Y mem, ACx, ACy)
ACy = ACy + Xmem * Ymem
ACx = rnd(AC x + (Xmem << #16))
lmsf (Xmem,Ymem, ACx, ACy )
ACx = T3 * Ymem
ACy = ACy + Xmem * Ymem
Ymem = HI(rnd(ACx + (Xmem << #16)))
•
Parallel Multiplies-Accumualates: (4 operands f or Dual-MAC operations)
ACx = M40(rnd(ACx + (uns(Smem)) * uns(LO(Cmem)),
ACy = M40(rnd(ACy + (uns(Smem)) * uns(H(Cmem))
•
Parallel Stores: (freed Address Y -unit to perf orm parallel store)
ACx = M40(rnd( (uns(Xmem)) * uns(LO(Cmem)),
ACy = M40(rnd( (uns(Xmem)) * uns(HI( Cmem))
|| uns(*Ymem) = pair(HI(ACz))
New Instruction: 4-Operand Dual-MAC using 32-bit
Bus
ACx = M40(rnd(ACx + (uns(HI(Lmem))) * uns(HI(Cmem)))),
ACy = M40(rnd(ACy + (uns(LO(Lmem))) * uns(LO(Cmem))))
D bus data from address Lmem
C bus data from address Lmem+1
B bus data from addresses Cmem (B[15:0]) and Cmem+1 (B[31:16])
*+ modifier increments Lmem and Cmem by 2 words.
Advantage: Y-DAGEN not used. Available to do a parallel store.
D bus [15:0]
C bus [15:0]
B bus [31:0]
B[15:0]
X Y C
DAGEN
MAC #1
B[31:16]
MAC #2
New Instruction: 3-Operand Dual-MAC using 32-bit
Bus
ACx = M40(rnd(ACx + (uns(Smem)) * uns(LO(Cmem)))),
ACy = M40(rnd(ACy + (uns(Smem)) * uns(HI(Cmem))))
D bus data from address Smem
C bus data from address Smem
B bus data from addresses Cmem(B[15:0]) and Cmem+1 (B[31:16])
*+ modifier increments Cmem pointer by 2 words.
Advantage: Y-DAGEN not used. Available to do a parallel store.
D bus [15:0]
C bus [15:0]
B bus [31:0]
B[15:0]
X Y C
DAGEN
MAC #1
B[31:16]
MAC #2
New Instruction: 2-Operand UNS MAC using B-bus
ACx = rnd(ACx + Smem*uns(Cmem))
D bus data from address Smem
B bus data from addresses Cmem (B[15:0])
*+ modifier increments XCDP pointer by 2 words.
Advantage: Y-DAGEN not used. Available to do a parallel store.
D bus [15:0]
C bus [15:0]
B bus [31:0]
B[15:0]
X Y C
DAGEN
MAC #1
MAC #2
3rd Party Network
Broad Third Party Network to Enable Faster Time to Market
BACKUP
C55x DSP Comparison – 11 Devices
Feature
C5501
C5502
C5503
C5504
C5505
C5514
C5515
C5506
C5507
C5509A
C5510A
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
CPU
C55x
C55x
C55x
C55x
C55x
C55x
C55x
C55x
C55x
C55x
C55x
Frequency
(MHz)
Peak MMACS
300
600
200/300
400/600
200
400
150
300
150
300
120
240
120
240
108
216
200
400
200
400
160/200
320/400
FFT Cop
-
-
-
-
Y
-
Y
-
-
-
-
RAM
32KB
64KB
64KB
256KB
320KB
256KB
320KB
128KB
128KB
256KB
320KB
ROM
32KB
32KB
64KB
128KB
128KB
128KB
128KB
64KB
64KB
64KB
32KB
On-chip L1
16KB
16KB
-
-
-
-
-
-
-
-
24KB
EMIF
32-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
32-bit
DMA
6
6
6
16
16
16
16
6
6
6
6
-
-
1 HS
1 HS
1 HS
1 HS
1 FS
1 FS
1 FS
-
USB2.0 FS/HS
-
MMC/SD
-
-
-
2
2
2
2
-
-
2
-
McBSP
2
3
3
0
0
0
0
3
3
3
3
HPI
1 8-b
1 8/16-b
1 8/16-b
-
-
-
-
-
-
1 8/16/-bit
1 8/16-bit
I2S/I2C
0/1
0/1
0/1
4/1
4/1
4/1
4/1
0/1
0/1
0/1
0/1
UART
1
1
0
1
1
1
1
0
0
0
0
SPI
-
-
-
1 w/
4CS
1 w/
4CS
1 w / 4CS
1 w / 4CS
-
-
-
-
ADC
-
-
-
1
1
Timer
3 (1
WD)
3 (1 WD)
4 (1
RTC,
1WD)
3 (WD),
1 RTC
3 (WD),
1 RTC
3 (WD), 1
RTC
3 (WD), 1
RTC
4 (1
RTC,
1WD)
4 (1 RTC,
1WD)
4 (1 RTC,
1WD)
2
LDO
0
0
0
1
1
3
3
0
0
0
0
LCD Bridge
-
-
-
-
1
-
1
-
-
-
-
Package
15x15
15x15
12x12
10x10
10x10
10x10
10x10
12x12
12x12
12x12
15x15
1
1
C54x DSP Comparison – 23 Devices
Feature
C549
C5401
C5402/A
C5404
C5407
C5409/A
C5410/A
C5416
C5420
C5421
C5441
C5470
C5471
Availabilit y
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
CPU
C54x
C54x
C54x
C54x
C54x
C54x
C54x
C54x
2 C54x
2 C54x
4 C54x
C54x +
C54x +
ARM7
ARM7
Peak MMACS
100
50
80/100
160
120
120
80/100
120/160
100
120/160
120/160
200
(2x100)
200
(2x100)
532
(4x133)
100 +
47.5
100 +
47.5
384KB
512KB
1280KB
160KB
160KB
1 16-bit
+1 32bit
1 16-bit
+1 32-bit
120
RAM
64KB
16KB
32KB
32KB
80KB
64KB
128KB
256KB
ROM
32KB
8KB
8/8/32KB
128KB
256KB
32KB
32KB
32KB
EMIF (Async)
1 16bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
DMA
-
-
6
6
6
6
6
6
6
2x6
4x6
6
6
McBSP
-
-
3
3
3
3
3
3
6
6
12
2
2
HPI
1 8-bit
1 8/16-bit
1 8/16-bit
1 8/16-bit
1 8/16-bit
1 8/16-bit
-
1 8/16-bit
-
-
1 16-bit
-
-
I2C
-
-
-
-
-
-
-
-
-
-
-
1
1
SPI
-
-
-
-
-
-
-
-
-
-
-
1
1
10/100 EM AC
-
-
-
-
-
-
-
-
-
-
-
ADC
-
-
-
-
-
-
-
-
-
-
-
UART
-
-
-
1
1
-
-
-
-
-
-
2
2
Timer
1
2
2/2/1
2
2
1
1
1
1
2
4
4 (1
WD)
4 (1 W D)
1.8
1.8/1.6
1.5
1.5
1.8
1.5/1.6
2.5/3.3
1.6/1.5
1.5/1.6
1.6
1.8
1.6
1.8
1.8
Core Voltag e
8KB
1
IO Voltag e
2.5/3.3
3.3
1.8-3.3
3.3
3.3
1.8-3.3
3.3
3.3
3.3
3.3
/3.3
/3.3
3.3
Pin No.
144
144
144
144
144
144
144/176
144
144
144
169/176
257
257
TMS320VC5502 DSP
Features
Package: 144-Pin LQFP, 201-Pin µ*BGA
In Production Today
6Chan.
DMA
19
8
2
INT
2
Timers
Memory
ICACHE ROM
DARAM
16 KB
64 KB
32 KB
I/O
– 3.0V - 3.3 V
I2 C
C55x™
DSP Core
JTAG
EMIF
32-bit
Peripheral Bus
68
HPI
Peripherals
2
Watchdog
System
PLL
– 80-KB On-Chip Memory
• 64-KB DARAM + 16-KB I-Cache
– 32-KB ROM
6
McBSP
McBSP
McBSP
Memory
– 2 McBSPs
– Multi-master and Slave I2C with 7 or 10-bit addressing
modes
– UART muxed with a McBSP
– 2 64-bit timers; 1 Watchdog
– 76 GPIO, 8 dedicated
– 6 Channel DMA
– Analog PLL
– 32-bit EMIF with asynchronous SRAM, SDRAM, SBR AM
– 8-bit/16-bit Host Port Interface
6
6
UART
– Dual MAC, C55x Rev 2 CPU
– 1.26V @ 200MH z, 300 MHz
GPIO
Core
5
7
TMS320VC5509A DSP
Portable Media/Comm/Audio Device
Package: 144-Pin LQFP, 179-Pin µ*BGA
In Production Today
I/O
– 2.7V - 3.6 V
2
GPIO
10-Bit
A/D
SARAM
DARAM 192 KB ROM
64 KB
64 KB
2 TQFP
4 BGA
7 TQFP
9 BGA
INT
JTAG
Peripheral Bus
Memory
Watchdog
DSP Core
3
2
Timers
2
RTC
I2 C
MMC/SD
2
System
PLL
6Chan.
DMA
6
C55x™
USB
– USB 2.0 full speed (12Mbps)
– 2 MultiMedia Card/Secure Digital (MMC/SD) serial ports
– 4ch/2ch 10-bit SAR, 500-us ADC 3 McBSPs
– Multi-master and Slave I2C with 7 or 10-bit addressing
modes
– 2 20-bit timers; 1 Watchdog
– 36/35 GPIO, 8/7 dedicated
– 6 Channel DMA
– PLL
– 16-bit EMIF with asynchronous SRAM, SDRAM, and
muxed with HPI
– Real-time clock with 32-KHz crystal input,
separate power
External
Memory
Interface
EHPI
45/47
GPIO
– 256-KB On-Chip Memory
• 64-KB DARAM + 192-KB SAR AM
– 64-KB ROM
McBSP
McBSP
Memory
Peripherals
6
6
DSK Available
MMC/SD
EVM Available
McBSP
– Dual MAC, C55x Rev 2 CPU
– 1.2V @ 108MHz, 1.35V @ 144MHz , 1.6V @ 200 MH z
USB
PLL
Core
5
7
TMS320VC5507 DSP
Features
– Dual MAC, C55x Rev 2 CPU
– 1.2V @ 108MHz, 1.35V @ 144MHz , 1.6V @ 200 MHz
Package: 144-Pin LQFP, 179-Pin µ*BGA
In Production Today
Core
Memory
6
– 128-KB On-Chip Memory:
6
6
2
2
3
2
2 TQFP
4 BGA
INT
2
Timers
7 TQFP
9 BGA
JTAG
SARAM ROM
64KB 64 KB
GPIO
DARAM
64 KB
Watchdog
Peripheral Bus
RTC
I2 C
Memory
10-Bit
A/D
– 2.7V - 3.6V
DSP Core
System
PLL
6Chan.
DMA
C55x™
USB
PLL
I/O
External
Memory
Interface
USB
USB 2.0 full speed (12Mbps)
2ch/4ch 10-bit SAR, 500- us ADC for keypad, button and battery monitoring func tions
3 McBSPs
Multi-master and Sl ave I2C with 7 or 10-bit addressing modes
2 20-bit ti mers; 1 Watc hdog
45/47
36/35 GPIO, 8/7 dedicated
6 Channel DMA
PLL
16-bit EMIF with as ync hronous SRAM, SDRAM, and muxed with HPI
Real-time cloc k with 32-KHz crystal input,
separate power
EHPI
–
–
–
–
–
–
–
–
–
–
McBSP
Peripherals
GPIO
McBSP
McBSP
• 64-KB DARAM + 64-KB SARAM
– 64-KB ROM
5
7
TMS320VC5506 DSP
Features
Package: 144-Pin LQFP, 179-Pin µ*BGA
In Production Today
Core
– Dual MAC, C55x Rev 2 CPU
– 1.2V @ 108MHz
Memory
6
– 128-KB On-Chip Memory:
6
6
2
2
3
2
2 TQFP
4 BGA
7 TQFP
9 BGA
INT
JTAG
SARAM BOOTR
64KB
OM
GPIO
DARAM
64 KB
2
Timers
Peripheral Bus
RTC
I2 C
Memory
10-Bit
A/D
– 2.7V - 3.6V
DSP Core
System
PLL
6Chan.
DMA
C55x™
Watchdog
External
Memory
Interface
USB
PLL
I/O
45/47
USB
USB 2.0 full speed (12Mbps)
2ch/4ch 10-bit, 500-us ADC for keypad, button and battery monitoring functions
3 McBSPs
Multi-master and Sl ave I2C with 7 or 10-bit addressing modes
2 20-bit ti mers; 1 Watc hdog
36/35 GPIO, 8/7 dedicated
6 Channel DMA
PLL
16-bit EMIF with as ync hronous SRAM, SDRAM, and muxed with HPI
Real-time cloc k with 32-KHz crystal input,
separate power
EHPI
–
–
–
–
–
–
–
–
–
–
McBSP
Peripherals
GPIO
McBSP
McBSP
• 64-KB DARAM + 64-KB SARAM
– Boot ROM
5
7
TMS320VC5503 DSP
Features
– Dual MAC, C55x Rev 2 CPU
– 1.2V @ 108MHz, 1.35V @ 144MHz , 1.6V @ 200 MHz
Package: 144-Pin LQFP, 179-Pin µ*BGA
In Production Today
Core
Memory
6
– 64-KB On-Chi p Memor y:
6
6
2
2
2
2 TQFP
4 BGA
Watchdog
ROM
64 KB
7 TQFP
9 BGA
INT
JTAG
Memory
DARAM
64 KB
2
Timers
Peripheral Bus
RTC
I2 C
DSP Core
GPIO
– 2.7V - 3.6V
6Chan.
DMA
C55x™
10-Bit
A/D
I/O
External
Memory
Interface
McBSP
2ch/4ch 10-bit SAR, 500- us ADC for keypad, button and battery monitoring func tions
3 McBSPs
Multi-master and Sl ave I2C with 7 or 10-bit addressing modes
2 20-bit ti mers; 1 Watc hdog
45/47
36/35 GPIO, 8/7 dedicated
6 Channel DMA
PLL
16-bit EMIF with as ync hronous SRAM, SDRAM, and muxed with HPI
Real-time cloc k with 32-KHz crystal input,
separate power
System
PLL
–
–
–
–
–
–
–
–
–
EHPI
Peripherals
GPIO
McBSP
McBSP
• 64-KB DARAM
– 64-KB ROM
5
7
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