Differential-to-HSTL Zero Delay Clock Generator ICS872S480 DATA SHEET General Description Features The ICS872S480 is a Zero Delay Clock Generator with hitless input clock switching capability. The ICS872S480 is ideal for use in redundant, fault tolerant clock trees where low jitter frequency synthesis are critical. The device receives two differential clock signals from which it generates two outputs with “zero” delay. The output and feedback dividers are configured to allow for a 1:1 frequency generation ratio. • • • Three differential HSTL output pairs • • • • Output frequency range: 350MHz to 950MHz • • • • • • • Static phase offset: ±100ps (maximum) The ICS872S480 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of an invalid clock input (stuck LOW or HIGH for at least one complete clock period of the VCO feedback frequency), the loss of reference monitor will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. Once the primary clock is restored to a good state, the DCS will automatically switch back to the primary clock input. The low jitter characteristics with input clock monitoring and DCS capability make the ICS872S480 an ideal choice for DDR3 applications requiring fault tolerant reference clocks. CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL Input frequency range: 350MHz to 950MHz VCO range: 970MHz to 2250MHz External feedback for “zero delay” clock regeneration with configurable frequencies Cycle-to-cycle jitter: 25ps (maximum) Output skew: 20ps (maximum) 3.3V operating voltage supply Selectable DDR3 or DDR3 low voltage output 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package 4 350 562.5 VDD 950 VOUT_SEL 485 nc 2 nc Maximum GND 1 (default) Minimum REF_SEL 0 Input & Output Frequency (MHz) VDD FREQ_SEL Output Divider AUTO_SEL Pin Assignment Function Table Input Selectable differential CLKx, nCLKx input pairs 32 31 30 29 28 27 26 25 CLK1 4 21 CLK_IND nCLK1 5 20 GND PLL_BYPASS 6 19 FREQ_SEL FB_IN 7 18 OE nFB_IN 8 17 VDDA 9 10 11 12 13 14 15 16 Q0 1.35V 22 LOR1 VDD VDD 1 3 nQ0 1.5V LOR0 GND Q1 0 (default) 23 nQ1 HSTL Output Style 2 VDD VOUT_SEL 24 nCLK0 QFB Input 1 nQFB Output Voltage Table CLK0 ICS872S480 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS872S480BK REVISION A APRIL 19, 2011 1 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Block Diagram VOUT_SEL OE PLL_Bypass Pulldown Pullup Pulldown Q0, nQ0 CLK0 nCLK0 Pullup Pulldown Activity Detector 1 0 PD + CP + LF LOR0 CLK1 nCLK1 1 Pullup Pulldown Activity Detector Dynamic Switch Logic CLK_IND AUTO_SEL FB_IN nFB_IN VCO Q1, nQ1 0 QFB, nQFB LOR1 REF_SEL Output Divider Pulldown 1 0 Pullup Pullup Pulldown FREQ_SEL Pullup ICS872S480BK REVISION A APRIL 19, 2011 2 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Number Name 1 CLK0 Input Type Pulldown Description 2 nCLK0 Input Pullup 3, 20, 28 GND Power 4 CLK1 Input Pulldown 5 nCLK1 Input Pullup 6 PLL_BYPASS Input Pulldown PLL bypass pin. When HIGH, the PLL is bypassed and the reference clock is passed directly to the output dividers. LVCMOS/LVTTL interface levels. 7 FB_IN Input Pulldown Non-inverting differential external feedback input. 8 nFB_IN Input Pullup 9, 10 nQFB, QFB Output Differential feedback output pair. HSTL interface levels. See Table 4D. 11, 16, 24, 25, 32 VDD Power Core supply pins. 12, 13 nQ1, Q1 Output Differential output pair. HSTL interface levels. 14, 15 nQ0, Q0 Output Differential output pair. HSTL interface levels. 17 VDDA Power Analog supply pin. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Non-inverting differential clock input. Inverting differential clock input. Inverting differential external feedback input. 18 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. 19 FREQ_SEL Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 21 CLK_IND Output Clock indicator pin. When LOW, CLK0, nCLK0 is selected. When HIGH, CLK1, nCLK1 is selected. 22 LOR1 Output Loss of Reference Indicator for CLK1, nCLK1. LVCMOS/LVTTL interface levels. 23 LOR0 Output Loss of Reference Indicator for CLK0, nCLK0. LVCMOS/LVTTL interface levels. 26 VOUT_SEL Input 27, 29 nc Unused Pulldown Output voltage select pin. LVCMOS/LVTTL interface levels. No connect. 30 AUTO_SEL Input Pullup Dynamic Clock switch enable pin. When LOW, disables internal Dynamic Clock Switch circuitry and CLK_INDICATOR will track REF_SEL. When HIGH, Dynamic Clock Switch is enabled. LVCMOS/LVTTL interface levels. 31 REF_SEL Input Pulldown Reference clock select pin. When LOW selects CLK0, nCLK0, when HIGH selects CLK1, nCLK1. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 2 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS872S480BK REVISION A APRIL 19, 2011 Test Conditions 3 Minimum Typical Maximum Units ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 42.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions VDD Core Supply Voltage VDDA Analog Supply Voltage IDD Power Supply Current IDDA Analog Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD –0.25 3.3 VDD V 275 mA 25 mA Outputs terminated 50Ω to GND Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2.2 VDD + 0.3 V -0.3 0.8 V PLL_BYPASS, REF_SEL, VOUT_SEL VDD = VIN = 3.465V 150 µA OE, FREQ_SEL, AUTO_SEL VDD = VIN = 3.465V 10 µA PLL_BYPASS, REF_SEL, VOUT_SEL VDD = 3.465V, VIN = 0V -10 µA OE, FREQ_SEL, AUTO_SEL VDD = 3.465V, VIN = 0V -150 µA ICS872S480BK REVISION A APRIL 19, 2011 4 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.75 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.3 VDD – 0.85 V CLK0, CLK1, FB_IN VDD = VIN = 3.465V 150 µA nCLK0, nCLK1, nFB_IN VDD = VIN = 3.465V 10 µA CLK0, CLK1, FB_IN VDD = 3.465V, VIN = 0V -10 µA nCLK0, nCLK1, nFB_IN VDD = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. HSTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOX Output Crosspoint Voltage, NOTE 1 VOUT_SEL = 0 0.7 0.8 0.9 V VOUT_SEL = 1 0.6 0.7 0.8 V VOD Differential Output Voltage; NOTE 1 VOUT_SEL = 0 0.8 0.9 1.0 V VOUT_SEL = 1 0.8 0.9 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to ground. Table 5. Input Frequency Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter FIN Input Frequency CLK0, nCLK0, CLK1, nCLK1 ICS872S480BK REVISION A APRIL 19, 2011 Test Conditions Minimum FSEL = 1 485 950 MHz FSEL = 0 350 562.5 MHz 5 Typical ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency t(Ø) tdyn(Ø) Test Conditions Static Phase Offset; NOTE 1, 2 Dynamic Phase Offset; NOTE 7 Minimum Typical Maximum Units 350 950 MHz fOUT = 400MHz -25 75 ps fOUT = 533.3MHz -50 50 ps fOUT = 666.6MHz -50 50 ps fOUT = 800MHz -50 50 ps fOUT = 400MHz ±20 ps fOUT = 533.3MHz ±25 ps fOUT = 666.6MHz ±20 ps fOUT = 800MHz ±20 ps pdev Output Period Deviation; NOTE 3, 7 100 ps tsk(o) Output Skew; NOTE 2, 4 20 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 3, 7 25 ps tL PLL Lock Time; NOTE 7 3 ms tLdcs DCS PLL Lock Time; NOTE 6, 7 VOUT_SEL = 0 tSLEW Output Slew Rate; NOTE 5 VOUT_SEL = 1 odc 1.7 µs fOUT = 400MHz 2.00 3.50 5.75 V/ns fOUT = 533.3MHz 2.00 4.25 6.50 V/ns fOUT = 666.6MHz 2.00 4.25 6.75 V/ns fOUT = 800MHz 2.50 5.25 8.65 V/ns fOUT = 400MHz 2.00 3.85 6.35 V/ns fOUT = 533.3MHz 2.00 4.50 6.85 V/ns fOUT = 666.6MHz 2.50 4.65 7.25 V/ns fOUT = 800MHz 3.00 5.65 8.25 V/ns 53 % Output Duty Cycle 47 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. Characterized using HSTL input level of 900mV, swing centered around 0.6V. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: This parameter is defined as the maximum output period deviation during a dynamic switch event with reference inputs 180° out of phase. This does not factor in any cycle-to-cycle jitter seen on the input or output. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5: Output slew rate is measured at VOX ± 150mV for VOUT_SEL = 0 and VOX ±135mV for VOUT_SEL = 1. NOTE 6: This parameter is defined as PLL lock time after a dynamic switch event with reference inputs 180° out of phase. NOTE 7: This parameter is guaranteed by characterization. Not tested in production. ICS872S480BK REVISION A APRIL 19, 2011 6 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V ± 5% 3.3V ± 5% VDD VDD Qx SCOPE nCLK0, nCLK1 V VDDA Cross Points PP V CMR CLK0, CLK1 HSTL nQx GND GND 0V 3.3V Output Load AC Test Circuit Differential Input Level nQ[0:1] nQx Q[0:1] Qx ➤ ➤ tcycle n ➤ tcycle n+1 ➤ nQy tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Qy tsk(o) Cycle-to-Cycle Jitter Output Skew nCLK[0:1] CLK[0:1] nQ[0:1] nFB_IN Q[0:1] t PW FB_IN t ➤ ➤ t(Ø) t(Ø)mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø)mean is the average of the sampled cycles measured on controlled edges) odc = t PW x 100% t PERIOD Static Phase Offset ICS872S480BK REVISION A APRIL 19, 2011 PERIOD Output Duty Cycle/Pulse Width/Period 7 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued nCLK[0:1] ∆t nCLK[0:1] ∆t +VAC t(Ø)mean VOD ➤ VOX nFB_IN -VAC FB_IN Histogram Dynamic Phase Offset VAC = 150mV for VOUT_SEL = 0 VAC = 135mV for VOUT_SEL = 1 ➤ ➤ t(Ø) Dynamic Phase Offset = t(Ø) – t(Ø)mean tdyn(Ø) = Peak-to-Peak value of Dynamic Phase Offset Histogram Where t(Ø) is any random sample, and t(Ø)mean is the average of the sampled cycles measured on the controlled edges tSLEW = 2 * VAC ∆t Slew Rate Dynamic Phase Offset PLL Lock Time ICS872S480BK REVISION A APRIL 19, 2011 8 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Applications Information Clock Redundancy and Reference Selection Output Transitioning The ICS872S480 accepts two differential input clocks, CLK0, nCLK0 and CLK1, nCLK1, for the purpose of redundancy. Only one of these clocks can be selected at any given time for use as the reference. CLK0, nCLK0 is defined as the initial, or primary clock, while the remaining clock is the redundant or secondary clock. The output signal CLK_IND indicates which clock input is being used as the reference (LOW = CLK0, nCLK0, HIGH = CLK1, nCLK1). After a successful DCS initiated clock switch, the internal PLL of the ICS872S480 will begin slewing to phase/frequency alignment of the newly selected clock input. The PLL will achieve lock to the new input with minimal phase disturbance at the outputs. Recommended Power-up Sequence 1.Before startup, set AUTO_SEL low so the PLL will operate in manual switch mode, plus set REF_SEL low to ensure that the primary reference clock, CLK0, nCLK0, is selected. This will ensure that during startup, the PLL will acquire lock using the primary reference clock input. Failure Detection and Alarm Signaling Within the ICS872S480 device, CLK0, nCLK0 and CLK1, nCLK1 are continuously monitored for failures. A failure on either of these clocks is detected when one of the clock signals is stuck HIGH or LOW for at least 1 period of the feedback. Upon detection of a failure, the corresponding loss-of-reference signal, LOR0 or LOR1, will be set HIGH. The input clocks are continuously monitored and the loss-of-reference signals will continue to reflect the real-time status of each input clock. 2.Once powered-up, and assuming a stable clock is present at the primary clock input, the PLL will begin to phase/frequency slew as it attempts to achieve lock with the input reference clock. 3.Drive AUTO_SEL HIGH to enable DCS mode. Manual Clock Switching Alternate Power-up Sequence When input signal AUTO_SEL is driven LOW, the clock specified by REF_SEL will always be used as the reference, even when a clock failure is detected at the reference. In order to switch between CLK0, nCLK0 and CLK1, nCLK1 as the reference clock, the level on REF_SEL must be driven to the appropriate level. When the level on REF_SEL is changed, the selection of the new clock will take place, and CLK_IND will be updated to indicate which clock is now supplying the reference to the PLL. If both input clocks are valid before power up, the part may be powered-up in DCS mode. However, it cannot be guaranteed that the PLL will achieve lock with one specific input clock. 1.Before startup, leave AUTO_SEL floating and the internal pullup will enable DCS mode. 2.Once powered up, the PLL will begin to phase/frequency slew as it attempts to achieve lock with one of the input reference clocks. Dynamic Clock Switching The Dynamic Clock Switching (DCS) process serves as an automatic safety mechanism to protect the stability of the PLL when a failure occurs on the reference. When input signal AUTO_SEL is not driven HIGH, an internal pullup pulls it HIGH so that DCS is enabled. If DCS is enabled and a failure occurs on the initial clock, the ICS872S480 device will check the status of the secondary clock. If the secondary clock is detected as a good input clock, the ICS872S480 will automatically de-select the initial clock as the reference and multiplex in the secondary clock. When a successful switch from the initial to secondary clock has been accomplished, CLK_IND will be updated to indicate the new reference. If and when the fault on the initial clock is corrected, the corresponding loss-of-reference flag will be updated to represent this clock as good again. Once updated, the DCS will undergo an automatic clock switch. See the Dynamic Clock Switch State Diagram and for additional details on the functionality of the Dynamic Clock Switching circuit. ICS872S480BK REVISION A APRIL 19, 2011 9 ©2011 Integrated Device Technology, Inc. DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR State Diagram ICS872S480 Data Sheet ICS872S480BK REVISION A APRIL 19, 2011 10 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS872S480BK REVISION A APRIL 19, 2011 11 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Differential Clock Input Interface with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, HSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω Zo = 50Ω nCLK nCLK LVHSTL R1 50Ω IDT LVHSTL Driver R2 50Ω Differential Input LVPECL Differential Input R1 50Ω R2 50Ω R2 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter HSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V 3.3V R4 125Ω Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK R1 84Ω Zo = 50Ω Differential Input LVPECL R2 84Ω LVDS nCLK Receiver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V *R3 33Ω Zo = 50Ω CLK Zo = 50Ω nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS872S480BK REVISION A APRIL 19, 2011 12 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Recommendations for Unused Input Pins Inputs: Outputs: LVCMOS Control Pins HSTL Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. HSTL Output Termination VDDO VDD Zo = 50 + Zo = 50 HSTL ICS HiPerClockS HSTL Driv er R1 50 HSTL R2 50 Figure 4. Output Termination ICS872S480BK REVISION A APRIL 19, 2011 13 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS872S480BK REVISION A APRIL 19, 2011 14 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Schematic Example Figure 6 shows an example of ICS872S480 application schematic. In this example, the device is operated at VDD = 3.3V. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS872S480 provides separate power supplies to isolate from coupling into the internal PLL. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. R1 LOR0 3.3V R2 125 2.2K R3 125 3.3V R8 125 1 2 3 4 5 6 7 8 PLL_BYPASS R9 125 R5 32 31 30 29 28 27 26 25 R7 84 CLK0 nCLK0 GND CLK1 nCLK1 PLL_BYPASS FB_IN nFB_IN LD2 CLK_IND 2.2K VD D R EF _SE L A U T O _S EL nc GN D nc V O U T _S EL VD D U1 Zo = 50 LVPECL Driv er 2.2K VDD nCLK0 R6 84 VDD VDD CLK0 LOR1 VOUT_SEL REF_SEL Zo = 50 VDD LOR0 LOR1 CLK_IND GND FREQ_SEL OE VDDA 24 23 22 21 20 19 18 17 LD3 Q0 + nQ F B QFB VD D nQ 1 Q1 nQ 0 Q0 VD D Zo = 50 Ohm R10 50 - R11 50 9 10 11 12 13 14 15 16 nF B _IN F B _IN CLK1 nCLK1 Zo = 50 Ohm FREQ_SEL OE nQ0 Zo = 50 LD1 R4 AUTO_SEL Zo = 50 R14 84 VDD C1 0.1u VDD R15 50 R16 50 VDD=3.3V 3.3V BLM18BB221SN1 Logic Control Input Examples 1 Set Logic Input to '1' RU1 1K Set Logic Input to '0' VDD RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins 10 C2 10u nQ1 Q1 nQ0 Q0 LVPECL Driv er VDD R12 VDDA R13 84 C3 0.1uF 2 VDD1 Ferrite Bead C4 C5 Q1 + 10uF 0.1uF nQ1 3.3V RD2 1K Zo = 50 Ohm Zo = 50 Ohm - BLM18BB221SN1 1 C6 0.1uF 2 (U1, 11) Ferrite Bead C7 10uF (U1, 16) C8 (U1, 24) C9 0.1u 0.1u (U1, 25) C10 0.1u (U1, 32) C11 0.1u VDD C12 R17 50 R18 50 0.1u Figure 6. ICS872S480 Schematic Layout ICS872S480BK REVISION A APRIL 19, 2011 15 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS872S480. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for theICS872S480 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX)= 3.465V * (275mA + 25mA) = 1039.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 42.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 1.040W * 42.7°C/W = 114.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS872S480BK REVISION A APRIL 19, 2011 0 1 2.5 42.7°C/W 37.3°C/W 33.5°C/W 16 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Reliability Information Table 8. θJA vs. Air Flow Table for a 32-lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 42.7°C/W 37.3°C/W 33.5°C/W Transistor Count The transistor count for ICS872S480 is: 2110 ICS872S480BK REVISION A APRIL 19, 2011 17 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N Anvil Anvil Singulation Singula tion e (Ty p.) 2 If N & N 1 are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e D2 2 N &N Odd 0. 08 C Bottom View w/Type A ID D2 C Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 Th er mal Ba se N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 9. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9. JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS872S480BK REVISION A APRIL 19, 2011 18 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 872S480BKLF 872S480BKLFT Marking ICS72S480BL ICS72S480BL Package “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS872S480BK REVISION A APRIL 19, 2011 19 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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