Data Sheet

74AHC86-Q100;
74AHCT86-Q100
Quad 2-input EXCLUSIVE-OR gate
Rev. 1 — 5 June 2013
Product data sheet
1. General description
The 74AHC86-Q100; 74AHCT86-Q100 are high-speed Si-gate CMOS devices and are
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard no. 7A.
The 74AHC86-Q100; 74AHCT86-Q100 provides a 2-input exclusive-OR function.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Balanced propagation delays
 All inputs have a Schmitt-trigger action
 Inputs accept voltages higher than VCC
 For 74AHC86-Q100 only: operates with CMOS input levels
 For 74AHCT86-Q100 only: operates with TTL input levels
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
74AHC86D-Q100
Package
Temperature range Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
74AHCT86D-Q100
74AHC86PW-Q100
74AHCT86PW-Q100
74AHC86BQ-Q100
74AHCT86BQ-Q100
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
4. Functional diagram
1
2
1A
1B
1Y
3
4
5
2A
2B
2Y
6
9
10
3A
3B
3Y
8
12
13
4A
4B
4Y
11
mna787
Fig 1. Logic symbol
1
=1
3
=1
6
=1
8
=1
11
2
4
5
9
10
A
12
Y
13
B
Fig 2. Logic diagram (one gate)
74AHC_AHCT86_Q100
Product data sheet
mna788
mna786
Fig 3. IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
2 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
5. Pinning information
5.1 Pinning
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<
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$
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$
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%
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DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration SO14, TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data input
1B to 4B
2, 5, 10, 13
data input
1Y to 4Y
3, 6, 8, 11
data outputs
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input nA
Input nB
Output nY
L
L
L
L
H
H
H
L
H
H
H
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
3 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7.0
V
VI
input voltage
IIK
input clamping current
VI < 0.5 V
[1]
0.5
+7.0
V
20
-
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
mA
-
20
mA
IO
output current
VO = 0.5 V to (VCC + 0.5 V)
-
25
mA
ICC
IGND
supply current
-
75
mA
ground current
75
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C
SO14 package
[2]
-
500
mW
TSSOP14 package
[3]
-
500
mW
DHVQFN14 package
[4]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 8 mW/K above 70 C.
[3]
Ptot derates linearly with 5.5 mW/K above 60 C.
[4]
Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC86-Q100
74AHCT86-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
VI
input voltage
0
-
5.5
0
-
5.5
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
40
+25
+125
C
t/V
input transition rise
and fall rate
VCC = 3.3 V  0.3 V
-
-
100
-
-
-
ns/V
VCC = 5.0 V  0.5 V
-
-
20
-
-
20
ns/V
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
4 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
For type 74AHC86-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 50 A; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = 50 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = 8.0 mA; VCC = 4.5 V
3.94
-
-
3.8
-
3.70
-
V
LOW-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
VI = 5.5 V or GND; VCC = 0 V
to 5.5 V
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
CI
input
capacitance
-
3.0
10
-
10
-
10
pF
CO
output
capacitance
-
4.0
-
-
-
-
-
pF
For type 74AHCT86-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.8
-
3.70
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
IO = 8.0 mA
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
5 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
VI = 5.5 V or GND; VCC = 0 V
to 5.5 V
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
ICC
additional
per input pin;
supply current VI = VCC  2.1 V; IO = 0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
3
10
-
10
-
10
pF
CO
output
capacitance
-
4.0
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
25 C
Conditions
Min
Typ[1]
CL = 15 pF
-
CL = 50 pF
-
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
4.8
11.0
1.0
13.0
1.0
14.0
ns
6.8
14.5
1.0
16.5
1.0
18.5
ns
-
3.4
6.8
1.0
8.0
1.0
8.5
ns
4.8
8.8
1.0
10.0
1.0
11.0
ns
-
10.0
-
-
-
-
-
pF
For type 74AHC86-Q100
tpd
propagation
delay
nA, nB to nY; see Figure 6
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
CPD
power
dissipation
capacitance
74AHC_AHCT86_Q100
Product data sheet
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[3]
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Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
6 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
Table 7.
Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
-
3.4
6.9
1.0
8.0
1.0
9.0
ns
-
4.9
8.8
1.0
10.0
1.0
11.0
ns
-
12.0
-
-
-
-
-
pF
For type 74AHCT86-Q100
propagation
delay
tpd
nA, nB to nY; see Figure 6
[2]
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
power
dissipation
capacitance
CPD
[3]
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[1]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL  VCC2  fo) = sum of the outputs.
11. Waveforms
VI
VM
nA, nB input
GND
t PHL
t PLH
VOH
VM
nY output
VOL
mna224
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay input (nA, nB) to output (nY)
Table 8.
Measurement points
Type
Input
Output
VM
VM
74AHC86-Q100
0.5VCC
0.5VCC
74AHCT86-Q100
1.5 V
0.5VCC
74AHC_AHCT86_Q100
Product data sheet
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Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
7 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 7. Load circuitry for switching times
Table 9.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74AHC86-Q100
VCC
3.0 ns
15 pF, 50 pF
1 k
open
GND
VCC
74AHCT86-Q100
3.0 V
3.0 ns
15 pF, 50 pF
1 k
open
GND
VCC
74AHC_AHCT86_Q100
Product data sheet
Load
S1 position
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Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
8 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 8. Package outline SOT108-1 (SO14)
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
9 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 9. Package outline SOT402-1 (TSSOP14)
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
10 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 10. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
11 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
74AHC_AHCT86_Q100 v.1 20130605
74AHC_AHCT86_Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
12 of 15
74AHC86-Q100; 74AHCT86-Q100
NXP Semiconductors
Quad 2-input EXCLUSIVE-OR gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT86_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
13 of 15
NXP Semiconductors
74AHC86-Q100; 74AHCT86-Q100
Quad 2-input EXCLUSIVE-OR gate
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© NXP B.V. 2013. All rights reserved.
14 of 15
NXP Semiconductors
74AHC86-Q100; 74AHCT86-Q100
Quad 2-input EXCLUSIVE-OR gate
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 June 2013
Document identifier: 74AHC_AHCT86_Q100