PRELIMINARY ICS843S2807 FEMTOCLOCK™ CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR • Maximum output frequency: 350MHz VCCO_LVCMOS QA0 VEE QB1 • Crystal input frequency: 25MHz QB0 PIN ASSIGNMENT VCCO_LVCMOS • Five banks of outputs: Bank A: one single-ended (QA0) LVCMOS output at: 133MHz and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz and 125MHz Bank B: two (QB0, QB1) LVCMOS outputs at: 50MHz Bank C: one (QC0/nQC0) differential LVPECL output at: 87.5MHz Bank D: one (QD0/nQD0) differential LVDS output at: 350MHz One single-ended LVCMOS reference clock output at: 25MHz REF_OUT FEATURES ICS843S2807 is a low phase noise Clock Generator ICS and is a member of the HiperClockS™ family of high HiPerClockS™ performance clock solutions from IDT. The device provides five banks of outputs and a reference clock. The banks can be enabled by using a common output enable pin. A 25MHz crystal is used to generate the 50MHz, 66.67MHz, 87.5MHz, 100MHz, 125MHz, 133MHz and 350MHz frequencies. VEE GENERAL DESCRIPTION • ±5% frequency margining • Full 3.3V operating supply • 0°C to 70°C ambient operating temperature 32 31 30 29 28 27 26 25 F_SEL0 1 F_SEL1 2 VCC 3 XTAL_IN 4 XTAL_OUT 5 VEE 6 VCCA2 7 RESET 8 ICS843S2807 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View • Available in both standard (RoHS 5) and lead-free (RoHS6) packages 24 VCC 23 QA1 22 nQA1 21 VCCA1 20 VEE 19 QC0 18 nQC0 17 VCC BLOCK DIAGRAM LVCMOS - 25MHz REF_OUT LVCMOS - 133MHz ÷5.2631 VCC nQD0 QD0 VEE PLL_BYPASS MARGIN_MODE OE MARGIN 9 10 11 12 13 14 15 16 QA0 2 F_SEL[1:0] Pullup PLL_BYPASS Pulldown 1 LVPECL - 66.67/100/ 125MHz 25MHz XTAL_IN VCO Phase Detector OSC 700MHz XTAL_OUT 0 ÷5.6, ÷7, ÷10.5 QA1 nQA1 LVCMOS - 50MHz QB0 ÷28 ÷14 QB1 ±5% Frequency Margining LVPECL - 87.5MHz QC0 ÷8 nQC0 LVDS - 350MHz QD0 ÷2 MARGIN Pulldown nQD0 MARGIN_MODE Pulldown RESET Pulldown OE Pullup The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 1 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 16, 17, 24 4, 5 6, 13, 20, 27, 32 Name F_SEL0, F_SEL1 VCC XTAL_IN, XTAL_OUT Type VEE Power Negative supply pins. 7, 21 VCCA2, VCCA1 Power Analog supply pins. 8 RESET Input 9 OE Input 10 MARGIN Input 11 MARGIN_MODE Input 12 PLL_BYPASS Input 14, 15 QD0, nQD0 Output 18, 19 nQC0, QC0 Output Differential Bank C clock outputs. LVPECL interface levels. 22, 23 nQA1, QA1 Output Differential Bank A clock outputs. LVPECL interface levels. 25, 30 VCCO_LVCMOS Power Output supply pins for LVCMOS/LVTTL outputs. Input Pullup Power Input Description Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3A. Core supply pins. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Pulldown Resets the dividers and PLL. LVCMOS/LVTTL interface levels. Pullup Output enable pin. LVCMOS/LVTTL interface levels. Selects between the margin and normal mode. Pulldown LVCMOS/LVTTL interface levels. See Table 3B. Selects between ±5% margin. Pulldown LVCMOS/LVTTL interface levels. See Table 3B. Selects between the PLL and XTAL as the input to the dividers. Pulldown When LOW, selects PLL. When HIGH, selects XTAL. LVCMOS/LVTTL interface levels. Differential Bank D clock outputs. LVDS interface levels. Single-ended Bank A clock output. 26 QA0 Output LVCMOS/LVTTL interface levels. 15Ω impedance. Single-ended Bank B clock outputs. 28, 29 QB1, QB0 Output LVCMOS/LVTTL interface levels. 15Ω impedance. Reference clock output. LVCMOS/LVTTL interface levels. 31 REF_OUT Output 15Ω impedance. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions QA0, QB0, QB1, REF_OUT Minimum Typical Maximum Units 4 pF TBD pF CPD Power Dissipation Capacitance RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ 15 Ω ROUT Output Impedance QA0, QB0, QB1, REF_OUT IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR VCC, VCCO_LVCMOS = 3.465V VCCO_LVCMOS = 3.465V 2 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR TABLE 3A. F_SELX FUNCTION TABLE Inputs PRELIMINARY TABLE 3B. MARGIN/MARGIN_MODE FUNCTION TABLE Inputs F_SEL1 0 F_SEL0 1 QA1 Output Frequency (MHz) 100 1 0 125 X 0 Nominal 1 1 66.67 (default) 1 1 +5% MARGIN 0 MARGIN_MODE 1 Operation -5 % ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVCMOS) -0.5V to VCCO_LVCMOS + 0.5V ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. 10mA 15mA Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Outputs, IO (LVDS) Continuous Current Surge Current Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA Junction-to-Case 71.9°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V ± 5%,TA = 0°C TO 70°C Symbol V CC Parameter Core Supply Voltage VCCA Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V Analog Supply Voltage VCC – ICCA * 10Ω 3.3 VCC V 3.135 3.3V 3.465 VCCO_LVCMOS Output Supply Voltage IEE Power Supply Current TBD mA ICCA Analog Supply Current TBD mA IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 3 V ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V ± 5%,TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V 15 0 µA 5 µA PLL_BYPASS, RESET, MARGIN, VCC = VIN = 3.465V Input IIH MARGIN_MODE High Current OE, F_SEL[1:0] PLL_BYPASS, Input RESET, MARGIN, VCC = 3.465V, VIN = 0V -5 IIL MARGIN_MODE Low Current OE, F_SEL[1:0] -150 Output REF_OUT, 2.6 VOH VCCO_LVCMOS = 3.465V±5% High Voltage; NOTE 1 QA0, QB0, QB1 Output REF_OUT, VOL VCCO_LVCMOS = 3.465V±5% Low Voltage; NOTE 1 QA0, QB0, QB1 NOTE 1: Outputs terminated with 50Ω to VCCO_LVCMOS/2. See Parameter Measurement Information, Output Load Test Circuit diagram. µA µA V 0.5 V Maximum Units TABLE 4C. LVDS DC CHARACTERISTICS, VCC = 3.3V ± 5%,TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical 400 mV 50 mV 1.25 V 50 mV TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V ± 5%,TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Ω Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant cr ystal. IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 4 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY TABLE 6. AC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V ± 5%,TA = 0°C TO 70°C Symbol fOUT tsk(b) tjit(cc) Parameter Output Frequency Bank Skew; NOTE 1, 2 Cycle-to-Cycle Jitter; NOTE 2 Test Conditions Minimum Typical Maximum Units QD0/nQD0 350 MH z QA0 13 3 MHz QA1/nQA1 F_SEL1 = 1, F_SEL0 = 1 66.67 MHz QA1/nQA1 F_SEL1 = 0, F_SEL0 = 1 100 MHz QA1/nQA1 F_SEL1 = 1, F_SEL0 = 0 125 MHz QB0, QB1 50 MHz QC0/nQC0 87.5 MHz REF_OUT 25 MHz QB0, QB1 TBD ps REF_OUT 75 ps QA0 150 ps QB0, QB1 75 ps QA1/nQA1 20 0 ps QC0/nQC0 50 ps QD0/nQD0 50 REF_OUT, 20% to 80% 350 QA0, QB0, QB1 Output QA1/nQA1, t R / tF 20% to 80% 250 Rise/Fall Time QC0/nQC0 QD0/nQD0 20% to 80% 400 REF_OUT, 45 QA0, QB0, QB1 QA1/nQA1, Output Duty Cycle odc 45 QC0/nQC0 QD0/nQD0 45 NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 5 ps ps ps ps 55 % 55 % 55 % ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.65V±5% SCOPE VCC 3.3V±5% POWER SUPPLY + Float GND – Qx LVCMOS VCCA1, VCCA2 SCOPE VCC, VCCO_LVCMOS VCCA1, VCCA2 Qx LVDS GND nQx -1.65V±5% 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 2V 2V VCC Qx SCOPE VCCO 2 QBx VCCA1, VCCA2 LVPECL VCCO 2 QBx nQx VEE t sk(b) -1.3V ± 0.165V 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT LVCMOS BANK SKEW nQA1, nQC0, nQD0 QA0, QB0, QB1, REF_OUT QA1, QC0, QD0 t PW t odc = t PERIOD t PW t PW odc = x 100% t PW x 100% t PERIOD t PERIOD DIFFERENTIAL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR PERIOD 6 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION, CONTINUED 80% 80% 80% 80% VOD VSW I N G Clock Outputs Clock Outputs 20% 20% tR 20% 20% tF tR tF LVDS OUTPUT RISE/FALL TIME LVPECL OUTPUT RISE/FALL TIME VDDO_LVDS Clock Outputs out 80% DC Input 20% 20% tR LVDS ➤ 80% tF out ➤ VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP LVCMOS OUTPUT RISE/FALL TIME Phase Noise Plot LVDS 100 ➤ VOD/Δ VOD out Phase Noise Mask ➤ DC Input ➤ out Noise Power VDD f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 7 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843S2807 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA1, VCCA2 and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that V CCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. LVDS OUTPUTS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CRYSTAL INPUT INTERFACE The ICS843S2807 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz crystal and were chosen to minimize the ppm error. XTAL_IN C1 14p X1 18pF Parallel Crystal XTAL_OUT C2 14p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 8 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY LVCMOS TO XTAL INTERFACE (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 9 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 5A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 84Ω FIGURE 5B. LVPECL OUTPUT TERMINATION 10 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 71.9°C/W 62.1°C/W 58.5°C/W TRANSISTOR COUNT The transistor count for ICS843S2807 is: 11,230 IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 11 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 12 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 843S2807BY TBD 32 Lead LQFP tray 0°C to 70°C 843S2807BYT TBD 32 Lead LQFP 1000 tape & reel 0°C to 70°C 843S2807BYLF ICS43S2807BL 32 Lead "Lead-Free" LQFP tray 0°C to 70°C 843S2807BYLFT ICS43S2807BL 32 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE: par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVPECL/LVDS/LVCMOS CLOCK GENERATOR 13 ICS843S2807BY REV. A JANUARY 30, 2008 ICS843S2807 FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Japan Asia Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) NIPPON IDT KK Sanbancho Tokyu Bld. 7F, 8-1 Sanbancho Chiyoda-ku, Tokyo 102-0075 +81 3 3221 9822 +81 3 3221 9824 (fax) Integrated Device Technology IDT (S) Pte. Ltd. 1 Kallang Sector, #07-01/06 Kolam Ayer Industrial Park Singapore 349276 +65 6 744 3356 +65 6 744 1764 (fax) IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA