ISL54059 Data Sheet March 11, 2011 Negative Signal Swing, Sub-ohm, Dual SPDT Single Supply Switch Features • Pb-Free (RoHS Compliant) The Intersil ISL54059 device is a low ON-resistance, low voltage, bi-directional, dual single-pole/double-throw (SPDT) analog switch. It is designed to operate from a single +1.8V to +6.5V supply and pass signals that swing down to 6.5V below the positive supply rail. Targeted applications include battery powered equipment that benefit from low rON (0.56Ω), low power consumption (8nA) and fast switching speeds (tON = 55ns, tOFF = 18ns). The digital inputs are 1.8V logic-compatible up to a +3V supply. The ISL54059 is offered in a small form factor package, alleviating board space limitations. It is available in a tiny 10 Ld 1.8x1.4mm µTQFN or 10 Ld 3x3mm TDFN package. The ISL54059 is a committed dual single-pole/double-throw (SPDT) that consists of two normally open (NO) and two normally closed (NC) switches with independent logic control. This configuration can be used as a dual 2-to-1 multiplexer. TABLE 1. FEATURES AT A GLANCE ISL54059 2 SW SPDT or 2-to-1 MUX 4.3V rON 0.65Ω 4.3V tON/tOFF 43ns/23ns 2.7V rON 0.9Ω 2.7V tON/tOFF 55ns/18ns 1.8V rON 1.8Ω 1.8V tON/tOFF 145ns/28ns Packages 10 Ld µTQFN, 10 Ld TDFN rON (Ω) 1.8 • ON-Resistance (rON) - V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.52Ω - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω - V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9Ω - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8Ω • rON Matching Between Channels . . . . . . . . . . . . . . . . . 10mΩ • rON Flatness Across Signal Range . . . . . . . . . . . . . . . . 0.33Ω • Low THD+N @ 32Ω Load . . . . . . . . . . . . . . . . . . . . . . .0.02% • Single Supply Operation . . . . . . . . . . . . . . . . .+1.8V to +6.5V • Low Power Consumption @ 3V (PD) . . . . . . . . . . . 24nW • Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ns • Guaranteed Break-before-Make • 1.8V Logic Compatible (+3V supply) • Low I+ Current when VINH is not at the V+ Rail • Available in 10 Ld µTQFN 1.8x1.4mm and 10 Ld 3x3mm TDFN Applications • Audio and Video Switching ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE ICOM = 100mA • Negative Signal Swing (Max 6.5V Below V+) • ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Number of Switches 2.0 FN6579.2 • Battery-powered, Handheld, and Portable Equipment - MP3 and Multimedia Players - Cellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Portable Test and Measurement V+ = 1.8V 1.6 • Medical Equipment 1.4 Related Literature 1.2 • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” 1.0 V+ = 2.7V 0.8 0.6 • Application Note AN557 “Recommended Test Procedures for Analog Switches” V+ = 4.5V 0.4 0.2 -6 -5 -4 -3 -2 0 -1 VCOM (V) 1 1 2 3 4 5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL54059 Pinout Truth Table (Note 1) ISL54059 (10 LD TDFN) TOP VIEW 10 IN2 IN1 1 9 NO2 NO1 2 8 COM2 COM1 3 NC1 4 7 NC2 GND 5 6 V+ IN2 7 6 NO1 8 COM1 9 4 NC1 10 3 5 IN2 NC1 NO1 NC2 NO2 0 0 ON OFF ON OFF 0 1 ON OFF OFF ON 1 0 OFF ON ON OFF 1 1 OFF ON OFF ON NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply. Pin Descriptions ISL54059 (10 LD µTQFN) TOP VIEW IN1 IN1 NO2 COM2 NC2 PIN FUNCTION V+ IC Power Supply (+1.8V to +6.5V). Decouple V+ to ground by placing a 0.1µF capacitor at the V+ and GND supply lines as near as the IC as possible. GND Ground Connection INx Digital Control Input COM Analog Switch Common Pin NOx Analog Switch Normally Open Pin NCx Analog Switch Normally Closed Pin 2 1 GND V+ NOTE: 1. Switches Shown for INx = Logic “0”. Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL54059IRTZ (Note 3) 4059 -40 to +85 10 Ld 3x3 TDFN L10.3x3A ISL54059IRTZ-T (Notes 2, 3) 4059 -40 to +85 10 Ld 3x3 TDFN (Tape and Reel) L10.3x3A ISL54059IRUZ-T (Notes 2, 4) 7 -40 to +85 10 Ld Thin µTQFN (Tape and Reel) L10.1.8x1.4A NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6579.2 March 11, 2011 ISL54059 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V Input Voltages NOx, NCx (Note 5) . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) INx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COMx (Note 5) . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) Continuous Current NOx, NCx, or COMx. . . . . . . . . . . . . ±300mA Peak Current NOx, NCx, or COMx (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld 3x3 TDFN Package (Notes 6, 8) 52 18 10 Ld µTQFN Package (Note 7) . . . . . 154 N/A Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Signals on NC, NO, IN, or COM exceeding V+ or GND by specified amount are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless Otherwise Specified. PARAMETER TEST CONDITIONS TEMP MIN (°C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS ANALOG SWITCH CHARACTERISTICS V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ - 6.5) to V+ (see Figure 5) 25 - 0.52 - Ω Full - 0.68 - Ω rON Matching Between Channels, ΔrON V+ = 4.5V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 13) 25 - 10 - mΩ Full - 13.1 - mΩ rON Flatness, RFLAT(ON) V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ - 6.5) to V+, (Note 12) 25 - 0.11 - Ω Full - 0.14 - Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = 5V, -1.5V 25 - -8.13 - nA COM ON Leakage Current, ICOM(ON) V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = Float ON-Resistance, rON Full - -0.4 - µA 25 - -4.42 - nA Full - -0.33 - µA 25 - 35 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) Full - 50 - ns 25 - 16 - ns Full - 22 - ns Break-Before-Make Time Delay, tD V+ = 5.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 3) Full - 18 - ns Charge Injection, Q VG = 0V, RG = 0Ω, CL = 1.0nF (see Figure 2) 25 - 170 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS (see Figure 4) 25 - 60 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VRMS (see Figure 6) 25 - -75 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω 25 - 0.02 - % -3dB Bandwidth VCOM = 1VRMS, RL = 50Ω, CL = 5pF 25 - 60 - MHz 3 FN6579.2 March 11, 2011 ISL54059 Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless Otherwise Specified. (Continued) PARAMETER TEST CONDITIONS TEMP MIN (°C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS NO x or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 25 - 88 - pF POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ 25 - 0.008 0.1 µA Full - 1.41 - µA Full - - 0.8 V Full 2.4 - - V 25 -0.1 - 0.1 µA Full - 0.3 - µA DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Electrical Specifications - 4.3V Supply PARAMETER Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9), Unless Otherwise Specified. TEST CONDITIONS TEMP MIN (°C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+, (See Figure 5) rON Matching Between Channels, ΔrON V+ = 4.3V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 12) rON Flatness, RFLAT(ON) V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+, (Note 13) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = 4.3V, -1.2V COM ON Leakage Current, ICOM(ON) V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = Float 25 - 0.65 - Ω Full - 0.72 - Ω 25 - 10 - mΩ Full - 15 - mΩ 25 - 0.1 - Ω Full - 0.14 - Ω 25 -0.1 - 0.1 µA Full -1 -0.33 1 µA 25 -0.1 - 0.1 µA Full -1 -0.33 1 µA 25 - 43 - ns Full - 50 - ns 25 - 23.1 - ns Full - 23.2 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) Break-Before-Make Time Delay, tD V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 3) Full - 22 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 200 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS (see Figure 4) 25 - 60 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VRMS (see Figure 6) 25 - -75 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω 25 - 0.04 - % NOx or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF 4 FN6579.2 March 11, 2011 ISL54059 Electrical Specifications - 4.3V Supply PARAMETER COMx ON Capacitance, CCOM(ON) Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9), Unless Otherwise Specified. (Continued) TEST CONDITIONS f = 1MHz (see Figure 7) TEMP MIN (°C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS 25 - 88 - pF 25 - 0.003 0.1 µA Full - 0.9 - µA 25 - 0.78 12 µA Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.6 - - V 25 -0.5 - 0.5 µA Full - 0.2 - µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ V+ = +4.2V, VIN = 2.85V DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 9), Unless Otherwise Specified. PARAMETER TEST CONDITIONS TEMP MIN MAX (°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+ (see Figure 5) rON Matching Between Channels, ΔrON V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 13) rON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+ (Note 12, 14) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 1) 25 Ω - 0.9 - Full - 0.96 - Ω 25 - 10 - mΩ Full - 17 - mΩ 25 - 0.33 0.5 Ω Full - 0.35 0.55 Ω 25 - 55 - ns Full - 82 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 1) Turn-OFF Time, tOFF V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 3) Break-Before-Make Time Delay, tD 25 - 18 - ns Full - 24 - ns Full - 30 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 150 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS (see Figure 4) 25 - 60 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VRMS (see Figure 6) 25 - -75 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω 25 - 0.04 - % NOx or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 25 - 88 - pF 25 - - 0.5 V DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ 5 25 1.4 - - V 25 -0.5 - 0.5 µA Full - 0.2 - µA FN6579.2 March 11, 2011 ISL54059 Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 9), Unless Otherwise Specified. PARAMETER TEST CONDITIONS TEMP (°C) MIN (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS 25 - 1.87 - Ω Full - 1.97 - Ω 25 - 16 - mΩ Full - 30 - mΩ 25 - 1.34 - Ω Full - 1.43 - Ω ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+, (see Figure 5) rON Matching Between Channels, ΔrON V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 13) rON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+ (Notes 12) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 1) Break-Before-Make Time Delay, V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF tD (see Figure 3) 25 - 145 - ns Full - 150 - ns 25 - 20 - ns Full - 22 - ns Full - 130 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 40 - pC NOx or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 25 - 88 - pF 25 - - 0.4 V DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL 25 1.0 - - V Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ 25 -0.5 - 0.5 µA Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ Full - 0.19 - µA Input Voltage High, VINH NOTES: 9. VIN = input voltage to perform proper function. 10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NC1 and NC2 or between NO1 and NO2. 14. Limits established by characterization and are not production tested. 6 FN6579.2 March 11, 2011 ISL54059 Test Circuits and Waveforms V+ LOGIC INPUT V+ tr < 5ns tf < 5ns 50% 0V tOFF SWITCH INPUT VNO SWITCH INPUT VOUT NO OR NC COM IN VOUT 90% SWITCH OUTPUT C 90% LOGIC INPUT CL 35pF RL 50Ω GND 0V tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------R L + r ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ RG SWITCH OUTPUT VOUT C VOUT COM NO OR NC ΔVOUT VG GND IN CL V+ LOGIC INPUT ON ON OFF LOGIC INPUT 0V Q = ΔVOUT x CL Repeat test for all switches. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ V+ LOGIC INPUT VNX NO VOUT COM NC 0V 90% 0V LOGIC INPUT CL 35pF RL 50Ω IN SWITCH OUTPUT VOUT C GND tBBM FIGURE 3A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 7 FN6579.2 March 11, 2011 ISL54059 Test Circuits and Waveforms (Continued) V+ C *50Ω SOURCE V+ C SIGNAL GENERATOR rON = V1/100mA NO OR NC NO OR NC IN VNX 0V OR V+ 100mA 0V OR V+ IN V1 COM ANALYZER GND COM RL GND Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. Repeat test for all switches. FIGURE 4. OFF-ISOLATION TEST CIRCUIT *50Ω SOURCE FIGURE 5. rON TEST CIRCUIT V+ V+ C SIGNAL GENERATOR NO1 OR NC1 COM1 C NO OR NC 50Ω IN INX 0V OR V+ IMPEDANCE ANALYZER 0V OR V+ COM NC2 OR NO2 COM2 ANALYZER GND NC GND RL Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Description The ISL54059 is a bi-directional, dual single pole-double throw (SPDT) analog switch that offers precise switching from a single 1.8V to 6.5V supply with low ON-resistance (0.83Ω) and high speed operation (tON = 55ns, tOFF = 18ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (8nA), and a tiny 1.8x1.4mm µTQFN package or a 3x3mm TDFN package. The low ON-resistance and rON flatness provide very low insertion loss and signal distortion for applications that require signal switching with minimal interference by the switch. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. The ISL54059 8 COM is connected to NO or NC during ON capacitance measurement. FIGURE 7. CAPACITANCE TEST CIRCUIT contains ESD protection diodes on each pin of the IC (see Figure 8). These diodes connect to either a +Ring or -Ring for ESD protection. To prevent forward biasing the ESD diodes to the +Ring, V+ must be applied before any input signals, and the input signal voltages must remain between recommended operating range. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a logic pin or switch terminal goes above the V+ rail. Logic inputs can be protected by adding a 1kΩ resistor in series with the logic input (see Figure 8). The resistor limits FN6579.2 March 11, 2011 ISL54059 the input current below the threshold that produces permanent damage. from -1.5V to +5V. If V+ = 2.7V then the range is from -3.8V to +2.7V. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting external Schottky diodes to the signal pins will shunt the fault current to the V+ supply instead of through the internal ESD diodes therefore protecting the switch. These Schottky diodes must be sized to handle the expected fault current. Logic-Level Thresholds V+ +RING VCOMx VNCx VNOx CLAMP 1kΩ LOGIC INPUTS GND -RING This switch family is 1.8V CMOS compatible (0.45V VOLMAX and 1.35V VOHMIN) over a supply range of 1.8V to 3.3V (see Figure 16). At 3.3V the VIL level is 0.5V maximum. This is still below the 1.8V CMOS guaranteed low output maximum level of 0.45V, but noise margin is reduced. At 3.3V the VIH level is 1.4V minimum. While this is above the 1.8V CMOS guaranteed high output minimum of 1.35V, under most operating conditions the switch will recognize this as a valid logic high. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54059 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example, driving the device with 2.85V logic high while operating with a 4.2V supply the device draws only 1µA of current. High-Frequency Performance FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL54059 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 5.5V maximum supply voltage, the ISL54059’s 6.5V maximum supply voltage provides plenty of head room for the 10% tolerance of 5V supplies due to overshoot and noise spikes. The minimum recommended supply voltage is 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the “Electrical Specifications” tables, beginning on page 3, and “Typical Performance Curves”, beginning on page 10, for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to V+ and GND signals levels to drive the analog switch gate terminals. A high frequency decoupling capacitor placed as close to the V+ and GND pin as possible is recommended for proper operation of the switch. A value of 0.1µF is highly recommended. Negative Signal Swing Capability The ISL54059 contains circuitry that allows the analog switch signal to swing below ground. The device has an analog signal range of 6.5V below V+ up to the V+ rail (see Figure 14) while maintaining low rON performance. For example, if V+ = 5V, then the analog input signal range is 9 In 50Ω systems, the ISL54065 has an ON switch -3dB bandwidth of 60MHz (see Figure 19). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor across the open terminals and AC couples higher frequencies, resulting in signal feed-through from a switch’s input to its output. Off Isolation is the resistance to this feed-through. Crosstalk indicates the amount of feed-through from one switch channel to another switch channel. Figure 20 details the high Off-Isolation and Crosstalk rejection provided by this part. At 100kHz, Off-Isolation is about 60dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. At 1MHz, Crosstalk is about -75dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin, V+ and GND. One of these diodes conducts if any analog signal exceeds the recommended analog signal range. Virtually all the analog switch leakage current comes from the ESD diodes and reversed biased junctions in the switch cell. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased to either the +Ring or -Ring and the analog input signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the +Ring or -Ring and the reverse biased junctions at the internal switch cell constitutes the analog-signal-path leakage current. FN6579.2 March 11, 2011 ISL54059 Typical Performance Curves TA = +25°C, Unless Otherwise Specified 1.00 2.0 ICOM = 100mA 1.8 0.90 0.85 1.6 0.80 1.4 0.75 1.2 rON (Ω) rON (Ω) V+ = 4.5V ICOM = 100mA 0.95 V+ = 1.8V 1.0 0.65 0.60 T = +25°C 0.55 V+ = 2.7V 0.8 T = +85°C 0.70 0.50 0.6 T = -40°C 0.45 V+ = 4.5V 0.40 0.4 0.35 0.2 -6 -5 -3 -4 -2 0 -1 1 2 3 4 0.30 5 -3 -2 0 -1 1 VCOM (V) VCOM (V) FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 3 4 5 FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE 1.25 1.00 0.95 V+ = 4.3V ICOM = 100mA 0.90 V+ = 2.7V ICOM = 100mA 1.15 0.85 1.05 0.80 0.95 0.70 rON (Ω) 0.75 rON (Ω) 2 T = +85°C 0.65 0.60 T = +25°C 0.55 0.85 0.75 0.65 T = +85°C 0.55 T = +25°C 0.50 T = -40°C 0.45 0.40 0.45 0.35 0.30 -3 -2 0 -1 1 2 3 4 0.35 -5 5 T = -40°C -4 -3 0 -1 VCOM (V) -2 VCOM (V) 2 3 FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE 2.2 6 V+ = 1.8V 2.0 ANALOG SIGNAL RANGE (V) 1.4 1.2 1.0 0.8 T = +85°C T = +25°C 0.4 0.2 -5 3 2 1 0 -1 -2 -3 SIGNAL MIN -4 -5 T = -40°C 6 SIGNAL MAX 4 1.6 0.6 4 5 ICOM = 100mA 1.8 rON (Ω) 1 -4 -3 -2 -1 VCOM (V) 0 1 2 FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE 10 3 -6 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 6.0 FIGURE 14. ANALOG SIGNAL RANGE vs SUPPLY VOLTAGE FN6579.2 March 11, 2011 ISL54059 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 700 V+ = 5.5V 650 ABSOLUTE VALUES 600 550 500 VINH AND VINL (V) V+ = 4.5V Q (pC) 450 400 350 V+ = 3.3V 300 250 200 150 100 V+ = 2.0V 50 0 -5 -4 -3 -2 -1 0 1 VCOM (V) 2 3 4 5 6 FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 VINH VINL 2.0 2.5 3.0 V+ (V) 3.5 40 T = -40°C 140 T = -40°C 35 T = +25°C T = +85°C 120 25 tOFF (ns) tON (ns) T = +25°C T = +85°C 30 100 80 20 60 15 40 10 20 5 1.8 3.3 V+ (V) 4.5 0 5.5 1.8 3.3 4.5 5.5 V+ (V) FIGURE 17. TURN - ON TIME vs SUPPLY VOLTAGE FIGURE 18. TURN - OFF TIME vs SUPPLY VOLTAGE 0 V+ = 1.8V TO 5.5V -1 -10 V+ = 1.8V TO 5.5V -20 RL = 50Ω VIN = 1VRMS @ 0VDC OFFSET -30 -2 CROSSTALK (dB) NORMALIZED GAIN (dB) 4.5 FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE 160 0 4.0 -3 -4 -5 -40 -50 OFF-ISOLATION -60 CROSSTALK -70 -80 -90 RL = 50Ω VIN = 1VRMS @ 0VDC OFFSET 1k 10k 100k 1M 10M FREQUENCY (Hz) -100 100M FIGURE 19. FREQUENCY RESPONSE 11 1G -110 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 20. CROSSTALK AND OFF ISOLATION FN6579.2 March 11, 2011 ISL54059 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 0.05 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): 707mVRMS 0.04 GND (DFN Paddle Connection: Tie to GND or Float) TRANSISTOR COUNT: THD+N (%) 360mVRMS 432 0.03 PROCESS: 0.01 Submicron CMOS 177mVRMS 0.02 V+ = 3.3V VBIAS = 0VDC RL = 32Ω 0 20 100 200 1k 2k FREQUENCY (Hz) 10k 20k FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY 12 FN6579.2 March 11, 2011 ISL54059 Thin Dual Flat No-Lead Plastic Package (TDFN) L10.3x3A 2X 0.10 C A A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.10 C B E B // A C SEATING PLANE D2 (DATUM B) 6 INDEX AREA 0.10 C 0.08 C A3 SIDE VIEW 7 8 MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - 0.20 REF b 0.20 0.25 1 0.30 5, 8 D 2.95 3.0 3.05 - D2 2.25 2.30 2.35 7, 8 E 2.95 3.0 3.05 - E2 1.45 1.50 1.55 7, 8 e 0.50 BSC - k 0.25 - - - L 0.25 0.30 0.35 8 N 10 2 Nd 5 3 Rev. 3 3/06 NOTES: 2 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. NX k 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. E2 E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 0.10 M C A B 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions. CL NX (b) NOMINAL D2/2 (DATUM A) 8 MIN A3 6 INDEX AREA TOP VIEW SYMBOL (A1) L1 5 9 L e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE 13 FN6579.2 March 11, 2011 ISL54059 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D 6 INDEX AREA 2X A L10.1.8x1.4A B N 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS E SYMBOL 0.10 C 1 2X 2 0.10 C TOP VIEW C A 0.05 C SIDE VIEW (DATUM A) PIN #1 ID 1 2 NX L NX b 5 10X 0.10 M C A B 0.05 M C L1 5 (DATUM B) 7 MAX NOTES 0.50 0.55 - A1 - - 0.05 - 0.127 REF - b 0.15 0.20 0.25 5 D 1.75 1.80 1.85 - E 1.35 1.40 1.45 - e A1 NOMINAL 0.45 A3 0.10 C SEATING PLANE MIN A 0.40 BSC - L 0.35 0.40 0.45 L1 0.45 0.50 0.55 - N 10 2 Nd 2 3 Ne 3 3 θ 0 - 12 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. e 3. Nd and Ne refer to the number of terminals on D and E side, respectively. BOTTOM VIEW 4. All dimensions are in millimeters. Angles are in degrees. NX (b) 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. CL (A1) 5 L 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. SECTION "C-C" e 8. Maximum allowable burrs is 0.076mm in all directions. TERMINAL TIP C C 2.20 1.00 0.60 1.00 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 0.50 1.80 0.40 0.20 0.20 0.40 10 LAND PATTERN All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6579.2 March 11, 2011