IDT IDT71V2577Y80PF

128K x 36, 256K x 18
3.3V Synchronous SRAMs
2.5V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Description
Features
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IDT71V2577S
IDT71V2579S
IDT71V2577SA
IDT71V2579SA
The IDT71V2577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V2577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
128K x 36, 256K x 18 memory configurations
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
Commercial and Industrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA)
Pin Description Summary
A0-A17
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0, CS1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
(1)
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
Sleep Mode
Input
Asynchronous
ZZ
I/O0-I/O31,
I/OP1-I/OP4
I/O
Synchronous
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Supply
N/A
VSS
Ground
Supply
N/A
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V2579.
4877 tbl 01
1
© 2003 ntegrated Device Technology, Inc.
JUNE 2003
DSC-4877/08
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definition(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of
CLK and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the
address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address
Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst
counter is not incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of
CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs
are blocked and only GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchro nous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active
byte write causes all outputs to be disabled.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS 0 and CS1 to enable the IDT71V2577/79. CE also gates
ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect to this input.
CS0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS 0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I
LOW
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
Enable
I
LOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge
of CLK. The data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Asynchronous burst ord er selection input. When LBO is HIGH, the inter-leaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not
change state while the device is operating.
OE
Output Enable
I
LOW
Asynchrono us output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the
chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS
Test ModeSelect
I
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test DataOutput
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST
JTAG Reset
(Optional)
I
LOW
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST
can be left floating. This pin has an internal pullup. Only available in BGA package.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK inte rnally and power down the IDT71V2577/79
to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal
pull down.
VDD
Power Supply
N/A
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
N/A
2.5V I/O Supply.
VSS
Ground
N/A
N/A
Ground.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the device.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
4877 tbl 02
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
Burst
Logic
Q0
CLR
ADSP
Q1
CLK EN
ADDRESS
REGISTER
A0 - A16/17
GW
BWE
INTERNAL
ADDRESS
Burst
Sequence
CEN
2
A0,A1
17/18
A0*
A1*
128K x 36/
256K x 18BIT
MEMORY
ARRAY
A2 - A17
36/18
17/18
Byte 1
Write Register
36/18
Byte 1
Write Driver
BW1
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
9
Byte 3
Write Register
Byte 3
Write Driver
BW3
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
9
CE
CS0
CS1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
OE
OE
I/O0 - I/O31
I/OP1 - I/OP4
OUTPUT
BUFFER
36/18
4877 drw 01
TMS
TDI
TCK
TRST
(Optional)
JTAG
(SA Version)
TDO
6.42
3
,
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Rating
Commerical &
Industrial Values
Unit
VTERM(2)
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
Operating Temperature
-0 to +70
Industrial
Operating Temperature
-40 to +85
o
C
Temperature
Under Bias
-55 to +125
o
C
Storage
Temperature
-55 to +125
TA
(7)
TBIAS
TSTG
o
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V
3.3V±5%
2.5V±5%
Industrial
-40°C to +85°C
0V
3.3V±5%
2.5V±5%
NOTES:
1. TA is the “instant on” case temperature.
Recommended DC Operating
Conditions
C
Symbol
o
C
Power Dissipation
2.0
W
IOUT
DC Output Current
50
mA
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDQ
I/O Supply Voltage
2.375
2.5
2.625
V
VSS
Supply Voltage
V
VIH
Input High Voltage - Inputs
VIH
VIL
PT
4877 tbl 04
Input High Voltage - I/O
Input Low Voltage
0
0
0
1.7
____
VDD + 0.3
____
1.7
(2)
-0.3
____
V
(1)
VDDQ + 0.3
0.7
V
V
4877 tbl 05
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
4877 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the “instant on” case temperature.
100 Pin TQFP Capacitance
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
(TA = +25°C, f = 1.0MHz)
Max.
Unit
Symbol
VIN = 3dV
5
pF
CIN
Input Capacitance
VOUT = 3dV
7
pF
CI/O
I/O Capacitance
4877 tbl 07
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Parameter(1)
Conditions
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
4877 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
Conditions
Max.
Unit
V IN = 3dV
7
pF
VOUT = 3dV
7
pF
4877 tbl 07a
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
4
78
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
NC
NC
A10
A11
A12
A13
A14
A15
A16
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
4877 drw 02a
,
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
A6
A7
CE
CS0
NC
NC
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration – 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
2
79
3
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VSS(1)
VDD
NC
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
78
77
5
76
6
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
15
67
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
VSS
VDD
NC
NC
A11
A12
A13
A14
A15
A16
A17
LBO
A5
A4
A3
A2
A1
A0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
4877 drw 02b
,
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 119 BGA
1
2
3
4
5
6
7
A
VDDQ
A6
A4
ADSP
A8
A16
VDDQ
B
NC
CS0
A3
ADSC
A9
CS1
NC
C
NC
A7
A2
VDD
A12
A15
NC
D
I/O16
I/OP3
VSS
NC
VSS
I/OP2
I/O15
E
I/O17
I/O18
VSS
CE
VSS
I/O13
I/O14
F
VDDQ
I/O19
VSS
OE
VSS
I/O12
VDDQ
G
I/O20
I/O21
BW3
ADV
BW2
I/O11
I/O10
H
I/O22
I/O23
VSS
GW
VSS
I/O9
I/O8
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
I/O24
I/O26
VSS
CLK
VSS
I/O6
I/O7
L
I/O25
I/O27
BW4
NC
BW1
I/O4
I/O5
M
VDDQ
I/O28
VSS
BWE
VSS
I/O3
VDDQ
N
I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P
I/O31
I/OP4
VSS
A0
VSS
I/O0
I/OP1
R
NC
A5
LBO
VDD
VSS
A13
NC
T
NC
NC
A10
A11
A14
NC
ZZ(3)
U
VDDQ
NC/TMS(2) NC/TDI(2) NC/TCK(2)
NC/TDO(2)
,
NC/TRST(2,4) VDDQ
4877 drw 02c
Top View
Pin Configuration – 256K x 18, 119 BGA
1
2
3
4
5
6
7
A
VDDQ
A6
A4
ADSP
A8
A16
VDDQ
B
NC
CS0
A3
ADSC
A9
CS1
NC
C
NC
A7
A2
VDD
A13
A17
NC
D
I/O8
NC
VSS
NC
VSS
I/O7
NC
E
NC
I/O9
VSS
CE
VSS
NC
I/O6
F
VDDQ
NC
VSS
OE
VSS
I/O5
VDDQ
G
NC
I/O10
BW2
ADV
VSS
NC
I/O4
H
I/O11
NC
VSS
GW
VSS
I/O3
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
I/O12
VSS
CLK
VSS
NC
I/O2
L
I/O13
NC
VSS
NC
BW1
I/O1
NC
M
VDDQ
I/O14
VSS
BWE
VSS
NC
VDDQ
N
I/O15
NC
VSS
A1
VSS
I/O0
NC
P
NC
I/OP2
VSS
A0
VSS
NC
I/OP1
R
NC
A5
LBO
VDD
VSS
A12
NC
T
NC
A10
A15
NC
A14
A11
ZZ(3)
U
VDDQ
NC/TMS(2) NC/TDI(2) NC/TCK(2)
NC/TDO(2) NC/TRST(2,4) VDDQ
Top View
,
4877 drw 02d
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
7
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC(4)
A7
CE1
BW3
BW2
CS1
BWE
ADSC
ADV
A8
NC
B
NC
A6
CS 0
BW4
BW1
CLK
GW
OE
ADSP
A9
NC(4)
C
I/OP3
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP2
D
I/O17
I/O16
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O15
I/O14
E
I/O19
I/O18
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O13
I/O12
F
I/O21
I/O20
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O11
I/O10
G
I/O23
I/O22
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O9
I/O8
H
VSS
(1)
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ(3)
J
I/O25
I/O24
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O7
I/O6
K
I/O27
I/O26
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O5
I/O4
L
I/O29
I/O28
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
I/O2
M
I/O31
I/O30
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
I/O0
NC
VSS
VDDQ
NC
I/OP1
(4)
N
I/OP4
NC
VDDQ
VSS
NC/TRST(2,5)
P
NC
NC(4)
A5
A2
NC/TDI(2)
A1
NC/TDO(2)
A10
A13
A14
NC(4)
R
LBO
NC(4)
A4
A3
NC/TMS(2)
A0
NC/TCK (2)
A11
A12
A15
A16
NC
4877 tbl 17
Pin Configuration – 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A7
CE
BW2
NC
CS1
BWE
ADSC
ADV
A8
A10
B
NC
A6
CS0
NC
BW1
CLK
GW
OE
ADSP
A9
NC(4)
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP1
D
NC
I/O8
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O7
E
NC
I/O9
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O6
F
NC
I/O10
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O5
G
NC
(4)
I/O11
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O4
H
VSS
(1)
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ(3)
J
I/O12
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
NC
K
I/O13
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O2
NC
L
I/O14
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
NC
M
I/O15
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O0
NC
N
I/OP2
NC
(4)
VDDQ
VSS
NC/TRST
(2, 5)
(4)
NC
(2)
NC
VSS
VDDQ
NC
NC
(2)
A11
A14
A15
NC(4)
A12
A13
A16
A17
P
NC
NC
A5
A2
NC/TDI
A1
NC/TDO
R
LBO
NC(4)
A4
A3
NC/TMS (2)
A0
NC/TCK (2)
4877 tbl 17a
NOTES:
1. H1 does not have to be directly VSS as long as input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
8
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Sym bol
Param eter
Test Conditions
M in.
M ax.
Unit
|ILI|
Inp ut Le ak ag e Curre nt
V DD = M ax., V IN = 0V to V DD
___
5
µA
|IL I|
ZZ, LBO and JTA G Inp ut Le akag e Curre nt(1)
V DD = M ax., V IN = 0V to V DD
___
30
µA
5
µA
|ILO |
O utp ut Le akag e Curre nt
V O UT = 0V to V DDQ , De v ice De se le cte d
___
VOL
O utp ut Lo w Vo ltag e
IO L = + 6m A , V DD = M in.
___
0.4
V
V OH
O utp ut Hig h Vo ltag e
IOH = -6m A , V DD = M in.
2.0
___
V
4877 tb l 0 8
NOTE:
1. The LBO, TMS, TDI, TCK, and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
7.5ns
Symbol
Parameter
Test Conditions
8ns
8.5ns
Com'l Only
Com'l
Ind
Com'l
Ind
Unit
IDD
Operating Power Supply Current
Device Selected, Outputs Open, V DD = Max.,
V DDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
255
200
210
180
190
mA
ISB1
CMOS Standby Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
V DDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
30
35
30
35
mA
ISB2
Clock Running Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
V DDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3)
90
85
95
80
90
mA
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, VDD = Max.
30
30
35
30
35
mA
4877 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
(VDDQ = 2.5V)
Input Pulse Levels
Input Rise/Fall Times
50Ω
0 to 2.5V
I/O
2ns
Input Timing Reference Levels
(VDDQ/2)
Output Timing Reference Levels
(VDDQ/2)
AC Test Load
VDDQ/2
Z0 = 50Ω
,
4877d03
Figure 1. AC Test Load
6
See Figure 1
5
4877 tbl 10
4
∆tCD 3
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
4877d05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
,
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,3)
Address
Used
CE
CS 0
CS1
ADSP
ADSC
ADV
GW
BWE
BWx
OE(2)
CLK
I/O
De se le cte d Cycle , Po we r Do wn
No ne
H
X
X
X
L
X
X
X
X
X
↑
HI-Z
De se le cte d Cycle , Po we r Do wn
No ne
L
X
H
L
X
X
X
X
X
X
↑
HI-Z
De se le cte d Cycle , Po we r Do wn
No ne
L
L
X
L
X
X
X
X
X
X
↑
HI-Z
De se le cte d Cycle , Po we r Do wn
No ne
L
X
H
X
L
X
X
X
X
X
↑
HI-Z
De se le cte d Cycle , Po we r Do wn
No ne
L
L
X
X
L
X
X
X
X
X
↑
HI-Z
Re ad Cycle , Be g in B urst
Exte rnal
L
H
L
L
X
X
X
X
X
L
↑
D OUT
Re ad Cycle , Be g in B urst
Exte rnal
L
H
L
L
X
X
X
X
X
H
↑
HI-Z
Re ad Cycle , Be g in B urst
Exte rnal
L
H
L
H
L
X
H
H
X
L
↑
D OUT
Re ad Cycle , Be g in B urst
Exte rnal
L
H
L
H
L
X
H
L
H
L
↑
D OUT
Re ad Cycle , Be g in B urst
Exte rnal
L
H
L
H
L
X
H
L
H
H
↑
HI-Z
Write Cycle , Be g in Burst
Exte rnal
L
H
L
H
L
X
H
L
L
X
↑
D IN
Write Cycle , Be g in Burst
Exte rnal
L
H
L
H
L
X
L
X
X
X
↑
D IN
Re ad Cycle , Co ntinue Burst
Ne xt
X
X
X
H
H
L
H
H
X
L
↑
D OUT
Re ad Cycle , Co ntinue Burst
Ne xt
X
X
X
H
H
L
H
H
X
H
↑
HI-Z
Re ad Cycle , Co ntinue Burst
Ne xt
X
X
X
H
H
L
H
X
H
L
↑
D OUT
Re ad Cycle , Co ntinue Burst
Ne xt
X
X
X
H
H
L
H
X
H
H
↑
HI-Z
Re ad Cycle , Co ntinue Burst
Ne xt
H
X
X
X
H
L
H
H
X
L
↑
D OUT
Re ad Cycle , Co ntinue Burst
Ne xt
H
X
X
X
H
L
H
H
X
H
↑
HI-Z
Re ad Cycle , Co ntinue Burst
Ne xt
H
X
X
X
H
L
H
X
H
L
↑
D OUT
Re ad Cycle , Co ntinue Burst
Ne xt
H
X
X
X
H
L
H
X
H
H
↑
HI-Z
Write Cycle , Co ntinue Burst
Ne xt
X
X
X
H
H
L
H
L
L
X
↑
D IN
Write Cycle , Co ntinue Burst
Ne xt
X
X
X
H
H
L
L
X
X
X
↑
D IN
Write Cycle , Co ntinue Burst
Ne xt
H
X
X
X
H
L
H
L
L
X
↑
D IN
Write Cycle , Co ntinue Burst
Ne xt
H
X
X
X
H
L
L
X
X
X
↑
D IN
Re ad Cycle , Susp e nd Burst
Curre nt
X
X
X
H
H
H
H
H
X
L
↑
D OUT
Re ad Cycle , Susp e nd Burst
Curre nt
X
X
X
H
H
H
H
H
X
H
↑
HI-Z
Re ad Cycle , Susp e nd Burst
Curre nt
X
X
X
H
H
H
H
X
H
L
↑
D OUT
Re ad Cycle , Susp e nd Burst
Curre nt
X
X
X
H
H
H
H
X
H
H
↑
HI-Z
Re ad Cycle , Susp e nd Burst
Curre nt
H
X
X
X
H
H
H
H
X
L
↑
D OUT
Re ad Cycle , Susp e nd Burst
Curre nt
H
X
X
X
H
H
H
H
X
H
↑
HI-Z
Re ad Cycle , Susp e nd Burst
Curre nt
H
X
X
X
H
H
H
X
H
L
↑
D OUT
Re ad Cycle , Susp e nd Burst
Curre nt
H
X
X
X
H
H
H
X
H
H
↑
HI-Z
Write Cycle , S usp e nd Burst
Curre nt
X
X
X
H
H
H
H
L
L
X
↑
D IN
Write Cycle , S usp e nd Burst
Curre nt
X
X
X
H
H
H
L
X
X
X
↑
D IN
Write Cycle , S usp e nd Burst
Curre nt
H
X
X
X
H
H
H
L
L
X
↑
D IN
Write Cycle , S usp e nd Burst
Curre nt
H
X
X
X
H
H
L
X
X
X
↑
Operation
D IN
4877 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.42
10
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
(3)
H
L
L
H
H
H
(3)
H
L
H
L
H
H
(3)
H
L
H
H
L
H
(3)
H
L
H
H
H
L
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
4877 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V2579.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
Operation (2)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
4877 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
1
0
0
1
0
0
4877 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
Fourth Address
(1)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
0
4877 tbl 15
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
8ns
7.5ns(5)
Symbol
Parameter
8.5ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
8.5
____
10
____
11.5
____
ns
Clock Parameter
tCYC
Clock Cycle Time
tCH(1)
Clock High Pulse Width
3
____
4
____
4.5
____
ns
tCL(1)
Clock Low Pulse Width
3
____
4
____
4.5
____
ns
____
7.5
____
8
____
8.5
ns
2
____
2
____
ns
Output Parameters
tCD
Clock High to Valid Data
tCDC
Clock High to Data Change
2
____
tCLZ(2)
Clock High to Output Active
0
____
0
____
0
____
ns
tCHZ(2)
Clock High to Data High-Z
2
3.5
2
3.5
2
3.5
ns
tOE
Output Enable Access Time
____
3.5
____
3.5
____
3.5
ns
tOLZ(2)
Output Enable Low to Output Active
0
____
0
____
0
____
ns
tOHZ(2)
Outp ut Enable High to Output High-Z
____
3.5
____
3.5
____
3.5
ns
Set Up Times
tSA
Address Setup Time
1.5
____
2
____
2
____
ns
tSS
Address Status Setup Time
1.5
____
2
____
2
____
ns
2
____
2
____
ns
tSD
Data In Setup Time
1.5
____
tSW
Write Setup Time
1.5
____
2
____
2
____
ns
tSAV
Address Advance Setup Time
1.5
____
2
____
2
____
ns
tSC
Chip Enable/Select Setup Time
1.5
____
2
____
2
____
ns
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
Hold Times
tHA
Address Hold Time
tHS
Address Status Hold Time
0.5
____
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
ns
tHW
Write Hold Time
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.5
____
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
____
100
____
ns
34
____
40
____
50
____
tCFG
(4)
Configuration Set-up Time
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.42
12
ns
4877 tbl 16
6.42
13
Output
Disabled
tSC
tSA
tSS
tHS
tOLZ
tOE
O1(Ax)
tHC
Flow-through
Read
Ax
tHA
tOHZ
Ay
(1)
tCH
tCD
tSAV
tHAV
O1(Ay)
tCDC
tSW
tCL
O3(Ay)
O4(Ay)
(Burst wraps around
to its initial state)
ADV HIGH suspends burst
Burst Flow-through Read
O2(Ay)
tHW
O1(Ay)
tCHZ
O2(Ay)
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW, BWE, BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
4877 drw 06
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Flow-Through Read Cycle(1,2)
,
6.42
14
Ax
(2)
Single Read
tSA
tHA
tSS
tHS
tCLZ
tCD
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tCD
tOLZ
O2(Az)
O3(Az)
Flow-through Burst Read
O1(Az)
tCDC
4877 drw 07
O4(Az)
,
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Flow-Through Read and Write Cycles(1,2,3)
6.42
15
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tHC
O4(Aw)
Ax
(1)
Ay
tCL
tOHZ
I1(Ax)
I1(Ay)
I2(Ay)
(ADV suspends burst)
tSAV
GW is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
tCH
I2(Ay)
(2)
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
I2(Az)
tHD
4877 drw 08
I3(Az)
,
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
O3(Aw)
tSC
tSA
tHA
tSS
tHS
tCYC
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)
6.42
16
tHC
Burst
Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
Burst Write
I2(Ay)
(ADV HIGH suspends burst)
I2(Ay)
BWx is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge
BWE is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
tCH
I3(Ay)
I4(Ay)
tSD
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
tHW
tSW
Az
I2(Az)
tHD
4877 drw 09
I3(Az)
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3)
6.42
17
tSS
tSC
tSA
Ax
tOE
tOLZ
tHS
Single Read
O1(Ax)
tHC
tHA
tCH
tCL
tZZPW
Snooze Mode
tZZR
NOTES:
1. Device must power up in deselected Mode
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
Az
4877 drw 13
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
DATAOUT
(Aw)
(Ax)
(Ay)
,
4877 drw 10
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
4877 drw 11
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
18
,
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
tJCYC
tJF
tJCL
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST(3)
x
M4877 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
Min.
Max.
Units
ns
Scan Register Sizes
tJCYC
JTAG Clock Input Period
100
____
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
5(1)
ns
tJF
JTAG Clock Fall Time
____
5(1)
ns
JTAG Identification (JIDR)
tJRST
JTAG Reset
50
____
ns
Boundary Scan (BSR)
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
20
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
25
____
ns
25
____
ns
tJH
JTAG Hold
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
32
Note (1)
I4877 tbl 03
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
I4877 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
19
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Value
Revision Number (31:28)
Description
0x2
IDT Device ID (27:12)
0x22D, 0x22F
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Reserved for version number.
Defines IDT part number 71V2577SA and 71V2579SA, respectively.
Allows unique identification of device vendor as IDT.
1
Indicates the presence of an ID register.
I4877 tbl 02
Available JTAG Instructions
Instruction
Description
OPCODE
EXTEST
Forces contents of the bound ary scan cells onto the device outputs (1).
Places the boundary scan registe r (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the bo undary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) be tween TDI and TDO. Forces all
device o utput drivers to a High-Z state.
0011
RESERVED
RESERVED
RESERVED
0100
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
RESERVED
CLAMP
0101
0110
0111
Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO.
RESERVED
1000
1001
RESERVED
1010
Same as above.
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I4877 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
20
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
XXX
Device
Type
X
S
X
XX
X
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF**
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
75*
80
85
Access Time in Tenths of Nanoseconds
S
SA
Standard Power
Standard Power with JTAG Interface
Blank
Y
First Generation or current stepping
Second Generation die step
71V2577
71V2579
,
128K x 36 Flow-Through Burst Synchronous SRAM with 2.5V I/O
256K x 18 Flow-Through Burst Synchronous SRAM with 2.5V I/O
4877 drw 12
*Commercial temperature range only.
** JTAG (SA version) is not available with 100 pin TQFP package
Package Information
100-Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website
6.42
21
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
7/23/99
9/17/99
12/31/99
04/04/00
Pg. 2
Pg. 3
Pg. 8
Pg. 18
Pg. 20
Pg. 1, 4, 8, 11, 19
Pg. 18
Pg. 4
06/01/00
07/15/00
Pg. 20
Pg. 7
Pg. 8
Pg. 20
10/25/00
04/22/03
06/30/03
Pg. 8
Pg.4
Pg. 1,2,3,5-9
Pg. 5-8
Pg. 19,20
Pg. 21-23
Pg. 24
Updated to new format
Revised I/O pin description
Revised block diagram for flow-through functionality
Revised ISB1 and IZZ for speeds 7.5 to 8.5ns
Added 119-lead BGA package diagram
Added Datasheet Document History
Added Industrial Temperature range offerings
Add 100pin TQFP Package Diagram Outline
Add capacitance table for BGA package; Add Industrial temperature to table; insert note to
Absolute Max Rating table and Recommended Operating Temperature tables.
Add new package offering, 13 x 15mm 165 fBGA
Correct 119BGA Package Diagram Outline
Add note reference to BG119 pinout
Add DNU reference note to BQ165 pinout
Update BG119 Package Diagram Outline Dimensions
Remove Preliminary status
Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
Updated 165 BGA table information from TBD to 7
Updated datasheet with JTAG information
Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))
requiring NC or connection to Vss.
Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions
Removed old package information from the datasheet
Updated ordering information with JTAG and Y stepping information. Added information
regarding packages available IDT website.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
22
for Tech Support:
[email protected]
800-544-7726, x4033