BGM15LA12 Data Sheet (743 KB, EN)

BGM15LA12
Low-Band LNA Multiplexer Module
Data Sheet
Revision 3.0 - 2015-07-24
Power Management & Multimarket
Edition 2015-07-24
Published by Infineon Technologies AG
81726 Munich, Germany
c
2015
Infineon Technologies AG
All Rights Reserved.
LEGAL DISCLAIMER
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.
With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding
the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon
Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used
in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such
components can reasonably be expected to cause the failure of that life-support device or system or to affect the
safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in
the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to
assume that the health of the user or other persons may be endangered.
BGM15LA12
Revision History
Document No.: BGM15LA12__v3.0.pdf
Revision History: Rev. v3.0
Previous Version: Preliminary, Revision v2.4 - 2014-08-21
Page
Subjects (major changes since last revision)
all
“Preliminary” status removed
19
Package Outline Drawing: Minimum package height specified
19
Marking Specification added
20
Footprint Recommendation added
Trademarks of Infineon Technologies AG
AURIXTM , C166TM , CanPAKTM , CIPOSTM , CIPURSETM , CoolGaNTM , CoolMOSTM , CoolSETTM , CoolSiCTM , CORECONTROLTM ,
CROSSAVETM , DAVETM , DI-POLTM , DrBLADETM , EasyPIMTM , EconoBRIDGETM , EconoDUALTM , EconoPACKTM , EconoPIMTM ,
EiceDRIVERTM , eupecTM , FCOSTM , HITFETTM , HybridPACKTM , ISOFACETM , IsoPACKTM , i-WaferTM , MIPAQTM , ModSTACKTM ,
my-dTM , NovalithICTM , OmniTuneTM , OPTIGATM , OptiMOSTM , ORIGATM , POWERCODETM , PRIMARIONTM , PrimePACKTM ,
PrimeSTACKTM , PROFETTM , PRO-SILTM , RASICTM , REAL3TM , ReverSaveTM , SatRICTM , SIEGETTM , SIPMOSTM , SmartLEWISTM ,
SOLID FLASHTM , SPOCTM , TEMPFETTM , thinQ!TM , TRENCHSTOPTM , TriCoreTM .
Other Trademarks
Advance Design SystemTM (ADS) of Agilent Technologies, AMBATM , ARMTM , MULTI-ICETM , KEILTM , PRIMECELLTM ,
REALVIEWTM , THUMBTM , µVisionTM of ARM Limited, UK. ANSITM of American National Standards Institute. AUTOSARTM
of AUTOSAR development partnership. BluetoothTM of Bluetooth SIG Inc. CAT-iqTM of DECT Forum. COLOSSUSTM , FirstGPSTM
of Trimble Navigation Ltd. EMVTM of EMVCo, LLC (Visa Holdings Inc.). EPCOSTM of Epcos AG. FLEXGOTM of Microsoft
Corporation. HYPERTERMINALTM of Hilgraeve Incorporated. MCSTM of Intel Corp. IECTM of Commission Electrotechnique
Internationale. IrDATM of Infrared Data Association Corporation. ISOTM of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLABTM of MathWorks, Inc. MAXIMTM of Maxim Integrated Products, Inc. MICROTECTM , NUCLEUSTM of Mentor
Graphics Corporation. MIPITM of MIPI Alliance, Inc. MIPSTM of MIPS Technologies, Inc., USA. muRataTM of MURATA MANUFACTURING CO., MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc., OmniVisionTM of OmniVision Technologies,
Inc. OpenwaveTM of Openwave Systems Inc. RED HATTM of Red Hat, Inc. RFMDTM of RF Micro Devices, Inc. SIRIUSTM of
Sirius Satellite Radio Inc. SOLARISTM of Sun Microsystems, Inc. SPANSIONTM of Spansion LLC Ltd. SymbianTM of Symbian
Software Limited. TAIYO YUDENTM of Taiyo Yuden Co. TEAKLITETM of CEVA, Inc. TEKTRONIXTM of Tektronix Inc. TOKOTM of
TOKO KABUSHIKI KAISHA TA. UNIXTM of X/Open Company Limited. VERILOGTM , PALLADIUMTM of Cadence Design Systems,
Inc. VLYNQTM of Texas Instruments Incorporated. VXWORKSTM , WIND RIVERTM of WIND RIVER SYSTEMS, INC. ZETEXTM of
Diodes Zetex.
Last Trademarks Update 2014-07-17
Data Sheet
3
Revision 3.0 - 2015-07-24
BGM15LA12
Contents
1 Features
6
2 Product Description
6
3 Maximum Ratings
7
4 DC Characteristics
8
5 RF Characteristics
5.1 BAND 8 . . . .
5.2 BAND 12 . . .
5.3 BAND 20 . . .
5.4 BAND 26 . . .
5.5 BAND 28 . . .
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9
9
10
11
12
13
6 MIPI RFFE Specification
14
7 Application Information
20
8 Package Information
22
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
BGM15LA12 Block diagram . . . . . . . . . . . . . . . . .
Received clock signal constraints . . . . . . . . . . . . . .
Bus active data receiver timing requirements . . . . . . .
Bus park cycle timing . . . . . . . . . . . . . . . . . . . .
Bus active data transmission timing specification . . . . .
Requirements for VIO-initiated reset . . . . . . . . . . . .
BGM15LA12 Pin Configuration (top view) . . . . . . . . .
BGM15LA12 Application Schematic . . . . . . . . . . . .
ATSLP-12-1 Package Outline (top, side and bottom views)
Marking Specification (top view) . . . . . . . . . . . . . .
Footprint Recommendation . . . . . . . . . . . . . . . . .
ATSLP-12-1 Carrier Tape . . . . . . . . . . . . . . . . . .
Data Sheet
4
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7
15
16
16
17
17
20
21
22
22
23
23
Revision 3.0 - 2015-07-24
BGM15LA12
List of Tables
1
2
4
5
6
7
8
9
10
11
12
13
14
15
16
Ordering Information . . . .
Maximum Ratings . . . . .
DC Characteristics . . . . .
RF Characteristics Band 8 .
RF Characteristics Band 12
RF Characteristics Band 20
RF Characteristics Band 26
RF Characteristics Band 28
MIPI Features . . . . . . . .
Startup Behavior . . . . . .
MIPI RFFE operating timing
Register Mapping . . . . . .
Truth Table, Register_0 . .
Pin Definition and Function
Bill of Materials . . . . . . .
Data Sheet
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6
7
8
9
10
11
12
13
14
14
15
17
19
20
21
Revision 3.0 - 2015-07-24
BGM15LA12
BGM15LA12 Low-Band LNA Multiplexer Module
1 Features
• Power gain: 17.5 dB
• Low noise figure: 1.1 dB
• Low current consumption: 4.9 mA
• Frequency range from 0.7 to 1.0 GHz
• RF output internally matched to 50 Ω
• Low external component count
• High port-to-port-isolation
• Suitable for LTE / LTE-Advanced and 3G applications
• No decoupling capacitors required if no DC applied on RF lines
• On chip control logic including ESD protection
• Supply voltage: 2.2 to 3.3 V
• Integrated MIPI RFFE interface operating in 1.1 to 1.95 V voltage
range
• Software programmable MIPI RFFE USID
• Small form factor 1.1 mm x 1.9 mm
• High EMI robustness
• RoHS and WEEE compliant package
2 Product Description
The BGM15LA12 is a LNA multiplexer module for LTE low-band frequencies that increases the data rate while
keeping flexibility and low footprint. It is a perfect solution for multimode handsets based on LTE-Advanced and
WCDMA. The BGM15LA12 is controlled via a MIPI RFFE controller. The device configuration is shown in Fig. 12.
Table 1: Ordering Information
Type
Package
Marking
BGM15LA12
ATSLP-12-1
L1
Data Sheet
6
Revision 3.0 - 2015-07-24
BGM15LA12
RX1
RX2
RX3
RX4
RX5
AO
SP5T
VDD
LNA
VIO
MIPI-RFFE
ControlOInterface
GND
SCLK
SDATA
Figure 1: BGM15LA12 Block diagram
3 Maximum Ratings
Table 2: Maximum Ratings
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Supply Voltage VDD
V DD
-0.3
–
3.6
V
1
Voltage at RF pins Rx
V Rx
-0.3
–
0.9
V
–
Voltage at RF output pin AO
V AO
-0.3
–
V DD+0.3
V
–
Voltage at GND pins
V GND
-0.3
–
0.3
V
–
Current into pin VDD
I DD
–
–
16
mA
–
RF input power
P IN
–
–
0
dBm
–
Total power dissipation
P tot
–
–
60
mW
Junction temperature
TJ
–
–
150
◦
C
–
85
◦
C
–
C
–
Ambient temperature range
TA
-40
–
Storage temperature range
T STG
-65
–
150
◦
ESD capability, HBM
V ESD_HBM
–
–
1000
V
according to JESD22A-114
RFFE Supply Voltage
V IO
-0.5
–
3.6
V
–
V SCLK,
-0.7
–
V IO+0.7
V
–
RFFE Supply Voltage Levels
V SDATA
(max.
3.6)
1 All
voltages refer to GND-Nodes unless otherwise noted
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
Data Sheet
7
Revision 3.0 - 2015-07-24
BGM15LA12
4 DC Characteristics
Table 4: DC Characteristics at T A = 25 ◦C
Parameter 1
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Supply Voltage
V DD
2.2
–
3.3
V
–
Supply Current
I DD
–
4.9
5.9
mA
ON-mode
–
0.1
2
µA
OFF-Mode
VIO
1.1
1.8
1.95
V
–
RFFE input high voltage
VIH
0.7*VIO
–
VIO
V
–
2
RFFE input low voltage
VIL
0
–
0.3*VIO
V
–
RFFE output high voltage2
VOH
0.8*VIO
–
VIO
V
–
RFFE output low voltage
VOL
0
–
0.2*VIO
V
–
RFFE control input capaci-
CCtrl
–
–
2
pF
–
IVIO
–
15
–
µA
Idle State
RFFE supply voltage
2
2
tance
RFFE supply current
1 Based
2 SCLK
on the application described in Chapter 7
and SDATA
Data Sheet
8
Revision 3.0 - 2015-07-24
BGM15LA12
5 RF Characteristics
5.1 BAND 8
Table 5: RF Characteristics Band 8 at T A = 25 ◦C, V DD = 2.8 V, f = 925 – 960 MHz, with matching described in
Chapter 7 (C=1.1 pF, L=11 nH )
Parameter 1
Symbol
2
2
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Insertion power gain
|S21 |
14.3
15.8
17.3
dB
–
Noise figure2
NF
–
1.1
1.6
dB
Z S=50 Ω
RLin
8
11
–
dB
–
12
>20
–
dB
–
2 3
Input return loss
2 3
Output return loss
RLout
2
Reverse isolation AO to RX
port2 3
1/|S12 |
19
23
–
dB
–
Inband
IP 1dB
-11
-8
–
dBm
–
IIP 3
-4
-1
–
dBm
f1 =937 MHz,
input
1dB2 3
compression point
Inband input 3rd -order inter2 3 4
cept point
f12 =927 MHz
2 5
Isolation RX to RX port
Isolation RX to AO port2
5
5
Stability
RF
Rise
Time
f2 =947 MHz,
RX
Port
ISO
35
40
–
dB
ISO
24
29
–
dB
k
>1
–
–
t on/off
0.5
1
5
forward direction
f =20 MHz–10 GHz
µs
5
On/Off
10 % to 90 % ON;
90 % to 10 % ON
5
Power Up Settling Time
t BC
–
10
25
µs
After power down mode
1 The
parameter values are valid at any RX port using the matching described in Chapter 7
losses are subtracted
3 Verification based on AQL; not 100% tested in production
4 Input power = −30 dBm for each tone
5 Guaranteed by device design; not tested in production
2 PCB
Data Sheet
9
Revision 3.0 - 2015-07-24
BGM15LA12
5.2 BAND 12
Table 6: RF Characteristics Band 12 at T A = 25 ◦C, V DD = 2.8 V, f = 729 – 746 MHz, with matching described in
Chapter 7 (C=2.2 pF, L=16 nH)
Parameter 1
Symbol
2
2
Min.
Values
Typ.
Max.
Unit
Note / Test Condition
Insertion power gain
|S21 |
15.2
16.7
18.2
dB
–
Noise figure2
NF
–
1.2
1.7
dB
Z S=50 Ω
RLin
8
11
–
dB
–
8
12
–
dB
–
1/|S12 |
19
23
–
dB
–
IP 1dB
-14
-11
–
dBm
–
IIP 3
-7
-4
–
dBm
f1 =732 MHz,
2 3
Input return loss
2 3
Output return loss
RLout
Reverse isolation AO to RX
2
2 3
port
Inband
input
1dB2 3
compression point
Inband input 3rd -order inter2 3 4
cept point
f12 =722 MHz
2 5
Isolation RX to RX port
Isolation RX to AO port2
5
5
Stability
RF
Rise
Time
f2 =742 MHz,
RX
Port
ISO
34
39
–
dB
ISO
24
29
–
dB
k
>1
–
–
t on/off
0.5
1
5
forward direction
f =20 MHz–10 GHz
µs
5
On/Off
10 % to 90 % ON;
90 % to 10 % ON
5
Power Up Settling Time
t BC
–
10
25
µs
After power down mode
1 The
parameter values are valid at any RX port using the matching described in Chapter 7
losses are subtracted
3 Verification based on AQL; not 100% tested in production
4 Input power = −30 dBm for each tone
5 Guaranteed by device design; not tested in production
2 PCB
Data Sheet
10
Revision 3.0 - 2015-07-24
BGM15LA12
5.3 BAND 20
Table 7: RF Characteristics Band 20 at T A = 25 ◦C, V DD = 2.8 V, f = 791 – 821 MHz, with matching described in
Chapter 7 (C=1.8 pF, L=15 nH)
Parameter 1
Symbol
2
2
Min.
Values
Typ.
Max.
Unit
Note / Test Condition
Insertion power gain
|S21 |
15
16.5
18
dB
–
Noise figure2
NF
–
1.15
1.65
dB
Z S=50 Ω
RLin
8
11
–
dB
–
11
19
–
dB
–
1/|S12 |
20
24
–
dB
–
IP 1dB
-13
-10
–
dBm
–
IIP 3
-5
-2
–
dBm
f1 =801 MHz,
2 3
Input return loss
2 3
Output return loss
RLout
Reverse isolation AO to RX
2
2 3
port
Inband
input
1dB2 3
compression point
Inband input 3rd -order inter2 3 4
cept point
f12 =791 MHz
2 5
Isolation RX to RX port
Isolation RX to AO port2
5
5
Stability
RF
Rise
Time
f2 =811 MHz,
RX
Port
ISO
34
39
–
dB
ISO
24
29
–
dB
k
>1
–
–
t on/off
0.5
1
5
forward direction
f =20 MHz–10 GHz
µs
5
On/Off
10 % to 90 % ON;
90 % to 10 % ON
5
Power Up Settling Time
t BC
–
10
25
µs
After power down mode
1 The
parameter values are valid at any RX port using the matching described in Chapter 7
losses are subtracted
3 Verification based on AQL; not 100% tested in production
4 Input power = −30 dBm for each tone
5 Guaranteed by device design; not tested in production
2 PCB
Data Sheet
11
Revision 3.0 - 2015-07-24
BGM15LA12
5.4 BAND 26
Table 8: RF Characteristics Band 26 at T A = 25 ◦C, V DD = 2.8 V, f = 859 – 894 MHz, with matching described in
Chapter 7 (C=1.5 pF, L=13 nH)
Parameter 1
Symbol
2
2
Min.
Values
Typ.
Max.
Unit
Note / Test Condition
Insertion power gain
|S21 |
14.8
16.3
17.8
dB
–
Noise figure2
NF
–
1.2
1.7
dB
Z S=50 Ω
RLin
8
11
–
dB
–
12
>20
–
dB
–
1/|S12 |
19
23
–
dB
–
IP 1dB
-11
-8
–
dBm
–
IIP 3
-4
-1
–
dBm
f1 =871 MHz,
2 3
Input return loss
2 3
Output return loss
RLout
Reverse isolation AO to RX
2
2 3
port
Inband
input
1dB2 3
compression point
Inband input 3rd -order inter2 3 4
cept point
f12 =861 MHz
2 5
Isolation RX to RX port
Isolation RX to AO port2
5
5
Stability
RF
Rise
Time
f2 =881 MHz,
RX
Port
ISO
34
39
–
dB
ISO
24
29
–
dB
k
>1
–
–
t on/off
0.5
1
5
forward direction
f =20 MHz–10 GHz
µs
5
On/Off
10 % to 90 % ON;
90 % to 10 % ON
5
Power Up Settling Time
t BC
–
10
25
µs
After power down mode
1 The
parameter values are valid at any RX port using the matching described in Chapter 7
losses are subtracted
3 Verification based on AQL; not 100% tested in production
4 Input power = −30 dBm for each tone
5 Guaranteed by device design; not tested in production
2 PCB
Data Sheet
12
Revision 3.0 - 2015-07-24
BGM15LA12
5.5 BAND 28
Table 9: RF Characteristics Band 28 at T A = 25 ◦C, V DD = 2.8 V, f = 758 – 803 MHz, with matching described in
Chapter 7 (C=2 pF, L=16 nH)
Parameter 1
Symbol
2
2
Min.
Values
Typ.
Max.
Unit
Note / Test Condition
Insertion power gain
|S21 |
15.1
16.6
18.1
dB
–
Noise figure2
NF
–
1.1
1.6
dB
Z S=50 Ω
RLin
8
11
–
dB
–
11
16
–
dB
–
1/|S12 |
21
25
–
dB
–
IP 1dB
-13
-10
–
dBm
–
IIP 3
-6
-3
–
dBm
f1 =775 MHz,
2 3
Input return loss
2 3
Output return loss
RLout
Reverse isolation AO to RX
2
2 3
port
Inband
input
1dB2 3
compression point
Inband input 3rd -order inter2 3 4
cept point
f12 =765 MHz
2 5
Isolation RX to RX port
Isolation RX to AO port2
5
5
Stability
RF
Rise
Time
f2 =785 MHz,
RX
Port
ISO
34
39
–
dB
ISO
24
29
–
dB
k
>1
–
–
t on/off
0.5
1
5
forward direction
f =20 MHz–10 GHz
µs
5
On/Off
10 % to 90 % ON;
90 % to 10 % ON
5
Power Up Settling Time
t BC
–
10
25
µs
After power down mode
1 The
parameter values are valid at any RX port using the matching described in Chapter 7
losses are subtracted
3 Verification based on AQL; not 100% tested in production
4 Input power = −30 dBm for each tone
5 Guaranteed by device design; not tested in production
2 PCB
Data Sheet
13
Revision 3.0 - 2015-07-24
BGM15LA12
6 MIPI RFFE Specification
All sequences are implemented according to the ’MIPI Alliance Specification for RF Front-End Control Interface’
document version 1.10 - 26. July 2011.
Table 10: MIPI Features
Feature
Supported
Comment
Register write command sequence
Yes
Register read command sequence
Yes
Extended register write command sequence
No
Up to 4 Bytes
Extended register read command sequence
No
Up to 4 Bytes
Register 0 write command sequence
Yes
Trigger function
Yes
Trigger assignment to each control register is supported
Programmable USID
Yes
3 register command sequence and extended register command sequence
Status Register
Yes
Register for debugging
Reset
Yes
By VIO, Power Mode and RFFE_STATUS
Group SID
Yes
USID_Sel pin
No
Full speed write
Yes
Half speed read
Yes
Full speed read
Yes
External pin for changing USID is not implemented
Table 11: Startup Behavior
Feature
State
Comment
Power status
LOW POWER
The chip is in low power mode after startup
Trigger function
ENABLED
Trigger function is enabled after startup. Trigger function can be disabled via PM_TRIG register.
Data Sheet
14
Revision 3.0 - 2015-07-24
BGM15LA12
Table 12: MIPI RFFE Operating Timing
Parameter
Symbol
SCLK Frequency
Values
FSCLK
SCLK Period
TSCLK
SCLK Low Period
TSCLKIL
SCLK High Period
TSCLKIH
SDATA Setup Time
TS
SDATA Hold Time
TH
SDATA Release Time
TSDATAZ
Time for Data Output
TD
Unit
Note / Test Condition
Min.
Typ.
Max.
0.032
–
26
MHz
Full speed
0.032
–
13
MHz
Half speed
0.038
0.077
–
–
32
32
µs
µs
Full speed
Half speed
11.25
–
–
ns
Full speed, see Fig. 2
24
–
–
ns
Half speed, see Fig. 2
11.25
–
–
ns
Full speed, see Fig. 2
24
–
–
ns
Half speed, see Fig. 2
1
–
–
ns
Full speed, see Fig. 3
2
–
–
ns
Half speed, see Fig. 3
5
–
–
ns
Full speed, see Fig. 3
5
–
–
ns
Half speed, see Fig. 3
–
–
10
ns
Full speed, see Fig. 4
–
–
18
ns
Half speed, see Fig. 4
–
–
10.25
ns
Full speed, see Fig. 5
–
–
22
ns
Half speed, see Fig. 5
2.1
–
6.5
ns
Full speed, see Fig. 5
2.1
–
10
ns
Half speed, see Fig. 5
SDATA Rise/Fall Time
TSDATAOTR
VIO Rise Time
TVIO-R
10
–
450
µs
See Fig. 6
VIO Reset Time
TVIO-RST
10
–
–
µs
See Fig. 6
Reset Delay Time
TSIGOL
0.12
–
–
µs
See Fig. 6
TSCLKIH
TSCLKIL
VTPmax
VTNmin
Figure 2: Received clock signal constraints
Data Sheet
15
Revision 3.0 - 2015-07-24
BGM15LA12
VTPmax
SCLK
VTPmin
TS
TH
TS
TH
VTPmax
SDATA
VTPmin
Figure 3: Bus active data receiver timing requirements
VTPmax
SCLK
VTNmin
TSDATAZ
VOHmin
SDATA
VOLmax
Bus Park Cycle
Signal driven
Signal not driven, pull down only
TSDATAZ is measured from SCLK VTN level for a device receiving SCLK and driving SDATA lines
Figure 4: Bus park cycle timing
Data Sheet
16
Revision 3.0 - 2015-07-24
BGM15LA12
VTPmax
SCLK
VTPmin
TD
TD
TSDATAOTR
TSDATAOTR
VOHmin
SDATA
VOLmax
Figure 5: Bus active data transmission timing specification
TSIGOL
VIO (V)
VIOmax
Not To Scale
VIOmin
SCLK & SDATA must be
held at low level from
deassertion of VIO until
the end of TSIGOL
TVIO-RST
All slave registers
set/reset to
manufacturer‘s
defaults
TVIO-R
VVIO-RST
(0.2V)
Time
Figure 6: Requirements for VIO-initiated reset
Table 13: Register Mapping
Register
Address
0x0000
0x001D
Register Name
Function
Description
REGISTER_0
PRODUCT_ID
Data
Bits
7:0
7:0
MODE_CTRL
PRODUCT_ID
MANUFACTURER_ID
7:0
MANUFACTURER_ID [7:0]
Module control
This is a read-only register. However,
during the programming of the USID
a write command sequence is performed on this register, even though
the write does not change its value.
This is a read-only register. However,
during the programming of the USID,
a write command sequence is performed on this register, even though
the write does not change its value.
0x001E
Default
00000000
11010001
00011010
Broadcast_ID
Support
No
No
No
Trigger
Support
Yes
No
No
R/W
R/W
R
R
Continued on next page
Data Sheet
17
Revision 3.0 - 2015-07-24
BGM15LA12
Table 13: Register Mapping – Continued from previous page
Register
Address
0x001C
0x001F
0x001A
Register Name
PM_TRIG
MAN_USID
RFFE_STATUS
Data
Bits
7:6
00: Normal operation
01: Default settings (STARTUP)
10: Low power (LOW POWER)
11: Reserved
If this bit is set, trigger 2 is disabled.
When all triggers disabled, if writing to
a register that is associated to trigger
2, the data goes directly to the destination register.
If this bit is set, trigger 1 is disabled.
When all triggers disabled, if writing to
a register that is associated to trigger
1, the data goes directly to the destination register.
If this bit is set, trigger 0 is disabled.
When all triggers disabled, if writing to
a register that is associated to trigger
0, the data goes directly to the destination register.
A write of a one to this bit loads trigger
2’s registers.
A write of a one to this bit loads trigger
1’s registers.
A write of a one to this bit loads trigger
0’s registers.
These are read-only bits that are reserved and yield a value of 0b00 at
readback.
These bits are read-only. However,
during the programming of the USID,
a write command sequence is performed on this register even though
the write does not change its value.
Programmable USID. Performing a
write to this register using the described programming sequences will
program the USID in devices supporting this feature. These bits store the
USID of the device.
0: Normal operation
1: Software reset
Command sequence received with
parity error - discard command.
Command length error
Address frame parity error = 1
4
TRIGGER_MASK_1
3
TRIGGER_MASK_0
2
TRIGGER_2
1
TRIGGER_1
0
TRIGGER_0
7:6
SPARE
5:4
MANUFACTURER_ID [9:8]
3:0
USID
7
SOFTWARE RESET
6
COMMAND_FRAME_
PARITY_ERR
COMMAND_LENGTH_ERR
ADDRESS_FRAME_
PARITY_ERR
DATA_FRAME_
PARITY_ERR
READ_UNUSED_REG
WRITE_UNUSED_REG
BID_GID_ERR
2
1
0
Data Sheet
PWR_MODE
TRIGGER_MASK_2
3
GROUP_SID
Description
5
5
4
0x001B
Function
7:4
3:0
RESERVED
GROUP_SID
Default
10
R/W
R/W
No
No
0
No
No
0
No
No
0
Yes
No
0
Yes
No
0
Yes
No
00
No
No
R/W
0
No
No
R/W
0
No
No
R
No
No
R/W
R/W
01
0001
0
0
0
Read command to an invalid address
Write command to an invalid address
Read command with a BROADCAST_ID or GROUP_SID
0
0
0
18
Trigger
Support
No
0
Data frame with parity error
Group slave ID
Broadcast_ID
Support
Yes
0
0
Revision 3.0 - 2015-07-24
BGM15LA12
Table 14: Modes of Operation (Truth Table, Register_0)
REGISTER_0 Bits
State
Mode
D7
D6
D5
D4
D3
D2
D1
D0
1
Isolation
x
x
x
0
0
0
0
0
2
RX1-AO
x
x
x
0
0
0
0
1
3
RX2-AO
x
x
x
0
0
0
1
0
4
RX3-AO
x
x
x
0
1
0
0
0
5
RX4-AO
x
x
x
0
0
1
0
0
6
RX5-AO
x
x
x
1
0
0
0
0
7
RX1&RX2-AO
x
x
x
0
0
0
1
1
8
RX2&RX3-AO
x
x
x
0
1
0
1
0
9
RX3&RX4-AO
x
x
x
0
1
1
0
0
10
RX4&RX5-AO
x
x
x
1
0
1
0
0
11
RX1&RX3-AO
x
x
x
0
1
0
0
1
12
RX2&RX4-AO
x
x
x
0
0
1
1
0
13
RX3&RX5-AO
x
x
x
1
1
0
0
0
14
RX1&RX4-AO
x
x
x
0
0
1
0
1
15
RX2&RX5-AO
x
x
x
1
0
0
1
0
16
RX1&RX5-AO
x
x
x
1
0
0
0
1
Data Sheet
19
Revision 3.0 - 2015-07-24
BGM15LA12
7 Application Information
Pin Configuration and Function
1
12
10
13
2
3
11
4
5
9
8
6
7
Figure 7: BGM15LA12 Pin Configuration (top view)
Table 15: Pin Definition and Function
Pin No.
Name
Function
1
SCLK
MIPI RFFE Clock
2
VIO
MIPI RFFE Power Supply
3
RX5
RF-Port RX No. 5
4
RX4
RF-Port RX No. 4
5
RX3
RF-Port RX No. 3
6
RX2
RF-Port RX No. 2
7
RX1
RF-Port RX No. 1
8
GND
Ground
9
GND
Ground
10
AO
RF-Output Port
11
VDD
Power Supply
12
SDATA
MIPI RFFE Data IO
13
GND
Ground
Data Sheet
20
Revision 3.0 - 2015-07-24
BGM15LA12
Application Board Configuration
N1
RX1
RX2
RX3
RX4
RX5
L1
C1
ioptional)
L2
C2
ioptional)
L3
AO
C3
ioptional)
LNA
L4
C4
ioptional)
L5
C5
ioptional)
SP5T
VDD=2.8V
VIO=1.8V
C6
ioptional)
MIPI-RFFE
ControlNInterface
GND
C7
ioptional)
SCLK
SDATA
Figure 8: BGM15LA12 Application Schematic
Table 16: Bill of Materials Table
Name
Value
Package
Manufacturer
Function
C1 (optional)
2 pF
0402
Various
Input matching Band 282)
C2 (optional)
1.1 pF
0402
Various
Input matching Band 82)
C3 (optional)
1.8 pF
0402
Various
Input matching Band 202)
C4 (optional)
2.2 pF
0402
Various
Input matching Band 122)
C5 (optional)
1.5 pF
0402
Various
Input matching Band 262)
C6 (optional)
1 nF
0402
Various
RF Bypass1)
C7 (optional)
1 nF
0402
Various
RF Bypass1)
L1
16 nH
0402
Various
Input matching Band 282)
L2
11 nH
0402
Various
Input matching Band 82)
L3
15 nH
0402
Various
Input matching Band 202)
L4
18 nH
0402
Various
Input matching Band 122)
L5
13 nH
0402
Various
Input matching Band 262)
N1
BGM15LA12
ATSLP-12-1
Infineon
LNA Multiplexer Module
1) RF
bypass recommended to mitigate power supply noise.
matching elements must be optimized with reference to the frequency band of interest. Each band can be arbiratily assigned to an RF
port. The configuration shown in the table is only an example of the port assignment.
2) The
Data Sheet
21
Revision 3.0 - 2015-07-24
BGM15LA12
8 Package Information
Toppview
Bottompview
0.6 ±0.05
7
9
10
5
11
4
12
2
1
0.4
B
0.1 A
0.1 A
0.2 ±0.05
12x
0.75 ±0.05
6
3
Pinp1pmarking
8
0.2 ±0.05
12x
0.1 B
0.1 B
0.4
4pxp 0.4p =p 1.6
A
0.05pMAX.
STANDOFF
1.9 ±0.05
1.1±0.05
0.2 ±0.05
2pxp 0.4p =p 0.8
ATSLP-12-1,p-2,p-3,p4,p-5-POp V03
Figure 9: ATSLP-12-1 Package Outline (top, side and bottom views)
12
Type(code
Date(code(
(YW)
Pin(1(marking
ATSLP-12-1,(-2,(-3,(4-MK( V03
Figure 10: Marking Specification (top view)
Data Sheet
22
Revision 3.0 - 2015-07-24
BGM15LA12
0.4
0.4
0.25
0.25
0.25
Copper
0.8
0.4
0.4
0.8
0.25
0.25
Stencildapertures
Solderdmask
ATSLP-12-1,d-2,d-3,d4-FPd V01
Figure 11: Footprint Recommendation
4
8
2.15
Pin 1
marking
0.75
1.4
ATSLP-12-1, -2, -3, 4-TP V01
Figure 12: ATSLP-12-1 Carrier Tape
Data Sheet
23
Revision 3.0 - 2015-07-24
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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