HD-4702/883 CMOS Programmable Bit Rate Generator June 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1. 2. 1. The HD-4702/883 Bit Rate Generator provides the necessary clock signals for digital data transmission systems, such as a UART. It generates 13 commonly used bit rates using an on-chip crystal oscillator or an external input. For conventional operation generating 16 output clock pulses per bit period, the input clock frequency must be 2.4576MHz (i.e., 9600 Baud x 16 x 16, since there is an internal ÷ 16 prescaler). A lower input frequency will result in a proportionally lower output frequency. • HD-4702/883 Provides 13 Commonly Used Bit Rates • Uses a 2.4576MHz Crystal/Input for Standard Frequency Output (16 Times Bit Rate) • Low Power Dissipation • Conforms to ElA RS-404 The HD-4702/883 can provide multi-channel operation with a minimum of external logic by having the clock frequency CO and the ÷ 8 prescaler outputs Q0 , Q1 , Q2 available externally. All signals have a 50% duty cycle except 1800 Baud, which has less than 0.39% distortion. • One HD-4702/883 Controls up to Eight Transmission Channels • Initialization Circuit Facilitates Diagnostic Fault Isolation The four rate select inputs (S0-S3) select which bit rate is at the output (Z). See Truth Table for Rate Select Inputs for select code and output bit rate. Two of the 16 select codes for the HD-4702/883 do not select an internally generated frequency, but select an input into which the user can feed either a different frequency, or a static level (High or Low) to generate “ZERO BAUD”. • On-Chip Input Pull-Up Circuit Ordering Information PART NUMBER HD1-4702/883 TEMPERATURE RANGE (oC) -55 to 125 PACKAGE CERDIP PKG. NO. F16.3 The bit rates most commonly used in modern data terminals (110,150, 300,1200, 2400 Baud) require that no more than one input be grounded for the HD-4702/883, which is easily achieved with a single 5-position switch. The HD-4702/883 has an initialization circuit which generates a master reset for the scan counter. This signal is derived from a digital differentiator that senses the first high level on the CP input after the ECP input goes low. When ECP is high, selecting the crystal input, CP must be low. A high level on CP would apply a continuous reset. See Clock Modes and Initialization below. Pinout HD-4702/883 (CERDIP) TOP VIEW Q0 1 16 VCC Q1 2 15 IM Q2 3 14 S0 ECP 4 13 S1 CP 5 12 S2 OX 6 11 S3 IX 7 10 Z GND 8 9 CO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 2955.2 HD-4702/883 Truth Table TRUTH TABLE FOR RATE SELECT INPUTS (Using 2.4576MHz Crystal) CLOCK MODES AND INITIALIZATION IX S3 S2 S1 S0 L L L L MUX Input (lM) L L L H MUX Input (lM) L L H L 50 Baud L L H H L H L L H L ECP CP H L OPERATION OUTPUT RATE (Z) Clocked from IX X L Clocked from CP 75 Baud X H L 134.5 Baud X L L H 200 Baud H H L 600 Baud L H H H 2400 Baud H L L L 9600 Baud H L L H 4800 Baud = HIGH Level = LOW Level = Don’t Care = Clock Pulse H L H L 1800 Baud = First HIGH Level Clock Pulse after ECP goes LOW H L H H 1200 Baud H H L L 2400 Baud H H L H 300 Baud H H H L 150 Baud H H H H 110 Baud H Continuous Reset Reset During First CP = High Time NOTE: 2. Actual output frequency is 16 times the indicated output rate, assuming a clock frequency of 2.4576MHz. H L X NOTE: 1. 19200 Baud by connecting Q2 to IM . 2 HD-4702/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Typical Derating Factor . . . . . . . . . . . . 1mA/MHz Increase in ICCOP Thermal Resistance, (Typical, Note 3) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . 78 23 Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC Operating Conditions Die Characteristics Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . . -55oC to 125oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested DC PARAMETER SYMBOL CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) Input High Voltage VIH VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 Input Low Voltage VIL VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 MIN MAX UNITS VCC 70% - V VCC 30% V - Output High Voltage VOH1 IOH ≤ -1µA, VCC = 4.5V, (Note 4) 1, 2, 3 -55 ≤ TA ≤ 125 VCC -0.1 - V Output Low Voltage VOL1 IOL ≤ +1µA, VCC = 4 5V, (Note 4) 1, 2, 3 -55 ≤ TA ≤ 125 - 0.1 V Input High Current IIH VIN = VCC. All Other Pins = 0V, VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -1 +1 µA Input Low Current (IX Input) IILX VIN = 0V, All Other Pins = VCC, VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -1 +1 µA Input Low Current (All Other Inputs) IlL VIN = 0V All Other Pins = VCC, VCC = 5.5V (Note 5) 1, 2, 3 -55 ≤ TA ≤ 125 - -100 µA Output High Current (OX) IOHX VOUT = VCC -0.5, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table 1, 2, 3 -55 ≤ TA ≤ 125 -0.1 - mA Output High Current (All Other Outputs) IOH1 VOUT = 2.5V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table 1, 2, 3 -55 ≤ TA ≤ 125 -1.0 - mA Output High Current (All Other Outputs) IOH2 VOUT = VCC -0.5, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table 1, 2, 3 -55 ≤ TA ≤ 125 -0.3 - mA Output Low Current (OX) IOLX VOUT = 0.4V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table 1, 2, 3 -55 ≤ TA ≤ 125 0.1 - mA Output Low Current (All Other Outputs) IOL VOUT = 0.4V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table 1, 2, 3 -55 ≤ TA ≤ 125 1.6 - mA 3 HD-4702/883 TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested DC PARAMETER SYMBOL Supply Current (Static) GROUP A SUBGROUPS CONDITIONS ICC TEMPERATURE (oC) MIN MAX UNITS ECP = VCC , CP = 0V, VCC = 5.5V All Other Inputs = GND, (Note 5) 1, 2, 3 -55 ≤ TA ≤ 125 - 1500 µA ECP = VCC , CP = 0V, VCC = 5.5V All Other Inputs = VCC (Note 5) 1, 2, 3 -55 ≤ TA ≤ 125 - 1000 µA NOTES: 4. Interchanging of force and sense conditions is permitted. 5. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all inputs except IX . TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested. AC PARAMETER SYMBOL CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS Propagation Delay, IX to CO tPLH 9, 10, 11 -55 ≤ TA ≤ 125 - 350 ns Propagation Delay, IX to CO tPHL 9, 10, 11 -55 ≤ TA ≤ 125 - 275 ns Propagation Delay, CP to CO tPLH 9, 10, 11 -55 ≤ TA ≤ 125 - 260 ns Propagation Delay, CP to CO tPHL 9, 10, 11 -55 ≤ TA ≤ 125 - 220 ns Propagation Delay, CO to Qn tPLH 9, 10, 11 -55 ≤ TA ≤ 125 - (Note 7) ns Propagation Delay, CO to Qn tPHL 9, 10, 11 -55 ≤ TA ≤ 125 - (Note 7) ns Propagation Delay, CO to Z tPLH 9, 10, 11 -55 ≤ TA ≤ 125 - 85 ns Propagation Delay, CO to Z tPHL 9, 10, 11 -55 ≤ TA ≤ 125 - 75 ns Output Transition Time (Except OX) tTLH 9, 10, 11 -55 ≤ TA ≤ 125 160 ns Output Transition Time (Except OX) tTHL 9, 10, 11 -55 ≤ TA ≤ 125 - 75 ns 9, 10, 11 -55 ≤ TA ≤ 125 350 - ns VCC = 4.5V CL ≤ 7pF on OX CL = 50pF (Note 6) Set-UpTime Select to CO tS Hold Time, Select to CO tH 9, 10, 11 -55 ≤ TA ≤ 125 0 - ns Set-UpTime, IM to CO tS 9, 10, 11 -55 ≤ TA ≤ 125 350 - ns Hold Time, IM to CO tH 9, 10, 11 -55 ≤ TA ≤ 125 0 - ns Minimum Clock Pulse Width, Low (Notes 8, 9) tWCP(L) 9, 10, 11 -55 ≤ TA ≤ 125 120 Minimum Clock Pulse Width, High (Notes 8, 9) tWCP(H) 9, 10, 11 -55 ≤ TA ≤ 125 120 - ns Minimum IX Pulse Width, Low (Note 9) tWCP(L) 9, 10, 11 -55 ≤ TA ≤ 125 160 - ns Minimum IX Pulse Width, High (Note 9) tWCP(H) 9, 10, 11 -55 ≤ TA ≤ 125 160 - ns ns NOTES: 6. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Set-Up Times (tS), Hold Times (tH), and Minimum Pulse Widths (tW) do not vary with load capacitance. 7. For multichannel operation, Propagation Delay (CO to Qn), plus Set-Up Time, Select to CO , is guaranteed to be ≤ 367ns. 8. The first High Level Clock Pulse alter ECP goes Low must be at least 350ns long to guarantee reset of all Counters. 9. It is recommended that input rise and fall times to the clock inputs (CP , IX) be less than 15ns. 4 HD-4702/883 TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS AC PARAMETER SYMBOL Input Capacitance CIN Output Capacitance CO CONDITIONS NOTES TEMPERATURE (oC) All Measurements are referenced to device ground, f = 1MHz. MIN MAX UNITS 10 TA = 25 - 7.0 pF 10 TA = 25 - 15.0 pF Propagation Delay IX to CO tPLH 10, 12 -55 ≤ TA ≤ 125 - 300 ns Propagation Delay IX to CO tPHL 10, 12 -55 ≤ TA ≤ 125 - 250 ns Propagation Delay CP to CO tPLH 10, 12 -55 ≤ TA ≤ 125 - 215 ns Propagation Delay CP to CO tPHL 10, 12 -55 ≤ TA ≤ 125 - 195 ns Propagation Delay CO to Qn tPLH 10, 12 -55 ≤ TA ≤ 125 - (Note 11) ns Propagation Delay CO to Qn tPHL 10, 12 -55 ≤ TA ≤ 125 - (Note 11) ns Propagation Delay CO to Z tPLH 10, 12 -55 ≤ TA ≤ 125 - 75 ns Propagation Delay CO to Z tPHL 10, 12 -55 ≤ TA ≤ 125 - 65 ns Output Transition Time (Except OX) tTLH 10, 12 -55 ≤ TA ≤ 125 - 80 ns Output Transition Time (Except OX) tTHL 10, 12 -55 ≤ TA ≤ 125 - 40 ns VCC = 4.5V CL ≤ 7pF on OX CL = 15pF NOTES: 10. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 11. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO , is guaranteed to be ≤ 367ns. 12. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Set-Up Times (tS), Hold Times (tH), and Minimum Pulse Widths (tW) do not vary with load capacitance. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 Group A - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C and D Samples/5005 1, 7, 9 5 HD-4702/883 Burn-In Circuit HD-4702/883 CERDIP VCC C1 R1 VCC/2 VCC/2 VCC/2 1 16 2 15 R1 R1 R1 3 14 4 R1 F0 13 GND F13 R1 5 12 R1 VCC/2 F12 R1 R1 GND F4 R1 F14 R1 6 11 R1 F15 R1 7 10 R1 8 9 GND NOTES: 13. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2., ... 14. R1 = 10kΩ, 1/4W, ±10%. 15. VCC = 5.5V ±0.5V, GND = 0V. 16. C1 = 0.01µF Min. 6 VCC/2 VCC/2 HD-4702/883 Die Characteristics DIE DIMENSIONS: GLASSIVATION: 100 mils x 97 mils x 19 mils Type: SiO2 Thickness: 7kÅ - 9kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: Si - AI 7.1 x 104A/cm2 Thickness: 10kÅ - 12kÅ Metallization Mask Layout HD-4702/883 Q0 VCC IM Q1 S0 S1 Q2 ECP S2 CP S3 OX IX GND CO 7 Z HD-4702/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) LEAD FINISH c1 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL INCHES (c) SYMBOL E M -Bbbb S C A-B S -C- S1 - 0.200 - 5.08 - 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 α eA A A b2 b ccc M C A - B S e eA/2 c e aaa M C A - B S D S D S NOTES b A L MAX A Q SEATING PLANE MIN M (b) D BASE PLANE MAX b1 SECTION A-A D S MILLIMETERS MIN NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 16 16 8 Rev. 0 4/94 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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