A pp l ic a t io n N o t e, R e v . 2. 0 , J a n. 2 00 7 A p p li c a t i o n N o t e N o . 0 8 2 A L o w - C o s t, T w o - S t a g e L o w N o i s e A m p l i fi e r f o r 5 - 6 GHz Applications Using the SiliconGermanium BFP640 Transistor R F & P r o t e c ti o n D e v i c e s Edition 2007-01-08 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2009. All Rights Reserved. LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. 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Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Application Note No. 082 Application Note No. 082 Revision History: 2007-01-08, Rev. 2.0 Previous Version: 2003-03-26 Page Subjects (major changes since last revision) All Document layout change Application Note 3 Rev. 2.0, 2007-01-08 Application Note No. 082 A Low-Cost, Two-Stage Low Noise Amplifier for 5-6 GHz Applications Using 1 A Low-Cost, Two-Stage Low Noise Amplifier for 5-6 GHz Applications Using the Silicon-Germanium BFP640 Transistor • • High Gain (20 dB minimum over 5-6 GHz range) Excellent Noise Figure: 1.4 dB @ 5470 MHz for two stage cascade Good Linearity: Input 3rd Order Intercept = +5 dBm High Reverse Isolation (>30 dB) Outstanding price / performance ratio Low Power Consumption: 16 mA @ 3.3 V Low PCB Area required (≅ 80 mm² for complete LNA) Applications: 5-6 GHz WLAN systems, 5 GHz Cordless Phones, other 5 GHz Systems • • • • • • 3 2 4 1 1 = B; 2 = E; 3 = C; 4 = E 1.1 Introduction Infineon Technologies’ BFP640 Silicon Germanium RF Transistor is shown in a two-stage Low Noise Amplifier (“LNA”) application targeted for Wireless LAN and other systems using the frequency range from 5 to 6 GHz. The BFP640 offers a remarkably low noise figure, high gain and excellent linearity at an unbeatable price-toperformance ratio, enabling the circuit designer to utilize low-cost, highly repeatable bipolar technology in industrystandard surface-mount packaging at frequencies previously attainable only with the use of more expensive device processes such as Gallium Arsenide. Figure 2 shows Infineon Technologies current SiGe transistor family, and Figure 6 and Table 4 give a schematic diagram and Bill Of Material (BOM) for the LNA. Measurement results are presented in Table 1. These results are mean values taken from a sample lot of 12 circuit boards. Please note the reference planes for all measurement data shown in Table 1 are at the PC board’s SMA RF connectors; in other words, if losses at the LNA input were subtracted, the noise figure values would be slightly lower than shown. Chapter 2 of this Application Note gives an overview of the BFP640 and Infineon’s SiGe RF Transistor products and Chapter 3 provides LNA design details including 1. 2. 3. 4. A schematic diagram A Bill Of Material (BOM) Photos of the PCB A PCB cross-section diagram Appendix A has complete electrical data including minimum, maximum, mean value, and standard deviation for a sample lot of 12 Printed Circuit Boards (PCBs). Data plots from a sample board are given in Appendix B, and temperature test data for the -40 °C to +85 °C range in located in Appendix C. Table 1 Typical performance, complete Two-Stage 5-6 GHz BFP640 LNA 1) Parameter Frequency Unit 5150 5470 5925 MHz Gain 23.5 22.2 20.3 dB Noise Figure 1.3 1.4 1.5 dB Input IP3 +5.0 dBm Input P1dB -14.2 dBm Application Note 4 Rev. 2.0, 2007-01-08 Application Note No. 082 Description of the BFP640 and Infineon’s SiGe Transistor Family Table 1 Typical performance, complete Two-Stage 5-6 GHz BFP640 LNA (cont’d) 1) Parameter Frequency Unit 5150 5470 5925 MHz Input Return Loss 15.3 19.0 16.4 dB Output Return Loss 10.9 14.7 17.0 dB Supply Current 16.3 16.3 16.3 mA PCB Area 80 80 80 mm² Number of SMT components2) 25 25 25 1)Conditions: Temperature = 25 °C, V = 3.3 V, n = 12 units, ZS = ZL = 50 Ω, network analyzer source power = -30 dBm 2) Includes bias resistors, DC blocks, chip coils & BFP640’s 2 Description of the BFP640 and Infineon’s SiGe Transistor Family The BFP640 is a Silicon-Germanium (SiGe) heterojunction bipolar transistor manufactured in Infineon Technologies’ B7HF process. The BFP640 is a derivative of Infineon’s original SiGe transistor, the BFP620. While sharing the same basic transistor die, the BFP640 has been enhanced to provide improved performance characteristics as compared to the BFP620, while maintaining the BFP620’s phenomenally low noise figure levels. These improvements bring the world-class, cost-effective performance of the BFP620 to an even higher level. In the BFP640, a lower or “lighter” dopant concentration in the transistor’s collector region is used. The lighter collector doping increases the minimum collector-emitter breakdown voltage (VCE0), reduces the transistor’s internal parasitic collector-base capacitance (CCB, Figure 1) and reduces undesired internal feedback, yielding increased gain and improved stability margin. CCB reduced via lighter collector doping => Higher Breakdown Voltage => Higher Gain => Improved Stability Margin CCB AN082_Prozess_Enhancements_CCB.vsd Figure 1 Process enhancements for BFP640, BFP650 and BFP690 transistors increase the minimum collector-emitter breakdown voltage (from 2.3 to 4.0 V VCE0) and reduce the transistor’s internal parasitic capacitance CCB. This results in a reduction in reverse transmission coefficient S12, yielding higher gain & improved stability The higher minimum breakdown voltage of the BFP640 (4.0 V VCE0, versus 2.3 V for the BFP620) makes operation in 3 Vsystems more convenient, as it is not possible to exceed the BFP640’s maximum collector-emitter voltage in a system using a 3 V power supply. The higher breakdown voltage permits the elimination of circuit Application Note 5 Rev. 2.0, 2007-01-08 Application Note No. 082 Description of the BFP640 and Infineon’s SiGe Transistor Family elements previously needed to reduce the 3 V system supply voltage to below 2.3 V, which were required for safe operation with the older BFP620. In addition to being useful in LNA applications, the BFP640 has been successfully employed as a Power Amplifier Driver (PA Driver) in 5 GHz WLAN designs. The BFP640’s two siblings, the BFP650 and BFP690, utilize the same process enhancements at the BFP640, but have larger emitter areas, allowing for increased collector current and higher RF output power levels. The maximum ratings for the BFP640, BFP650 and BFP690 are given in Table 2. A chart showing details of Infineon Technologies’ current SiGe transistor offering is given in Figure 2. Table 2 Overview of Maximum Ratings and Packaging 1) RthJS2) Package 1853) ≤ 300 °C / W SOT343 80 1853) ≤ 280 °C / W TSFP-4 50 4) ≤ 300 °C / W SOT343 5) ≤ 140 °C / W SOT343 ≤ 60 °C / W SCT595 VCE0 ICmax PDISS Volts mA mW BFP620 2.3 80 BFP620F 2.3 Device BFP640 BFP650 BFP690 1) 2) 3) 4) 5) 6) 4.0 4.0 4.0 150 350 200 500 6) 1000 Infineon Technologies SiGe RF Transistors Thermal resistance, device junction to soldering point Soldering point temperature ≤ 95 °C Soldering point temperature ≤ 90 °C Soldering point temperature ≤ 75 °C Soldering point temperature ≤ 80 °C Application Note 6 Rev. 2.0, 2007-01-08 Figure 2 Application Note 7 (Reduced Size Package "Flat Pack") (Higher Current Capability) Footprint: 2.1 x 2.0 mm 2.3 Volt Breakdown Voltage (VCEO) RthJS < 280 K/W PTOT = 185 mW IC MAX = 80 mA VCE MAX = 2.3 V RthJS < 60 K/W PTOT = 1000 mW IC MAX = 350 mA VCE MAX = 4.0 V NF MIN = 1.0 dB @ 1.8 GHz, = 1.2 dB @ 3 GHz Gma = 17.5 dB @ 1.8 GHz, = 13.0 dB @ 3 GHz fT = 37 GHz NF MIN = 0.7 dB @ 1.8 GHz, = 1.3 dB @ 6 GHz Gms / Gma = 21.0 dB @ 1.8 GHz, = 10.5 dB @ 6 GHz Footprint: 2.9 x 2.6 mm BFP690 (SCT595) RthJS < 140 K/W PTOT = 500 mW IC MAX = 150 mA VCE MAX = 4.0 V NF MIN = 0.8 dB @ 1.8 GHz, = 1.9 dB @ 6 GHz Gma = 21.0 dB @ 1.8 GHz, =10.5 dB @ 6 GHz fT = 37 GHz BFP650 (SOT343) (Higher Current Capability) 4.0 Volt Breakdown Voltage (VCEO) RthJS < 300 K/W PTOT = 200 mW IC MAX = 50 mA VCE MAX = 4.0 V NF MIN = 0.65 dB @ 1.8 GHz, = 1.2 dB @ 6 GHz Gms / Gma = 24.0 dB @ 1.8 GHz, = 12.5 dB @ 6 GHz fT = 40 GHz BFP640 (SOT343) (Smaller Package Size, Reduced Parasitics, Higher Gain, Higher Usable Frequencies) fT = 65 GHz BFP620F (TSFP4) Footprint: 1.35 x 1.35 mm RthJS < 300 K/W PTOT = 185 mW IC MAX = 80 mA VCE MAX = 2.3 V NF MIN = 0.7 dB @ 1.8 GHz, = 1.3 dB @ 6 GHz Gms / Gma = 21.5 dB @ 1.8 GHz, = 11.0 dB @ 6 GHz fT = 65 GHz BFP620 (SOT343) Footprint: 2.1 x 2.0 mm (Higher Gain, Higher Breakdown Voltage) Footprint: 2.1 x 2.0 mm Performance: To be determined BFP650 in Leadless Package (In Development) (Smaller Package Size, Reduced Parasitics, Higher Gain, Higher Usable Frequencies) Performance: To be determined BFP640 in Leadless Package (In Development) Evolution of Infineon Technologies Silicon-Germanium RF Transistors, B7HF Process Application Note No. 082 Description of the BFP640 and Infineon’s SiGe Transistor Family AN082_Evolution_B7HF_Process.vsd Overview of Infineon Technologies Silicon-Germanium RF Transistors Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details 3 5-6 GHz Two-Stage LNA Design Details Overview The LNA consists of two identical BFP640 stages in cascade. All RF simulations and Printed Circuit Board design steps took place within the Eagleware GENESYS® [1] software design package. Effort was made to minimize noise figure as well as the number of external matching elements required. The circuit board is laid out in such a manner as to permit easy testing of either stage individually. Lumped element matching techniques are used exclusively to minimize required PC Board area. Stability In general, for a linear two-port device characterized by s-parameters, the two necessary and sufficient conditions to guarantee unconditional stability (e.g. no possibility of oscillation when the input and output of the device are both terminated in any passive real impedance) are a) K > 1 and b) |∆| < 1 where (1) 2 2 2 1 – s11 – s22 + ∆ K = ---------------------------------------------------------2 s12 ⋅ s21 |∆| = |s11 . s22 - s12 . s21| In the literature one may encounter an alternative form for these two conditions as a) K > 1 and b) B1 > 0 where (2) 2 2 B 1 = 1 + s11 – s22 – ∆ 2 A single stage of the two-stage LNA was measured for S-parameters from 125 MHz to 2 GHz, and than from 2-15 GHz. The S-parameter files from each measurement were imported into the Eagleware GENESYS® package. GENESYS was employed to calculate and plot Stability Factor “K” and Stability Measure “B1” in each case. Refer to Table 3 and Table 4. One can see K>1 and B1>0, showing that the necessary and sufficient conditions for unconditional stability have been met. Since both stages are of identical design and layout, it is sufficient to check for unconditional stability of either one of the two stages. If the criteria for unconditional stability are satisfied for a single stage, then an additional identical stage may be safely cascaded after the first stage, provided the two stages do not have an undesired feedback path between them. In other words, unless the individual unconditionally stable stage can “talk” to each other via leakage paths through shared DC supply lines or other PC board features, cascading individual unconditionally stable stages will result in an unconditionally stable multi-stage amplifier. In making stability calculations using measured S-parameters, one must bear in mind that the reverse transmission coefficient (S12) of high-transition frequency devices like the BFP640 becomes vanishingly small at lower frequencies. Therefore, the signal being measured may well fall into the noise floor of the network analyzer being used. It is important that network analyzer dynamic range considerations are taken into account when making the S-parameter measurements. Otherwise, the measurement S-parameter results may be suspect, and Application Note 8 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details one may not get a “clear curve” when plotting K and B1 - particularly for frequencies below 1 GHz. An excellent reference for the interested reader is given in [2]. Linearity This LNA makes use of a “trick” to enhance third-order intercept performance. In brief, a relatively large-value capacitor is placed across the base-emitter and collector-emitter junctions to provide a low impedance path at low frequencies. This low-frequency path serves to bypass the low-frequency difference product (f2 - f1) resulting from a two-tone test. (See schematic Figure 6; C2, C8, C6 and C11 perform this function). A rule of thumb states that there exists approximately 10 dB difference between the amplifier compression point and the third order intercept point. Use of this ”trick” gets around this general rule, and increases the difference from the expected 10 dB to between 15 and 20 dB. Employment of this technique is why the LNA’s input third order intercept point (IIP3) of +5.0 dBm is more than 10 dB higher than the amplifier’s typical input 1 dB compression point (IP1dB) of -14 dBm. For additional detail on how this “capacitor trick” works, please refer to reference [3]. AN082_K_B1_to_2GHz.vsd Figure 3 Stability Factor “K” and Stability Measure “B1” for one stage of the 5 GHz LNA. The frequency range for this plot is 125 MHz to 2 GHz. Note that K>1 and B1>0. The plot is generated in Eagleware’s GENESYS simulation, from a measurement S-parameter file Application Note 9 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details AN082_K_B1_to_15GHz.vsd Figure 4 Stability Factor “K” and Stability Measure “B1” for one stage of the 5 GHz LNA. The frequency range for this plot is 2 GHz to 15 GHz. Note that K>1 and B1>0. The plot is generated in Eagleware’s GENESYS simulator, from a measured amplifier S-parameter file Noise Figure The BFP640 is an excellent low-noise device and offers noise figure performance comparable to far more expensive GaAs MESFET and GaAs PHEMT devices. Unlike GaAs FETs, no negative supply voltage is required with bipolar heterojunction transistors like the BFP640. As one would expect with RF transistors housed in standard, low-cost surface-mount packaging, the gain of the BFP640 transistor chip is limited by the package parasitics as one moves above the 3 GHz range. Near 5 GHz, the bias current for minimum noise figure is about 5 mA. A tradeoff of gain, noise figure and linearity resulted in the DC operating point 3 V VCE and 8 mA collector current being selected. Table 3 gives noise parameters for the BFP640 at the 3 V, 8 mA bias point. Note the excellent minimum noise figure values (FMIN) and the modest, easyto-handle optimum reflection coefficient magnitudes (ΓOPT). The superb minimum noise figure values, coupled with the relatively low reflection coefficient magnitudes required for achieving minimum noise figure amplifier designs makes the BFP640 easy to work with. The BFP640 enables the circuit designer to create LNAs which are forgiving of variations in PC board characteristics and tolerances in chip components. Table 3 BFP640 device Noise Parameters at VCE = 3.0 V, IC = 8 mA Freq. (GHz) FMIN ΓOPT (mag) ΓOPT (angle) RN/50 (dB) 0.9 0.42 0.22 21 0.12 (ohms) 1.8 0.68 0.08 2 0.11 2.4 0.74 0.08 50 0.11 3.0 0.84 0.06 141 0.09 4.0 0.91 0.11 -101 0.10 Application Note 10 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details Table 3 BFP640 device Noise Parameters at VCE = 3.0 V, IC = 8 mA (cont’d) Freq. (GHz) FMIN ΓOPT (mag) ΓOPT (angle) RN/50 (dB) 5.0 1.01 0.25 -61 0.14 6.0 1.20 0.22 -82 0.13 (ohms) In designing the LNA for both low parts count and best possible noise figure, it was decided to avoid any external input impedance matching elements, if at all possible. In addition to the possibility of pulling the input impedance presented to the transistor further away from it is optimum impedance for noise figure, any practical matching elements will introduce loss of some sort at the LNA input and therefore degrade the amplifier noise figure. This is especially true up to 5 GHz. The next section describes how a compromise between good return loss and minimum noise figure was achieved. A plot of noise figure vs. frequency for the two-stage cascade LNA is given in Figure 5. AN082_BFP640_Noise_Figure.vsd Figure 5 Noise Figure at T = 25 °C for the complete two-stage cascaded BFP640 LNA Input / Output Impedance Match Please refer to the schematic diagram in Figure 6. Lumped-element matching techniques are used exclusively, to reduce required PC board area. The output impedance matching circuit consists of L2 and L3 for the first stage, and L5 and L6 for the second stage. Due to the nonzero reverse transmission coefficient of the transistor (S12 ≠ 0), the output match favorably influences the input impedance match, with better than 10 dB input and output return loss values achieved across the band. As a result, no input impedance matching elements are required only an input DC block and a “choke” (L1 on first stage) to bring in base bias current is needed at the input. The value of L1 and L4 were chosen such that the chip coils operate just below their self resonant frequency (SRF), ensuring that these elements have minimal loading effects on the input of each stage. A Bill Of Material (BOM) is presented in Table 4. Note that a low-cost, industry-standard 0402 case-size chip components are used throughout. Application Note 11 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details V cc = 3.3 V J4 DC Connector Inductors are Murata LQP15M Series (formerly LQP10A) 0402 case size. Capacitors and resistors are 0402 case size. I = 8 mA R2 43K C3 0.033uF C4 1.5pF L1 6.2nH J1 RF INPUT R3 30 ohms C8 0.033uF C9 1.5pF C5 1.5pF L2 5.6nH Q1 BFP640 SiGe Transistor I = 8 mA R6 30 ohms R5 43K C6 0.033uF R1 10 ohms PCB = 640-052402 Rev C PC Board Material = Standard FR4 L4 6.2nH C2 1.5pF C11 0.033uF R4 10 ohms C10 1.5pF L5 5.6nH Q2 BFP640 SiGe Transistor J2 C7 1.5 pF RF OUTPUT L6 1.5nH L3 1.3nH C1 1.5pF Note: black rectangles are 50 ohm traces or "tracks" on the Printed Circuit Board - these marks are NOT Surface-Mount Components. Note: C2 serves as a DC block between stages when running the two-stage cascade. If it is desired to test Stage 1 or Stage 2 individually, C2 may be repositioned to steer the output of Stage 1 into RF connector J3 (to test Stage 1 alone), or to steer the input of Stage 2 to J3 (for testing Stage 2 alone). J3 RF INPUT / OUTPUT AN082_Schematic_Diagram.vsd Figure 6 Schematic Diagram for the Complete Two-Stage 5-6 GHz LNA Table 4 Bill OF Material (BOM) for the complete two-stage LNA Reference Designator Value Manufacturer Case Size Function C1, C2, C7 1.5 pF Various 0402 DC blocking C4, C5, C9, C10 1.5 pF Various 0402 RF bypass / RF block C3, C6, C8, C11 0.0033µF Various 0402 Low frequency ground at base (input 3rd order intercept improvement), lowfrequency decoupling / Blocking L1, L4 6.2 nH Murata lQP15M series 0402 Tight Tolerance Inductor (Former Murata series = LQP10A) RF “Choke” to the DC bias on base of Q1 and Q2 L2, L5 5.6 nH Murata IQP15M Tight Tolerance Inductor 0402 RF’Choke’ to collector of Q1 and Q2; also influences output match of each stage L3 1.3 nH Murata IQP15M Tight Tolerance Inductor 0402 Output matching, stage 1 L6 1.5 nH Murata LQP15M Tight Tolerance Inductor 0402 Output matching stage 2 R1, R4 10 Ω Various 0402 For stability, output matching R2, R5 43 kΩ Various 0402 DC bias for base of Q1, Q2 Application Note 12 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details Table 4 Bill OF Material (BOM) for the complete two-stage LNA (cont’d) Reference Designator Value Manufacturer Case Size Function R3, R6 30 Ω Various 0402 Drop supply voltage by approx. 0.3 V, provide DC feedback for bias compensation (Beta Variation, Temp., ect.) Q1, Q2 Infineon Technologies SOT343 BFP640 SiGe Transistor, 40 GHz fT J1, J2, J3 Johnson 142.0701-841 RF input / output connectors (J2 only used when testing stages individually) J4 AMP 5 Pin Header MTA-100 series 640456-5 (Standard PIN Plating) or 641215-5(Gold Plated Pins) DC connector PIN 1, 5 = ground PIN 3 = VCC PIN 2, 4 = no connection Details on the Printed Circuit Board As staged previously, the PC board used in this application note was simulated within and generated from the Eagleware GENESYS® software package. After simulations, CAD files required for PCB fabrication, including Gerber274X and Drill files, were created within and output from GENESYS. Photos of the PC board are provided in Figure 8 to Figure 10. A cross-sectional diagram of the PCB is in Figure 11. The PC Board material used is standard low-cost FR4. Note that each stage of the LNA may be tested individually; capacitor C2 (see schematic) may be positioned to “steer” the RF from the output of the first stage to the SMA connector on the bottom of the PCB, or, C2 may be used to link the track from this same RF connector to the input of the second stage, to permit testing of Stage 2 individually. The total PCB area consumed for a single stage is approximately 0.300 x 0.200 inch / 7.6 x 5.1 mm or approximatly 40 mm², giving about 80 mm² for the complete two-stage amplifier. The total component count, including all passives and the two BFP640 transistors, is 25. Application Note 13 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details Figure 7 Top View of 5 GHz LNA PC Board Figure 8 Bottom View of LNA PC Board Application Note 14 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details Figure 9 Close-In Shot of PCB showing component placement THIS SPACING CRITICAL ! PCB CROSS SECTION 0.010 inch / 0.254 mm TOP LAYER INTERNAL GROUND PLANE 0.031 inch / 0.787 mm ? LAYER FOR MECHANICAL RIGIDITY OF PCB, THICKNESS HERE NOT CRITICAL AS LONG AS TOTAL PCB THICKNESS DOES NOT EXCEED 0.045 INCH / 1.14 mm (SPECIFICATION FOR TOTAL PCB THICKNESS: 0.040 + 0.005 / - 0.005 INCH; 1.016 + 0.127 mm / - 0.127 mm ) BOTTOM LAYER AN082_Cross_Section_Diagram.vsd Figure 10 Cross-Section Diagram of the LNA Printed Circuit Board. Note spacing between top layer RF traces and internal ground plane is 0.010 inch / 0.254 mm Conclusions Infineon Technologies’ BFP640 Silicon-Germanium RF transistor offers a very high performance, power-efficient and cost-effective solution for a broad range of high-frequency low-noise amplifier (LNA) designs. The BFP640 improves on the world-class performance of its predecessor, the BFP620. There are other SiGe transistors in Infineon’s high-frequency transistor family, covering a full spectrum of applications and output power requirements. The flexibility of these devices allows one part of fulfill several different functions. For example, the BFP640 may be used as an LNA or a PA Driver amplifier in 5 GHz WLAN applications. This application note describes a high-performance, low cost, lumped-element discrete LNA design for 5-6 GHz frequency range. Evaluation boards for the LNA application shown in this applications note are available from Infineon Technologies. The company’s website is http://www.infineon.com. Application Note 15 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design Details References [1] Eagleware Corporation, 653 Pinnable Court, Norcross, GA 30071 USA. Tel: +1.678.2910995 http://eagleware.com (Eagleware software suite GENESYS Version 8 was used in all simulation, synthesis, and PC board CAD file generation done for the circuit described in this Application Note.) [2] “Understanding and Improving Network Analyzer Dynamic Range”, Application Note 1363-1, Agilent Technologies. (This application note explains how to minimize the noise floor / maximize the dynamic range of your network analyzer.) [3] “A High IIP3 Low Noise Amplifier for 1900 MHz Applications Using the SiGe BFP620 Transistor”. Applications Note AN060, Silicon Discretes Group, Infineon Technologies. (The section entitled “Effect of adding additional charge-storage across the base-emitter junction” explains the “capacitor trick” used to enhance third-order intercept performance. Application Note 16 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes Appendixes Appendix A. Data on 12 two-stage BFP640 LNA Circuit Boards, 640-052402 Rev C, taken randomly from a batch of assembled units 12 two-stage BFP640 LNA Circuit Boards, TA = 25 °C, Part 1 Table 5 Board S/N dB[s11]² dB[s21]² dB[s22]² 5150 MHz 5470 MHz 5925 MHz 5150 MHz 5470 MHz 5925 MHz 5150 MHz 5470 MHz 5925 MHz 002 15.2 17.7 15.1 23.4 22.1 20.2 10.2 13.0 16.3 005 16.9 21.1 15.9 24.0 22.7 20.6 11.9 16.4 16.9 006 15.6 20.2 16.1 23.6 22.4 20.4 10.5 14.3 17.7 009 16.0 18.0 15.4 23.6 22.3 20.3 10.6 14.1 15.8 012 13.5 16.5 16.1 23.4 22.1 20.1 12.4 17.5 17.7 016 15.1 20.4 18.3 23.3 22.2 20.2 10.0 13.0 16.8 017 15.5 21.2 17.7 23.5 22.4 20.5 9.6 13.4 17.7 019 14.2 19.3 18.0 23.6 22.4 20.5 11.2 15.4 18.6 023 14.5 20.0 19.5 23.6 22.4 20.4 11.3 15.5 16.9 029 15.6 17.2 14.7 23.5 22.2 20.2 10.9 14.4 16.5 036 16.1 19.0 15.7 23.1 21.8 19.9 11.2 15.2 17.1 041 15.6 17.7 14.8 23.3 21.9 20.0 11.5 14.7 15.9 ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ Min. 13.5 16.5 14.7 23.1 21.8 19.9 9.6 13.0 16.3 Max 16.9 21.2 19.5 24.0 22.7 20.6 12.4 17.5 17.7 Mean 15.3 19.0 16.4 23.5 22.2 20.3 10.9 14.7 17.0 Std. Dev. σn 0.87 1.57 1.49 0.21 0.24 0.20 0.77 1.30 0.79 Note: Population Standard Deviation is used (σn), not sample standard deviation (σn-1) Table 6 Board S/N 12 two-stage BFP640 LNA Circuit Boards, TA = 25 °C, Part 2 Noise Figure, dB Input IP3, dBm Input P1dB, dBm Current Consumption, mA 5150 MHz 5470 MHZ 5925 MHz 5470 MHz 5470 MHz 002 1.3 1.4 1.5 +6.9 -14.3 16.4 005 1.3 1.4 1.5 +7.0 -13.9 16.8 006 1.3 1.4 1.5 +5.8 -13.9 16.5 009 1.3 1.4 1.5 +2.5 -15.0 16.4 012 1.3 1.4 1.5 +4.0 -14.1 16.1 016 1.3 1.4 1.5 +3.9 -14.3 16.2 017 1.4 1.4 1.5 +6.9 -14.0 16.7 019 1.3 1.4 1.5 +3.6 -14.5 15.8 Application Note 17 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes Table 6 Board S/N 12 two-stage BFP640 LNA Circuit Boards, TA = 25 °C, Part 2 (cont’d) Noise Figure, dB Input IP3, dBm Input P1dB, dBm Current Consumption, mA 5150 MHz 5470 MHZ 5925 MHz 5470 MHz 5470 MHz 023 1.3 1.4 1.5 +6.1 -14.1 16.2 029 1.3 1.4 1.5 +4.5 -14.3 16.3 036 1.3 1.4 1.5 +4.6 -14.0 15.8 041 1.3 1.4 1.5 +4.2 -14.1 16.1 ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ Min. 1.3 1.4 1.5 +2.5 -15.0 15.8 Max 1.4 1.4 1.5 +7.0 -13.9 16.8 Mean 1.3 1.4 1.5 +5.0 -14.2 16.3 Std. Dev. σn 0.03 0 0 1.4 0.30 0.30 Note: Population Standard Deviation is used (σn), not sample standard deviation (σn-1) Application Note 18 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes Appendix B. Data Plots for the two-stage BFP640 5-6 GHz LNA (from one sample PC Board) Rohde & Schwarz FSEK3 13 Mar 2003 Noise Figure EUT Name: Manufacturer: Operating Conditions: Operator Name: Test Specification: Comment: Two Stage BFP640 5 - 6 GHz Low Noise Amplifier Infineon Technologies V = 3.3 V, I = 16 mA, T = 25 C Gerard Wevers AN082 On BFP640 PCB 640-052402 Rev C 10 March 2003 Analyzer RF Att: Ref Lvl: 0.00 dB -54.00 dBm RBW : VBW : 1 MHz 100 Hz Range: 30.00 dB Ref Lvl auto: ON Measurement 2nd stage corr: ON Mode: Direct ENR: HP346A.ENR Noise Figure /dB 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 5000 MHz 100 MHz / DIV 6000 MHz AN082_Noise_Figure_Plot.vsd Figure 11 Noise Figure Plot for complete two-stage cascaded LNA, T = 25 °C Application Note 19 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes CH 1 S2 1 log MAG 10 dB/ 14 Mar 2003 11:09:58 2_: 22.231 dB 5 470.000 000 MHz REF 0 dB PR m Co r De l Sm o 1_: 23.546 dB 5.15 GHz 3_: 20.195 5.925 dB GHz 4_: 29.049 dB 2.4 GHz 2 4 1 3 START .030 000 MHz STOP 6 000.000 000 MHz A N082_Forward_Gain_Wide.vsd Figure 12 Forward Gain, Wide Span (30 kHz - 6 GHz), T = 25 °C Application Note 20 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes CH 1 S1 1 log MAG 10 dB/ REF 0 dB 14 Mar 2003 11:32:08 4_:-18.623 dB 5 470.000 000 MHz PR m Co r De l 1_:-14.9 dB 5.15 GHz 2_:-15.813 dB 5.25 GHz 3_:-17.514 dB 5.35 GHz 5_:-16.27 5.925 dB GHz Sm o 4 1 2 5 3 START 5 000.000 000 MHz STOP 6 000.000 000 MHz AN082_Input_Return_Narrow.vsd Figure 13 Input Return Loss, Log Mag, Narrow Span, (5 - 6 GHz), T = 25 °C Application Note 21 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes CH 1 S 1 1 1U FS 4_: 53.457 11.6 14 Mar 2003 11:32:18 2.5084 pF 5 470.000 000 MHz PR m Co r De l 1_: 71.855 5.15 1.1914 GHz 2_: 68.465 5.25 5.5039 3_:GHz 60.998 5.35 9.9551 GHz 5_: 38.277 5.925 7.5703 GHz Sm o 4 3 5 START 5 000.000 000 MHz 1 2 STOP 6 000.000 000 MHz AN082_Input_Return_NarrowSC.vsd Figure 14 Input Return Loss, Narrow Span, Smith Chart, (5 - 6 GHz, Reference Plan = PCB Input SMA Connector) T = 25 °C Application Note 22 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes CH 1 S2 1 log MAG 10 dB/ REF 20 dB PR m Co r De l 14 Mar 2003 11:32:32 4_: 22.372 dB 5 470.000 000 MHz 1_: 23.637 dB 5.15 GHz 2_: 23.264 dB 5.25 GHz 3_: 22.88 dB 5.35 GHz 5_: 20.318 5.925 dB GHz Sm o 4 1 2 3 5 START 5 000.000 000 MHz STOP 6 000.000 000 MHz AN082_Forward_Gain_Narrow.vsd Figure 15 Forward Gain, Narrow Span, (5 - 6 GHz) T = 25 °C Application Note 23 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes CH 1 S 1 2 log MAG 10 dB/ 14 Mar 2003 11:32:48 4_:-36.037 dB 5 470.000 000 MHz REF -30 dB PR m Co r De l 1_:-36.876 dB 5.15 GHz 2_:-36.426 dB 5.25 GHz 3_:-36.073 dB 5.35 GHz 5_:-35.248 5.925 dB GHz Sm o 4 1 2 5 3 START 5 000.000 000 MHz STOP 6 000.000 000 MHz AN082_Reverse_Isolation_Narrow.vsd Figure 16 Reverse Isolation, Narrow Span, (5 - 6 GHz), T = 25 °C Application Note 24 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes CH 1 S2 2 log MAG 10 dB/ REF 0 dB 14 Mar 2003 11:33:02 4_:-15.851 dB 5 470.000 000 MHz PR m Co r De l 1_:-11.471 dB 5.15 GHz 2_:-12.86 dB 5.25 GHz 3_:-14.307 dB 5.35 GHz 5_:-17.476 5.925 dB GHz Sm o 4 1 2 3 5 START 5 000.000 000 MHz STOP 6 000.000 000 MHz AN082_Output_Return_Narrow.vsd Figure 17 Output Return Loss, Log Mag, Narrow Span (5 - 6 GHz) T = 25 °C Application Note 25 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes CH 1 S2 2 1U FS 14 Mar 2003 11:33:10 4_: 67.789 5.9961 174.46 pH 5 470.000 000 MHz PR m Co r De l 1_: 49.586 5.15 27.6 GHz 2_: 57.123 5.25 23.957 GHz 3_: 64.668 5.35 16.539 GHz 5_: 55.115 5.925 13.26 GHz Sm o 1 2 4 3 5 START 5 000.000 000 MHz STOP 6 000.000 000 MHz AN082_Output_Return_NarrowS C.vsd Figure 18 Output Return Loss, Narrow Span, Smith Chart, (5 -6 GHz, Reference Plane = PCB SMA Output Connector) T = 25 °C Application Note 26 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes AN082_Third_Order_Intercept.vsd Figure 19 Input Stimulus for Two-Tone Third Order Intercept Test; Two Tones, 5469.5 MHz and 5470.5 MHz, -23 dBm power per tone, T = 25 °C Application Note 27 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes AN082_Output_Response.vsd Figure 20 Two-Stage LNA Output Response to Two-Tone Test, Input 3rd Order Intercept = -23 + (53.3/2) = +3.7 dBm; T = 25 °C Application Note 28 Rev. 2.0, 2007-01-08 Application Note No. 082 5-6 GHz Two-Stage LNA Design DetailsAppendixes Appendix C. Temperature Test Data for one sample unit Table 7 Single LNA Stage Only (Stage 1) Temperature Frequency °C MHz dB [s11]² dB [s21]² dB [s12]² dB [s22]² -40 5150 17.1 11.8 17.8 11.4 -40 5470 18.1 11.4 17.3 14.4 -40 5925 17.9 10.8 16.6 16.9 +25 5150 15.4 11.3 18.2 10.4 +25 5470 18.5 10.9 17.7 13.2 +25 5925 18.7 10.3 17.0 15.2 +85 5150 13.5 10.7 18.5 9.5 +85 5470 17.8 10.4 18.0 12.2 +85 5925 20.7 9.8 17.4 14.3 IDC mA 8.4 7.7 7.2 Conclusions: 1. Gain change vs. temperature is approximately -0.008 dB / °C (≈ 1 dB gain change cold to hot) 2. Current change over full temperature range is 1.2 mA, or 16% 3. Slight degradation in output return loss when hot Table 8 Two-Stage LNA (another unit, both stages in cascade) Temperature Frequency °C MHz dB [s11]² dB [s21]² dB [s12]² dB [s22]² -40 5150 15.6 23.9 35.5 11.2 -40 5470 15.6 22.6 35.0 15.8 -40 5925 14.3 20.9 33.3 21.7 +25 5150 17.1 23.1 35.7 10.2 +25 5470 17.9 21.8 35.8 14.9 +25 5925 14.5 19.9 35.2 23.0 +85 5150 17.8 22.2 37.2 9.6 +85 5470 22.1 20.8 36.7 14.7 +85 5925 15.2 18.8 36.5 25.0 IDC mA 16.2 15.0 14.2 Conclusions: 1. Gain change vs. temperature is approximately -0.014 dB / °C (1.8 dB change cold to hot) 2. Current change over full temperature range is 2.0 mA, or 13% Application Note 29 Rev. 2.0, 2007-01-08