DATASHEET Radiation Tolerant 30V 16-Channel Analog Multiplexer ISL73840SEH Features The ISL73840SEH is a radiation tolerant, 16-channel high ESD protected multiplexer that is fabricated using Intersil’s proprietary P6SOI (Silicon On Insulator) process technology. It operates with a dual supply voltage ranging from ±10.8V to ±16.5V. It has a 4-bit address plus an enable pin that can be driven with adjustable logic thresholds to conveniently select 1 of 16 available channels. An inactive channel is separated from an active channel by a high impedance, which inhibits any interaction between them. • DLA SMD# 5962-15219 The ISL73840SEH’s low rON allows for improved signal integrity and reduced power losses. The ISL73840SEH is also designed for cold sparing making it excellent for high reliability applications that have redundancy requirements. It is designed to provide a high impedance to the analog source in a powered off condition, making it easy to add additional backup devices without loading signal sources. The ISL73840SEH also incorporates input analog overvoltage protection, which will disable the switch to protect downstream devices. The ISL73840SEH is available in a 28 Ld CDFP or die form and operates across the extended temperature range of -55°C to +125°C. There is also a 32-channel version available offered in a 48 Ld CQFP, please refer to the ISL73841SEH datasheet for more information. For a list of differences please refer to Table 1 on page 3. • Fabricated using P6SOI process technology • ESD protection 8kV (HBM) • Rail-to-rail operation • Overvoltage protection • Low rON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <500Ω (typical) • Flexible split rail operation - Positive supply above GND (V+) . . . . . . . +10.8V to +16.5V - Negative supply below GND (V-) . . . . . . . . -10.8V to -16.5V • Adjustable logic threshold control with VREF pin • Cold sparing capable (from ground). . . . . . . . . . . . . . . . .±25V • Analog overvoltage range (from ground) . . . . . . . . . . . . .±35V • Off switch leakage . . . . . . . . . . . . . . . . . . . 100nA (maximum) • Transition times (tR, tF) . . . . . . . . . . . . . . . . . . . 500ns (typical) • Break-before-make switching • Grounded metal lid (internally connected) • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation tolerance - Low dose rate (0.01rad(Si)/s) . . . . . 50krad(Si) (see Note) - SEB LETTH . . . . . . . . . . . . . . . . . . . . . . . . .86.4 MeV•cm2/mg NOTE: Product capability established by initial characterization. All subsequent lots are assurance tested to 50krad (0.01rad(Si)/s) wafer-by-wafer. 600 ISL73840SEHM 500 IN01 IN03 . . . OUT ADC IN16 400 +125°C +25°C 300 200 100 4 -55°C 0 -20 ADDRESS EN FIGURE 1. TYPICAL APPLICATION May 31, 2016 FN8845.1 rDS(ON) (Ω) IN02 1 -15 -10 -5 0 5 10 SWITCH INPUT VOLTAGE (V) 15 20 FIGURE 2. rDS(ON) vs POWER SUPPLY ACROSS SWITCH INPUT COMMON-MODE VOLTAGE AT +25°C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL73840SEH Table of Contents Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications (±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications (±12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Post Low Dose Rate Radiation Characteristics (V± = ±15V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Post Low Dose Rate Radiation Characteristics (V± = ±12V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREF and Logic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 19 ISL73840SEH vs ISL73841SEH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Assembly Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 20 Metalization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ceramic Metal Seal Flatpack Packages (Flatpack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Submit Document Feedback 2 FN8845.1 May 31, 2016 ISL73840SEH Ordering Information ORDERING/SMD NUMBER (Note 2) TEMP RANGE (°C) PART NUMBER PACKAGE (RoHS Compliant) PKG. DWG. # 5962L1521902VXC ISL73840SEHVF (Note 1) -55 to +125 28 LD CDFP K28.A N/A ISL73840SEHF/PROTO (Note 1) -55 to +125 28 LD CDFP K28.A 5962L1521902V9A ISL73840SEHVX -55 to +125 Die N/A N/A ISL73840SEHX/SAMPLE -55 to +125 Die N/A NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. TABLE 1. TABLE OF DIFFERENCES SPECIFICATION ISL73840SEH ISL73841SEH Number of Channels 16 32 Supply Current (I+/I-) 350µA (Maximum) 400µA (Maximum) 60nA (Maximum) 120nA (Maximum) Output Leakage (+125°C) Submit Document Feedback 3 FN8845.1 May 31, 2016 ISL73840SEH Pin Configuration ISL73840SEH (28 LD CDFP) TOP VIEW V+ 1 28 VOUT NC 2 27 V- NC 3 26 IN08 IN16 4 25 IN07 IN15 5 24 IN06 IN14 6 23 IN05 IN13 7 22 IN04 IN12 8 21 IN03 IN11 9 20 IN02 IN10 10 19 IN01 IN09 11 18 EN GND 12 17 A0 VREF 13 16 A1 A3 14 15 A2 Pin Descriptions PIN NAME PIN NUMBER VOUT 28 Output for multiplexer V+ 1 Positive power supply V- 27 Negative power supply NC 2, 3 Not electrically connected INx DESCRIPTION 4, 5, 6, 7, 8, 9, 10, 11, 19, 20, 21, Input for multiplexer 22, 23, 24, 25, 26 Ax 14, 15, 16, 17 EN 18 Enable control for multiplexer (active low) VREF 13 Reference voltage used to set logic thresholds GND 12 Ground LID - Submit Document Feedback 4 Address lines for multiplexer Package Lid is internally connected to GND (Pin 12) FN8845.1 May 31, 2016 ISL73840SEH Absolute Maximum Ratings Thermal Information (V+) Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 28 Ld CDFP (Notes 3, 4) . . . . . . . . . . . . . . . 48 4 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Positive Supply Voltage above GND (Note 5). . . . . . . . . . . . . . . . . +20V Negative Supply Voltage below GND (V-) (Note 5 . . . . . . . . . . . . . . . . . .-20V Maximum Supply Voltage Differential (V+ to V-) (Note 5) . . . . . . . . . . . 40V Maximum Current Through Selected Switch. . . . . . . . . . . . . . . . . . . . 10mA Analog Input Voltage (INx) From GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35V Digital Input Voltage Range (EN, Ax) . . . . . . . . . . . . . . . . . . . . . . . . GND to V+ VREF to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16.5V ESD Tolerance Human Body Model (Tested per MIL-STD-883 TM 3015) . . . . . . . . . 8kV Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 250V Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 250V Recommended Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Positive Supply Voltage Above GND (V+) . . . . . . . . . . . . . +10.8V to +16.5V Negative Supply Voltage Below GND (V-) . . . . . . . . . . . . . . .-10.8V to -16.5V Supply Voltage Differential (V+ to V-) . . . . . . . . . . . . . . . . . . . . 21.6V to 33V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is the center of the package underside. 5. Tested in a heavy ion environment at LET = 86.3 MeV•cm2/mg at +125°C. Electrical Specifications (±15V) V+ = 15V, V- = -15V, VAH = 4V, VAL = 0.8V, VREF = VEN = 5V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. SYMBOL VS Analog Input Signal Range rON Channel ON-Resistance ΔrON RFLAT(ON) IS(OFF) MIN (Note 6) TYP MAX (Note 6) UNIT V- - V+ V V± = ±15.0V, ±16.5V IOUT = -1mA, VIN = +5V, -5V - - 500 Ω V± = ±15.0V, ±16.5V IOUT = -1mA, VIN = V+, V- - - 700 Ω VIN = +5V, -5V; IOUT = -1mA - 10 20 Ω PARAMETER rON Match Between Channels TEST CONDITIONS ON-Resistance Flatness VIN = +5V, -5V - - 25 Ω Switch Off Leakage VIN = V+ - 5V, V± = ±16.5V, All unused inputs are tied to V- + 5V -10 - 10 nA Post radiation -100 - 100 nA VIN = V- + 5V, V± = ±16.5V All other inputs = V+ - 5V TA = +25°C -10 - 10 nA TA = +125°C -20 - 20 nA Post radiation -100 - 100 nA VIN = +25V, V± = VEN = VA = VREF = 0V TA = +25°C, V± = 0V -10 - 10 nA TA = -55°C, +125°C -10 - 80 nA Post radiation -100 - 100 nA VIN = -25V, V± = VEN = VA = VREF = 0V TA = +25°C, V± = 0V -10 - 10 nA TA = -55°C, +125°C -80 - 10 nA Post radiation -100 - 100 nA IS(OFF) POWER OFF Switch Off Leakage with Device Powered Off Submit Document Feedback 5 FN8845.1 May 31, 2016 ISL73840SEH Electrical Specifications (±15V) V+ = 15V, V- = -15V, VAH = 4V, VAL = 0.8V, VREF = VEN = 5V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) SYMBOL IS(OFF) POWER OFF Switch Off Leakage with Device Powered Off IS(ON) OVERVOLT IS(OFF) OVERVOLT ID(OFF) MIN (Note 6) TYP MAX (Note 6) UNIT VIN = +25V, VEN/VA/VREF = 0V V± = OPEN, TA = +25°C -10 - 10 nA TA = -55°C, +125°C -10 - 80 nA Post radiation -100 - 100 nA VIN = -25V, VEN/VA/VREF = 0V V± = OPEN, TA = +25°C -10 - 10 nA TA = -55°C, +125°C -80 - 10 nA Post radiation -100 - 100 nA VIN = +35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA TA = +125°C -80 - 80 nA Post radiation -500 - 500 nA VIN = -35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA TA = +125°C -20 - 20 nA Post radiation -500 - 500 nA VIN = +35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA PARAMETER Switch On Leakage Current Into the Source (overvoltage) Switch Off Leakage Current Into the Source (overvoltage) Switch Off Leakage Submit Document Feedback 6 TEST CONDITIONS TA = +125°C -80 - 80 nA Post radiation -750 - 750 nA VIN = -35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA TA = +125°C -20 - 20 nA Post radiation -750 - 750 nA VOUT = V+ - 5V, All inputs = V- + 5V V± = ±16.5V, TA = +25°C, -55°C -10 - 10 nA TA = +125°C 0 - 60 nA Post radiation -80 - 80 nA VOUT = V- + 5V, All inputs = V+ - 5V V± = ±16.5V, TA = +25°C, -55°C -10 - 10 nA TA = +125°C -60 - 0 nA Post radiation -80 - 80 nA FN8845.1 May 31, 2016 ISL73840SEH Electrical Specifications (±15V) V+ = 15V, V- = -15V, VAH = 4V, VAL = 0.8V, VREF = VEN = 5V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) MIN (Note 6) TYP MAX (Note 6) UNIT VOUT = 0V, VIN = +35V, V± = ±16.5V All unused inputs are tied to GND -10 - 10 nA Post radiation -500 - 500 nA VOUT = 0V, VIN = -35V, V± = ±16.5V All unused inputs are tied to GND -10 - 10 nA Post radiation -500 - 500 nA -10 - 10 nA TA = +125°C 0 - 60 nA Post radiation -100 - 100 nA V- VIN = VOUT = + 5V, TA = +25°C, -55°C All unused inputs = V -+ 5V, V± = ±16.5V -10 - 10 nA TA = +125°C -60 - 0 nA Post radiation -100 - 100 nA Logic Input High/Low Voltage VREF = 5.0V 1.2 - 1.6 V IAH, IENH Input Current with VAH, VENH VA = VEN = 4.0V V+ = 16.5V, V- = -16.5V -100 - 100 nA IAL, IENL Input Current with VAL, VENL VA = VEN = 0.8V V+ = 16.5V, V- = -16.5V -100 - 100 nA - 350 µA SYMBOL ID(OFF) OVERVOLT ID(ON) VAH/L, VENH/L I+ PARAMETER Switch Off Leakage Current Into the Drain (overvoltage) Switch On Leakage Current Into the Source/Drain Quiescent Supply Current II+ Standby Supply Current IIREF TEST CONDITIONS V+ - VIN = VOUT = 5V, TA = +25°C, -55°C All unused inputs = V- + 5V, V± = ±16.5V VIN = VA = VEN = 0.8V, V± = ±15.0V, ±16.5V - VIN = VA = VEN = 0.8V, V± = ±15.0V, ±16.5V -350 - - µA VIN = VA = VEN = 4.0V, V± = ±15.0V, ±16.5V - - 350 µA VIN = VA = VEN = 4.0V, V± = ±15.0V, ±16.5V -350 - - µA Supply Current Into VREF VREF = 5.5V, VIN = VA = VEN = 0.8V, V± = ±15.0V, ±16.5V - - 35 µA Transition Time Figures 4, 5 - 0.5 800 ns DYNAMIC tALH Figures 4, 5 - 0.5 800 ns Break-Before-Make Delay Figures 8, 9 5 50 200 ns Post radiation 5 - 400 ns tENABLE Enable Turn-On Time Figures 6, 7 - 0.5 600 ns tDISABLE Disable Turn-Off Time tAHL tBBM Post radiation - - 800 ns Figures 6, 7 - 0.5 600 ns Post radiation - - 800 ns VCTE Charge Injection CL = 100pF, VIN = 0V, (Figure 6) - 2 5 pC VISO OFF Isolation VEN = 4V, RL = 1kΩ, f = 200kHz, CL = 7pF, VRMS = 3V 75 - - dB VCT Crosstalk VEN = 0.8V, RL = 1kΩ, f = 200kHz, CL = 7pF, VRMS = 3V 47 - - dB CA Digital Input Capacitance f = 1MHz, V+ = V- = 0V - - 7 pF Input Capacitance f = 1MHz, V+ = V- = 0V - - 5 pF V+ - - 50 pF CIN(OFF) COUT(OFF) Output Capacitance Submit Document Feedback 7 f = 1MHz, = V- = 0V FN8845.1 May 31, 2016 ISL73840SEH Electrical Specifications (±12V) V+ = 12V, V- = -12V, VAH = 4.0V, VAL = 0.8V, VREF = VEN = 5.0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. SYMBOL PARAMETER VS Analog Input Signal Range rON Channel ON-Resistance ΔrON RFLAT(ON) I+ TYP V- MAX (Note 6) UNIT V+ V - - 500 Ω V± = ±10.8V, ±13.2V IOUT = -1mA, VIN = V+, V- - - 700 Ω rON Match Between Channels VIN = +5V, -5V; IOUT = -1mA - 10 20 Ω ON-Resistance Flatness VIN = +5V, -5V, V± = ±13.2V - - 25 Ω VIN = +5V, -5V, V± = ±10.8V TA = +25°C, -55°C, +125°C - - 30 Ω VIN = +5V, -5V, V± = ±10.8V, post radiation - - 40 Ω VIN = VA = VEN = 0.8V, V± = ±10.8V, ±13.2V - - 350 µA VIN = VA = VEN = 0.8V, V± = ±10.8V, ±13.2V -350 - - µA VIN = VA = VEN = 4.0V, V± = ±10.8V, ±13.2V - - 350 µA VIN = VA = VEN = 4.0V, V± = ±10.8V, ±13.2V -350 - - µA Quiescent Supply Current Standby Supply Current IIREF MIN (Note 6) V± = ±10.8V, ±13.2V IOUT = -1mA, VIN = +5V, -5V II+ TEST CONDITIONS Supply Current Into VREF VREF = 5.5V, VIN = VA = VEN = 0.8V, V± = ±10.8V, ±13.2V - - 35 µA Transition Time Figures 4, 5 - 0.5 800 ns Figures 4, 5 - 0.5 800 ns Figures 8, 9 5 50 200 ns Post radiation - - 400 ns Figures 6, 7 - 0.5 600 ns Post radiation - - 800 ns Figures 6, 7 - 0.5 600 ns Post radiation - - 800 ns DYNAMIC tALH tAHL tBBM tENABLE tDISABLE Break-Before-Make Delay Enable Turn-On Time Disable Turn-Off Time NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Submit Document Feedback 8 FN8845.1 May 31, 2016 ISL73840SEH TABLE 2. TRUTH A3 A2 A1 A0 EN “ON” CHANNEL X X X X 1 None 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 0 12 1 1 0 0 0 13 1 1 0 1 0 14 1 1 1 0 0 15 1 1 1 1 0 16 NOTE: 7. X = Don’t care, “1” = Logic High, “0” = Logic Low. Submit Document Feedback 9 FN8845.1 May 31, 2016 ISL73840SEH Block Diagram V+ IN1 A0 1 OUT A1 A2 A3 IN16 16 EN ADDRESS INPUT BUFFER AND LEVEL SHIFTER DECODERS VMULTIPLEX SWITCHES FIGURE 3. BLOCK DIAGRAM Submit Document Feedback 10 FN8845.1 May 31, 2016 ISL73840SEH Timing Diagrams 4V “1111” I SL71840SEH +4.0V A3 A2 A1 A0 50Ω +15V, 0V IN01 ADDRESS 50% 50% IN02-IN15 0V, +15V IN16 “0000” 0.8V +0.8V 15V +0.8V EN VOUT OUT 50pF 10kΩ tAHL OUTPUT tALH 50% 50% 0V FIGURE 5. ADDRESS TIME TO OUTPUT DIAGRAM FIGURE 4. ADDRESS TIME TO OUTPUT TEST CIRCUIT I SL71840SEH A3 A2 A1 A0 4V IN01 +10V IN02-IN16 ENABLE 50% 50% 0.8V 10V EN +4.0V OUT VOUT 1kΩ 50Ω tDISABLE tENABLE OUTPUT 50pF 50% 50% +0.8V 0V FIGURE 6. TIME TO ENABLE/DISABLE OUTPUT TEST CIRCUIT FIGURE 7. TIME TO ENABLE/DISABLE OUTPUT DIAGRAM 4V I SL71840SEH A3 A2 A1 A0 +4.0V 50Ω IN01 ADDRESS +5V IN02-IN15 IN16 0.8V +0.8V 5V +0.8V EN E N 50% VOUT OUT OUT 1kΩ 50pF 0V FIGURE 9. BREAK-BEFORE-MAKE DIAGRAM FIGURE 8. BREAK-BEFORE-MAKE TEST CIRCUIT 4V I SL71840SEH +4.0V 50Ω A3 A2 A1 A0 IN01 tBBM 0V ADDRESS IN02-IN15 IN16 0.8V +0.8V 15V +0.8V EN OUT Q = 100pF * ΔVOUT VOUT OUT 100pF ΔVOUT 0V FIGURE 10. CHARGE INJECTION TEST CIRCUIT Submit Document Feedback 11 FIGURE 11. CHARGE INJECTION DIAGRAM FN8845.1 May 31, 2016 ISL73840SEH Typical Performance Curves V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. 600 600 500 500 +25°C +125°C 400 rDS(ON) (Ω) 400 rDS(ON) (Ω) +125°C 300 200 +25°C 300 200 100 100 -55°C 0 -20 -15 -55°C -10 -5 0 5 10 15 0 -20 20 -15 -10 SWITCH INPUT VOLTAGE (V) FIGURE 12. rDS(ON) vs VCM (V± = 14.5V) rDS(ON) (Ω) rDS(ON) (Ω) 15 20 +125°C 500 +125°C 300 200 +25°C 400 300 200 100 100 -55°C 0 -20 -15 -10 -5 0 5 10 15 -55°C 0 -15 20 -10 -5 0 5 10 15 10 15 SWITCH INPUT VOLTAGE (V) SWITCH INPUT VOLTAGE (V) FIGURE 14. rDS(ON) vs VCM (V± = 16.5V) FIGURE 15. rDS(ON) vs VCM (V± = 10.8V) 600 600 500 500 +125°C +25°C 400 rDS(ON) (Ω) rDS(ON) (Ω) 10 600 400 +25°C 300 +125°C +25°C 300 200 200 0 -15 5 700 500 100 0 FIGURE 13. rDS(ON) vs VCM (V± = 15.0V) 600 400 -5 SWITCH INPUT VOLTAGE (V) 100 -55°C -10 -5 0 5 SWITCH INPUT VOLTAGE (V) FIGURE 16. rDS(ON) vs VCM (V± = 12.0V) Submit Document Feedback 12 10 15 0 -15 -55°C -10 -5 0 5 SWITCH INPUT VOLTAGE (V) FIGURE 17. rDS(ON) vs VCM (V± = 13.2V) FN8845.1 May 31, 2016 ISL73840SEH Typical Performance Curves V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 700 600 t ADDHL (ns) 500 5V/DIV +125°C 400 +25°C -55°C 300 200 2V/DIV 100 tADDLH = 211.199ns tADDHL = 561.469ns 0 10 11 12 500ns/DIV 13 14 15 16 17 SPLIT SUPPLY RAILS (±V) FIGURE 19. ADDRESS TO OUTPUT DELAY (HIGH TO LOW) FIGURE 18. TYPICAL ADDRESS TO OUTPUT DELAY (V± = ±15V, +25°C) 300 t ADDLH (ns) 250 200 5V/DIV -55°C +125°C 150 +25°C 1V/DIV 100 50 0 10 11 12 13 14 15 16 17 tDISABLE = 202.207ns tENABLE = 352.379ns SPLIT SUPPLY RAILS (±V) 500ns/DIV FIGURE 21. TYPICAL ENABLE TO OUTPUT DELAY (V± = ±15V, +25°C) FIGURE 20. ADDRESS TO OUTPUT DELAY (LOW TO HIGH) 400 600 350 500 400 300 t DISABLE (ns) t ENABLE (ns) 300 +125°C 200 +25°C -55°C 250 200 150 100 100 0 10 -55°C +25°C +125°C 50 11 12 13 14 15 16 SPLIT SUPPLY RAILS (±V) FIGURE 22. ENABLE TO OUTPUT DELAY (LOW TO HIGH) Submit Document Feedback 13 17 0 10 11 12 13 14 15 16 17 SPLIT SUPPLY RAILS (±V) FIGURE 23. DISABLE TO OUTPUT DELAY (LOW TO HIGH) FN8845.1 May 31, 2016 ISL73840SEH Typical Performance Curves V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 120 100 +125°C 80 tBBM (ns) 2V/DIV 60 +25°C 40 1V/DIV -55°C 20 0 tBBM = 73.425ns 10 11 12 13 14 15 16 200ns/DIV SPLIT SUPPLY RAILS (±V) FIGURE 24. TYPICAL BREAK-BEFORE-MAKE DELAY (V± = 15V, +25°C) FIGURE 25. BREAK-BEFORE-MAKE DELAY 160 120 100 120 OFF ISOLATION (dB) OFF ISOLATION (dB) 140 100 80 60 40 80 60 40 20 20 0 100 1k 10k 100k 1M 0 10 10M 100 FREQUENCY (Hz) 10k 100k 1M FIGURE 27. OFF ISOLATION (V± = ±15V, RL = OPEN, +25°C) 140 120 120 100 100 CROSSTALK (dB) CROSSTALK (dB) 1k FREQUENCY (Hz) FIGURE 26. OFF ISOLATION (V± = ±15V, RL = 1kΩ, +25°C) 80 60 40 80 60 40 20 20 0 100 17 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 28. CROSSTALK (V± = ±15V, RL = 1kΩ, +25°C) Submit Document Feedback 14 10M 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 29. CROSSTALK (V± = ±15V, RL = OPEN, +25°C) FN8845.1 May 31, 2016 ISL73840SEH Typical Performance Curves V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) VIN: 5V/DIV V+ = +12V VOUT: 5V/DIV VOUT V- = -12V VIN 100µs/DIV FIGURE 30. OVERVOLTAGE/UNDERVOLTAGE PROTECTION (+25°C) Post Low Dose Rate Radiation Characteristics (V± = ±15V) Unless otherwise specified, V± = ±15V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. 0 SUPPLY CURRENT SHIFT (µA) SUPPLY CURRENT SHIFT (µA) 1.2 1.0 GROUNDED 0.8 0.6 0.4 BIASED 0.2 0 0 10 20 30 40 50 -0.2 -0.4 -0.8 GROUNDED -1.0 -1.2 -1.4 60 BIASED -0.6 0 FIGURE 31. ICC SUPPLY CURRENT SHIFT vs LDR RADIATION 30 40 50 60 10 8 GROUNDED 2.0 rDS(ON) SHIFT (Ω) SUPPLY CURRENT SHIFT (µA) 20 FIGURE 32. IEE SUPPLY CURRENT SHIFT vs LDR RADIATION 2.5 1.5 BIASED 1.0 0.5 0 10 LOW DOSE RATE RADIATION (krad(Si)) LOW DOSE RATE RADIATION (krad(Si)) BIASED 6 4 2 GROUNDED 0 -2 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 33. IREF SUPPLY CURRENT SHIFT vs LDR RADIATION Submit Document Feedback 15 -4 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 34. rDS(ON) SHIFT (VIN = +5V) vs LDR RADIATION FN8845.1 May 31, 2016 ISL73840SEH Post Low Dose Rate Radiation Characteristics (V± = ±15V) Unless otherwise specified, V± = ±15V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 6 25 5 BIASED 20 3 rDS(ON) SHIFT (Ω) rDS(ON) SHIFT (Ω) 4 2 1 GROUNDED 0 -1 -2 15 10 5 0 -3 -4 BIASED 0 10 20 30 40 50 -5 60 GROUNDED 0 LOW DOSE RATE RADIATION (krad(Si)) 0 250 ADDRESS TIME SHIFT (ns) -2 rDS(ON) SHIFT (Ω) 30 40 50 60 FIGURE 36. rDS(ON) SHIFT (VIN = V+) vs LDR RADIATION BIASED -1 GROUNDED -4 -5 -6 -7 BIASED -8 20 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 35. rDS(ON) SHIFT (VIN = -5V) vs LDR RADIATION -3 10 200 GROUNDED 150 100 50 -9 -10 0 10 20 30 40 50 0 60 0 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 37. rDS(ON) SHIFT (VIN = V-) vs LDR RADIATION FIGURE 38. tADD SHIFT (LOW TO HIGH) vs LDR RADIATION 0 14 GROUNDED -10 12 -20 -30 tBBM SHIFT (ns) ADDRESS TIME SHIFT (ns) 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) BIASED -40 -50 -60 -70 -80 GROUNDED 8 BIASED 6 4 2 -90 -100 0 10 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 39. tADD SHIFT (HIGH TO LOW) vs LDR RADIATION Submit Document Feedback 16 60 0 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 40. tBBM SHIFT vs LDR RADIATION FN8845.1 May 31, 2016 ISL73840SEH Post Low Dose Rate Radiation Characteristics (V± = ±15V) Unless otherwise specified, V± = ±15V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 20 300 15 250 BIASED tDISABLE SHIFT (ns) tENABLE SHIFT (ns) BIASED 10 5 0 GROUNDED -5 -10 0 10 20 30 40 200 GROUNDED 150 100 50 50 0 0 60 LOW DOSE RATE RADIATION (krad(Si)) 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 41. tENABLE SHIFT vs LDR RADIATION FIGURE 42. tDISABLE SHIFT vs LDR RADIATION Post Low Dose Rate Radiation Characteristics (V± = ±12V) Unless otherwise specified, V± = ±12V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. 0 SUPPLY CURRENT SHIFT (µA) SUPPLY CURRENT SHIFT (µA) 1.2 GROUNDED 1.0 0.8 0.6 BIASED 0.4 0.2 0 0 10 20 30 40 50 -0.2 -0.6 -0.8 -1.0 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 43. ICC SUPPLY CURRENT SHIFT vs LDR RADIATION 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 35 30 rDS(ON) SHIFT (Ω) GROUNDED 2.0 1.5 BIASED 1.0 0.5 25 BIASED 20 15 10 5 GROUNDED 0 0 60 FIGURE 44. IEE SUPPLY CURRENT SHIFT vs LDR RADIATION 2.5 SUPPLY CURRENT SHIFT (µA) GROUNDED -1.2 -1.4 0 60 BIASED -0.4 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 45. IREF SUPPLY CURRENT SHIFT vs LDR RADIATION Submit Document Feedback 17 -5 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 46. rDS(ON) SHIFT (VIN = V+) vs LDR RADIATION FN8845.1 May 31, 2016 ISL73840SEH Post Low Dose Rate Radiation Characteristics (V± = ±12V) Unless otherwise specified, V± = ±12V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 8 12 6 6 4 2 GROUNDED 0 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 350 0 300 -2 GROUNDED -4 -6 -8 BIASED -10 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 20 30 40 50 60 BIASED GROUNDED 200 150 100 50 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 50. tADD SHIFT (LOW TO HIGH) vs LDR RADIATION 20 16 15 14 BIASED GROUNDED tBBM SHIFT (ns) 12 5 0 -5 GROUNDED -10 10 8 BIASED 6 4 -15 -20 10 250 0 60 FIGURE 49. rDS(ON) SHIFT (VIN = V-) vs LDR RADIATION 10 0 FIGURE 48. rDS(ON) SHIFT (VIN = -5V) vs LDR RADIATION 2 -12 BIASED 0 LOW DOSE RATE RADIATION (krad(Si)) ADDRESS TIME SHIFT (ns) rDS(ON) SHIFT (Ω) 2 -4 60 FIGURE 47. rDS(ON) SHIFT (VIN = +5V) vs LDR RADIATION ADDRESS TIME SHIFT (ns) 4 -2 -2 -4 GROUNDED BIASED 8 rDS(ON) SHIFT (Ω) rDS(ON) SHIFT (Ω) 10 2 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 51. tADD SHIFT (HIGH TO LOW) vs LDR RADIATION Submit Document Feedback 18 60 0 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 52. tBBM SHIFT vs LDR RADIATION FN8845.1 May 31, 2016 ISL73840SEH Post Low Dose Rate Radiation Characteristics (V± = ±12V) Unless otherwise specified, V± = ±12V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 25 300 20 250 BIASED tDISABLE SHIFT (ns) tENABLE SHIFT (ns) BIASED 15 10 5 GROUNDED 0 150 100 50 -5 -10 GROUNDED 200 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 53. tENABLE SHIFT vs LDR RADIATION 0 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 54. tDISABLE SHIFT vs LDR RADIATION Applications Information ISL73840SEH vs ISL73841SEH Power-Up Considerations There is a 32-channel version of the ISL73840SEH available in a 48 Ld CQFP. In terms of performance specs, the parts are very similar in behavior. Apart from the apparent increase in channel density, the ISL73841SEH does have slightly higher output leakage compared to the ISL73840SEH due to having more channels connected to the output. The supply current for the ISL73841SEH is also a bit higher compared to the ISL73840SEH. (See Table 1 on page 3). The circuit is designed to be insensitive to any given power-up sequence between V+, V- and VREF, however, it is recommended that all supplies power up relatively close to each other. Overvoltage Protection The ISL73840SEH has overvoltage protection on both the input as well as the output. On the output, the voltage is limited to a diode past the rails. Each of the inputs has independent overvoltage protection that works regardless of the switch being selected. If a switch experiences an overvoltage condition (3V to 4V) past the rail, the switch is turned off. As soon as the voltage returns within the rails, the switch returns to normal operation. VREF and Logic Functionality The VREF pin sets the logic threshold for the ISL73840SEH. The range for VREF is between 4.5V and 5.5V with a nominal voltage of 5V. The address pins and enable are compared against roughly 30% of VREF voltage (refer to Figure 55). With 5V on VREF, the switching point is set to around 1.4V. This switching point allows for both 5V and 3.3V logic control. ISL73840SEHM A/EN 400kΩ VREF To Decoder 200kΩ FIGURE 55. SIMPLIFIED VREF CIRCUITRY Submit Document Feedback 19 FN8845.1 May 31, 2016 ISL73840SEH Die Characteristics Assembly Related Information Die Dimensions SUBSTRATE POTENTIAL Floating 2820µm x 4080µm (111 mils x 161 mils) Thickness: 483µm ± 25µm (19 mils ± 1 mil) Additional Information Interface Materials WORST CASE CURRENT DENSITY GLASSIVATION 1.6 x 105 A/cm2 Type: 12kÅ Silicon Nitride on 3kÅ Oxide TRANSISTOR COUNT TOP METALLIZATION 5682 Type: 300Å TiN on 2.8µm AlCu In Bondpads, TiN has been removed. Weight of Packaged Device 2.096 grams BACKSIDE FINISH Lid Characteristics Silicon Finish: Gold Potential: Grounded, tied to package pin 12 PROCESS P6SOI Metalization Mask Layout IN16 20 OUT IN8 V- IN15 IN7 IN14 IN6 IN13 IN5 IN12 IN4 IN11 IN3 IN10 IN2 IN9 IN1 GND Submit Document Feedback V+ A4 A3 A2 A1 A0 EN BAR FN8845.1 May 31, 2016 ISL73840SEH TABLE 3. ISL73840SEH DIE LAYOUT X-Y COORDINATES PAD NUMBER PAD NAME PACKAGING PIN ΔX (µm) ΔY (µm) X (µm) Y (µm) 1 IN8 P26 127 127 979.5 1768.5 3 V+ P27 125 125 417.5 1754.5 4 OUT P28 125 125 -79.5 1774.5 5 V- P1 125 125 -474.5 1756.5 7 IN16 P4 127 127 -947.5 1752.5 10 IN15 P5 127 127 -1133.5 1310.5 11 IN14 P6 127 127 -1133.5 868.5 12 IN13 P7 127 127 -1133.5 426.5 13 IN12 P8 127 127 -1133.5 -15.5 14 IN11 P9 127 127 -1133.5 -457.5 15 IN10 P10 127 127 -1133.5 -899.5 16 IN9 P11 127 127 -1133.5 -1341.5 17 GND P12 250 125 -1147 -1839.5 18 VREF P13 127 127 -781.5 -1763.5 19 A3 P14 127 127 -451.5 -1763.5 20 A2 P15 127 127 -121.5 -1763.5 21 A1 P16 127 127 208.5 -1763.5 22 A0 P17 127 127 538.5 -1763.5 23 EN_B P18 127 127 868.5 -1763.5 25 IN1 P19 127 127 1133.5 -1341.5 26 IN2 P20 127 127 1133.5 -899.5 27 IN3 P21 127 127 1133.5 -457.5 28 IN4 P22 127 127 1133.5 -15.5 29 IN5 P23 127 127 1133.5 426.5 30 IN6 P24 127 127 1133.5 868.5 31 IN7 P25 127 127 1133.5 1310.5 NOTE: Origin of coordinates is the center of the die. Submit Document Feedback 21 FN8845.1 May 31, 2016 ISL73840SEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE May 31, 2016 FN8845.1 Added SMD in Features. Updated Ordering Information table on page 3. Updated header in 1st and 2nd columns of “Electrical Specifications (±15V)” on page 5 and “Electrical Specifications (±12V)” on page 8 from “Parameter” and “Description” to “Symbol” and “Parameter” May 13, 2016 FN8845.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 22 FN8845.1 May 31, 2016 ISL73840SEH Ceramic Metal Seal Flatpack Packages (Flatpack) K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B) A e 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A INCHES PIN NO. 1 ID AREA -A- D -B- S1 b E1 0.004 M H A-B S D S Q 0.036 M H A-B S D S C E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 BASE METAL (c) b1 M M (b) NOTES: SYMBOL MIN MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.740 E 0.460 0.520 E1 - 0.550 - E2 0.180 - 4.57 - - E3 0.030 - 0.76 - 7 e LEAD FINISH SECTION A-A MILLIMETERS 11.68 0.050 BSC 18.80 3 13.21 - 13.97 3 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.00 - 0.00 - 6 M - 0.0015 - N 28 0.04 28 - Rev. 0 5/18/94 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Submit Document Feedback 23 FN8845.1 May 31, 2016