an1556

Application Note 1556
Author: Don LaFontaine
Building an Accurate SPICE Model for Low Noise,
Low Power Precision Amplifiers
Abstract
In today's fast moving competitive markets, more and
more customers are requesting SPICE models to run
comprehensive circuit simulations. System engineers are
requiring increasingly accurate models for all types of
integrated circuits. Earlier SPICE models (1980) had to
minimize the number of nonlinear elements to minimize
simulation time, all at the cost of accuracy. Today's
models, thanks to the advancement of computing power,
can increase the number of nonlinear elements and
improve the accuracy of the models. The focus of this
Application Note is to provide a method for developing a
multi-stage SPICE model for low noise and low power
operational amplifiers. The model presented, started with
the work from Mark Alexander and Derek F. Bowers from
Analog Devices (Appnote AN-138, 1990) [1]. The final
model ended up with several key architectural changes
that were required to model today's low noise, and low
power precision amplifiers.
This application note provides a systematic process that
simplifies the understanding of how to build an accurate
straightforward SPICE model. This is accomplished by a
model architecture that processes the input signal
through several stages. The model parameters can easily
be calculated using a hand calculator or Excel
spreadsheet. The application note does not discuss the
process of using SPICE, and assumes the user is familiar
with this software.
The model presented in this application note is the
ISL28127 single-pole 10MHz amplifier. The model
enables the user to simulate important AC and DC
parameters of an amplifier. For higher speed amplifiers,
with multiple poles and zeros, reference AN-138 [1].
The AC parameters incorporated into the model are: 1/f
and flat-band noise, slew rate, CMRR, gain and phase.
The DC parameters are VOS, IOS, total supply current
and output voltage swing. The model uses typical
(+25°C) parameters given in the “Electrical
Specifications” table of the data sheet [2].
the mid point of the supplies, much like the actual
operation of an amplifier.
Discussed in this application note are the following
topics:
1. The different cascaded stages of the SPICE Model:
- Voltage Noise Stage
- Input Stage
- 1st Gain Stage
- 2nd Gain Stage
- Mid Supply Stage
- Supply Isolation Stage
- Common Mode Gain Stage
- Output Stage
2. How the VCCS stages works
3. How the VCCS output stage works
4. Systematic process for calculating model
parameters
5. Simulation results. Actual device vs simulation
6. Conclusions
Cascaded Stages
Figure 1 is the schematic for the SPICE model and
Figure 2 is the net list. Notice from the schematic, the
only circuitry resembling an amplifier is the Input Stage.
All other stages process the input signal with Voltage
Controlled Current Sources (VCCS) and Voltage
Controlled Voltage Sources (VCVS) along with diodes, DC
supplies, simple resistors, capacitors and inductors.
The circuit schematic is built from eight different
functional blocks. Each block is discussed in the following
sections, with details of the blocks’ functionality and
design considerations.
Introduction
The key to an accurate model is the input stage. The
closer you model the input stage to the actual amplifier,
the better your results. With only a few of the process
parameters of the input stage transistors or MOSFETs,
you can achieve very accurate AC representation of the
amplifiers performance.
Another advantage of this model's architecture is the
ability to model amplifiers with split supplies. There is no
ground reference in any of the signal processing blocks.
Instead, after the differential to single-ended conversion,
all internally generated node voltages are referenced to
April 19, 2010
AN1556.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
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Application Note 1556
.
V++
V++
R3
4.45k
CASCODE
4
5
Q4
CASCODE
2
D1
SUPERB
DX
-
+
V5
24
D12
C6
2pF
0.1V
DN
7
EOS
+
+
-
En
+ VOS
-
In+
VIN+
VMID
9
IEE
200E-6
R2
5E11
Vc
+
-
+
-
Q3
1E-9
377.4
C5
2.5pF
MIRROR
VCM
R17
25
8
1
IOS
5
3
Q1 Q2
R1
5E11
4
6
Q5
C4
2.5pF SUPERB
VIN-
VIN-
IEE1
96E-6
R4
4.45k
10E-6
V-VCM
VOLTAGE NOISE
INPUT STAGE
V++
V++
10
+
-
4
5
D2
DX
+
V1
- 1.86V
G3
13
+
-
R5
1
D4
DX
+
V3
- 1.86V
11
G5
R7
572.9E6
Vg
12
-
R8
572.9E6
G4
V2
1.86V
+
+
-
+
D3
DX
+
V-VCM
R6
1
G2
1ST GAIN STAGE
14
-
17
V4
1.86V
3.18E-3
R11
1
Vc
Vmid
Vc
Vmid
+
-
R9
1
C2
55.55pF
L1
R10
1
C3
55.55pF
R12
1
G6
18
VCM
D5
DX
Vg
+
-
G1
L2
3.18E-3
V--
2ND GAIN STAGE
MID SUPPLY REF
COMMON MODE GAIN STAGE
V++
E2
22
ISY
2.2mA
Vg
D6
DX
23
20
G7
+
V5
1.12V
V-
V6
21
+
DX
-
D7
R15
90
-
+
-
D9
DX
+
+
-
D8
DX
V+
1.12V
G8
+
+
E3
V-
V--
D10
DY
+
G9
+
-
D11
DY
VOUT
VOUT
R16
90
+
-
V+
G10
SUPPLY ISOLATION STAGE
OUTPUT STAGE
FIGURE 1. SPICE SCHEMATIC
2
AN1556.0
April 19, 2010
Application Note 1556
* source ISL28127_SPICEmodel
* Revision C, August 8th 2009 LaFontaine
* Model for Noise, supply currents, 150dB f=50Hz
CMRR, *128dB f=5Hz AOL
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
*
|
-input
*
|
|
+Vsupply
*
|
|
|
-Vsupply
*
|
|
|
|
output
*
|
|
|
|
|
.subckt ISL28127subckt Vin+ Vin-V+ V- VOUT
* source ISL28127_SPICEMODEL_0_0
*
*Voltage Noise
E_En
IN+ VIN+ 25 0 1
R_R17
25 0 377.4
D_D12
24 25 DN
V_V7
24 0 0.1
*
*Input Stage
I_IOS
IN+ VIN- DC 1e-9
C_C6
IN+ VIN- 2E-12
R_R1
VCM VIN- 5e11
R_R2
IN+ VCM 5e11
Q_Q1
2 VIN- 1 SuperB
Q_Q2
3 8 1 SuperB
Q_Q3
V-- 1 7 Mirror
Q_Q4
4 6 2 Cascode
Q_Q5
5 6 3 Cascode
R_R3
4 V++ 4.45e3
R_R4
5 V++ 4.45e3
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
D_D1
6 7 DX
I_IEE
1 V-- DC 200e-6
I_IEE1
V++ 6 DC 96e-6
V_VOS
9 IN+ 10e-6
E_EOS
8 9 VC VMID 1
*
*1st Gain Stage
G_G1
V++ 11 4 5 0.0487707
G_G2
V-- 11 4 5 0.0487707
R_R5
11 V++ 1
R_R6
V-- 11 1
D_D2
10 V++ DX
D_D3
V-- 12 DX
V_V1
10 11 1.86
V_V2
11 12 1.86
*
*2nd Gain Stage
G_G3
V++ VG 11 VMID 4.60767E-3
G_G4
V-- VG 11 VMID 4.60767E-3
R_R7
VG V++ 572.958E6
R_R8
V-- VG 572.958E6
C_C2
VG V++ 55.55e-12
C_C3
V-- VG 55.55e-12
D_D4
13 V++ DX
D_D5
V-- 14 DX
V_V3
13 VG 1.86
V_V4
VG 14 1.86
*
*Mid supply Ref
R_R9
VMID V++ 1
R_R10
V-- VMID 1
I_ISY
V+ V- DC 2.2E-3
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
*
*Common Mode Gain Stage with Zero
G_G5
V++ VC VCM VMID 31.6228e-9
G_G6
V-- VC VCM VMID 31.6228e-9
R_R11
VC 17 1
R_R12
18 VC 1
L_L1
17 V++ 3.183e-3
L_L2
18 V-- 3.183e-3
*
*Output Stage with Correction Current Sources
G_G7
VOUT V++ V++ VG 1.11e-2
G_G8
V-- VOUT VG V-- 1.11e-2
G_G9
22 V-- VOUT VG 1.11e-2
G_G10
23 V-- VG VOUT 1.11e-2
D_D6
VG 20 DX
D_D7
21 VG DX
D_D8
V++ 22 DX
D_D9
V++ 23 DX
D_D10
V-- 22 DY
D_D11
V-- 23 DY
V_V5
20 VOUT 1.12
V_V6
VOUT 21 1.12
R_R15
VOUT V++ 9E1
R_R16
V-- VOUT 9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28127subckt
FIGURE 2. SPICE NET LIST
3
AN1556.0
April 19, 2010
Application Note 1556
Voltage Noise Stage
The first stage in the model schematic, moving from left
to right, is the Voltage Noise Stage. This stage generates
the 1/f and flat-band noise. To generate a flat-band
voltage noise of a precision amplifier with only 4nV/√Hz,
all diodes and transistor model parameters kf (flicker
noise coefficient) and af (flicker noise exponent) need to
be set to zero. To lower the noise floor of the model to
single digit nanovolts, it may be necessary to reduce the
network's Johnson noise [3] by reducing the resistance
values where possible. Before reducing the resistor
values, the process is to calculate the standard resistor
values and complete all simulation tweaks. Once this is
done, the last step is to tweak the Voltage Noise Stage
by dropping the resistor values to 1Ω while recalculating
the gm and time constants of the stages to maintain the
same transfer function for that stage. Resistors R5, R6,
and R9 thru R12 are resistors that can easily be set to
1Ω. For amplifiers with noise levels in the flat-band range
of 100's of nV, reducing the network's Johnson noise may
not be necessary. Initial noise simulations will tell you if
this step is necessary. With the model's flat-band noise
set below the amplifier's noise floor, the user can now
adjust the 1/f and flat-band noise with adjustments to
DN, R17 and V5.
Input Stage
The ISL28127 was selected for this application note to
illustrate the level of accuracy obtainable by modeling an
amplifiers exact input structure. The Input Stage of the
ISL28127 consists of five bipolar transistors that model
the actual device configuration, as shown in Figure 1.
This however will not be the case for most SPICE models.
Figure 3 and Figure 4 show typical NMOS and PMOS
input stages respectively.
FIGURE 4. TYPICAL PMOS INPUT STAGE
The Input Stage can be configured with the same type of
input device (NPN, PNP, P and N channel MOSFETs or
J-FETS) as the physical op amp being modeled. The
Input Stage includes a current supply to model IOS, a
voltage supply to model VOS and a VCVS along with R1
and R2 to account for CMRR of the device.
1st Gain Stage
The purpose of the 1st Gain Stage is to set the combined
gain of the Input Stage and the 1st Gain Stage to 1.
Setting the combined gains to 1 simplifies the calculation
to determine the slew-rate limiting components in the
2nd Gain Stage. Diodes D2 and D3 along with DC
supplies V1 and V2 might be unnecessary, because their
function is to clamp the output voltage swing and were
going to do that in the next stage. We left them in
because they're free. DC supply voltages V1 and V2
should be slightly larger than V3 and V4 in the 2nd Gain
Stage. The thought is to limit most of the signal
amplitude in the 1st stage and do the final amplitude
tweak in the 2nd stage.
2nd Gain Stage
The 2nd Gain Stage is where the AVOL, bandwidth and
slew-rate of the amplifier are set using G3, G4, R7, R8,
C2 and C3. Diodes D4 and D5 along with DC supplies V3
and V4 are used to set the maximum output voltage
swing.
Mid Supply Reference Stage
FIGURE 3. TYPICAL NMOS INPUT STAGE
4
The Mid Supply Reference Stage is simply two equal
resistors R9 and R10. These resistors are used to
generate a mid supply reference voltage. The resistor
values are set to 1Ω to reduce the Johnson voltage noise
of the model. The high current that flows through these
resistors is transparent to the model user because of the
Supply Isolation Stage, more free stuff.
AN1556.0
April 19, 2010
Application Note 1556
The Common Mode Gain Stage consists of two VCCS's
that drive two equal resistors in series with an inductor
connected to the supply rails. The inductors simulate the
typical fall-off of CMRR that most amplifiers exhibit as the
input frequency is increased. The current sources are
controlled by the input common mode voltage
(generated by resistors R1 and R2 in the Input Stage)
relative to the mid supply voltage. Each control source
has a gm equal to the reciprocal of the associated
resistor value divided by the CMRR of the amplifier at DC
(Equation 10). The inductors add a zero to the
common-mode gain, which is equivalent to adding a pole
to the CMRR. The common-mode voltage, after being
scaled and appropriately frequency shaped, is then added
back into the Input Stage via the VCVS called EOS.
How the VCCS Stage Works
When the voltage at the inputs to G1 and G2 (Figure 5)
increases, the resultant voltage at the Midpoint will rise.
Likewise, when the voltage at the inputs decrease, the
midpoint voltage will decrease. If the gm of the stage is
equal to the reciprocal of the parallel resistor, the stage
has a positive unity gain.
V++
G1
V +-
Supply Isolation Stage
Output Stage
The operation of the Output Stage is not entirely obvious.
The amplifier's output signal, after receiving all the
appropriate frequency shaping, appears as a voltage
referenced to mid supply at the inputs to G7 and G8. G7
and G8 drive two equal resistors connected to the supply
rails and act as active current generators. Both G7 and
G8 generate just enough current to provide the desired
voltage drop across its parallel resistor. Refer to the
section “How the VCCS Output Stage Works” on page 6.
When there is no load on the output, the model draws no
current from either supply rail, thus behaving like an
amplifier output. Simulating the right output resistance
means the DC open loop gain will be properly reduced as
the amplifier is loaded.
When a load is applied to the output, equal currents will
be pulled from both supply rails. To make the output
behave like a real amplifier, G9 and G10 force the
appropriate amount of current to make it appear as if all
the current is being sourced or sunk from the correct
supply.
+
G2
MIDPOINT VOLTAGE
+
R6
1Ω
12
V--
R5
1Ω
INPUT VOLTAGE GOES UP
• CURRENT GOES UP
• NET CURRENT THROUGH R5
DROPS
• MIDPOINT VOLTAGE GOES UP
11
-
+
-
The Supply Isolation Stage consists of two VCVS's and a
current source. This stage enables the user to program
the total supply current of the amplifier with just one
entry in the node list. It also isolates the internal supply
currents from the external supply current seen by the
user. This enables the model to provide the correct
supply current for low power amplifiers with low voltage
noise.
10
+
-
INPUT VOLTAGE GOES UP
• CURRENT GOES UP
• NET CURRENT THROUGH R6
GOES UP
• MIDPOINT VOLTAGE GOES UP
FIGURE 5. HOW THE VCCS WORKS
The single-ended equivalent circuit of Figure 5 is shown
in Figure 6. The circuit shown in Figure 6 is sometimes
easier to help visualize the signal flow through the
stages.
MIDPOINT VOLTAGE
+
V
+
-
+
-
Common Mode Gain Stage
-
R#
1Ω
12
FIGURE 6. SINGLE-ENDED EQUIVALENT CIRCUIT TO FIGURE 5
Output short circuit protection is provided by diodes D6
and D7 along with DC supplies V5 and V6. Under fault
conditions, the output voltage is clamped to the previous
frequency shaping stage. The output short circuit current
limit is determined by adjusting the value of V5 and V6.
5
AN1556.0
April 19, 2010
Application Note 1556
How the VCCS Output Stage
Works
Figure 7 explains how the Output Stage works for a
steady input voltage, an increasing input voltage and a
decreasing input voltage.
G7
+
+
VOUT
+
-
V
+
G8
-
R15
90Ω
VOUT
R16
90Ω
INPUT VOLTAGE CONSTANT
• VOLTAGE DROP ACROSS
RESISTORS EQUALLY
OPPOSE EACH OTHER
• OUTPUT VOLTAGE STAYS
AT MID SUPPLY
INPUT VOLTAGE GOES UP
• CURRENT REDUCES IN R15
• CURRENT INCREASES IN
R16
• MIDPOINT VOLTAGE GOES
UP
+
-
INPUT VOLTAGE GOES UP
• CURRENT INCREASES IN
R15
• CURRENT REDUCES IN R16
• MIDPOINT VOLTAGE GOES
DOWN
OUTPUT STAGE
FIGURE 7. HOW THE VCCS OUTPUT STAGE WORKS
A Systematic Process for
Calculating Model Parameters
Table 1 is a list of the amplifiers parameters required to
calculate the model parameters. The values shown in the
table are for the ISL28127 model.
Once the values in Table 1 are determined, the model
parameters given in Equations 1 through 15 can be
calculated and put into the SPICE schematic.
TABLE 1. DEVICE PARAMETERS
PARAMETER
VALUE UNITS
COMMENTS
TABLE 1. DEVICE PARAMETERS (Continued)
PARAMETER
VALUE UNITS
COMMENTS
Fcm
50
Hz
Common mode pole
Rout
45
Ω
Isc
45
mA
Voh
13.7
V
Vout max
Vol
-13.7
V
Vout max
The following equations will determine the model
parameters for the SPICE schematic. Putting them into
an Excel spreadsheet will enable the user to change
critical specs and quickly see the effect on the op amp
performance. The calculations are given for each stage of
the model.
Input Stage and Gain Stage Calculations
The process to set the Slew Rate and unity gain
bandwidth, for a single pole stage, is accomplished in
3 steps:
• Determine the Capacitor value knowing IEE and the
Slew Rate (Equation 1). This effectively sets the
maximum frequency for the single pole RC network,
and therefore the unity gain bandwidth.
• Determine the Resistor value knowing the dominant
pole frequency (Equation 2). This effectively sets the
break point for the RC network.
• Determine the gm of the VCCS knowing the desired
AVOL and R value of the RC network.
STEP 1
IEE
C 2 = C 3 = ---------------------------SlewRate
(EQ. 1)
–6
200 × 10
C 2 = C 3 = ---------------------------- = 55.55pF
–6
3.6 × 10
IEE is the value of the current source feeding the input
differential pair (reference Figure 1). Under Slew Rate
conditions, instantaneously all of this current is flowing
through one side of the differential pair (until the
feedback loop catches up). Equation 1 is used to
calculate the capacitor value to set the Slew Rate of the
model. Equation 1 is basically IC = Cdv/dt , with Slew
Rate equal to dv/dt and IEE equal to IC.
Quiescent Supply 2.2E-3
Current
A
VCC
15
V
VEE
-15
V
IEE
200E-6
A
3.6E6
V/sec
5
Hz
Dominant Pole (Figure 8)
Equation 2 calculates the value of the resistor for a set
capacitor value of C2,3 and dominant pole frequency fp1.
AVOL
2640E3
V/V
128.43dB
STEP 2
VOS
1E-5
V
IOS
1E-9
A
25
C
Vt
0.0257
V
Differential Input
Resistance
5E-11
Ω
CMRR
3.16E7
V/V
Slew Rate
Fp1
Temperature
6
Differential input current
source
1
R 7 = R 8 = ---------------------------2πf p1 C 2 ,3
(EQ. 2)
1
R 7 = R 8 = -------------------------------------------- = 572.958MΩ
2π ( 5 ) ( 55.55pF )
Where fp1 = dominant pole (reference Figure 8).
Default value if unknown
150dB
AN1556.0
April 19, 2010
Application Note 1556
Figure 8 shows the relationship of the unity gain
bandwidth to the dominant pole frequency and AVOL.
Equations 7 and 8 are used to set V1 through V4
voltages for the maximum output voltage swing. The
output voltage will be clamped at a voltage equal to
V++ - (V1,3 + VD2,D4) for positive input voltage swings
and V-- + (V2,4 + VD3,D5) for negative input voltage
swings.
⎛ 2I EE⎞
V 1 ,3 = V CC – ( V OUTMAX ) + V T Ln ⎜ -------------⎟
⎝ IS ⎠
(EQ. 7)
⎛ 2I EE⎞
V 2 ,4 = ( – V OUTMAX ) – V EE + V T Ln ⎜ -------------⎟
⎝ IS ⎠
(EQ. 8)
Where VT = 0.02585V at T = +25°C.
IS = 1 x 10-12 A (for both diodes).
You can substitute some data sheet parameters directly
into the model. These parameters are:
FIGURE 8. AVOL vs FREQUENCY
EOS = Input Offset Voltage (DC component only).
IOS = Input Offset Current.
STEP 3
AVOL
G 3 = G 4 = ----------------R 7 ,8
(EQ. 3)
6
–3
2640 ×10
G 3 = G 4 = ---------------------------------- = 4.6 ×10
6
572.958 ×10
–6
(EQ. 4)
During Slew Rate limit, the current through either
resistor R3 or R4 will be clamped by the 200 x 10-6
current sink. Which resistor has the current depends
upon the polarity of the input voltage (positive R4,
negative R3). This current will flow through the 4.45kΩ
resistor resulting in a voltage drop of (200 x 10-6) x
(4.45kΩ) = 890mV. This voltage drop appears at the
input to G1 and G2. In order to set the combined gain of
the input stage and the 1st stage to one, we need to
calculate the gm of G1 and G2 so their output voltage
equals 43.4mV (Equation 4) when 890mV is at their
inputs. If we set the resistor value in parallel with the
outputs of G1 and G2 to 1Ω, then the voltage will equal
the current and we can write Equation 5 to solve for the
gm of G1 and G2.
3
–3
I
43.4 × 10
G 1 = G 2 ⇒ g m = ---- = ---------------------------- = 48.77 × 10
–3
V
890 × 10
(EQ. 5)
If the design review document is not available, set R3
and R4 to 1Ω for the calculation of the voltage appearing
at the inputs to G1 and G2.
R 3 = R 4 = 4.45kΩ
( from design review )
7
Common-Mode Gain Stage
R 11 = R 12 = 1MΩ
Once again, the 1st Gain Stage is used to set the
combined gain of the input stage and the 1st Gain Stage
to 1. The voltage required at the input of G3 and G4 to
cause 200 x 10-6 to flow through R7 and R8 is calculated
in Equation 4.
200 ×10
I
I
g m = ---- ⇒ V G
= ------- = ------------------------- = 43.4mV
–3
V
3,4 g m
4.6 ×10
Cdiff = Input differential capacitance (not shown in this
model).
(EQ. 9)
1
G 7 = G 8 = ------------------------------------------R 11 ,12 × CMRR
(EQ. 10)
R 11 ,12
L 1 = L 2 = -------------------------2πfp ( cm )
(EQ. 11)
Where fcm is common-mode pole from the CMRR vs
Frequency curve (similar to the dominant frequency pole
shown in Figure 8).
Output Stage
Setting the gm equal to the reciprocal of 2ROUT results in
unity gain through G7-G10. The value of 2ROUT results
from the need to have the output currents appear to be
coming from one supply rail.
1
G 7 = G 8 = G 9 = G 10 = -------------------2R OUT
(EQ. 12)
R 15 = R 16 = 2 × R OUT
(EQ. 13)
⎛ 20 × 10 6⎞
V 3 = I SC ( 0.764 )R OUT – V T Ln ⎜ ----------------------⎟
IS ⎠
⎝
(EQ. 14)
⎛ 20 × 10 6⎞
V 4 = I SC ( 0.764 )R OUT – V T Ln ⎜ ----------------------⎟
IS ⎠
⎝
(EQ. 15)
Simulation Results
Figures 9 through 14 compare actual device performance
to simulation results. For a complete set of comparisons,
reference the data sheet [2].
(EQ. 6)
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Application Note 1556
Characterization vs Simulation Results
100
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
100
VS = ±19V
AV = 1
10
1
0.1
1
10
100
1k
10k
10
V(INOISE)
1
0.1
100k
1
10
FIGURE 9. CHARACTERIZED INPUT NOISE VOLTAGE
Rg = 100, Rf = 100k
Rg = 10k, Rf = 100k
10
0
100k
10k
100k
1M
FREQUENCY (Hz)
10M
11
9
Rf = Rg = 1k
7
5
1k
10k
20
AV = 10
Rg = 10k, Rf = 100k
Rf = Rg = 100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 13. CHARACTERIZED CLOSED LOOP GAIN vs
Rf/Rg
8
AV = 1
Rg = OPEN, Rf = 0
1k
10k
15
Rf = Rg = 10k
3 VS = ±15V
RL = 10k
1
CL = 3.5pF
-1 A = +2
V
-3 VOUT = 100mVP-P
30
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 12. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
Rf = Rg = 100k
13
Rg = 1k, Rf = 100k
-10
100
100M
FIGURE 11. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
15
40
0
Rg = OPEN, Rf = 0
1k
Rg = 100, Rf = 100k
AV = 100
10
AV = 1
-10
100
NORMALIZED GAIN (dB)
GAIN (dB)
20
VS = ±15V
CL = 3.5pF
RL = INF
VOUT = 100mVP-P
AV = 10
AV = 1000
50
Rf = Rg = 100k
13
NORMALIZED GAIN (dB)
GAIN (dB)
60
Rg = 1k, Rf = 100k
AV = 100
30
-5
10k
70
AV = 1000
50
40
1k
FIGURE 10. SIMULATED INPUT NOISE VOLTAGE
70
60
100
FREQUENCY (Hz)
FREQUENCY (Hz)
11
Rf = Rg = 10k
9
7
Rf = Rg = 1k
5
3 VS = ±15V
RL = 10k
1
CL = 3.5pF
-1 A = +2
V
-3 VOUT = 100mVP-P
-5
1k
10k
Rf = Rg = 100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 14. SIMULATED CLOSED LOOP GAIN vs Rf/Rg
AN1556.0
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Application Note 1556
Characterization vs Simulation Results (Continued)
2
2
1
RL = 1k
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 10k
0
-1
RL = 499
-2
RL = 100
VS = ±15V
-3
RL = 49.9
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
-4
-5
1k
10k
100k
1M
FREQUENCY (Hz)
10M
RL = 100
VS = ±15V
-3
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
-4
10k
RL = 49.9
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 16. SIMULATED CLOSED LOOP GAIN vs RL
5
4
3
CL = 100pF
2
CL = 25.5pF
1
0
-1
CL = 3.5pF
-2
1k
10k
100k
1M
FREQUENCY (Hz)
5
4
CL = 1000pF
3
2
10M
0
CL = 25.5pF
-1
-3
100M
CL = 100pF
CL = 220pF
1
-2
FIGURE 17. CHARACTERIZED CLOSED LOOP GAIN vs CL
CL = 3.5pF
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 18. SIMULATED CLOSED LOOP GAIN vs CL
6
5
6
5
4
4
2
1
0
LARGE SIGNAL (V)
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0, Rg = INF
VOUT = 10VP-P
3
1
-2
-3
RL = 2k
RL = 10k
-4
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0, Rg = INF
VOUT = 10VP-P
3
2
1
0
1
-2
-3
RL = 10k
-4
-5
-6
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
6
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 499
-2
7
VS = ±15V
RL = 10k
AV = +1
CL = 1000pF
VOUT = 100mVP-P
CL = 220pF
6
LARGE SIGNAL (V)
RL = 1k
-1
7
-3
RL = 10k
0
-5
1k
100M
FIGURE 15. CHARACTERIZED CLOSED LOOP GAIN vs RL
1
-5
0
5
10
15
TIME (µs)
20
25
30
FIGURE 19. CHARACTERIZED LARGE SIGNAL 10V STEP
RESPONSE
-6
0
5
10
15
TIME (µs)
20
25
30
FIGURE 20. SIMULATED LARGE SIGNAL 10V STEP
RESPONSE
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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Application Note 1556
200
180
160
140
PHASE
120
100
80
60
40
GAIN
20
0
-20
-40 RL = 10k
-60 CL = 10pF
-80 SIMULATION
-100
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
150
PHASE
100
50
GAIN
0
RL = 10k
-50 CL = 10pF
MODEL VOS SET TO
ZERO FOR THIS TEST
-100
0.1Hz
10Hz
1.0k
100k
10M
FREQUENCY (Hz)
FIGURE 22. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
150
VS = ±5V
VS = ±2.25V
100
CMRR (dB)
CMRR (dB)
FIGURE 21. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
200
OPEN LOOP GAIN (dB)/PHASE (°)
OPEN LOOP GAIN (dB)/PHASE (°)
Characterization vs Simulation Results (Continued)
VS = ±15V
RL = INF
CL = 5.25pF
AV = +1
VCM = 1VP-P
100
50
0
1k
10k
100k
1M
10M
GENERATED USING FULL
MODEL. CMRR DELTA INPUT
BASE VOLTAGE/VCM
INPUT VOLTAGE
-50
10m
1.0Hz
100Hz 10k
FREQUENCY (Hz)
FIGURE 23. CHARACTERIZED CMRR vs FREQUENCY
1.0M
100M
10G 1.0T
FREQUENCY (Hz)
FIGURE 24. SIMULATED CMRR vs FREQUENCY
Conclusions
References
This Application Note has presented a method for
building an accurate straightforward SPICE model for
today's low noise and low power precision amplifiers. The
extremely close simulation to actual part comparison
results was achieved by taking advantage of today's
improved computing power and modeling 5 bipolar
transistors with their specific model parameters for each
type of transistor. Improvements to previous models
include the ability to model single digit nanovolt noise
parameters and very low total system supply currents for
micro-powered amplifiers.
[1] Mark Alexander and Derek F. Bowers, Application
Note AN-138, “SPICE-Compatible Op Amp MacroModels”, Analog Devices.
[2] ISL28127, ISL28227 FN6633 Intersil data sheet
http://www.intersil.com/data/fn/fn6633.pdf.
[3] Derek F. Bowers, IEEE 1989, “Minimizing Noise in
Analog Bipolar Circuit Design”, Precision
Monolithics, Inc.
Acknowledgment
I would like to thank Oscar Mansilla for all his help with
the SPICE software, and especially his help with
generating sub-circuits from a node list and building my
own libraries in SPICE.
I would also like to thank Bob Pospisil for his technical
expertise with op amps and helping me solve various
problems along the way.
10
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