BS84B06A-3v120.pdf

Touch A/D 8-Bit Flash MCU
BS84B06A-3
Revision: V1.20
Date: ������������
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Table of Contents
Features............................................................................................................. 6
CPU Features.......................................................................................................................... 6
Peripheral Features.................................................................................................................. 6
General Description.......................................................................................... 7
Block Diagram................................................................................................... 7
Pin Assignment................................................................................................. 8
Pin Descriptions............................................................................................... 9
Absolute Maximum Ratings........................................................................... 10
D.C. Characteristics........................................................................................ 10
A.C. Characteristics........................................................................................ 12
Sensor Oscillator Electrical Characteristics................................................ 13
A/D Converter Electrical Characteristics...................................................... 17
Power-on Reset Characteristics ................................................................... 17
System Architecture....................................................................................... 18
Clocking and Pipelining.......................................................................................................... 18
Program Counter.................................................................................................................... 19
Stack...................................................................................................................................... 20
Arithmetic and Logic Unit – ALU............................................................................................ 20
Flash Program Memory.................................................................................. 21
Structure................................................................................................................................. 21
Special Vectors...................................................................................................................... 21
Look-up Table......................................................................................................................... 21
Table Program Example......................................................................................................... 22
In Circuit Programming.......................................................................................................... 23
On-Chip Debug Support – OCDS.......................................................................................... 24
RAM Data Memory.......................................................................................... 24
Structure................................................................................................................................. 24
Special Function Register Description......................................................... 25
Indirect Addressing Registers – IAR0, IAR1.......................................................................... 25
Memory Pointers – MP0, MP1............................................................................................... 27
Bank Pointer – BP.................................................................................................................. 28
Accumulator – ACC................................................................................................................ 28
Program Counter Low Register – PCL................................................................................... 28
Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 28
Status Register – STATUS..................................................................................................... 29
Rev. 1.20
2
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
EEPROM Data Memory................................................................................... 31
EEPROM Data Memory Structure......................................................................................... 31
EEPROM Registers............................................................................................................... 31
Reading Data from the EEPROM ......................................................................................... 33
Writing Data to the EEPROM................................................................................................. 33
Write Protection...................................................................................................................... 33
EEPROM Interrupt................................................................................................................. 33
Programming Considerations................................................................................................. 34
Oscillator......................................................................................................... 35
Oscillator Overview................................................................................................................ 35
System Clock Configurations................................................................................................. 35
Internal RC Oscillator – HIRC................................................................................................ 36
Internal 32kHz Oscillator – LIRC............................................................................................ 36
Operating Modes and System Clocks.......................................................... 36
System Clocks....................................................................................................................... 36
System Operation Modes....................................................................................................... 37
Control Register..................................................................................................................... 39
Operating Mode Switching .................................................................................................... 40
NORMAL Mode to SLOW Mode Switching............................................................................ 41
SLOW Mode to NORMAL Mode Switching ........................................................................... 41
Entering the SLEEP Mode..................................................................................................... 43
Entering the IDLE0 Mode....................................................................................................... 43
Entering the IDLE1 Mode....................................................................................................... 43
Standby Current Considerations............................................................................................ 44
Wake-up................................................................................................................................. 44
Watchdog Timer.............................................................................................. 45
Watchdog Timer Clock Source............................................................................................... 45
Watchdog Timer Control Register.......................................................................................... 45
Watchdog Timer Operation.................................................................................................... 46
Reset and Initialisation................................................................................... 47
Reset Functions..................................................................................................................... 47
Reset Initial Conditions.......................................................................................................... 49
Input/Output Ports.......................................................................................... 52
I/O Register List..................................................................................................................... 52
Pull-high Resistors................................................................................................................. 52
Port A Wake-up...................................................................................................................... 53
I/O Port Control Registers...................................................................................................... 54
Source Current Selection....................................................................................................... 55
I/O Pin Structures................................................................................................................... 56
Programming Considerations................................................................................................. 57
Rev. 1.20
3
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Timer/Event Counter...................................................................................... 57
Configuring the Timer/Event Counter Input Clock Source..................................................... 57
Timer Register – TMR............................................................................................................ 58
Timer Control Register – TMRC............................................................................................. 58
Timer Operation..................................................................................................................... 59
Prescaler................................................................................................................................ 59
Programming Considerations................................................................................................. 59
Analog to Digital Converter........................................................................... 60
A/D Overview......................................................................................................................... 60
A/D Converter Register Description....................................................................................... 60
A/D Converter Data Registers – ADRL, ADRH...................................................................... 61
A/D Converter Control Registers – ADCR0, ADCR1, ACERL................................................ 61
A/D Operation........................................................................................................................ 64
A/D Input Pins........................................................................................................................ 65
Summary of A/D Conversion Steps........................................................................................ 66
Programming Considerations................................................................................................. 67
A/D Transfer Function............................................................................................................ 67
A/D Programming Examples.................................................................................................. 68
Touch Key Function....................................................................................... 70
Touch Key Structure............................................................................................................... 70
Touch Key Register Definition................................................................................................ 71
Touch Key Operation.............................................................................................................. 76
Touch Key Interrupt................................................................................................................ 77
Programming Considerations................................................................................................. 77
Serial Interface Module – SIM ....................................................................... 78
SPI Interface ......................................................................................................................... 78
SPI Interface Operation ......................................................................................................... 78
SPI Registers......................................................................................................................... 79
SPI Communication .............................................................................................................. 82
I2C Interface .......................................................................................................................... 84
I2C Interface Operation .......................................................................................................... 84
I2C Registers.......................................................................................................................... 85
I2C Bus Communication......................................................................................................... 89
I2C Bus Start Signal ............................................................................................................... 89
Slave Address ....................................................................................................................... 90
I2C Bus Read/Write Signal .................................................................................................... 90
I2C Bus Slave Address Acknowledge Signal ......................................................................... 90
I2C Bus Data and Acknowledge Signal ................................................................................. 90
I2C Time-out Control............................................................................................................... 92
Rev. 1.20
4
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Interrupts......................................................................................................... 93
Interrupt Registers.................................................................................................................. 93
Interrupt Operation................................................................................................................. 95
External Interrupt.................................................................................................................... 96
Time Base Interrupt................................................................................................................ 96
Timer/Event Counter Interrupt................................................................................................ 97
EEPROM Interrupt................................................................................................................. 97
Touch Key Interrupt................................................................................................................ 98
SIM Interrupt.......................................................................................................................... 98
A/D Converter Interrupt.......................................................................................................... 98
Interrupt Wake-up Function................................................................................................... 98
Programming Considerations................................................................................................. 99
Application Circuits...................................................................................... 100
Instruction Set............................................................................................... 101
Introduction.......................................................................................................................... 101
Instruction Timing................................................................................................................. 101
Moving and Transferring Data.............................................................................................. 101
Arithmetic Operations........................................................................................................... 101
Logical and Rotate Operation.............................................................................................. 102
Branches and Control Transfer............................................................................................ 102
Bit Operations...................................................................................................................... 102
Table Read Operations........................................................................................................ 102
Other Operations.................................................................................................................. 102
Instruction Set Summary............................................................................. 103
Table Conventions................................................................................................................ 103
Instruction Definition.................................................................................... 105
Package Information.....................................................................................114
16-pin NSOP (150mil) Outline Dimensions...........................................................................115
20-pin DIP (300mil) Outline Dimensions...............................................................................116
20-pin SOP (300mil) Outline Dimensions.............................................................................118
Rev. 1.20
5
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Features
CPU Features
• Operating Voltage
♦♦
fSYS = 8MHz: 2.7~5.5V
♦♦
fSYS = 12MHz: 2.7~.5.5V
♦♦
fSYS = 16MHz: 4.5V~5.5V
• Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Fully integrated low and high speed internal oscillators
♦♦
Low Speed -- 32kHz
♦♦
High speed -- 8MHz, 12MHz, 16MHz
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• Up to 6-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: 3K×16
• RAM Data Memory: 288×8
• EEPROM Memory: 64×8
• Watchdog Timer function
• Up to 18 bidirectional I/O lines
• Single external interrupt input shared with I/O pin
• Single 8-bit Timer/Event Counter
• Single Time-Base function for generation of fixed time interrupt signals
• Multi-channel 12-bit resolution A/D converter
• I2C and SPI interfaces
• PMOS Source current adjustable
• Low voltage reset function
• Fully integrated 6 touch key functions -- require no external components
• Package types: 16-pin NSOP and 20-pin DIP/SOP
Rev. 1.20
6
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
General Description
This device is a Flash Memory A/D type 8-bit high performance RISC architecture microcontroller
with fully integrated touch key functions. With all touch key functions provided internally and with
the convenience of Flash Memory multi-programming features, this device has all the features
to offer designers a reliable and easy means of implementing Touch Keyes within their products
applications.
Analog feature includes a multi-channel 12-bit A/D converter. Protective features such as an internal
Watchdog Timer and Low Voltage Reset coupled with excellent noise immunity and ESD protection
ensure that reliable operation is maintained in hostile electrical environments.
The touch key functions are fully integrated completely eliminating the need for external
components. In addition to the flash program memory, other memory includes an area of RAM Data
Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
The device includes fully integrated low and high speed oscillators which require no external
components for their implementation. The ability to operate and switch dynamically between a range
of operating modes using different clock sources gives users the ability to optimise microcontroller
operation and minimise power consumption. Easy communication with the outside world is provided
using the internal I2C and SPI interfaces, while the inclusion of flexible I/O programming features,
Timer/Event Counter and many other features further enhance device functionality and flexibility.
This touch key device will find excellent use in a huge range of modern Touch Key product
applications such as instrumentation, household appliances, electronically controlled tools to name
but a few.
Block Diagram
Watchdog
Timer
Flash/EEPRO�
Programming Circuitr�
EEPRO�
Data
�emor�
Flash
Program
�emor�
Low
Voltage
Reset
RA�
Data
�emor�
Reset
Circuit
8-bit
RISC
�CU
Core
Interrupt
Controller
Internal RC
Oscillators
12-bit A/D
Converter
SI�
I/O
Rev. 1.20
Timer
Base
8-bit
Timer
7
Touch Ke�s
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Pin Assignment
PB0/Ke�1
1
16
PA0/SDI/SDA/ICPDA/OCDSDA
PB1/Ke�2
2
1�
PA1/SDO
PB2/Ke��
�
14
PA2/SCK/SCL/ICPCK/OCDSCK
PB�/Ke�4
PB4/Ke��
4
1�
�
12
PA�/SCS
PA4/INT
PB�/Ke�6
6
11
PA7
VSS
7
10
PD1/AN1
VDD
8
9
PD0/AN0/VREF
BS84B06A-3/BS84BV06A-3
16 NSOP-A
PB0/Ke�1
1
20
PB1/Ke�2
2
19
PA0/SDI/SDA/ICPDA/OCDSDA
PA1/SDO
PB2/Ke��
�
18
PB�/Ke�4
PB4/Ke��
4
17
�
16
PB�/Ke�6
6
1�
PA4/INT
PA7
PB6
PB7
7
14
PD�/AN�
8
1�
PD2/AN2
VSS
9
12
PD1/AN1
VDD
10
11
PD0/AN0/VREF
PA2/SCK/SCL/ICPCK/OCDSCK
PA�/SCS
BS84B06A-3/BS84BV06A-3
20 DIP-A/SOP-A
Note: The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the
BS84BV06A-3 device which is the OCDS EV chip for the BS84B06A-3 device.
Rev. 1.20
8
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Pin Descriptions
The function of each pin is listed in the following table, however the details behind how each pin is
configured is contained in other sections of the datasheet.
Pin Name
PA0/SDI/SDA/
ICPDA/OCDSDA
PA1/SDO
PA2/SCK/SCL/
ICPCK/OCDSCK
Function
OP
I/T
O/T
PA0
PAWU
PAPU
ST
CMOS
Description
General purpose I/O. Register enabled pull-up and
wake-up.
SDI
SIMC0
ST
—
SDA
SIMC0
ST
NMOS
SPI data input
I2C data
ICPDA
—
ST
CMOS
ICP data/address
OCDSDA
—
ST
CMOS
OCDS data/address, only for EV chip
PA1
PAWU
PAPU
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SDO
SIMC0
—
CMOS
SPI data output
PA2
PAWU
PAPU
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCK
SIMC0
ST
CMOS
SPI serial clock
SCL
SIMC0
ST
NMOS
I2C clock
ICPCK
—
ST
—
ICP clock pin
OCDSCK
—
ST
—
OCDS clock pin, only for EV chip
PA3
PAWU
PAPU
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCS
SIMC0/
SIMC2
ST
CMOS
SPI slave select
PA4
PAWU
PAPU
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT
INTEG
ST
—
PA7
PAWU
PAPU
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
PB0~PB3
PBPU
ST
CMOS
General purpose I/O. Register enabled pull-up.
KEY1~
KEY4
TKM0C1
NSI
—
PB4~PB5
PBPU
ST
CMOS
KEY5~
KEY6
TKM1C1
NSI
—
PB6~PB7
PBPU
ST
CMOS
General purpose I/O. Register enabled pull-up.
PD0
PDPU
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN0
ACERL
AN
—
A/D Converter input
VREF
ADCR1
AN
—
A/D Converter reference input
PD1~PD3
PDPU
ST
CMOS
AN1~AN3
ACERL
AN
—
A/D Converter input
VDD
VDD
—
PWR
—
Power supply
VSS
VSS
—
PWR
—
Ground
PA3/SCS
PA4/INT
PA7
PB0/KEY1~
PB3/KEY4
PB4/KEY5~
PB5/KEY6
PB6, PB7
PD0/AN0/VREF
PD1/AN1~
PD3/AN3
External interrupt
Touch key inputs
General purpose I/O. Register enabled pull-up.
Touch key inputs
General purpose I/O. Register enabled pull-up.
Legend: I/T: Input type
O/T: Output type
OP: Optional by register selection
AN: Analog Signal
PWR: Power
ST: Schmitt Trigger input
CMOS: CMOS output
NMOS: NMOS output
NSI: Non-standard input
Rev. 1.20
9
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
IOL Total...................................................................................................................................... 80mA
IOH Total.....................................................................................................................................-80mA
Total Power Dissipation.......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.
D.C. Characteristics
Ta=25˚C
Symbol
VDD
Parameter
Operating Voltage
(HIRC)
Test Conditions
─
3V
Operating Current (Normal)
(HIRC OSC, fSYS=fH,
fS=fSUB=fLIRC)
5V
3V
5V
3V
5V
3V
IDD
Operating Current (Normal)
(HIRC OSC, fSYS=fL,
fS=fSUB=fLIRC)
5V
3V
5V
Operating Current (slow)
(LIRC OSC, fSYS=fL=fLIRC,
fS=fSUB=fLIRC)
Rev. 1.20
Min.
Typ.
Max.
Unit
fSYS=8MHz
2.7
─
5.5
V
fSYS=12MHz
2.7
─
5.5
V
fSYS=16MHz
4.5
─
5.5
V
No load, fH=8MHz, A/D Converter off,
WDT enable, LVR enable
─
1.2
1.8
mA
─
2.2
3.3
mA
No load, fH=12MHz, A/D Converter
off, WDT enable, LVR enable
─
1.6
2.4
mA
─
3.3
5.0
mA
No load, fH=16MHz, A/D Converter
off, WDT enable, LVR enable
─
2.0
3.0
mA
─
4.0
6.0
mA
No load, fH=12MHz, fL=fH/2,
A/D Converter off, WDT enable,
LVR enable
─
1.2
2.0
mA
─
2.2
3.3
mA
No load, fH=12MHz, fL=fH/64,
A/D Converter off, WDT enable,
LVR enable
─
0.8
1.2
mA
─
1.5
2.3
mA
No load, A/D Converter off,
WDT enable, LVR enable
─
50
100
μA
─
70
150
μA
VDD
3V
5V
Conditions
10
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
─
0.9
1.4
mA
─
1.4
2.1
mA
─
1.4
3.0
μA
Standby Current (Idle)
(HIRC OSC, fSYS=fH,
fS=fSUB=fLIRC)
3V
Standby Current (Idle)
(HIRC OSC, fSYS=off,
fS=fSUB=fLIRC)
3V
5V
─
2.7
5.0
μA
Standby Current (Idle)
(HIRC OSC, fSYS=fL,
fS=fSUB=fLIRC)
3V
─
0.7
1.1
mA
─
1.4
2.1
mA
Standby Current (Idle)
(HIRC OSC, fSYS=off,
fS=fSUB=fLIRC)
3V
─
1.3
3.0
μA
5V
─
2.3
5.0
μA
Standby Current (Idle)
(LIRC OSC, fSYS=fL=fLIRC,
fS=fSUB=fLIRC)
3V
─
1.9
4.0
μA
─
3.3
7.0
μA
Standby Current (Idle)
(LIRC OSC, fSYS=off,
fS=fSUB=fLIRC)
3V
─
1.3
3.0
μA
─
2.4
5.0
μA
Standby Current (Sleep)
(HIRC OSC, fSYS=off,
fS=fSUB=fLIRC)
3V
No load, system HALT,
A/D Converter off, WDT enable,
fSYS=12MHz
─
1.4
5
μA
─
2.7
10
μA
Standby Current (Sleep)
(LIRC OSC, fSYS=off,
fS=fSUB=fLIRC)
3V
No load, system HALT,
A/D Converter off, WDT enable,
fSYS=32kHz
─
1.3
3.0
μA
─
2.4
5.0
μA
VIL
Input Low Voltage for I/O
Ports or Input Pins
5V
─
0
─
1.5
V
─
─
0
─
0.2VDD
V
VIH
Input High Voltage for I/O
Ports or Input Pins
5V
─
3.5
─
5.0
V
─
─
0.8VDD
─
VDD
V
VLVR
Low Voltage Reset Voltage
─
-5%
2.55
+5%
V
I/O Port Sink Current
(PA, PB, PD)
3V
16
32
─
mA
ISTB
IOL
5V
5V
5V
5V
5V
5V
5V
3V
IOH
5V
3V
5V
3V
5V
RPH
Rev. 1.20
Pull-high Resistance of I/O
Ports
No load, system HALT,
A/D Converter off, WDT enable,
fSYS=12MHz/64
No load, system HALT,
A/D Converter off, WDT enable,
fSYS=32kHz
5V
3V
I/O Port, Source Current
(PA, PB, PD)
No load, system HALT,
A/D Converter off, WDT enable,
fSYS=12MHz
LVR enable, fixed at 2.55V
VOL=0.1VDD
VOH=0.9VDD, PxPS = 00
VOH=0.9VDD, PxPS = 01
VOH=0.9VDD, PxPS = 10
VOH=0.9VDD, PxPS = 11
3V
─
5V
11
32
64
─
mA
-1.0
-2.0
─
mA
-2.0
-4.0
─
mA
-1.75
-3.5
─
mA
-3.5
-7.0
─
mA
-2.5
-5.0
─
mA
-5.0
-10
─
mA
-5.5
-11
─
mA
-11
-22
─
mA
20
60
100
kΩ
10
30
50
kΩ
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
A.C. Characteristics
Ta=25˚C
Symbol
fSYS
Parameter
System Clock (HIRC)
Test Conditions
VDD
3V/5V
Condition
Ta = 25°C
2.7V~5.5V
fTIMER
Timer I/P Frequency
2.7V~5.5V
fLIRC
System Clock (32K)
5V
System Start-up Timer Period (Wake-up
from HALT)
─
System Start-up Timer Period (Wake-up
from HALT, fSYS on at HALT State)
─
tINT
Interrupt Pulse Width
tLVR
tEERD
tEEWR
─
4.5V~5.5V
tSST
Min.
Typ.
Max.
Unit
-2%
8
+2%
MHz
-2%
12
+2%
MHz
-2%
16
+2%
MHz
─
─
8
MHz
─
─
12
MHz
─
─
16
MHz
-10%
32
+10%
kHz
fSYS= HIRC OSC
16
─
─
fSYS= LIRC OSC
2
─
─
─
2
─
─
─
─
1
5
10
Low Voltage Width to Reset
─
─
120
240
480
μs
EEPROM Read Time
─
─
1
2
4
tSYS
EEPROM Write Timet
─
─
1
2
4
ms
Ta = 25°C
tSYS
μs
Note: 1. tSYS = 1/fSYS
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Rev. 1.20
12
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Sensor Oscillator Electrical Characteristics
Ta=25°C
Touch Key RC OSC=500kHz
Symbol
Parameter
Test Conditions
VDD
3V
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
30
60
60
120
—
40
80
—
80
160
*fREFOSC=500kHz,
M0TSS=0, M0FILEN=0
—
30
60
—
60
120
*fREFOSC=500kHz,
M0TSS=0, M0FILEN=1
—
30
60
—
60
120
*fREFOSC=500kHz,
M0TSS=1, M0FILEN=0
—
30
60
—
60
120
—
40
80
5V
*fREFOSC=500kHz,
M0TSS=1, M0FILEN=1
—
80
160
3V
5V
3V
5V
3V
IREFOSC2
Only Reference Oscillator
Operating Current
Typ. Max. Unit
—
3V
Only Reference Oscillator
Operating Current
Min.
—
5V
5V
IREFOSC1
Condition
5V
3V
*fSENOSC=500kHz, M0FILEN=0
*fSENOSC=500kHz, M0FILEN=1
μA
μA
μA
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator External
Capacitance
5V
*fSENOSC=500kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal
Capacitance
5V
*fSENOSC=500kHz
5
10
20
pF
fKEYOSC
Sensor (KEY) Oscillator Operating
Frequency
5V
*External Capacitance
=7,8,9,10,11,12,13,14,15, … 50pF
100
500
1000
kHz
fREFYOSC
Reference Oscillator Operating
Frequency
5V
*Internal Capacitance
=7,8,9,10,11,12,13,14,15, … 50pF
100
500
1000
kHz
Note: *fSENOSC=500kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =500kHz.
*fREFOSC=500kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator
frequency =500kHz.
Rev. 1.20
13
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key RC OSC=1000kHz
Symbol
Parameter
Test Conditions
VDD
3V
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
40
80
80
160
—
60
120
—
100
200
*fREFOSC=1000kHz,
M0TSS=0, M0FILEN=0
—
40
80
—
80
160
*fREFOSC=1000kHz,
M0TSS=0, M0FILEN=1
—
50
100
—
100
200
*fREFOSC=1000kHz,
M0TSS=1, M0FILEN=0
—
40
80
—
80
160
—
60
120
5V
*fREFOSC=1000kHz,
M0TSS=1, M0FILEN=1
—
150
130
3V
5V
3V
5V
3V
IREFOSC2
Only Reference Oscillator
Operating Current
Typ. Max. Unit
—
3V
Only Reference Oscillator
Operating Current
Min.
—
5V
5V
IREFOSC1
Condition
5V
3V
*fSENOSC=1000kHz, M0FILEN=0
*fSENOSC=1000kHz, M0FILEN=1
μA
μA
μA
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator External
Capacitance
5V
*fSENOSC=1000kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal
Capacitance
5V
*fSENOSC=1000kHz
5
10
20
pF
fKEYOSC
Sensor (KEY) Oscillator Operating
Frequency
5V
*External Capacitance
=2,3,4,5,6,7,8,9,10,11, … 50pF
150
1000 2000
kHz
fREFYOSC
Reference Oscillator Operating
Frequency
5V
*Internal Capacitance
=2,3,4,5,6,7,8,9,10,11, … 50pF
150
1000 2000
kHz
Note: *fSENOSC=1000kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =1000kHz.
*fREFOSC=1000kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator
frequency =1000kHz.
Rev. 1.20
14
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key RC OSC=1500kHz
Symbol
Parameter
Test Conditions
VDD
3V
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
60
120
120
240
—
90
180
—
150
300
*fREFOSC=1500kHz,
M0TSS=0, M0FILEN=0
—
60
120
—
120
240
*fREFOSC=1500kHz,
M0TSS=0, M0FILEN=1
—
60
120
—
140
280
*fREFOSC=1500kHz,
M0TSS=1, M0FILEN=0
—
60
120
—
120
240
—
90
180
5V
*fREFOSC=1500kHz,
M0TSS=1, M0FILEN=1
—
225
450
3V
5V
3V
5V
3V
IREFOSC2
Only Reference Oscillator
Operating Current
Typ. Max. Unit
—
3V
Only Reference Oscillator
Operating Current
Min.
—
5V
5V
IREFOSC1
Condition
5V
3V
*fSENOSC=1500kHz, M0FILEN=0
*fSENOSC=1500kHz, M0FILEN=1
μA
μA
μA
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator External
Capacitance
5V
*fSENOSC=1500kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal
Capacitance
5V
*fSENOSC=1500kHz
5
10
20
pF
fKEYOSC
Sensor (KEY) Oscillator Operating
Frequency
3V
5V
*External Capacitance
=2,3,4,5,6,7,8,9,10,11, … 50pF
150
1500 3000
kHz
fREFYOSC
Reference Oscillator Operating
Frequency
3V
5V
*Internal Capacitance
=2,3,4,5,6,7,8,9,10,11, … 50pF
150
1500 3000
kHz
Note: *fSENOSC=1500kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =1500kHz.
*fREFOSC=1500kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator
frequency =1500kHz.
Rev. 1.20
15
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key RC OSC=2000kHz
Symbol
Parameter
Test Conditions
VDD
3V
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
80
160
160
320
—
120
240
—
200
400
*fREFOSC=2000kHz,
M0TSS=0, M0FILEN=0
—
80
160
—
160
320
*fREFOSC=2000kHz,
M0TSS=0, M0FILEN=1
—
80
160
—
160
320
*fREFOSC=2000kHz,
M0TSS=1, M0FILEN=0
—
80
160
—
160
320
—
120
240
5V
*fREFOSC=2000kHz,
M0TSS=1, M0FILEN=1
—
300
600
3V
5V
3V
5V
3V
IREFOSC2
Only Reference Oscillator
Operating Current
Typ. Max. Unit
—
3V
Only Reference Oscillator
Operating Current
Min.
—
5V
5V
IREFOSC1
Condition
5V
3V
*fSENOSC=2000kHz, M0FILEN=0
*fSENOSC=2000kHz, M0FILEN=1
μA
μA
μA
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator External
Capacitance
5V
*fSENOSC=2000kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal
Capacitance
5V
*fSENOSC=2000kHz
5
10
20
pF
fKEYOSC
Sensor (KEY) Oscillator Operating
Frequency
3V
5V
*External Capacitance
=2,3,4,5,6,7,8,9,10,11, … 50pF
150
2000 4000
kHz
fREFYOSC
Reference Oscillator Operating
Frequency
3V
5V
*Internal Capacitance
=2,3,4,5,6,7,8,9,10,11, … 50pF
150
2000 4000
kHz
Note: *fSENOSC=2000kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =2000kHz.
*fREFOSC=2000kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator
frequency =2000kHz.
Rev. 1.20
16
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
A/D Converter Electrical Characteristics
Ta=25˚C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
AVDD
A/D Converter Operating Voltage
─
─
2.7
─
5.5
V
VADI
A/D Converter Input Voltage
─
─
0
─
VREF
V
VREF
A/D Converter Reference Voltage
─
─
2.7
─
AVDD
V
VBG
Bandgap reference with buffer
voltage
─
─
-3%
1.19
+3%
V
Differential Non-linearity
2.7V VREF=AVDD=VDD
3V tADCK =0.5μs
5V Ta=25°C
-3
─
+3
LSB
Differential Non-linearity
2.7V VREF=AVDD=VDD
3V tADCK =0.5μs
5V Ta=-40°C~85°C
-4
─
+4
LSB
Integral Non-linearity
2.7V VREF=AVDD=VDD
3V tADCK =0.5μs
5V Ta=25°C
-4
─
+4
LSB
Integral Non-linearity
2.7V VREF=AVDD=VDD
3V tADCK =0.5μs
5V Ta=-40°C~85°C
-8
─
+8
LSB
─
0.9
1.35
mA
─
1.2
1.8
mA
DNL
INL
3V
IADC
Additional Power Consumption if A/D
Converter is used
IBG
Additional Power Consumption
if VBG Reference with Buffer is Used
─
─
─
200
300
μA
tADCK
A/D Converter Clock Period
─
─
0.5
─
10
μs
tADC
A/D Conversion Time (Include
Sample and Hold Time)
─
─
16
─
tADCK
tADS
A/D Converter Sampling Time
─
─
─
4
─
tADCK
tON2ST
A/D Converter On-to-Start Time
─
─
2
─
─
μs
tBG
VBG Turn on Stable Time
─
─
─
─
200
μs
Min.
Typ.
Max.
Unit
5V
No load (tADCK =0.5μs )
12-bit A/D Converter
Power-on Reset Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
VPOR
VDD Start Voltage to Ensure Power-on
Reset
─
─
─
─
100
mV
RRVDD
VDD Raising Rate to Ensure Power-on
Reset
─
─
0.035
─
─
V/ms
tPOR
Minimum Time for VDD Stays at VPOR
to Ensure Power-on Reset
─
─
1
─
─
ms
Rev. 1.20
17
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and Periodic performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution
are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch
or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which
carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions,
etc. The internal data path is simplified by moving data through the Accumulator and the ALU.
Certain internal registers are implemented in the Data Memory and can be directly or indirectly
addressed. The simple addressing methods of these registers along with additional architectural
features ensure that a minimum of external components is required to provide a functional I/O and
A/D control system with maximum reliability and flexibility. This makes this device suitable for
low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a high or low speed oscillator is subdivided into four
internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
   
 
  
System Clock and Pipelining
Rev. 1.20
18
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
     
  
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
High Byte
Low Byte(PCL)
PC11~PC8
PCL7~PCL0
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Rev. 1.20
19
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is neither part of the data nor part of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed
onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction,
RET or RETI, the Program Counter is restored to its previous value from the stack. After a device
reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or
RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer
to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can
still be executed which will result in a stack overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program branching. If the stack is overflow, the first Program
Counter save in the stack will be lost.
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
C o u n te r
S ta c k L e v e l 3
o f S ta c k
P ro g ra m
M e m o ry
S ta c k L e v e l 6
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC
• Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Rev. 1.20
20
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device series
the Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device. By
using the appropriate programming tools, the Flash device offers users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming and
updating.
Structure
The Program Memory has a capacity of 3K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by a separate table pointer
register.
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Program Memory Structure
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the "TABRD[m]" or "TABRDL[m]" instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as "0".
The accompanying diagram illustrates the addressing data flow of the look-up table.
A d d re s s
L a s t p a g e o r
T B H P R e g is te r
T B L P R e g is te r
Rev. 1.20
D a ta
1 6 b its
R e g is te r T B L H
U s e r S e le c te d
R e g is te r
H ig h B y te
L o w B y te
21
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is "0B00H" which refers to the
start address of the last page within the 3K words Program Memory of the device. The table pointer
is setup here to have an initial value of "06H". This will ensure that the first data read from the data
table will be at the Program Memory address "0B06H" or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address specified by the TBLP and
TBHP if the "TABRD [m]" instruction is being used. The high byte of the table data which in this
case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]"
instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a ; to the last page or specified page
mov a,0Bh ; initialise high table pointer
mov tbhp,a
:
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address "0B06H" transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address "0B05H" transferred to tempreg2 and TBLH in this
; example the data "1AH" is transferred to tempreg1 and data "0FH" to
; register tempreg2
:
:
org 0B00h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.20
22
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
In Circuit Programming
The provision of Flash type Program Memory provides the user with a means of convenient and easy
upgrades and modifications to their programs on the same device. As an additional convenience,
Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface.
This provides manufacturers with the possibility of manufacturing their circuit boards complete with
a programmed or un-programmed microcontroller, and then programming or upgrading the program
at a later stage. This enables product manufacturers to easily keep their manufactured products
supplied with the latest program releases without removal and re-insertion of the device.
The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows:
Holtek Writer Pins
MCU Programming Pins
ICPDA
PA0
Serial Address and data -- read/write
Function
ICPCK
PA2
Programming Serial Clock
VDD
VDD
Power Supply(5.0V)
VSS
VSS
Ground
The Program Memory and EEPROM data memory can both be programmed serially in-circuit using
this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional
line for the clock. Two additional lines are required for the power supply. The technical details
regarding the in-circuit programming of the device are beyond the scope of this document and will
be supplied in supplementary literature.
During the programming process the PA0 and PA2 I/O pins for data and clock programming
purposes. The user must there take care to ensure that no other outputs are connected to these two
pins.
W r ite r C o n n e c to r
S ig n a ls
M C U
W r ite r _ V D D
V D D
IC P D A
P A 0
IC P C K
P A 2
W r ite r _ V S S
V S S
*
P r o g r a m m in g
P in s
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance
of * must be less than 1nF.
Rev. 1.20
23
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
On-Chip Debug Support – OCDS
There is an EV chip which is used to emulate the BS84BV06A-3 device series. This EV chip device
also provides an "On-Chip Debug" function to debug the device during the development process.
The EV chip and the actual MCU devices are almost functionally compatible except for the "OnChip Debug" function. Users can use the EV chip device to emulate the real chip device behavior
by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The
OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS
clock input pin. When users use the EV chip for debugging, other functions which are shared with
the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip.
However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as
the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the
corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide".
Holtek e-Link Pins
EV Chip Pins
OCDSDA
OCDSDA
On-chip Debug Support Data/Address input/output
Pin Description
OCDSCK
OCDSCK
On-chip Debug Support Clock input
VDD
VDD
Power Supply
GND
VSS
Ground
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some
remain protected from user manipulation.
The second area of Data Memory is known as the General Purpose Data Memory, which is reserved
for general purpose use. All locations within this area are read and write accessible under program
control.
The overall Data Memory is subdivided into several banks for the device. The Special Purpose Data
Memory registers are accessible in all banks, with the exception of the EEC register at address 40H,
which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved
by setting the Bank Pointer to the correct value. The start address of the Data Memory for this
device is the address 00H.
Capacity
Bank 0
Bank 1
288×8
60H~FFH
80H~FFH
General Purpose Data Memory
Rev. 1.20
24
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section,
however several registers require a separate description in this section.
Indirect Addressing Registers – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the
registers indirectly will result in no operation.
Rev. 1.20
25
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
 
 
 
 
    
 
 
 
 
 









 
 
 
 
 
 
 
 
 
 
   
 
          
 
 
 
 
 
 
 
 
 
 
 
Special Purpose Data Memory
Rev. 1.20
26
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to
access data from all banks according to BP register. Direct Addressing can only be used with Bank 0,
all other Banks must be addressed indirectly using MP1 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example
data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ´code´
org 00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp0,a ; setup memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by mp0
inc mp0; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Rev. 1.20
27
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Bank Pointer – BP
The Data Memory is divided into two banks, Bank0 and Bank1. Selecting the required Data
Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer are used to select Data
Memory Banks 0~1.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power
Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the
Special Function Data Memory is not affected by the bank selection, which means that the Special
Function Registers can be accessed from within any bank. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing
data from Bank1 must be implemented using Indirect Addressing.
BP Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
DMBP0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7 ~ 1
Unimplemented, read as "0"
Bit 0
DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location
where the table data is located. Their value must be setup before any table read commands are
executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.
Rev. 1.20
28
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing
the "HALT" or "CLR WDT" instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by
executing the "HALT" instruction.
• TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
Rev. 1.20
29
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
—
—
R
R
R/W
R/W
R/W
R/W
POR
—
—
0
0
×
×
×
×
"×" unknown
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5TO: Watchdog Time-Out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred.
Bit 4PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation
C is also affected by a rotate through carry instruction.
Rev. 1.20
30
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
EEPROM Data Memory
One of the special features in the device is its internal EEPROM Data Memory. EEPROM, which
stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile
form of memory, with data retention even when its power supply is removed. By incorporating
this kind of data memory, a whole new host of application possibilities are made available to the
designer. The availability of EEPROM storage allows information such as product identification
numbers, calibration values, specific user data, system setup data or other product information to
be stored directly within the product microcontroller. The process of reading and writing data to the
EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is up to 64×8 bits. Unlike the Program Memory and RAM
Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not directly
accessible in the same way as the other types of memory. Read and Write operations to the
EEPROM are carried out in single byte operations using an address and data register in Bank 0 and
a single control register in Bank 1.
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Bank 0, they can be directly accessed in the same way as any other
Special Function Register. The EEC register however, being located in Bank1, cannot be directly
addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer
and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H
in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register,
BP, set to the value, 01H, before any operations on the EEC register are executed.
EEPROM Control Registers List
Name
Bit
7
6
5
4
3
2
1
0
EEA
—
—
D5
D4
D3
D2
D1
D0
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
EEA Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
—
—
D5
D4
D3
D2
D1
D0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5 ~ 0
Data EEPROM address
Data EEPROM address bit 5 ~ bit 0
31
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
Data EEPROM data
Data EEPROM data bit 7 ~ bit 0
EEC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7 ~ 4
Unimplemented, read as "0"
Bit 3WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The
WR and RD can not be set to "1" at the same time.
Rev. 1.20
32
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM
To write data to the EEPROM, the EEPROM address of the data to be written must first be placed
in the EEA register and the data placed in the EED register. Then the write enable bit, WREN,
in the EEC register must first be set high to enable the write function. After this, the WR bit in
the EEC register must be immediately set high to initiate a write cycle. These two instructions
must be executed consecutively. The global interrupt bit EMI should also first be cleared before
implementing any write operations, and then set again after the write cycle has started. Note that
setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the
EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to
microcontroller system clock, a certain time will elapse before the data will have been written into
the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the
WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates,
the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the
data has been written to the EEPROM. The application program can therefore poll the WR bit to
determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a
further measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an
EEPROM write cycle ends, the DEF request flag will be set. If the global, EEPROM is enabled and
the stack is not full, a jump to the associated Interrupt vector will take place. When the interrupt is
serviced, the EEPROM interrupt flag will automatically reset. More details can be obtained in the
Interrupt section.
Rev. 1.20
33
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also
the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where
the EEPROM control register exist. Although certainly not necessary, consideration might be given
in the application program to the checking of the validity of new write data by a simple read back
process. When writing data the WR bit must be set high immediately after the WREN bit has been
set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be
cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that
the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is
totally complete. Otherwise, the EEPROM read or write operation will fail.
Programming Examples
• Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES ;
MOV EEA, A
MOV A, 040H ;
MOV MP1, A ;
MOV A, 01H ;
MOV BP, A
SET IAR1.1 ;
SET IAR1.0 ;
BACK:
SZ IAR1.0 ;
JMP BACK
CLR IAR1 ;
CLR BP
MOV A, EED ;
MOV READ_DATA, A
user defined address
setup memory pointer MP1
MP1 points to EEC register
setup Bank Pointer
set RDEN bit, enable read operations
start Read Cycle - set RD bit
check for read cycle end
disable EEPROM read/write
move read data to register
• Writing Data to the EEPROM – polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA
MOV EED, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
CLR EMI
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ IAR1.2
JMP BACK
CLR IAR1
CLR BP
Rev. 1.20
; user defined address
; user defined data
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM read/write
34
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimization can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. Fully integrated internal oscillators, requiring no
external components, are provided to form a wide range of both fast and slow system oscillators.
The higher frequency oscillators provide higher performance but carry with it the disadvantage of
higher power requirements, while the opposite is of course true for the lower frequency oscillators.
With the capability of dynamically switching between fast and slow system clock, the device has the
flexibility to optimize the performance/power ratio, a feature especially important in power sensitive
portable applications.
Type
Name
Freq.
Internal High Speed RC
HIRC
8/12/16MHz
Internal Low Speed RC
LIRC
32kHz
Oscillator Types
System Clock Configurations
There are two methods of generating the system clock, a high speed oscillator and a low speed
oscillator. The high speed oscillator is the internal 8MHz, 12MHz, 16MHz RC oscillator. The low
speed oscillator is the internal 32kHz (LIRC) oscillator. Selecting whether the low or high speed
oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0
bits in the SMOD register and as the system clock can be dynamically selected.
‚ 
 
  
 
  ­ € System Clock Configurations
Rev. 1.20
35
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a power on default frequency of 8 MHz but can be selected to be
either 8MHz, 12MHz or 16MHz using the HIRCS1 and HIRCS0 bits in the CTRL register. Device
trimming during the manufacturing process and the inclusion of internal frequency compensation
circuits are used to ensure that the influence of the power supply voltage, temperature and process
variations on the oscillation frequency are minimised.
Internal 32kHz Oscillator – LIRC
The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated
RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its
implementation. Device trimming during the manufacturing process and the inclusion of internal
frequency compensation circuits are used to ensure that the influence of the power supply voltage,
temperature and process variations on the oscillation frequency are minimised. After power on this
LIRC oscillator will be permanently enabled; there is no provision to disable the oscillator using.
Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided this device with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source,
and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Both the high and
low speed system clocks are sourced from internal RC oscillators.
Rev. 1.20
36
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
 … 
    
    † ‡ ƒ ­
€ ‚ ƒ 
 „ …  
System Clock Configurations
Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will
stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use.
System Operation Modes
There are five different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining three modes, the SLEEP,
IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power.
Rev. 1.20
Description
Operating
Mode
CPU
fSYS
fSUB
NORMAL mode
On
fH~fH/64
On
SLOW mode
On
fSUB
On
ILDE0 mode
Off
Off
On
IDLE1 mode
Off
On
On
SLEEP mode
Off
Off
On
37
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by the high speed oscillator. This
mode operates allowing the microcontroller to operate normally with a clock source will come from
the high speed oscillator, HIRC. The high speed oscillator will however first be divided by a ratio
ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the
SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided
clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from fSUB. Running the microcontroller in this mode
allows it to run with much lower operating currents. In the SLOW Mode, the fH is off.
SLEEP Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP mode the CPU will be stopped. However the fSUB clocks will
continue to run the Watchdog Timer will continue to operate.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in
the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode
the system oscillator will be stop and will therefore be inhibited from driving the CPU but some
peripheral functions will remain operational such as the Watchdog Timer, Timer/Event Counter.
IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in
the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode
the system oscillator will be inhibited from driving the CPU but may continue to provide a clock
source to keep some peripheral functions operational. In the IDLE1 Mode, the system oscillator will
continue to run, and this system oscillator may be the high speed or low speed system oscillator. In
the IDLE1 Mode the Watchdog Timer clock, will be on.
Rev. 1.20
38
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Control Register
The SMOD register is used to control the internal clocks within the device.
SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
—
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
—
R
R
R/W
R/W
POR
0
0
0
—
0
0
1
1
Bit 7 ~ 5
CKS2 ~ CKS0: The system clock selection when HLCLK is "0"
000: fSUB (fLIRC)
001: fSUB (fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be LIRC, a divided version of the high
speed system oscillator can also be chosen as the system clock source.
Bit 4
Unimplemented, read as 0.
Bit 3LTO: LIRC System OSC SST ready flag
0: Not ready
1: Ready
This is the low speed system oscillator SST ready flag which indicates when the low
speed system oscillator is stable after power on reset or a wake-up has occurred. The
flag will change to a high level after 1~2 cycles.
Bit 2HTO: HIRC System OSC SST ready flag
0: Not ready
1: Ready
This is the high speed system oscillator SST ready flag which indicates when the high
speed system oscillator is stable after a wake-up has occurred. This flag is cleared to
"0" by hardware when the device is powered on and then changes to a high level after
the high speed system oscillator is stable. Therefore this flag will always be read as "1"
by the application program after device power-on. The flag will be low when in the
SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag
will change to a high level after 15~16 clock cycles if the HIRC oscillator is used.
Bit 1IDLEN: IDLE Mode Control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0HLCLK: System Clock Selection
0: fH/2 ~ fH/64 or fSUB
1: fH
This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fSUB clock is used as the
system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~
fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to
the fSUB clock and the fH clock will be automatically switched off to conserve power.
Rev. 1.20
39
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
HIRCS1
HIRCS0
—
LVRF
D1
WRF
R/W
R/W
—
R/W
R/W
—
R/W
R/W
R/W
POR
0
—
0
0
—
×
0
0
"×"Unknown
Bit 7 FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Bit 6
Unimplemented, read as 0.
Bit 5~4
HIRCS1~HIRCS0: High frequency clock select
00: 8MHz
01: 16MHz
10: 12MHz
11: 8MHz
Bit 3
Unimplemented, read as 0.
Bit 2
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1
Undefined bit
This bit can be read or written by user software program.
Bit 0WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Operating Mode Switching
The device can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed
using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the
NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When
a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is
determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL
register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the
high speed clock source will stop running to conserve power. When this happens it must be noted
that the fH/16 and fH/64 internal clock sources will also stop running. The accompanying flowchart
shows what happens when the device moves between the various operating modes.
Rev. 1.20
40
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
      
   
   
   NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the
HLCLK bit to "0" and setting the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This
will then use the low speed system oscillator which will consume less power. Users may decide to
do this for certain operations which do not require high performance and can subsequently reduce
power consumption.
The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be
stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL
Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or
HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain
amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is
checked.
Rev. 1.20
41
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
                                                        Rev. 1.20
42
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Entering the SLEEP Mode
There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "0". When this
instruction is executed under the conditions described above, the following will occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the "HALT" instruction, but the fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the
FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the "HALT" instruction,
but the Time Base and the low frequency fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the
FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions
described above, the following will occur:
• The system clock and the low frequency fSUB will be on and the application program will stop at
the "HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.20
43
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 Mode, there are other considerations which must also be taken into account by the circuit
designer if the power consumption is to be minimised. Special attention must be made to the I/O pins
on the device. All high-impedance input pins must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations and result in increased current consumption.
This also applies to devices which have different package types, as there may be unbounded pins.
These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as
outputs. These should be placed in a condition in which minimum current is drawn or connected
only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode
the system oscillator is on, if the system oscillator is from the high speed system oscillator, the
additional standby current will also be perhaps in the order of several hundred micro-amps.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The PDF
flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set
when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes
a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their
original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
System Oscillator
Wake-up Time
(SLEEP Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
HIRC
15~16 HIRC cycles
1~2 HIRC cycles
LIRC
1~2 LIRC cycles
1~2 LIRC cycles
Wake-Up Time
Rev. 1.20
44
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal fSUB clock which is in turn supplied
by the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to
218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC
register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V.
However, it should be noted that this specified internal clock period can vary with VDD, temperature
and process variations.
The WDT is always enabled.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable operation. The
WDTC register is initiated to 01010011B at any reset but keeps unchanged at the WDT time-out
occurrence in a power down state.
WDTC Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~ 3
WE4 ~ WE0: WDT function software control
10101B or 01010B: Enabled
Other values: Reset MCU (Reset will be active after 2~3 LIRC clock for debounce time.)
If the MCU reset caused by the WE [4:0] in WDTC software reset, the WRF flag of
CTRL register will be set).
Bit 2~ 0
WS2 ~ WS0: WDT Time-out period selection
000: 28/fSUB
001: 210/fSUB
010: 212/fSUB
011: 214/fSUB(default)
100: 215/fSUB
101: 216/fSUB
110: 217/fSUB
111: 218/fSUB
These three bits determine the division ratio of the Watchdog Timer source clock,
which in turn determines the timeout period.
45
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
HIRCS1
HIRCS0
—
LVRF
D1
WRF
R/W
R/W
—
R/W
R/W
—
R/W
R/W
R/W
POR
0
—
0
0
—
×
0
0
"×"unknown
Bit 7
FSYSON: fSYS Control in IDLE Mode
Describe elsewhere
Bit 6
Unimplemented, read as "0"
Bit 5~ 4
HIRCS1~HIRCS0: High frequency clock select
Describe elsewhere
Bit 3
Unimplemented, read as "0"
Bit 2LVRF: LVR function reset flag
Describe elsewhere
Bit 1
Undefined bit
This bit can be read or written by user software program
Bit 0
WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Watchdog Timer Operation
In this device the Watchdog Timer supplied by the fSUB oscillator and is therefore always on. The
Watchdog Timer operates by providing a device reset when its timer overflows. This means that in
the application program and during normal operation the user has to strategically clear the Watchdog
Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using
the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an
unknown location, or enters an endless loop, the clear WDT instruction will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. There are
five bits, WE4~WE0, in the WDTC register to enable the WDT function. When the WE4~WE0 bits
value is equal to 01010B or 10101B, the WDT function is enabled. However, if the WE4~WE0 bits
are changed to any other values except 01010B and 10101B, which is caused by the environmental
noise, it will reset the microcontroller after 2~3 LIRC clock cycles.
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value is written into the WE4~WE0 bit filed except
01010B and 10101B, the second is using the Watchdog Timer software clear instructions and the
third is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single "CLR WDT" instruction to clear the WDT.
The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
Rev. 1.20
46
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
WDTC WE4~WE0 bits
Register
Reset �CU
CLR
“HALT”Instruction
“CLR WDT”Instruction
LIRC
fSUB
8-stage Divider
fS/28
WS2~WS0
(fSUB/28 ~ fSUB/218)
WDT Prescaler
8-to-1 �UX
WDT Time-out
(28/fSUB ~ 218/fSUB )
Watchdog Timer
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup. Another reset exists in the
form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power
supply voltage falls below a certain threshold.
Reset Functions
There are four ways in which a microcontroller reset can occur, through events occurring internally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
VDD
Power-on
Reset
tRSTD
SST Time-out
Power-On Reset Timing Chart
Rev. 1.20
47
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device, which is fixed at 2.55V. If the supply voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the
device internally and the LVRF bit in the CTRL register will also be set. For a valid LVR signal, a
low voltage, i.e., a voltage in the range between 0.9V~ VLVR must exist for greater than the value tLVR
specified in the A.C. characteristics. If the low voltage state does not exceed this value, the LVR will
ignore the low supply voltage and will not perform a reset function. Note that the LVR function will
be automatically disabled when the device enters the power down mode.
Low Voltage Reset Timing Chart
• CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
HIRCS1
HIRCS0
—
LVRF
D1
WRF
R/W
R/W
—
R/W
R/W
—
R/W
R/W
R/W
POR
0
—
0
0
—
×
0
0
"×"unknown
Bit 7FSYSON: fSYS Control IDLE Mode
Describe elsewhere
Bit 6
Unimplemented, read as "0"
Bit 5~ 4HIRCS1~HIRCS0: High frequency clock select
Describe elsewhere
Bit 3
Unimplemented, read as "0"
Bit 2
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1
Undefined bit
This bit can be read or written by user software program.
Bit 0
WRF: WDT Control register software reset flag
Describe elsewhere
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a LVR reset except that the
Watchdog time-out flag TO will be set to "1".
WDT Time-out Reset during Normal Operation Timing Chart
Rev. 1.20
48
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for
tSST details.
Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC.
The tSST is 1~2 clock for the LIRC.
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
0
0
Power-on reset
RESET Conditions
u
u
LVR reset during NORMAL or SLOW Mode operation
1
u
WDT time-out reset during NORMAL or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
Note: "u" stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Rev. 1.20
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Event Counter
Timer/Event Counter will be turned off
Input/Output Ports
I/O ports will be setup as inputs and AN0~AN3 as A/D input pins
Stack Pointer
Stack Pointer will point to the top of the stack
49
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers.
Register
Rev. 1.20
Reset
(Power On)
----
WDT Time-out
(Normal Operation)
IAR0
----
MP0
xxxx xxxx
xxxx xxxx
uuuu uuuu
IAR1
----
----
----
MP1
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBHP
---- xxxx
---- uuuu
---- uuuu
STATUS
--00 xxxx
--1u uuuu
- - 11 u u u u
SMOD
0 0 0 - 0 0 11
0 0 0 - 0 0 11
uuu- uuuu
CTRL
0-00 -x00
0-00 -x00
u-uu -uuu
INTEG
---- --00
---- --00
---- --uu
INTC0
-000 0000
-000 0000
-uuu uuuu
INTC1
0000 0000
0000 0000
uuuu uuuu
PA
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAC
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAPU
0--0 0000
0--0 0000
u--u uuuu
PAWU
0--0 0000
0--0 0000
u--u uuuu
SLEDC0
0101 0101
0101 0101
uuuu uuuu
SLEDC1
---- --01
---- --01
---- --uu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
--00 ----
--00 ----
--uu ----
TMR
0000 0000
0000 0000
uuuu uuuu
TMRC
--00 -000
--00 -000
--uu -uuu
EEA
--00 0000
--00 0000
--uu uuuu
EED
0000 0000
0000 0000
uuuu uuuu
PB
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
uuuu uuuu
PBPU
0000 0000
0000 0000
uuuu uuuu
I2CTOC
0000 0000
0000 0000
uuuu uuuu
SIMC0
111 - - - 0 -
111 - - - 0 -
uuu- --u-
SIMC1
1000 0001
1000 0001
uuuu uuuu
SIMD
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIMC2 (SPI mode)
--00 0000
--00 0000
--uu uuuu
SIMA (I2C mode)
0000 000-
0000 000-
uuuu uuu-
ADRL (ADRFS=0)
xxxx ----
xxxx ----
uuuu ----
ADRL (ADRFS=1)
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH (ADRFS=0)
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH (ADRFS=1)
---- xxxx
---- xxxx
---- uuuu
ADCR0
0 11 0 - - 0 0
0 11 0 - - 0 0
uuuu --uu
ADCR1
00-0 -000
00-0 -000
uu-u -uuu
----
50
----
----
WDT Time-out
(HALT)*
----
----
-------
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Reset
(Power On)
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)*
ACERL
- - - - 1111
- - - - 1111
---- uuuu
PD
- - - - 1111
- - - - 1111
---- uuuu
PDC
- - - - 1111
- - - - 1111
---- uuuu
PDPU
---- 0000
---- 0000
---- uuuu
TKTMR
0000 0000
0000 0000
uuuu uuuu
TKC0
-000 0000
-000 0000
-uuu uuuu
TK16DL
0000 0000
0000 0000
uuuu uuuu
TK16DH
0000 0000
0000 0000
uuuu uuuu
TKC1
---- --11
---- --11
---- --uu
TKM016DL
0000 0000
0000 0000
uuuu uuuu
TKM016DH
0000 0000
0000 0000
uuuu uuuu
TKM0ROL
0000 0000
0000 0000
uuuu uuuu
TKM0ROH
---- --00
---- --00
---- --uu
TKM0C0
0000 0000
0000 0000
uuuu uuuu
TKM0C1
0-00 0000
0-00 0000
u-uu uuuu
TKM116DL
0000 0000
0000 0000
uuuu uuuu
TKM116DH
0000 0000
0000 0000
uuuu uuuu
TKM1ROL
0000 0000
0000 0000
uuuu uuuu
TKM1ROH
---- --00
---- --00
---- --uu
TKM1C0
-000 0000
-000 0000
-uuu uuuu
TKM1C1
0-00 --00
0-00 --00
u-uu --uu
EEC
---- 0000
---- 0000
---- uuuu
Register
Note: "-" not implement
"u" stands for "unchanged"
"x" stands for "unknown"
Rev. 1.20
51
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA, PB and PD. These
I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special
Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For
input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising
edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the
data is latched and remains unchanged until the output latch is rewritten.
I/O Register List
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
D7
—
—
D4
D3
D2
D1
D0
PAPU
D7
—
—
D4
D3
D2
D1
D0
PA
D7
—
—
D4
D3
D2
D1
D0
PAC
D7
—
—
D4
D3
D2
D1
D0
PBPU
D7
D6
D5
D4
D3
D2
D1
D0
PB
D7
D6
D5
D4
D3
D2
D1
D0
PBC
D7
D6
D5
D4
D3
D2
D1
D0
PDPU
—
—
—
—
D3
D2
D1
D0
PD
—
—
—
—
D3
D2
D1
D0
PDC
—
—
—
—
D3
D2
D1
D0
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using registers PAPU, PBPU and PDPU, and are implemented using
weak PMOS transistors.
PAPU Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
D7
—
—
D4
D3
D2
D1
D0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
0
—
—
0
0
0
0
0
Bit 7
I/O Port A bit 7 Pull-High Control
0: Disable
1: Enable
Bit 6 ~ 5
Unimplemented, read as "0"
Bit 4 ~ 0
I/O Port A bit 4~ bit 0 Pull-High Control
0: Disable
1: Enable
52
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
PBPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
I/O Port B bit 7~ bit 0 Pull-High Control
0: Disable
1: Enable
PDPU Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
D3
D2
D1
D0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7 ~ 4
Unimplemented, read as "0"
Bit 3 ~ 0
I/O Port D bit 3~ bit 0 Pull-High Control
0: Disable
1: Enable
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the
Port A pins from high to low. This function is especially suitable for applications that can be woken
up via external switches. Each pin on Port A can be selected individually to have this wake-up
feature using the PAWU register.
PAWU Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
D7
—
—
D4
D3
D2
D1
D0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
0
—
—
0
0
0
0
0
Bit 7
I/O Port A bit 7 Pull-High Control
0: Disable
1: Enable
Bit 6 ~ 5
Unimplemented, read as "0"
Bit 4 ~ 0
I/O Port A bit 4 ~ bit 0 Wake Up Control
0: Disable
1: Enable
53
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
I/O Port Control Registers
Each I/O port has its own control register known as PAC, PBC and PDC, to control the input/
output configuration. With this control register, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of the
control register must be written as a "1". This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a "0",
the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
PAC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
—
—
D4
D3
D2
D1
D0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
1
—
—
1
1
1
1
1
Bit 7
I/O Port A bit 7 Input/Output Control
0: Disable
1: Enable
Bit 6 ~ 5
Unimplemented, read as "0"
Bit 4 ~ 0
I/O Port A bit 4 ~ bit 0 Input/Output Control
0: Disable
1: Enable
PBC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7 ~ 0
I/O Port B bit 7~ bit 0 Input/Output Control
0: Output
1: Input
PDC Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
D3
D2
D1
D0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
1
1
1
1
Bit 7 ~ 4
Unimplemented, read as "0"
Bit 3 ~ 0
I/O Port D bit 3~ bit 0 Input/Output Control
0: Disable
1: Enable
54
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Source Current Selection
The source current of each pin in these device can be configured with different source current which
is selected by the corresponding pin source current select bits. These source current bits are available
when the corresponding pin is configured as a CMOS output. Otherwise, these select bits have no
effect. Users should refer to the D.C. Characteristics section to obtain the exact value for different
applications.
SLEDC0 Register
Bit
7
6
5
4
3
2
1
0
Name
PBPS3
PBPS2
PBPS1
PBPS0
PAPS3
PAPS2
PAPS1
PAPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~6PBPS3~PBPS2: PB7~PB4 source current select
00: Source = Level 0 (min.)
01: Source = Level l
10: Source = Level 2
11: Source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 5 ~ 4PBPS1~PBPS0: PB3~PB0 source current select
00: Source = Level 0 (min.)
01: Source = Level l
10: Source = Level 2
11: Source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 3 ~ 2PAPS3~PAPS2: PA7 and PA4 source current select
00: Source = Level 0 (min.)
01: Source = Level l
10: Source = Level 2
11: Source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
Bit 1 ~ 0
PAPS1~PAPS0: PA3~PA0 source current select
00: Source = Level 0 (min.)
01: Source = Level l
10: Source = Level 2
11: Source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
SLEDC1 Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PDPS1
PDPS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
1
Bit 7~2
Unimplemented, read as "0"
Bit 1 ~ 0
PDPS1~PDPS0: PD3~PD0 source current select
00: Source = Level 0 (min.)
01: Source = Level l
10: Source = Level 2
11: Source = Level 3 (max.)
These bits are available when the corresponding pin is configured as a CMOS output.
55
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
 
     Generic Input/Output Structure
 ‚ ­

 ­
€
­
€
­
   
A/D Input/Output Structure
Rev. 1.20
56
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of
the I/O data and port control registers will be set high. This means that all I/O pins will default to
an input state, the level of which depends on the other connected circuitry and whether pull-high
selections have been chosen. If the port control registers, PAC, PBC and PDC, are then programmed
to setup some pins as outputs, these output pins will have an initial high output value unless the
associated port data registers, PA, PB and PD, are first programmed. Selecting which pins are inputs
and which are outputs can be achieved byte-wide by loading the correct values into the appropriate
port control register or by programming individual bits in the port control register using the "SET [m].
i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modifywrite operation takes place. The microcontroller must first read in the data on the entire port, modify
it to the required new bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Timer/Event Counter
The provision of timers form an important part of any microcontroller, giving the designer a means
of carrying out time related functions. The device contains one 8-bit counter up timer. The 8-bit
timer is a general timer. The provision of an internal prescaler to the clock circuitry on gives added
range to the timers.
There are two types of registers related to the Timer/Event Counter. The first is the register that
contains the actual value of the timer and into which an initial value can be preloaded. Reading from
this register retrieves the contents of the Timer/Event Counter. The second type of associated register
is the Timer Control Register which defines the timer options.
        
   ­  € ‚  Timer/Event Counter
Configuring the Timer/Event Counter Input Clock Source
The Timer/Event Counter clock source can originate from either the system clock fSYS or the fSUB
oscillator, the choice of which is determined by the TS bit in the TMRC register. This internal clock
source is first divided by a prescaler, the division ratio of which is conditioned by the Timer Control
Register bits TPSC0~TPSC2.
Rev. 1.20
57
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Timer Register – TMR
The timer register is a special function register located in the Special Purpose Data Memory and is
the place where the actual timer value is stored, it is known as TMR. The value in the timer register
increases by one each time an internal clock pulse is received The timer will count from the initial
value loaded by the preload register to the full count of FFH at which point the timer overflows and
an internal interrupt signal is generated. The timer value will then be reset with the initial preload
register value and continue counting.
Note that to achieve a maximum full range count of FFH, the preload register must first be cleared
to all zeros. It should be noted that after power-on, the preload registers will be in an unknown
condition. Note that if the Timer/Event Counter is in an OFF condition and data is written to its
preload register, this data will be immediately written into the actual counter. However, if the
counter is enabled and counting, any new data written into the preload data register during this
period will remain in the preload register and will only be written into the actual counter the next
time an overflow occurs.
Timer Control Register – TMRC
The Timer Control Register is known as TMRC. It is the Timer Control Register together with the
corresponding timer register that control the full operation of the Timer/Event Counter. Before
the timer can be used, it is essential that the Timer Control Register is fully programmed with the
right data to ensure its correct operation, a process that is normally carried out during program
initialisation.
The timer-on bit, which is bit 4 of the Timer Control Register and known as TON, provides the
basic on/off control of the timer. Setting the bit high allows the counter to run, clearing the bit stops
the counter. Bits 0~2 of the Timer Control Register determine the division ratio of the input clock
prescaler. The TS bit selects the internal clock source.
TMRC Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
—
—
TS
TON
—
TPSC2
TPSC1
TPSC0
R/W
—
—
R/W
R/W
—
R/W
R/W
R/W
POR
—
—
0
0
—
0
0
0
Bit 7 ~ 6 Unimplemented, read as "0"
Bit 5
TS: Timer/Event Counter Clock Source
0: fSYS
1: fSUB
Bit 4
TON: Timer/Event Counter Counting Enable
0: disable
1: enable
Bit 3 Unimplemented, read as "0"
Bits 2 ~ 0
TPSC2~TPSC0: Timer prescaler rate selection
Timer internal clock=
000: fTP
001: fTP/2
010: fTP/4
011: fTP/8
100: fTP/16
101: fTP/32
110: fTP/64
111: fTP/128
58
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Timer Operation
The Timer/Event Counter is utilized to measure fixed time intervals, providing an internal interrupt
signal each time the Timer/Event Counter overflows. The timer input clock source is either fSYS
or fSUB, however, this timer clock source is further divided by a prescaler, the value of which is
determined by the bits TPSC2~TPSC0 in the Timer Control Register. The timer-on bit, TON must
be set high to enable the timer to run. Each time an internal clock transition occurs, the timer
increments by one; when the timer is full and overflows, an interrupt signal is generated and the
timer will reload the value already loaded into the preload register and continue counting. A timer
overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the
internal interrupts can be disabled by ensuring that the timer enable bit in the interrupt register is
reset to zero.
Prescaler
Bits TPSC0~TPSC2 of the TMRC register can be used to define a division ratio for the internal
clock source of the Timer/Event Counter enabling longer time out periods to be setup.
Programming Considerations
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is
inhibited to avoid errors, however as this may result in a counting error, this should be taken into
account by the programmer. Care must be taken to ensure that the timer is properly initialised before
using it for the first time. The associated timer enable bits in the interrupt control register must be
properly set otherwise the internal interrupt associated with the timer will remain inactive. It is also
important to ensure that an initial value is first loaded into the timer registers before the timer is
switched on; after power-on the initial values of the timer registers are zero.
After the timer has been initialised the timer can be turned on and off by controlling the enable bit
in the timer control register. When the Timer/Event Counter overflows, its corresponding interrupt
request flag in the interrupt control register will be set. If the Timer/Event Counter interrupt is
enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts
are enabled or not, a Timer/Event Counter overflow will also generate a wake-up signal if the device
is in a Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request
flag should first be set high before issuing the HALT instruction to enter the Idle/Sleep Mode.
Rev. 1.20
59
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Overview
The device contains a multi-channel analog to digital converter which can directly interface to
external analog signals, such as that from sensors or other control signals and convert these signals
directly into a 12-bit digital value.
Input Channels
A/D Channel Select Bits
Input Pins
4
ACS4,ACS1, ACS0
AN0~AN3
The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
  
­ 
… † ‡ ˆ
ƒ

  
  
  
 
„ ‚  €    
  
  
A/D Converter Structure
A/D Converter Register Description
Overall operation of the A/D converter is controlled using five registers. A read only register
pair exists to store the A/D Converter data 12-bit value. The remaining three registers are control
registers which setup the operating and control function of the A/D converter.
Name
ADRL(ADRFS=0)
Bit
7
6
5
4
3
2
1
0
D3
D2
D1
D0
—
—
—
—
ADRL(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
ADRH(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
ADRH(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
ADCR0
START
EOCB
ADOFF
ADRFS
—
—
ACS1
ACS0
ADCR1
ACS4
V119EN
—
VREFS
—
ADCK2
ADCK1
ADCK0
ACERL
—
—
—
—
ACE3
ACE2
ACE1
ACE0
A/D Converter Register List
Rev. 1.20
60
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
A/D Converter Data Registers – ADRL, ADRH
As the device contains an internal 12-bit A/D converter, it requires two data registers to store the
converted value. These are a high byte register, known as ADRH, and a low byte register, known
as ADRL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitized conversion value. As only 12 bits of the 16-bit register space
is utilized, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any
unused bits will be read as zero.
ADRFS
0
1
ADRH
7
6
D11 D10
0
0
ADRL
5
4
3
2
1
0
7
6
5
4
3
2
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Data Registers
A/D Converter Control Registers – ADCR0, ADCR1, ACERL
To control the function and operation of the A/D converter, three control registers known as ADCR0,
ADCR1, ACERL are provided. These 8-bit registers define functions such as the selection of which
analog channel is connected to the internal A/D converter, the digitized data format, the A/D clock
source as well as controlling the start function and monitoring the A/D converter end of conversion
status. The ACS1~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register define
the A/D Converter input channel number. As the device contains only one actual analog to digital
converter hardware circuit, each of the individual 4 analog inputs must be routed to the converter. It
is the function of the ACS4 and ACS1 ~ ACS0 bits to determine which analog channel input signals
or internal 1.19V is actually connected to the internal A/D converter.
The ACERL control register contains the ACE3~ACE0 bits which determine which pins on Port D
are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D
converter input. Setting the corresponding bit high will select the A/D input function, clearing the
bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an
A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In
addition, any internal pull-high resistors connected to these pins will be automatically removed if the
pin is selected to be an A/D input.
Rev. 1.20
61
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
ADCR0 Register
Bit
7
6
5
4
3
2
1
0
Name
START
EOCB
ADOFF
ADRFS
—
—
ACS1
ACS0
R/W
R/W
R
R/W
R/W
—
—
R/W
R/W
POR
0
1
1
0
—
—
0
0
Bit 7START: Start the A/D conversion
0-->1-->0: start
0-->1 : reset the A/D converter and set EOCB to "1"
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
When the bit is set high the A/D converter will be reset.
Bit 6EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed.
When the conversion process is running the bit will be high.
Bit 5ADOFF : A/D Converter module power on/off control bit
0: A/D Converter module power on
1: A/D Converter module power off
This bit controls the power to the A/D internal function. This bit should be cleared
to zero to enable the A/D converter. If the bit is set high then the A/D converter will
be switched off reducing the device power consumption. As the A/D converter will
consume a limited amount of power, even when not executing a conversion, this may
be an important consideration in power sensitive battery powered applications.
Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for
saving power.
2. ADOFF=1 will power down the A/D Converter module.
Bit 4ADRFS: A/D Converter Data Format Control
0: A/D Converter Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: A/D Converter Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D data register section.
Bit 3~2
Unimplemented, read as "0"
Bit 1 ~ 0ACS1 ~ ACS0: Select A/D channel (when ACS4 is "0")
00: AN0
01: AN1
10: AN2
11: AN3
These are the A/D channel select control bits. As there is only one internal hardware
A/D converter each of the four A/D inputs must be routed to the internal converter
using these bits. If bit ACS4 in the ADCR1 register is set high then the internal 1.19V
will be routed to the A/D Converter.
Rev. 1.20
62
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
ADCR1 Register
Bit
7
6
5
4
3
2
1
0
Name
ACS4
V119EN
—
VREFS
—
ADCK2
ADCK1
ADCK0
R/W
R/W
R/W
—
R/W
—
R/W
R/W
R/W
POR
0
0
—
0
—
0
0
0
Bit 7ACS4: Select Internal 1.19V as A/D Converter input Control
0: Disable
1: Enable
This bit enables 1.19V to be connected to the A/D converter. The V119EN bit must
first have been set to enable the bandgap circuit 1.19V voltage to be used by the A/D
converter. When the ACS4 bit is set high, the bandgap 1.19V voltage will be routed to
the A/D converter and the other A/D input channels disconnected.
Bit 6V119EN: Internal 1.19V Control
0: Disable
1: Enable
This bit controls the internal bandgap circuit on/off function to the A/D converter.
When the bit is set high the bandgap 1.19V voltage can be used by the A/D converter.
If 1.19V is not used by the A/D converter and the LVR function is disabled then the
bandgap reference circuit will be automatically switched off to conserve power. When
1.19V is switched on for use by the A/D converter, a time tBG should be allowed for the
bandgap circuit to stabilise before implementing an A/D conversion.
Bit 5
Unimplemented, read as "0"
Bit 4VREFS: Select A/D Converter reference voltage
0: Internal A/D Converter power
1: VREF pin
This bit is used to select the reference voltage for the A/D converter. If the bit is high
then the A/D converter reference voltage is supplied on the external VREF pin. If the
pin is low then the internal reference is used which is taken from the power supply pin
VDD.
Rev. 1.20
Bit 3
Unimplemented, read as "0"
Bit 2 ~ 0
ADCK2 ~ ADCK0: Select A/D Converter clock source
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: Undefined
These three bits are used to select the clock source for the A/D converter.
63
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
ACERL Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
ACE3
ACE2
ACE1
ACE0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
1
1
1
1
Bit 7~ 4
Unimplemented, read as "0"
Bit 3ACE3: Define PD3 is A/D input or not
0: Not A/D input
1: A/D input, AN3
Bit 2ACE2: Define PD2 is A/D input or not
0: Not A/D input
1: A/D input, AN2
Bit 1ACE1: Define PD1 is A/D input or not
0: Not A/D input
1: A/D input, AN1
Bit 0ACE0: Define PD0 is A/D input or not
0: Not A/D input
1: A/D input, AN0
A/D Operation
The START bit in the ADCR0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset.
It is the START bit that is used to control the overall start operation of the internal analog to digital
converter.
The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to "0" by the microcontroller after a
conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set
in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
ADCK2~ADCK0 bits in the ADCR1 register.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0,
there are some limitations on the maximum A/D clock source speed that can be selected. As the
minimum value of permissible A/D clock period, tADCK, is from 0.5μs to 100μs, care must be taken
for system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the
ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D clock periods that
are less than the minimum A/D clock period or greater than the maximum A/D clock period which
may result in inaccurate A/D conversion values.
Refer to the following table for examples, where values marked with an asterisk * show where,
depending upon the device, special care must be taken, as the values may be less than the specified
minimum A/D Clock Period.
Rev. 1.20
64
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
A/D Clock Period (tADCK)
fSYS
1MHz
ADCK2,
ADCK1,
ADCK0
=000
(fSYS)
ADCK2,
ADCK1,
ADCK0
=001
(fSYS/2)
ADCK2,
ADCK1,
ADCK0
=010
(fSYS/4)
ADCK2,
ADCK1,
ADCK0
=011
(fSYS/8)
ADCK2,
ADCK1,
ADCK0
=100
(fSYS/16)
ADCK2,
ADCK1,
ADCK0
=101
(fSYS/32)
ADCK2,
ADCK1,
ADCK0
=110
(fSYS/64)
ADCK2,
ADCK1,
ADCK0
=111
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
Undefined
2MHz
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
Undefined
4MHz
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
Undefined
8MHz
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
Undefined
12MHz
83ns*
167ns*
333ns*
667ns
1.33μs
2.67μs
5.33μs
Undefined
16MHz
62.5ns*
125ns*
250ns*
500ns
1μs
2μs
4μs
Undefined
A/D Clock Period Examples
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the
ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no
pins are selected for use as A/D inputs by clearing the ACE3~ACE0 bits in the ACERL registers, if
the ADOFF bit is zero then some power will still be consumed. In power conscious applications it
is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D
converter function is not being used.
The reference voltage supply to the A/D Converter can be supplied from either the positive power
supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection
is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS
bit is set high, the VREF pin function will be selected and the other pin functions will be disabled
automatically.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port D as well as other
functions. The ACE3~ACE0 bits in the ACERL registers, determine whether the input pins are setup
as A/D converter analog inputs or whether they have other functions. If the ACE3~ACE0 bits for its
corresponding pin is set high then the pin will be setup to be an A/D converter input and the original
pin functions disabled. In this way, pins can be changed under program control to change their
function between A/D inputs and other functions. All pull-high resistors, which are setup through
register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note
that it is not necessary to first setup the A/D pin as an input in the PDC port control register to enable
the A/D input as when the ACE3~ACE0 bits enable an A/D input, the status of the port control
register will be overridden.
The A/D converter has its own reference voltage pin, VREF, however the reference voltage can
also be supplied from the power supply pin, a choice which is made through the VREFS bit in the
ADCR1 register. The analog input values must not be allowed to exceed the value of VREF.
Rev. 1.20
65
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
        A/D Input Structure
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the
ADCR1 register.
• Step 2
Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero.
• Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming
the ACS4, ACS1~ACS0 bits which are also contained in the ADCR1 and ADCR0 register.
• Step 4
Select which pins are to be used as A/D inputs and configure them by correctly programming the
ACE3~ACE0 bits in the ACERL register.
• Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to
ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and
the A/D converter interrupt bit, ADE, must both be set high to do this.
• Step 6
The analog to digital conversion process can now be initialised by setting the START bit in
the ADCR0 register from low to high and then low again. Note that this bit should have been
originally cleared to zero.
• Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0
register can be polled. The conversion process is complete when this bit goes low. When this
occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an
alternative method, if the interrupts are enabled and the stack is not full, the program can wait for
an A/D interrupt to occur.
Note: When checking for the end of the conversion process, if the method of polling the EOCB bit
in the ADCR0 register is used, the interrupt enable step above can be omitted.
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16 tADCK where tADCK is equal to the A/D clock period.
Rev. 1.20
66
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
ƒ ƒ
„  ­
‚

‚   ­  
  ­                ­   ­  €  ­
  A/D Conversion Timing
Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the
ADCR0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.
A/D Transfer Function
As the device contains a 12-bit A/D converter, its full-scale converted digitized value is equal to
FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single
bit analog input value of VDD or VREF divided by 4096.
1 LSB= (VDD or VREF) / 4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage = A/D output digital value × (VDD or VREF) / 4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitized value will change at a point 1.5 LSB below the VDD or VREF level.
    
 
      Ideal A/D Transfer Function
Rev. 1.20
67
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
A/D Programming Examples
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion
clr ADE
;
mov a,03H
mov ADCR1,a ;
clr ADOFF
mov a,0Fh ;
mov ACERL,a
mov a,01h
mov ADCR0,a ;
:
start_conversion:
clr START ;
set START ;
clr START ;
polling_EOC:
sz EOCB ;
jmp polling_EOC ;
mov a,ADRL ;
mov ADRL_buffer,a ;
mov a,ADRH ;
mov ADRH_buffer,a ;
:
:
jmp start_conversion ;
Rev. 1.20
disable A/D Converter interrupt
select fSYS/8 as A/D clock and switch off 1.19V
setup ACERL to configure pins AN0~AN3
enable and connect AN0 channel to A/D converter
high pulse on start bit to initiate conversion
reset A/D
start A/D
poll the ADCR0 register EOCB bit to detect end of A/D conversion
continue polling
read low byte conversion result value
save result to user defined register
read high byte conversion result value
save result to user defined register
start next A/D conversion
68
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Example: using the interrupt method to detect the end of conversion
clr ADE ; disable A/D Converter interrupt
mov a,03H
mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.19V
clr ADOFF
mov a,0Fh ; setup ACERL to configure pins AN0~AN3
mov ACERL,a
mov a,01h
mov ADCR0,a ; enable and connect AN0 channel to A/D converter
Start_conversion:
clr START ; high pulse on START bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear A/D Converter interrupt request flag
set ADE ; enable A/D Converter interrupt
set EMI ; enable global interrupt
:
:
; A/D Converter interrupt service routine
ADC_ISR:
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
:
mov a,ADRL ; read low byte conversion result value
mov adrl_buffer,a ; save result to user defined register
mov a,ADRH ; read high byte conversion result value
mov adrh_buffer,a ; save result to user defined register
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti
Rev. 1.20
69
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key Function
This device provides multiple touch key functions. The touch key function is fully integrated and
requires no external components, allowing touch key functions to be implemented by the simple
manipulation of internal registers.
Touch Key Structure
The touch keys are pin shared with the PB logic I/O pins, with the desired function chosen via
register bits. Keys are organized into groups of two, with each group known as a module and having
a module number, M0 to M1(M1 only exists two keys). Each module is a fully independent set of
four Touch Keys (M1 only exists two keys) and each Touch Key has its own oscillator. Each module
contains its own control logic circuits and register set. Examination of the register names will reveal
the module number it is referring to.
Keys - n
Touch Key Module
Touch Key
Shared I/O Pin
M0
K1~K4
PB0~PB3
M1
K5~K6
PB4~PB5
6
KEY 1
Key
OSC
TKMn16DL/H
( to RAM)
MnFILEN
KEY 2
Key
OSC
Mux .
KEY 3
Key
5MHz
Analog
Filter
Multifrequency
fCFTMCK
TKCFOV
16-bit C/F counter
OSC
MnDFEN
KEY 4
Key
OSC
TKMnC2
TKMnROL/H
( from RAM)
MnFILEN
Ref OSC
5MHz
Analog
Filter
MnTSS
TKTMR
fsys/4
Mux .
8-bit time slot
timer counter
5- bit counter
TKRCOV
Module 0
Module n
TKTMR
fSYS/1, fSYS/2, fSYS/4, fSYS/8
8-bit time slot timer
counter preload register
Mux .
Overflow
16-bit counter
TK16OV
Touch
Key
RAM
TK16DL/TK16DH
TK16S1~0
Note: 1: Each touch key module contains the content in the red dash line.
2. The content in the black dash line is the module number (0~n), each module contains 4 or 2
touch keys.
Touch Key Module Block Diagram (n=0~1)
Rev. 1.20
70
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key Register Definition
Each touch key module, which contains four or two touch key functions, has its own suite registers.
The following table shows the register set for this touch key module. The Mn within the register
name refers to the Touch Key module number, this device has a range of M0 to M1.
Register
Name
Bit
7
6
5
4
3
2
1
0
TKTMR
D7
D6
D5
D4
D3
D2
D1
D0
TKC0
—
TKRCOV
TKST
TKCFOV
TK16OV
TSCS
TK16S1
TK16S0
D0
TK16DL
D7
D6
D5
D4
D3
D2
D1
TK16DH
D15
D14
D13
D12
D11
D10
D9
D8
—
—
—
—
—
—
TKFS1
TKFS0
TKC1
TKMn16DL
D7
D6
D5
D4
D3
D2
D1
D0
TKMn16DH
D15
D14
D13
D12
D11
D10
D9
D8
TKMnROL
D7
D6
D5
D4
D3
D2
D1
D0
TKMnROH
—
—
—
—
—
—
D9
D8
TKM0C0
M0MXS1
M0MXS0
M0DFEN
M0FILEN
M0SOFC
M0SOF2
M0SOF1
M0SOF0
TKM0C1
M0TSS
—
M0ROEN
M0KOEN
M0K4IO
M0K3IO
M0K2IO
M0K1IO
TKM1C0
—
M1MXS0
M1DFEN
M1FILEN
M1SOFC
M1SOF2
M1SOF1
M1SOF0
TKM1C1
M1TSS
—
M1ROEN
M1KOEN
—
—
M1K2IO
M1K1IO
Touch Key Register List (n=0~1)
TKTMR Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Touch Key 8-bit timer/counter register
Time slot counter overflow set-up time is (256-TKTMR[7:0]) x 32
TKC0 Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
—
TKRCOV
TKST
TKCFOV
TK16OV
TSCS
TK16S1
TK16S0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7 Unimplemented, read as "0"
Bit 6
TKRCOV: Time slot counter overflow flag
0: No overflow
1: Overflow
If module 0 or all module (select by TSCS bit) time slot counter is overflow, the Touch
Key Interrupt request flag will be set (TKMF) and all module key OSC and ref OSC
auto stop. All module 16-bit C/F counter, 16-bit counter, 5-bit time slot counter and
8-bit time slot timer counter will be automatically switched off.
Note: Software can set this bit to 1, but touch key interrupt request flag can not be set.
This bit must be clear by software.
71
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Bit 5
TKST: Start Touch Key detection control bit
0: Stopped
0->1: Started
In all modules the16-bit C/F counter, 16-bit counter, 5-bit time slot counter will
be automatically cleared when this bit is cleared to "0" (8-bit programmable time
slot counter will not be cleared, which overflow time is setup by user). When this
bit changes from low to high, the 16-bit C/F counter, 16-bit counter, 5-bit time slot
counter and 8-bit time slot timer counter will be automatically on and enable key OSC
and ref OSC output clock input these counter.
Bit 4
TKCFOV: Touch key module 16-bit C/F counter overflow flag
0: Not overflow
1: Overflow
This bit must be cleared by software.
Bit 3
TK16OV: Touch key module 16-bit counter overflow flag
0: Not overflow
1: Overflow
This bit must be cleared by software.
Bit 2
TSCS: Touch Key time slot counter select
0: Each Module use own time slot counter.
1: All Touch Key Module use Module 0 time slot counter.
Bit 1~0
TK16S1~ TK16S0: The touch key module 16-bit counter clock source select
00: fSYS
01: fSYS/2
10: fSYS/4
11: fSYS/8
TKC1 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
TKFS1
TKFS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
1
1
Bit 7 ~2
Unimplemented, read as "0"
Bit 1~0
TKFS1~TKFS0: Touch key OSC frequency select
00: 500kHz
01: 1000kHz
10: 1500kHz
11: 2000kHz
TK16DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Touch key module 16-bit counter low byte contents
TK16DH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D15~D8: Touch key module 16-bit counter high byte contents
Rev. 1.20
72
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
TKMn16DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Module n 16-bit counter low byte contents
TKMn16DH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0D15~D8: Module n 16-bit counter high byte contents
TKMnROL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Reference OSC internal capacitor select
OSC internal capacitor select : (TKMnRO[9:0] x 50pF) / 1024
TKMnROH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7 ~2
Unimplemented, read as "0"
Bit 1~0D9~D8: Reference OSC internal capacitor select
OSC internal capacitor select: (TKMnRO[9:0] x 50pF) / 1024
TKM0C0 Register
Bit
Name
7
6
5
4
3
2
M0MXS1 M0MXS0 M0DFEN M0FILEN M0SOFC M0SOF2
1
0
M0SOF1
M0SOF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~6M0MXS1~M0MXS0: Multiplexer key select
00: KEY1
01: KEY2
10: KEY3
11: KEY4
Bit 5M0DFEN: Multi-frequency control
0: Disable
1: Enable
Bit 4M0FILEN: Filter function control
0: Disable
1: Enable
Rev. 1.20
73
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Bit 3M0SOFC: C to F OSC frequency hopping function control
0: The frequency hopping function is controlled by M0SOF2~ M0SOF0 bits
1: The frequency hoping function is controlled by hardware and regardless of what
is the state of M0SOF2~ M0SOF0 bits
Bit 2~0
M0SOF2~ M0SOF0: Selecting key OSC and ref OSC frequency as C to F OSC is
controlled by software
000: 1380kHz
001: 1500kHz
010: 1670kHz
011: 1830kHz
100: 2000kHz
101: 2230kHz
110: 2460kHz
111: 2740kHz
The frequency which is mentioned here will be changed when the external or internal
capacitor is with different value. If the touch key operates at 2MHz frequency, users
can adjust the frequency in scale when select other frequency.
TKM0C1 Register
Bit
7
6
Name
M0TSS
—
5
R/W
R/W
—
R/W
POR
0
—
0
4
3
2
1
0
M0K4IO
M0K3IO
M0K2IO
M0K1IO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
M0ROEN M0KOEN
Bit 7 M0TSS: Time slot counter clock select
0: Reference oscillator
1: fSYS/4
Bit 6
Unimplemented, read as "0"
Bit 5M0ROEN: Reference OSC control
0: Disable
1: Enable
Bit 4M0KOEN: Key OSC control
0: Disable
1: Enable
Rev. 1.20
Bit 3
M0K4IO: Touch key 4 control
0: Disable
1: Enable
Bit 2
M0K3IO: Touch key 3 control
0: Disable
1: Enable
Bit 1
M0K2IO: Touch key 2 control
0: Disable
1: Enable
Bit 0
M0K1IO: Touch key 1 control
0: Disable
1: Enable
74
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
TKM1C0 Register
Bit
7
Name
—
6
5
4
3
R/W
—
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
2
1
0
M1SOF1
M1SOF0
R/W
R/W
R/W
0
0
0
M1MXS0 M1DFEN M1FILEN M1SOFC M1SOF2
Bit 7
Unimplemented, read as "0"
Bit 6M1MXS0: Multiplexer key select
0: KEY 5
1: KEY 6
Bit 5M1DFEN: Multi-frequency control
0: Disable
1: Enable
Bit 4M1FILEN: Filter function control
0: Disable
1: Enable
Bit3M1SOFC: C to F OSC frequency hopping function control
0: The frequency hopping function is controlled by M1SOF2~ M1SOF0 bits
1: The frequency hopping function is controlled by hardware regardless of what is
the state of M1SOF2~ M1SOF0 bits
Bit 2~0
M1SOF2~ M1SOF0: Selecting key OSC and ref OSC frequency as C to F OSC is
controlled by software
000: 1380kHz
001: 1500kHz
010: 1670kHz
011: 1830kHz
100: 2000kHz
101: 2230kHz
110: 2460kHz
111: 2740kHz
The frequency which is mentioned here will be changed when the external or internal
capacitor is with different value. if the touch key operates at 2MHz frequency, users
can adjust the frequency in scale when select other frequency.
TKM1C1 Register
Bit
7
6
Name
M1TSS
—
5
R/W
R/W
—
R/W
POR
0
—
0
4
3
2
1
0
—
—
M1K2IO
M1K1IO
R/W
—
—
R/W
R/W
0
—
—
0
0
M1ROEN M1KOEN
Bit 7 M1TSS: Time slot counter clock select
0: Reference oscillator
1: fSYS/4
Bit 6
Unimplemented, read as "0"
Bit 5M1ROEN: Reference OSC control
0: Disable
1: Enable
Bit 4M1KOEN: Key OSC control
0: Disable
1: Enable
Bit 3~2
Unimplemented, read as "0"
Bit 1
M1K2IO: Touch key 6 control
0: Disable
1: Enable
Bit 0
M1K1IO: Touch key 5 control
0: Disable
1: Enable
Rev. 1.20
75
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key Operation
When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase.
By using this capacitance variation to change slightly the frequency of the internal sense oscillator,
touch actions can be sensed by measuring these frequency changes. Using an internal programmable
divider the reference clock is used to generate a fixed time period. By counting the number of
generated clock cycles from the sense oscillator during this fixed time period touch key actions can
be determined.
Each touch key module contains four or two touch key inputs which are either dedicated touch key
pins or are shared logical I/O pins. If shared, the desired function is selected using register bits. Each
touch key has its own independent sense oscillator. There are therefore four or two sense oscillators
within each touch key module.
During this reference clock fixed interval, the number of clock cycles generated by the sense
oscillator is measured, and it is this value that is used to determine if a touch action has been made
or not. At the end of the fixed reference clock time interval, a Touch Key interrupt signal will be
generated.
The touch key sense oscillator and reference oscillator timing diagram is shown in the following
figure:
TKST
�nKOEN
�nROEN
Hardware Set to "0"
KEY OSC CLK
Reference OSC CLK
2�6-TKT�R overflow
fCFT�CK Enable
�2
fCFT�CK (�nDFEN=0)
fCFT�CK (�nDFEN=1)
TKRCOV
Set Touch Ke�
interrupt request flag
Touch Key Timing Diagram
Rev. 1.20
76
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key Interrupt
The touch key only has single interrupt, when the time slot counter in all the touch key modules or
in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys
mentioned here are the keys which are enabled. The16-bit C/F counter, 16-bit counter, 5-bit time slot
counter and 8-bit time slot counter in all modules will be automatically cleared.
The TKCFOV flag, which is the 16-bit C/F counter overflow flag will go high when any of the
Touch Key Module 16-bit C/F counter overflows. As this flag will not be automatically cleared, it
has to be cleared by the application program.
The module 0 only contains one 16-bit counter. The TK16OV flag, which is the 16-bit counter
overflow flag will go high when the 16-bit counter overflows. As this flag will not be automatically
cleared, it has to be cleared by the application program. More details regarding the touch key
interrupt is located in the interrupt section of the datasheet.
Programming Considerations
After the relevant registers are setup, the touch key detection process is initiated the changing the
TKST bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV
flag, which is the time slot counter flag will go high and remain high until the counter overflows.
When this happens an interrupt signal will be generated.
When the external touch key size and layout are defined, their related capacitances will then
determine the sensor oscillator frequency.
Rev. 1.20
77
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Serial Interface Module – SIM
This device contains a Serial Interface Module, which include both the four line SPI interface and
the two line I2C interface types, to allow an easy method of communication with external peripheral
hardware. Having relatively simple communication protocols, these serial interface types allow the
microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash memory
or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and must be
selected using the SIMEN bit in the SIMC0 register. As both interface types share the same pins and
registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode
control bits, named SIM2~SIM0, in the SIMC0 register.
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the device can be
either master or slave. Although the SPI interface specification can control multiple slave devices
from a single master, but this device provided only one SCS pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pin to select the slave devices.
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data
Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins
are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be
enabled by setting the correct bits in the SIMC0 and SIMC2 registers. Communication between
devices connected to the SPI interface is carried out in a slave/master mode with all data transfer
initiations being implemented by the master. The Master also controls the clock signal. As the device
only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by
software, set CSEN bit to "1" to enable SCS pin function, set CSEN bit to "0" the SCS pin will be as
I/O function.
SPI Master/Slave Connection
Rev. 1.20
78
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU

    ­    
€ ‚ ƒ „ …
  SPI Block Diagram
The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN and
SIMEN.
SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These are
the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only
used by the I2C interface.
Bit
Register
Name
7
6
5
SIMC0
SIM2
SIM1
SIM0
—
SIMD
D7
D6
D5
D4
SIMC2
—
—
CKPOLB
CKEG
MLS
4
3
2
1
0
—
—
SIMEN
—
D3
D2
D1
D0
CSEN
WCOL
TRF
SIM Registers List
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
Rev. 1.20
79
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
SIMD Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x" unknown
There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2
register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used
by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable
function and to set the data transmission clock frequency. Although not connected with the SPI
function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2
is used for other control functions such as LSB/MSB selection, write collision flag etc.
SIMC0 Register
Bit
7
6
5
4
3
2
1
0
Name
SIM2
SIM1
SIM0
—
—
—
SIMEN
—
R/W
R/W
R/W
R/W
—
—
—
R/W
—
POR
1
1
1
—
—
—
0
—
Bit 7 ~ 5 Rev. 1.20
SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is TIMER overflow frequency/2
101: SPI slave mode
110: I2C mode
111: Reserved
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock but
can also be chosen to be sourced from the fSUB or Timer/Event counter. If the SPI Slave
Mode is selected then the clock will be supplied by an external Master device.
Bit 4~2
unimplemented, read as "0"
Bit 1
SIMEN: SIM Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA
and SCL lines will be as I/O function and the SIM operating current will be reduced
to a minimum value. If the SIM is configured to operate as an SPI interface via the
SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous
settings when the SIMEN bit changes from low to high and should therefore be first
initialised by the application program. If the SIM is configured to operate as an I2C
interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the
contents of the I2C control bits such as HTX and TXAK will remain at the previous
settings and should therefore be first initialised by the application program while the
relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their
default states.
Bit 0 Unimplemented, read as "0"
80
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
SIMC2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5
CKPOLB: Determines the base condition of the clock line
0: the SCK line will be high when the clock is inactive
1: the SCK line will be low when the clock is inactive
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4
CKEG: Determines SPI SCK active clock edge type
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive.
Bit 3 MLS: SPI Data shift order
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Bit 2CSEN: SPI SCS pin Control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the
SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS
pin will be enabled and used as a select pin.
Bit 1WCOL: SPI Write Collision flag
0: No collision
1: Collision
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it
means that data has been attempted to be written to the SIMD register during a data
transfer operation. This writing operation will be ignored if data is being transferred.
The bit can be cleared by the application program.
Bit 0TRF: SPI Transmit/Receive Complete flag
0: Data is being transferred
1: SPI data transmission is completed
The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when
an SPI data transmission is completed, but must set to "0" by the application program.
It can be used to generate an interrupt.
Rev. 1.20
81
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the TRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into
the SIMD register. The master should output an SCS signal to enable the slave device before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG
bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal
for various configurations of the CKPOLB and CKEG bits.
The SPI will continue to function even in the IDLE Mode.
          ­
 €  ‚
 ‚  €
 ­    
  
         ­
 €  ‚
 ‚  €
 ­    
  
   ƒ „ 
SPI Master Mode Timing
        ­€   SPI Slave Mode Timing – CKEG=0
Rev. 1.20
82
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
               ­  €‚   € ƒ „ …  ‚ † ‡ ˆ ‰€  Š ƒ  ˆ Š ƒ ‰  ‚ ‹   Œ ‚ ˆ
 ˆ     ‚ † ‚Ž
SPI Slave Mode Timing – CKEG=1

  †‡ ˆ‰ Š ‰ ‰ ‰ „
‰ ‰ „‰ ‰ „‰ ‰ ‰  †‡ ˆ‰ Š ‰ ­ € ‚ ƒ „
‚ … „  
 

   SPI Transfer Control Flowchart
Rev. 1.20
83
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Master/Slave Bus Connection
I2C Interface Operation
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I2C bus is identified by a unique address which
will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For this device, which only
operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
The debounce time of the I2C interface uses the system clock to in effect add a debounce time to the
external clock to reduce the possibility of glitches on the clock line causing erroneous operation.
The debounce time, is 2 system clocks. To achieve the required I2C data transfer speed, there exists
a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard
or Fast mode operation, users must take care of the selected system clock frequency and the
configured debounce time to match the criterion shown in the following table.
I2C Debounce Time Selection
I2C Standard Mode (100kHz)
I2C Fast Mode (400kHz)
fSYS > 4MHz
fSYS > 10MHz
2 system clock debounce
I C Minimum fSYS Frequency
2
Rev. 1.20
84
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
S T A R T s ig n a l
fro m M a s te r
S e n d s la v e a d d r e s s
a n d R /W b it fr o m M a s te r
A c k n o w le d g e
fr o m s la v e
S e n d d a ta b y te
fro m M a s te r
A c k n o w le d g e
fr o m s la v e
S T O P s ig n a l
fro m M a s te r
I2C Registers
There are four control registers associated with the I2C bus, SIMC0, SIMC1, SIMA and I2CTOC
and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to
store the data being transmitted and received on the I2C bus. Before the microcontroller writes data
to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is
received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission
or reception of data from the I2C bus must be made via the SIMD register. The SIM pins are pin
shared with other I/O pins and must be selected using the SIMEN bit in the SIMC0 register.
Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN
and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface.
Bit
Register
Name
7
6
5
4
3
2
1
0
SIMC0
SIM2
SIM1
SIM0
—
—
—
SIMEN
—
SIMC1
HCF
HAAS
HBB
HTX
TXAK
SRW
RNIC
RXAK
SIMD
D7
D6
D5
D4
D3
D2
D1
D0
SIMA
A6
A5
A4
A3
A2
A1
A0
—
I2CTOC
I2CTOEN
I2CTOF
I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0
I2C Registers List
Rev. 1.20
85
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
SIMC0 Register
Bit
7
6
5
4
3
2
1
0
Name
SIM2
SIM1
SIM0
—
—
—
SIMEN
—
R/W
R/W
R/W
R/W
—
—
—
R/W
—
POR
1
1
1
—
—
—
0
—
Bit 7 ~ 5 SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is TIMER Overflow frequency/2
101: SPI slave mode
110: I2C mode
111: Reserved
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock but
can also be chosen to be sourced from the fSUB or Timer/Event counter. If the SPI Slave
Mode is selected then the clock will be supplied by an external Master device.
Bit 4~2
unimplemented, read as "0"
Bit 1
SIMEN: SIM Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared
to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines
will be as I/O function and the SIM operating current will be reduced to a minimum
value. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the
contents of the SPI control registers will remain at the previous settings when the SIMEN
bit changes from low to high and should therefore be first initialised by the application
program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits
and the SIMEN bit changes from low to high, the contents of the I2C control bits such
as HTX and TXAK will remain at the previous settings and should therefore be first
initialised by the application program while the relevant I2C flags such as HCF, HAAS,
HBB, SRW and RXAK will be set to their default states.
Bit 0 Unimplemented, read as "0"
SIMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
HCF
HAAS
HBB
HTX
TXAK
SRW
RNIC
RXAK
R/W
R
R
R
R/W
R/W
R
R/W
R
POR
1
0
0
0
0
0
0
1
Bit 7 HCF: I C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
2
Bit 6HAAS: I2C Bus address match flag
0: Not address match
1: Address match
The HAAS flag is the address match flag. This flag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match then
this bit will be high, if there is no match then the flag will be low.
Rev. 1.20
86
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Bit 5HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which
will occur when a START signal is detected. The flag will be set to "0" when the bus is
free which will occur when a STOP signal is detected.
Bit 4HTX: Select I2C slave device is transmitter or receiver
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3
TXAK: I2C Bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave do not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits
of data, this bit will be transmitted to the bus on the 9th clock from the slave device.
The slave device must always set TXAK bit to "0" before further data is received.
Bit 2
SRW: I2C Slave Read/Write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus. When the
transmitted address and slave address is match, that is when the HAAS flag is set high,
the slave device will check the SRW flag to determine whether it should be in transmit
mode or receive mode. If the SRW flag is high, the master is requesting to read data
from the bus, so the slave device should be in transmit mode. When the SRW flag
is zero, the master will write data to the bus, therefore the slave device should be in
receive mode to read this data.
Bit 1RNIC: I2C running using Internal Clock Control
0: I2C running using internal clock
1: I2C running not using Internal Clock
The I2C module can run without using internal clock, and generate an interrupt
if the SIM interrupt is enabled, which can be used in SLEEP Mode, IDLE Mode,
NORMAL(SLOW) Mode. If this bit is set to "1" and MCU is in "HALT", slavereceiver can work well but slave-transmitter doesn’t work since it needs system clock .
Bit 0
Rev. 1.20
RXAK: I2C Bus Receive acknowledge flag
0: Slave receive acknowledge flag
1: Slave do not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it
means that a acknowledge signal has been received at the 9th clock, after 8 bits of data
have been transmitted. When the slave device in the transmit mode, the slave device
checks the RXAK flag to determine if the master receiver wishes to receive the next
byte. The slave transmitter will therefore continue sending out data until the RXAK
flag is "1". When this occurs, the slave transmitter will release the SDA line to allow
the master to send a STOP signal to release the I2C Bus.
87
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the
device can read it from the SIMD register. Any transmission or reception of data from the I2C bus
must be made via the SIMD register.
SIMD Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x" unknown
SIMA Register
Bit
7
6
5
4
3
2
1
0
Name
A6
A5
A4
A3
A2
A1
A0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
POR
0
0
0
0
0
0
0
0
Bit 7~1 A6~A0: I2C slave address
A6~ A0 is the I2C slave address bit 6 ~ bit 0.
The SIMA register is also used by the SPI interface but has the name SIMC2. The
SIMA register is the location where the 7-bit slave address of the slave device is
stored. Bits 7~ 1 of the SIMA register define the device slave address. Bit 0 is not
defined.
When a master device, which is connected to the I2C bus, sends out an address, which
matches the slave address in the SIMA register, the slave device will be selected. Note
that the SIMA register is the same register address as SIMC2 which is used by the SPI
interface.
Bit 0
Unimplemented, read as "0"
† ‡ ‡ Š ­ …
    ‚  ƒ  €
     ˆ ‰  ­   
   „   „ I2C Block Diagram
Rev. 1.20
88
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival
of data on the bus. The first seven bits of the data will be the slave address with the first bit being
the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit
in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt
service routine, the slave device must first check the condition of the HAAS and I2CTOF bit to
determine whether the interrupt source originates from an address match or from the completion
of an 8-bit data transfer or an I2C time-out condition. During a data transfer, note that after the
7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit
whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine
whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the
microcontroller must initialise the bus, the following are steps to achieve this:
Step 1
Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "110" and "1" respectively to enable
the I2C bus.
Step 2
Write the slave address of the device to the I2C bus address register SIMA.
Step 3
Set the SIME interrupt enable bit of the interrupt control register to enable the SIM interrupt.
  
 € ‚  ƒ „ … † ‚    ­
  ­
I2C Bus Initialisation Flow Chart
I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by the
slave device. This START signal will be detected by all devices connected to the I2C bus. When detected,
this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs
when a high to low transition on the SDA line takes place when the SCL line remains high.
Rev. 1.20
89
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines
the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will
then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set
the status flag HAAS when the addresses match.
As an I 2C bus interrupt can come from two sources, when the program enters the interrupt
subroutine, the HAAS and I2CTOF bit should be examined to see whether the interrupt source has
come from a matching slave address or from the completion of a data byte transfer or an I2C timeout condition. When a slave address is matched, the device must be placed in either the transmit
mode and then write data to the SIMD register, or in the receive mode where it must implement a
dummy read from the SIMD register to release the SCL line.
I2C Bus Read/Write Signal
The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the
I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to
be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes
to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as
a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C
bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. The
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the HAAS flag is high, the addresses have matched and the slave
device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag
is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register
should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as
a receiver and the HTX bit in the SIMC1 register should be set to "0".
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt
of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After
receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can
receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from
the master receiver, then the slave transmitter will release the SDA line to allow the master to send
a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register.
If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD
register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the SIMC1 register to determine if it is to send another data byte, if not then it will release the
SDA line and await the receipt of a STOP signal from the master.
Rev. 1.20
90
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
€

€

­
         ­ I C Communication Timing Diagram
2
Note: *When a slave address is matched, the device must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a
dummy read from the SIMD register to release the SCL line.
          I2C Bus ISR Flow Chart
Rev. 1.20
91
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
I2C Time-out Control
In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, clock, a
time-out function is provided. If the clock source to the I2C is not received then after a fixed time
period, the I2C circuitry and registers will be reset.
The time-out counter starts counting on an I2C bus "START" & "address match" condition, and
is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is
greater than the time-out setup by the I2CTOC register, then a time-out condition will occur. The
time-out function will stop when an I2C "STOP" condition occurs.
When an I2C time-out counter overflow occurs, the counter will stop and the I2CTOEN bit will be
cleared to zero and the I2CTOF bit will be set high to indicate that a time-out condition as occurred.
The time-out condition will also generate an interrupt which uses the I2C interrupt vector. When an
I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the
following condition:
Register
After I2C Time-out
SIMD, SIMA, SIMC0
No change
SIMC1
Reset to POR condition
I2C Registers After Time-out
The I2CTOF flag can be cleared by the application program. There are 64 time-out periods which
can be selected using bits in the I2CTOC register. The time-out time is given by the formula:
((1~64) × 32) / fSUB.
This gives a range of about 1ms to 64ms. Note also that the LIRC oscillator is continuously enabled.
I2CTOC Register
Bit
7
6
Name
I2CTOEN
I2CTOF
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0
Bit 7 I2CTOEN: I2C Time-out Control
0: Disable
1: Enable
Bit 6
I2CTOF: Time-out flag
0: No time-out
1: Time-out occurred
Bit 5~0I2CTOS5~I2CTOS0: Time-out Definition
I2C time-out clock source is fSUB/32.
I2C time-out time is given by: ([I2CTOS5 : I2CTOS0]+1) x (32/fSUB)
Rev. 1.20
92
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Touch Action or Timer/Event Counter overflow requires microcontroller
attention, their corresponding interrupt will enforce a temporary suspension of the main program
allowing the microcontroller to direct attention to their respective needs. The device contains several
external interrupt and internal interrupts functions. The external interrupt is generated by the action
of the external INT pin, while the internal interrupts are generated by various internal functions such
as the Touch Keys, Timer/Event Counter, Time Base, SIM etc.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the
accompanying table. The number of registers fall into two categories. The first is the INTC0~INTC1
registers which setup the primary interrupts, the second is the INTEG registers to setup the external
interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual registers as well as
interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an "E" for enable/disable bit or "F" for request flag.
Function
Enable Bit
Request Flag
Global
EMI
—
INT Pin
INTE
INTF
Touch Key Module
TKME
TKMF
Timer/Event Counter
SIM
TE
TF
SIME
SIMF
Time Base
TBE
TBF
EEPROM
DEE
DEF
A/D Converter interrupt
ADE
ADF
Interrupt Register Bit Naming Conventions
Interrupt Register Contents
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
INTEG
—
—
—
—
—
—
INTS1
INTS0
INTC0
—
TF
TKMF
INTF
TE
TKME
INTE
EMI
INTC1
ADF
DEF
TBF
SIMF
ADE
DEE
TBE
SIME
INTEG Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
INTS1
INTS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7 ~ 2 Unimplemented, read as "0"
Bit 1 ~ 0
INTS1, INTS0: Defines INT interrupt active edge
00: Disabled interrupt
01: Rising Edge interrupt
10: Falling Edge interrupt
11: Dual Edge interrupt
93
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
TF
TKMF
INTF
TE
TKME
INTE
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6
TF: Timer/Event Counter interrupt request flag
0: No request
1: Interrupt request
Bit 5
TKMF: Touch key module interrupt request flag
0: No request
1: Interrupt request
Bit 4
INTF: INT pin interrupt request flag
0: No request
1: Interrupt request
Bit 3 TE: Timer/Event Counter interrupt control
0: Disable
1: Enable
Bit 2
TKME: Touch key module interrupt control
0: Disable
1: Enable
Bit 1
INTE: INT pin interrupt control
0: Disable
1: Enable
Bit 0EMI: Global Interrupt control
0: Disable
1: Enable
INTC1 Register
Rev. 1.20
Bit
7
6
5
4
3
2
1
0
Name
ADF
DEF
TBF
SIMF
ADE
DEE
TBE
SIME
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
ADF: A/D Converter interrupt request flag
0: No request
1: Interrupt request
Bit 6
DEF: Data EEPROM interrupt request flag
0: No request
1: Interrupt request
Bit 5
TBF: Time Base interrupt request flag
0: No request
1: Interrupt request
Bit 4
SIMF:SIM interrupt request flag
0: No request
1: Interrupt request
Bit 3 ADE: A/D Converter Interrupt control
0: Disable
1: Enable
Bit 2
DEE: Data EEPROM control
0: Disable
1: Enable
94
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Bit 1
TBE: Time Base interrupt control
0: Disable
1: Enable
Bit 0
SIME: SIM interrupt control
0: Disable
1: Enable
Interrupt Operation
When the conditions for an interrupt event occur, such as a Touch Key Counter overflow, Timer/
Event Counter overflow, etc, the relevant interrupt request flag will be set. Whether the request flag
actually generates a program jump to the relevant interrupt vector is determined by the condition of
the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector;
if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be
generated and the program will not jump to the relevant interrupt vector. The global interrupt enable
bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a "JMP" which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a "RETI", which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Here all interrupt sources have their own
individual vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked,
as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further
interrupt nesting from occurring. However, if other interrupt requests occur during this interval,
although the interrupt will not be immediately serviced, the request flag will still be recorded.
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
Rev. 1.20
95
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
xxF
Legend
Request Flag, no auto reset in ISR
xxF
Request Flag, auto reset in ISR
xxE
Enable Bits
EMI auto disabled in ISR
Interrupt
Name
External
Request
Flags
INTF
Enable
Bits
INTE
Master
Enable
EMI
Touch Key Module
TKMF
TKME
EMI
08H
Timer/Event Counter
TF
TE
EMI
0CH
SIM
SIMF
SIME
EMI
10H
Time Base
TBF
TBE
EMI
14H
EEPROM
DEF
DEE
EMI
18 H
A/D Converter
ADF
ADE
EMI
1CH
Vector
04H
Priority
High
Low
Interrupt Structure
External Interrupt
The external interrupt is controlled by signal transitions on the pin INT. An external interrupt
request will take place when the external interrupt request flag, INTF, is set, which will occur
when a transition, whose type is chosen by the edge select bits, appears on the external interrupt
pin. To allow the program to branch to its respective interrupt vector address, the global interrupt
enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally
the correct interrupt edge type must be selected using the INTEG register to enable the external
interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared
with I/O pin, its can only be configured as external interrupt pin if its external interrupt enable bit in
the corresponding interrupt register has been set. The pin must also be setup as an input by setting
the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full
and the correct transition type appears on the external interrupt pin, a subroutine call to the external
interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag,
INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other
interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid
even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
Time Base Interrupt
The function of the Time Base Interrupt is to provide regular time signal in the form of an internal
interrupt. It is controlled by the overflow signal from its timer function. When this happens its
interrupt request flag TBF will be set. To allow the program to branch to its interrupt vector address,
the global interrupt enable bit, EMI and Time Base enable bit, TBE, must first be set. When the
interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its vector
location will take place. When the interrupt is serviced, the interrupt request flag, TBF, will be
automatically reset and the EMI bit will be cleared to disable other interrupts.
Rev. 1.20
96
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its
clock source originate from the internal clock source fTP. This fTP input clock passes through a
divider, the division ratio of which is selected by programming the appropriate bits in the TBC
register to obtain longer interrupt periods whose value ranges. The clock source that generates fTP,
which in turn controls the Time Base interrupt period, can originate from several different sources,
as shown in the System Operating Mode section.
TBC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TB1
TB0
—
—
—
—
R/W
—
—
R/W
R/W
—
—
—
—
POR
—
—
0
0
—
—
—
—
Bit 7~6
Unimplemented, read as "0"
Bit 5~4
TB1 ~ TB0: Select Time Base Time-out Period
00: 1024/fTP
01: 2048/fTP
10: 4096/fTP
11: 8192/fTP
Bit 3~ 0
Unimplemented, read as "0"
Time Base Structure
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timer interrupt enable bit, TE, must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag, TF, is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack
is not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer
interrupt vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TF,
will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
EEPROM Interrupt
An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit,
DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write
cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the
EEPROM Interrupt is serviced, the DEF flag will be automatically cleared and the EMI bit will be
automatically cleared to disable other interrupts.
Rev. 1.20
97
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Touch Key Interrupt
For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the corresponding
Touch Key interrupt enable TKME must be first set. An actual Touch Key interrupt will take place
when the Touch Key request flag. TKMF, is set, a situation that will occur when the time slot counter
overflows. When the interrupt is enabled, the stack is not full and the Touch Key time slot counter
overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the
interrupt is serviced, the Touch Key interrupt request flag, TKMF, will be automatically reset and the
EMI bit will be automatically cleared to disable other interrupts.
The TKCFOV flag, which is the 16-bit C/F counter overflow flag will go high when any of the
Touch Key Module 16-bit C/F counter overflows. As this flag will not be automatically cleared, it
has to be cleared by the application program.
Module 0 only contains one 16-bit counter. The TK16OV flag, which is the 16-bit counter overflow
flag will go high when the 16-bit counter overflows. As this flag will not be automatically cleared, it
has to be cleared by the application program.
SIM Interrupt
A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which
occurs when a byte of data has been received or transmitted by the SIM interface or an I2C address
match occurs or an I2C communication time-out occurs. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface
Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and a
byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective
interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the SIM interrupt
request flag, SIMF, will be automatically cleared and the EMI bit will be automatically cleared to
disable other interrupts.
A/D Converter Interrupt
The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D
Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is
set, which occurs when the A/D conversion process finishes. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit,
ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion
process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the
interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI
bit will also be automatically cleared to disable other interrupts.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pins may cause their respective interrupt flag to be set high and
consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are
to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt
request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt
enable bits have no effect on the interrupt wake-up function.
Rev. 1.20
98
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared
by the application program.
It is recommended that programs do not use the "CALL" instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will
be damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If
it is required to prevent a certain interrupt from waking up the microcontroller then its respective
request flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The
RETI instruction in addition to executing a return to the main program also automatically sets
the EMI bit high to allow further interrupts. The RET instruction however only executes a return
to the main program leaving the EMI bit in its present zero state and therefore disabling the
execution of further interrupts.
Rev. 1.20
99
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Application Circuits
V
D D
V D D
0 .1 F
I/O
S P I/I2C
C o n tr o l D e v ic e
S P I/I2C
D e v ic e
V S S
K E Y 1
K E Y 2
K E Y n -1
K E Y n
Rev. 1.20
100
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
Rev. 1.20
101
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].
i" instructions respectively. The feature removes the need for programmers to first read the 8-bit
output port, manipulate the input data to ensure that other bits are not changed and then output the
port with the correct new data. This read-modify-write process is taken care of automatically when
these bit operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
Rev. 1.20
102
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rev. 1.20
103
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (specific page) to TBLH and Data Memory
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
2Note
None
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRD [m]
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2"
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.20
104
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
Rev. 1.20
105
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
Rev. 1.20
106
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
Rev. 1.20
107
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
Rev. 1.20
108
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
Rev. 1.20
109
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
Rev. 1.20
110
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
Rev. 1.20
111
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.20
112
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
TABRD [m]
Description
Operation
Affected flag(s)
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDC [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.20
113
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.20
114
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
16-pin NSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.236 BSC
—
B
—
0.154 BSC
—
C
0.012
—
0.020
C’
—
0.390 BSC
—
D
—
—
0.069
E
—
0.050 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.20
Dimensions in mm
Min.
Nom.
Max.
A
—
6 BSC
—
B
—
3.9 BSC
—
C
0.31
—
0.51
C’
—
9.9 BSC
—
D
—
—
1.75
E
—
1.27 BSC
—
F
0.10
—
0.25
G
0.40
—
1.27
H
0.10
—
0.25
α
0°
—
8°
115
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
20-pin DIP (300mil) Outline Dimensions
Fig 1. Full Lead Packages
Fig 2. 1/2 Lead Packages
See fig 1
Symbol
Nom.
Max.
A
0.980
1.030
1.060
B
0.240
0.250
0.280
C
0.115
0.130
0.195
D
0.115
0.130
0.150
E
0.014
0.018
0.022
F
0.045
0.060
0.070
G
—
0.1BSC
—
H
0.300
0.310
0.325
I
—
—
0.430
Symbol
Rev. 1.20
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
24.89
26.16
26.92
B
6.10
6.35
7.11
C
2.92
3.30
4.95
D
2.92
3.30
3.81
E
0.36
0.46
0.56
F
1.14
1.52
1.78
G
—
2.54 BSC
—
H
7.62
7.87
8.26
I
—
—
10.92
116
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
See fig2
Symbol
Min.
Nom.
Max.
A
0.945
0.965
0.985
B
0.275
0.285
0.295
C
0.120
0.135
0.150
D
0.110
0.130
0.150
E
0.014
0.018
0.022
F
0.045
0.050
0.060
G
—
0.1BSC
—
H
0.300
0.310
0.325
I
—
—
0.430
Symbol
Rev. 1.20
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
24.00
24.51
25.02
B
6.99
7.24
7.49
C
3.05
3.43
3.81
D
2.79
3.30
3.81
E
0.36
0.46
0.56
F
1.14
1.27
1.52
G
—
2.54 BSC
—
H
7.62
7.87
8.26
I
—
—
10.92
117
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
20-pin SOP (300mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.406 BSC
—
B
—
0.295 BSC
—
C
0.012
—
0.020
C’
—
0.504 BSC
—
D
—
—
0.104
E
—
0.050 BSC
—
F
0.004
—
0.012
G
0.016
—
0.050
H
0.008
—
0.013
α
0°
—
8°
Symbol
Rev. 1.20
Dimensions in mm
Min.
Nom.
Max.
A
—
10.30 BSC
—
B
—
7.50 BSC
—
C
0.31
—
0.51
C’
—
12.80 BSC
—
D
—
—
2.65
E
—
1.27 BSC
—
F
0.10
—
0.30
G
0.40
—
1.27
H
0.20
—
0.33
α
0°
—
8°
118
May 13, 2015
BS84B06A-3
Touch A/D 8-Bit Flash MCU
Copyright© 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.20
119
May 13, 2015
Similar pages