Data Sheet

74AUP1G373-Q100
Low-power D-type transparent latch; 3-state
Rev. 1 — 10 March 2014
Product data sheet
1. General description
The 74AUP1G373-Q100 provides the single D-type transparent latch with 3-state output.
While the latch-enable (LE) input is high, the Q output follows the data (D) input. When
pin LE is LOW, the latch stores the information that was present at the D-input one set-up
time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents
of the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the
high-impedance OFF-state. Operation of input pin OE does not affect the state of the
latch. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and
fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-12 (0.8 V to 1.3 V)
 JESD8-11 (0.9 V to 1.65 V)
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-B (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
 HBM JESD22-A114F Class 3A. Exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Low static power consumption; ICC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial Power-down mode operation
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
74AUP1G373GW-Q100
Temperature range Name
Description
Version
40 C to +125 C
plastic surface-mounted package; 6 leads
SOT363
SC-88
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G373GW-Q100
aW
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
D
3
D
Q
LE
4
6
Fig 1.
3
LE
OE
4
LE
LE
OE
001aae248
Fig 2.
Q
EN
6
001aae247
Logic symbol
Q
C1
1
1
D
IEC logic symbol
Fig 3.
001aae249
Logic diagram
6. Pinning information
6.1 Pinning
$83*4
/(
2(
*1'
9&&
'
4
DDD
Fig 4.
Pin configuration SOT363
74AUP1G373_Q100
Product data sheet
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Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
LE
1
latch enable input (active HIGH)
GND
2
ground (0 V)
D
3
data input
Q
4
latch output
VCC
5
supply voltage
OE
6
output enable input (active LOW)
7. Functional description
Table 4.
Function table[1]
Operating modes
Input
Internal latch
Output
OE
LE
D
Enable and read register (transparent
mode)
L
H
L
L
L
L
H
H
H
H
Latch and read register
L
L
l
L
L
L
L
h
H
H
Latch register and disable outputs
H
X
X
X
Z
[1]
Q
H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition;
X = Don’t care;
Z = high-impedance OFF-state.
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
-
20
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
Tamb = 40 C to +125 C
total power dissipation
Ptot
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Conditions
Tamb
ambient temperature
t/V
input transition rise and fall rate
Min
Max
Unit
0.8
3.6
V
0
3.6
V
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
40
+125
C
-
200
ns/V
Typ
Max
Unit
VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
VCC = 0.8 V
0.70  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
Tamb = 25 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOH
VI = VIH or VIL
VOL
HIGH-level output voltage
LOW-level output voltage
Min
Typ
Max
Unit
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.75  VCC -
-
V
IO = 1.7 mA; VCC = 1.4 V
1.11
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.32
-
-
V
IO = 2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.6
-
-
V
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.1
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
0.1
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.2
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
40
A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.8
-
pF
CO
output capacitance
output enabled; VO = GND; VCC = 0 V
-
1.7
-
pF
output disabled; VCC = 0 V to 3.6 V;
VO = GND or VCC
-
1.5
-
pF
VCC = 0.8 V
0.70  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
[1]
Tamb = 40 C to +85 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOH
VI = VIH or VIL
VOL
HIGH-level output voltage
LOW-level output voltage
Min
Typ
Max
Unit
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.7  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.03
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.30
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.55
-
-
V
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.5
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
0.5
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.6
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
50
A
[1]
Tamb = 40 C to +125 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
74AUP1G373_Q100
Product data sheet
VCC = 0.8 V
0.75  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.70  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.25  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.30  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOH
VI = VIH or VIL
HIGH-level output voltage
LOW-level output voltage
VOL
Min
Typ
Max
Unit
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.11 -
-
V
IO = 1.1 mA; VCC = 1.1 V
0.6  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
0.93
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.17
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.30
-
-
V
V
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.11
IO = 1.1 mA; VCC = 1.1 V
-
-
0.33  VCC V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.41
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.75
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
0.75
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
75
A
[1]
[1]
One input at VCC  0.6 V, other input at VCC or GND.
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Min
Typ[1]
Max
-
21.4
-
Unit
Min
Max
Min
Max
(85 C) (85 C) (125 C) (125 C)
CL = 5 pF
tpd
propagation D to Q; see Figure 5
delay
VCC = 0.8 V
[2]
ns
2.8
6.6
13.5
2.6
13.8
2.6
15.2
ns
4.6
7.8
2.1
8.3
2.1
9.1
ns
VCC = 1.65 V to 1.95 V
1.9
3.7
6.2
1.6
6.7
1.6
7.3
ns
VCC = 2.3 V to 2.7 V
1.8
2.9
4.1
1.5
4.5
1.5
4.9
ns
1.5
2.5
3.5
1.2
4.0
1.2
4.5
ns
-
20.3
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.7
6.2
13.6
2.5
14.0
2.5
15.4
ns
VCC = 1.4 V to 1.6 V
2.3
4.4
7.6
2.0
8.5
2.0
9.3
ns
VCC = 1.65 V to 1.95 V
1.8
3.5
5.8
1.5
6.7
1.5
7.3
ns
VCC = 2.3 V to 2.7 V
1.5
2.6
4.0
1.3
4.4
1.3
4.8
ns
1.3
2.2
3.3
1.1
3.8
1.1
4.2
ns
-
17.9
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.2
5.1
9.2
3.0
9.2
3.0
10.1
ns
VCC = 1.4 V to 1.6 V
2.6
3.8
5.8
2.4
6.1
2.4
6.7
ns
[2]
VCC = 3.0 V to 3.6 V
enable time OE to Q; see Figure 8
[3]
VCC = 0.8 V
VCC = 1.65 V to 1.95 V
2.2
3.3
4.8
2.0
5.0
2.0
5.5
ns
VCC = 2.3 V to 2.7 V
2.0
2.7
3.8
1.8
4.0
1.8
4.4
ns
1.9
2.5
3.4
1.8
3.6
1.8
4.0
ns
VCC = 3.0 V to 3.6 V
disable time OE to Q; see Figure 8
VCC = 0.8 V
Product data sheet
-
2.4
VCC = 0.8 V
74AUP1G373_Q100
-
VCC = 1.4 V to 1.6 V
VCC = 3.0 V to 3.6 V
tdis
-
VCC = 1.1 V to 1.3 V
LE to Q; see Figure 6
ten
-
[4]
-
9.4
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.9
4.2
7.5
2.8
7.9
2.8
8.7
ns
VCC = 1.4 V to 1.6 V
2.2
3.2
4.9
2.1
5.3
2.1
5.8
ns
VCC = 1.65 V to 1.95 V
2.2
3.0
4.4
2.1
4.9
2.1
5.4
ns
VCC = 2.3 V to 2.7 V
1.6
2.2
3.1
1.5
3.4
1.5
3.7
ns
VCC = 3.0 V to 3.6 V
1.9
2.6
3.3
1.8
3.6
1.8
4.0
ns
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
-
24.4
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.0
7.5
15.3
2.7
15.9
2.7
17.4
ns
Min
Max
Min
Max
(85 C) (85 C) (125 C) (125 C)
CL = 10 pF
tpd
propagation D to Q; see Figure 5
delay
VCC = 0.8 V
[2]
VCC = 1.4 V to 1.6 V
2.6
5.3
9.0
2.2
9.4
2.2
10.3
ns
VCC = 1.65 V to 1.95 V
2.5
4.3
6.9
2.1
7.3
2.1
8.0
ns
VCC = 2.3 V to 2.7 V
2.0
3.5
4.8
1.8
5.3
1.8
5.9
ns
1.8
3.1
4.2
1.7
4.6
1.7
5.1
ns
-
23.3
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.9
7.1
15.4
2.7
16.1
2.7
17.7
ns
VCC = 1.4 V to 1.6 V
2.5
5.0
8.8
2.1
9.5
2.1
10.4
ns
VCC = 3.0 V to 3.6 V
LE to Q; see Figure 6
[2]
VCC = 0.8 V
VCC = 1.65 V to 1.95 V
2.3
4.1
6.6
2.0
7.3
2.0
8.1
ns
VCC = 2.3 V to 2.7 V
1.9
3.1
4.7
1.6
5.2
1.6
5.8
ns
1.7
2.8
4.0
1.4
4.4
1.4
4.9
ns
VCC = 3.0 V to 3.6 V
ten
enable time OE to Q; see Figure 8
[3]
VCC = 0.8 V
tdis
-
21.2
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.7
6.0
10.6
3.4
10.6
3.4
11.7
ns
VCC = 1.4 V to 1.6 V
3.1
4.5
6.7
2.8
7.0
2.8
7.7
ns
VCC = 1.65 V to 1.95 V
2.7
3.9
5.5
2.5
5.8
2.5
6.4
ns
VCC = 2.3 V to 2.7 V
2.4
3.3
4.5
2.2
4.7
2.2
5.2
ns
VCC = 3.0 V to 3.6 V
2.3
3.1
4.1
2.2
4.3
2.2
4.7
ns
-
11.3
-
-
-
-
-
ns
disable time OE to Q; see Figure 8
VCC = 0.8 V
74AUP1G373_Q100
Product data sheet
[4]
VCC = 1.1 V to 1.3 V
3.9
5.3
8.7
3.8
9.2
3.8
10.1
ns
VCC = 1.4 V to 1.6 V
3.0
4.1
5.8
2.9
6.2
2.9
6.8
ns
VCC = 1.65 V to 1.95 V
3.2
4.2
5.7
3.1
6.0
3.1
6.6
ns
VCC = 2.3 V to 2.7 V
2.3
3.0
4.0
2.2
4.3
2.2
4.7
ns
VCC = 3.0 V to 3.6 V
3.0
3.8
4.7
2.9
5.0
2.9
5.5
ns
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
-
27.3
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.5
8.3
16.9
3.2
17.5
3.2
19.2
ns
VCC = 1.4 V to 1.6 V
3.1
5.9
9.6
2.7
10.5
2.7
11.6
ns
VCC = 1.65 V to 1.95 V
2.6
4.8
7.6
2.2
8.5
2.2
9.3
ns
VCC = 2.3 V to 2.7 V
2.5
3.9
5.5
2.2
5.9
2.2
6.5
ns
2.2
3.6
4.9
1.8
5.5
1.8
6.0
ns
-
26.1
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.3
7.9
17.3
3.0
18.0
3.0
19.8
ns
VCC = 1.4 V to 1.6 V
3.0
5.6
9.7
2.5
10.7
2.5
11.8
ns
Min
Max
Min
Max
(85 C) (85 C) (125 C) (125 C)
CL = 15 pF
tpd
propagation D to Q; see Figure 5
delay
VCC = 0.8 V
[2]
VCC = 3.0 V to 3.6 V
LE to Q; see Figure 6
[2]
VCC = 0.8 V
VCC = 1.65 V to 1.95 V
2.5
4.6
7.4
2.2
8.3
2.2
9.1
ns
VCC = 2.3 V to 2.7 V
2.3
3.6
5.3
2.0
5.9
2.0
6.4
ns
2.1
3.2
4.6
1.8
5.1
1.8
5.6
ns
VCC = 3.0 V to 3.6 V
ten
enable time OE to Q; see Figure 8
[3]
VCC = 0.8 V
tdis
-
24.6
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.1
6.8
12.1
3.8
12.1
3.8
13.3
ns
VCC = 1.4 V to 1.6 V
3.5
5.1
7.5
3.2
7.9
3.2
8.7
ns
VCC = 1.65 V to 1.95 V
3.1
4.4
6.1
2.8
6.5
2.8
7.2
ns
VCC = 2.3 V to 2.7 V
2.8
3.7
5.0
2.5
5.3
2.5
5.8
ns
VCC = 3.0 V to 3.6 V
2.6
3.5
4.7
2.5
4.9
2.5
5.4
ns
-
13.1
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.9
6.5
9.8
4.8
10.4
4.8
11.4
ns
VCC = 1.4 V to 1.6 V
3.9
5.0
6.8
3.8
7.3
3.8
8.0
ns
VCC = 1.65 V to 1.95 V
4.2
5.3
6.9
4.1
7.3
4.1
8.0
ns
VCC = 2.3 V to 2.7 V
3.0
3.8
4.8
2.9
5.1
2.9
5.6
ns
VCC = 3.0 V to 3.6 V
4.1
5.0
6.1
4.0
6.4
4.0
7.0
ns
disable time OE to Q; see Figure 8
VCC = 0.8 V
74AUP1G373_Q100
Product data sheet
[4]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
-
35.9
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.0
10.6
22.1
3.7
23.3
3.7
25.6
ns
VCC = 1.4 V to 1.6 V
3.6
7.5
12.3
3.5
13.6
3.5
15.0
ns
VCC = 1.65 V to 1.95 V
3.5
6.2
9.5
3.2
10.5
3.2
11.5
ns
VCC = 2.3 V to 2.7 V
3.3
5.1
6.9
2.9
7.6
2.9
8.3
ns
3.0
4.7
6.4
2.9
7.2
2.9
7.9
ns
-
34.8
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.9
10.2
22.2
3.7
23.5
3.7
25.9
ns
VCC = 1.4 V to 1.6 V
3.5
7.2
12.4
3.4
13.7
3.4
15.1
ns
Min
Max
Min
Max
(85 C) (85 C) (125 C) (125 C)
CL = 30 pF
tpd
propagation D to Q; see Figure 5
delay
VCC = 0.8 V
[2]
VCC = 3.0 V to 3.6 V
LE to Q; see Figure 6
[2]
VCC = 0.8 V
VCC = 1.65 V to 1.95 V
3.3
5.9
9.5
3.0
10.5
3.0
11.6
ns
VCC = 2.3 V to 2.7 V
3.1
4.8
6.8
2.7
7.5
2.7
8.2
ns
2.9
4.4
6.1
2.6
7.0
2.6
7.7
ns
VCC = 3.0 V to 3.6 V
ten
enable time OE to Q; see Figure 8
[3]
VCC = 0.8 V
tdis
-
34.5
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
5.5
9.1
16.2
4.9
16.2
4.9
17.8
ns
VCC = 1.4 V to 1.6 V
4.6
6.7
9.9
4.2
10.5
4.2
11.6
ns
VCC = 1.65 V to 1.95 V
4.2
5.7
7.9
3.7
8.6
3.7
9.5
ns
VCC = 2.3 V to 2.7 V
3.6
4.9
6.4
3.4
6.9
3.4
7.6
ns
VCC = 3.0 V to 3.6 V
3.4
4.7
6.1
3.3
6.5
3.3
7.2
ns
-
19.2
-
-
-
-
-
ns
disable time OE to Q; see Figure 8
VCC = 0.8 V
[4]
VCC = 1.1 V to 1.3 V
8.0
9.9
13.7
7.9
14.5
7.9
16.0
ns
VCC = 1.4 V to 1.6 V
6.3
7.7
9.7
6.2
10.5
6.2
11.6
ns
VCC = 1.65 V to 1.95 V
7.3
8.7
10.6
7.2
11.3
7.2
12.4
ns
VCC = 2.3 V to 2.7 V
5.2
6.2
7.5
5.1
7.8
5.1
8.6
ns
VCC = 3.0 V to 3.6 V
7.5
8.8
10.2
7.4
10.5
7.4
11.6
ns
VCC = 0.8 V
-
4.0
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
-
0.7
-
2.1
-
2.1
-
ns
VCC = 1.4 V to 1.6 V
-
0.5
-
1.3
-
1.3
-
ns
VCC = 1.65 V to 1.95 V
-
0.4
-
1.0
-
1.0
-
ns
VCC = 2.3 V to 2.7 V
-
0.3
-
0.8
-
0.8
-
ns
VCC = 3.0 V to 3.6 V
-
0.2
-
0.8
-
0.8
-
ns
CL = 5 pF, 10 pF, 15 pF and 30 pF
tW
pulse width
74AUP1G373_Q100
Product data sheet
LE HIGH; see Figure 6
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 9.
Symbol Parameter
tsu(H)
tsu(L)
th
set-up time
HIGH
set-up time
LOW
hold time
74AUP1G373_Q100
Product data sheet
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
VCC = 0.8 V
-
4.6
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
-
0.9
-
2.2
-
2.2
-
ns
VCC = 1.4 V to 1.6 V
-
0.6
-
1.4
-
1.4
-
ns
Min
Max
Min
Max
(85 C) (85 C) (125 C) (125 C)
D to LE; see Figure 7
VCC = 1.65 V to 1.95 V
-
0.4
-
1.0
-
1.0
-
ns
VCC = 2.3 V to 2.7 V
-
0
-
0.6
-
0.6
-
ns
VCC = 3.0 V to 3.6 V
-
0.1
-
0.4
-
0.4
-
ns
D to LE; see Figure 7
VCC = 0.8 V
-
4.0
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
-
1.2
-
2.7
-
2.7
-
ns
VCC = 1.4 V to 1.6 V
-
0.7
-
1.5
-
1.5
-
ns
VCC = 1.65 V to 1.95 V
-
0.6
-
1.2
-
1.2
-
ns
VCC = 2.3 V to 2.7 V
-
0.4
-
0.9
-
0.9
-
ns
VCC = 3.0 V to 3.6 V
-
0.3
-
0.7
-
0.7
-
ns
D to LE HIGH or LOW;
see Figure 7
VCC = 0.8 V
-
4.6
-
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
-
0.9
-
0.1
-
0.1
-
ns
VCC = 1.4 V to 1.6 V
-
0.6
-
0.1
-
0.1
-
ns
VCC = 1.65 V to 1.95 V
-
0.4
-
0
-
0
-
ns
VCC = 2.3 V to 2.7 V
-
0.2
-
0.2
-
0.2
-
ns
VCC = 3.0 V to 3.6 V
-
0.1
-
0.3
-
0.3
-
ns
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 9.
Symbol Parameter
CPD
25 C
Conditions
power
fi = 1 MHz; VI = GND to VCC
dissipation output enabled
capacitance
VCC = 0.8 V
Unit
Min
Max
-
2.0
-
-
-
-
-
pF
-
2.0
-
-
-
-
-
pF
Min
Max
Min
Max
(85 C) (85 C) (125 C) (125 C)
[5][6]
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
-
2.0
-
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
2.1
-
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
2.4
-
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
2.8
-
-
-
-
-
pF
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
ten is the same as tPZH and tPZL.
[4]
tdis is the same as tPHZ and tPLZ.
[5]
All specified values are the average typical values over all stated loads.
[6]
40 C to +125 C
Typ[1]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
(CL  VCC2  fo) = sum of the outputs;
N = number of inputs switching.
12. Waveforms
VI
VM
D input
GND
t PHL
t PLH
VOH
VM
Q output
VOL
001aae253
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
The data input (D) to output (Q) propagation delays
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
VI
LE input
VM
GND
tW
tPLH
tPHL
VOH
Q output
VM
VOL
001aae254
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
The latch enable input (LE) to output (Q) propagation delays, the latch enable input (LE) pulse width
VI
VM
D input
GND
tsu
th
tsu
th
VI
VM
LE input
GND
001aae255
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Data set-up and hold times for the D input to the LE input
Table 9.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5  VCC
0.5  VCC
VCC
 3.0 ns
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
VI
OE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna644
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
Turn-on and turn-off times
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
0.8 V to 1.6 V
0.5  VCC
0.5  VCC
VOL + 0.1 V
VOH  0.1 V
1.65 V to 2.7 V
0.5  VCC
0.5  VCC
VOL + 0.15 V
VOH  0.15 V
3.0 V to 3.6 V
0.5  VCC
0.5  VCC
VOL + 0.3 V
VOH  0.3 V
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
VY
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
VCC
VEXT
5 kΩ
G
VI
VO
DUT
CL
RT
RL
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9.
Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Load
VEXT
RL[1]
VCC
CL
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2  VCC
For measuring enable and disable times, RL = 5 k, for measuring propagation delays, setup and hold times, and pulse width RL = 1
M.
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT363
JEITA
SC-88
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
Fig 10. Package outline SOT363 (SC-88)
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
14. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
15. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP1G373_Q100 v.1
20140310
Product data sheet
-
-
74AUP1G373_Q100
Product data sheet
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Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP1G373_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
19 of 21
74AUP1G373-Q100
NXP Semiconductors
Low-power D-type transparent latch; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AUP1G373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
20 of 21
NXP Semiconductors
74AUP1G373-Q100
Low-power D-type transparent latch; 3-state
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 March 2014
Document identifier: 74AUP1G373_Q100