AN1707: Intersil’s Radiation Hardened FPGA Power Solutions

Application Note 1707
Authors: Kiran Bernard, Oscar Mansilla, and Eric Thomson
Intersil’s Radiation Hardened FPGA Power Solutions
Introduction
The evolution of rad hard power solutions are being driven by
changes implemented in the commercial market which have
proven to provide higher efficiency and better performance.
Space power is gradually adapting the distributed power
architecture which dominates commercial power systems.
Benefits of this architecture include reduction of distribution
losses, improvement in regulation performance and a solution
that can be modular. Another contribution that aids in the
definition of radiation hardened power IC’s is the rapid
qualification and/or development of high performance digital
components for space applications such as FPGA’s and
microprocessors. These digital IC’s rival commercial
counterparts in computing performance, low supply voltage
and increased power consumption. Couple-in the need for a
smaller, light-weight power solution and you will find Intersil at
the forefront developing leading edge point-of-load (POL)
regulators that meet the demands of today’s space
applications.
This application note discusses the VIRTEX5MEZPWREV1Z
board, Intersil’s reference design to power FPGA's in a
radiation hardened environment. This particular board is
optimized to power a Xilinx’s Virtex-5 FPGA and features the
ISL70001SRH and ISL70002SRH, rad hard POL buck
regulators along with the ISL75051RH rad hard LDO.
FPGA Power Solution
The Virtex-5 requires a core voltage of 1.0V, which is supplied
by the ISL70002SRH, an auxiliary voltage of 2.5V, which is
supplied by the ISL70001SRH, and an I/O voltage of 3.3V
which is supplied by the ISL75051RH (see Figure 1).
voltage. The ISL70001SRH can provide up to 6A (TJ ≤ +145°C)
of output current while the ISL70002SRH can provide up to
12A (TJ ≤ +150°C) of output current.
The ISL75051SRH is a radiation hardened, low voltage, high
current, single output LDO specified for up to 3.0A of
continuous output current. It can operate over an input voltage
range of 2.2V to 6.0V and is capable of providing output
voltages of 0.8V to 5V with an external resistor divider. Dropout
voltages as low as 65mV can be realized with this device.
Circuits Description
The 5V AC-DC adapter provides the input source through the
2.1mm barrel-jack connector. Proper sequence during
power-up is maintained by connecting the PGOOD line of the
ISL70002SRH to the ISL70001SRH’s EN pin, which in turn has
its PGOOD line tied to the EN pin of the ISL75051RH. This
ensures that the core voltage is up first, followed by the
auxiliary and then the I/O voltage (see Figure 3).
The output capacitors for each device have been chosen to
minimize ESR in an effort to maintain output ripple <1% of the
regulated voltage (for ISL70001SRH and ISL70002SRH) and to
optimize the stability of the systems. KEMET’s T530 series of
tantalum capacitors offer ultra low ESR <15mΩ and are DLA
certified.
Provisions for stability measurements are included. By
replacing R23, R35 and R36 with 10Ω to 100Ω resistors and
injecting the AC signal across TP1/TP2 for the ISL70001SRH,
TP3/TP4 for the ISL70002SRH and TP5/TP6 for the
ISL75051RH, AC measurements of the loop may be taken.
Radiation Tolerance
Total Iodizing Dose
5V SUPPLY
ISL70002SRH
CORE
ISL70001SRH
AUX
ISL75051SRH
I/O
RAD TOLERANT
FPGA
FIGURE 1. VIRTEX5MEZPWREV1Z BLOCK DIAGRAM
The ISL70001SRH and ISL70002SRH are both radiation
hardened and SEE hardened high efficiency, monolithic
synchronous buck regulators with integrated MOSFETs. These
single chip power solutions operate over an input voltage range
of 3V to 5.5V and provide a tightly regulated output voltage
that is externally adjustable from 0.8V to ~85% of the input
October 21, 2011
AN1707.0
1
These circuits are fabricated on a 0.6μm BiCMOS junction
isolated process optimized for power management
applications. They were hardened by design to achieve a Total
Ionizing Dose (TID) rating of at least 100krads(Si) at the
standard 50 to 300rad(Si)/s high dose rate as well as the
standard <10mrad(Si)/s low dose rate. Well known TID
hardening methods were employed such as closed geometry
NMOS devices to reduce leakage and optimized bias levels for
bipolar devices to compensate for gain reduction. For further
information on radiation performance please navigate to
www.intersil.com/space.
Single Event Effects
All three IC’s were also hardened by design to a Linear Energy
Transfer (LET) of 86.4MeV/mg/cm2 by employing various SEE
hardening techniques such as proper device sizing, filtering
and special layout constraints. All three devices exhibit no
latch-up or burnout up to their respective input voltage at an
LET of 86.4 MeV/mg/cm2.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1707
20
18
1.90
1.85
AMPLITUDE (V)
Intersil is also the leader in Single Event Transient (SET)
performance. The ISL70001SRH and the ISL70002SRH offer a
<1% output voltage deviation due to SETs at an LET of
86.4MeV/mg/cm2 (see Figure 2). Modern processors and FPGA
offer a 5% tolerance window for the supply voltage. In some
cases, the 5% tolerance includes DC voltage tolerance and
transients due to load step or release and transients due to SETs.
1.80
1.75
16
AMPLITUDE (V)
14
1.70
13
TRG = CH1 = ±15mV
1.65
10
-1
0
1
2
8
4
5
6
7
8
x10-5
TIME DIV (s)
FIGURE 3. ISL75051SRH SET RESPONSE
6
4
Additional Design Features
2
0
3
-6
-4
-2
0
2
4
TIME (s)
6
8
10
12
14
x10-6
FIGURE 2. ISL70001SRH SET RESPONSE
Take for example, the ISL70001SRH. The output voltage
tolerance is specified at 2%, this includes line and load
regulation, and reference voltage tolerance over-temperature
and radiation. An additional 1% may be attributed to end of life
for the external resistors needed to set the output voltage. Load
transients and SETs, it can safely be said, would not occur at the
same time. Therefore, 2% can be allotted to a load transient
which can be met with proper output filter selection. A total
output voltage tolerance of 4% can be achieved - this includes DC
shifts due to line, load and reference and SETs transients. A 5%
output voltage tolerance will be achieved when there is a load
transient. Intersil’s rad hard POLs could easily meet the stringent
requirements of modern space applications.
The ISL75051SRH also has class leading SET performance
without the need of additional external filters as seen in other rad
hard linear regulators. Figure 3 shows superimposed plots of
LDO response during SETs. The upper and lower limits correlate
to a 4% voltage perturbation. It can be seen that a -50mV
deviation was the worst deviation seen in this run.
This section discusses two additional features that may be added
to further improve reliability and enhance the power capability of
the reference design.
Current Sharing for the ISL70002SRH
Modern digital components are requiring greater supply currents
to meet the demands for the ever increasing need of processing
power in space systems. For applications where the core voltage
requires more than 12A of continuous current, the ISL70002SRH
may be used in a multiphase solution. Two ISL70002SRH’s can
current share and provide up to 19A of continuous current to the
processor, FPGA, or any other load. The current share
architecture features triple redundancy for single event transient
mitigation. For a detailed description on current sharing refer to
the ISL70002SRH datasheet.
Power-on Reset
The addition of a rad tolerant POR chip such as the ISL705ARH
could further improve reliability by allowing proper sequence to
initiate only after the 5V intermediate voltage has reached its
optimal steady-state condition. With the added feature of a
watchdog timer, the ISL705ARH will also monitor the FPGA or
processor for proper execution and send a reset signal if not
toggled within 1.0s. Intersil also offers the ISL706XRH series of
voltage supervisors dedicated to 3.3V rails. For more information
on the ISL705XRH and ISL706XRH see datasheet FN7662.
Related Literature
• ISL70001SRH Datasheet FN6947
• ISL70002SRH Datasheet
• ISL75051SRH Datasheet
2
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Application Note 1707
FIGURE 4. RADIATION HARDENED FPGA POWER SOLUTIONS REFERENCE DESIGN
3
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Application Note 1707
Typical Performance Curves
I/O
AUX
VOUT CORE
CORE
FIGURE 5. START-UP SEQUENCE
FIGURE 6. ISL70002SRH CORE OUTPUT VOLTAGE RIPPLE
LOAD
VOUT AUX
CORE VOLTAGE
FIGURE 7. ISL70001SRH AUXILIARY VOLTAGE RIPPLE
ILOAD
FIGURE 8. CORE VOLTAGE 3A LOAD TRANSIENT RESPONSE
ILOAD
AUX VOLTAGE
I/O VOLTAGE
FIGURE 9. AUXILIARY VOLTAGE 3A LOAD TRANSIENT RESPONSE
4
FIGURE 10. I/O VOLTAGE 1.5A LOAD TRANSIENT RESPONSE
AN1707.0
October 21, 2011
Application Note 1707
80
180
150
70
150
60
120
60
90
50
40
60
40
60
30
30
30
30
20
0
PHASE
GAIN
20
0
GAIN (dB)
180
70
PHASE (°)
80
50
PHASE
120
90
10
-30
0
-60
0
-10
-90
-10
-90
-20
-120
-20
-120
-30
-40
10
-150
-30
-40
10
-150
100
1k
10k
-180
1M
100k
10
-30
GAIN
100
1k
10k
-60
100k
-180
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. ISL70002SRH AC RESPONSE AT 12A LOAD
FIGURE 12. ISL70001SRH AC RESPONSE AT 6A LOAD
60
180
50
150
40
120
90
PHASE
20
10
60
30
GAIN
0
0
-10
-30
-20
-60
-30
-90
-40
-120
-50
-60
500
-150
5k
50k
500k
5M
PHASE (°)
30
GAIN (dB)
GAIN (dB)
(Continued)
PHASE (°)
Typical Performance Curves
-180
FREQUENCY (Hz)
FIGURE 13. ISL75051SRH AC RESPONSE AT 3A LOAD
5
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1K
R27
1UF
C41
C4
1UF
47UF
C40
C3
47UF
22
47UF
33
C2
C1
11
J1
150UF
ISL70001SRH Schematic
LED1
1UF
C9
LX5
2
1UF
C15
47UF
C14
47UF
C13
C12
330UF
P4
D1
MBRS320T3
LX
34
33
VIN
32
31
0
TP1
35
TP2
LX
GND
PGND5
30
29
PGND6
PGND6
PGND5
28
27
26
PVIN6
LX6
25
VIN
24
FB
EN
22
19
20
PORSEL
PVIN6
PVIN5
PVIN5
36
GND
P3
1K
PVIN4
AGND
AGND
3
43
44
PVIN2
46
45
PVIN2
47
PGND2
LX2
1
2
48
PGND2
PGND1
PGND1
4
LX
37
DGND
R3
C8
PGND4
PVIN4
ISL70001SRHF
23
17
38
R23
DGND
39
PGND4
2V5
1UH
R6
DVDD
15
PGND3
LX4
L1
LX
40
4700PF
14
41
FB
LX
R7
DVDD
42
316
SS
13
Q1
WURTH ELEKTRONIK
744 311 100
C11
12
AVDD
1
U1
PGOOD
18
VIN
LX1
TDO
16
S1
PGND3
REF
1UF
C7
VIN
LX3
21
1K
R1
1
R2
0.01UF
C5
DVDD
PVIN3
1
P2
PVIN3
TDI
11
2N7002
PGOOD1
P1
Application Note 1707
9
C6
2V5
VIN
ZAP
10
0.1UF
5
M/S
8
PGOOD1
PVIN1
6
7
PVIN1
SYNC
3
VIN
LX
6
SYNC
VIN
GND
PJ_002AH
0.22UF
R20
DVDD
FB
0
PGOOD2
R4
C10
1K
R5
499
0.01UF
S1
DRAWN BY:
DATE:
KIRAN BERNARD
06/22/2011
RELEASED BY:
DATE:
UPDATED BY:
DATE:
ENGINEER:
KIRAN BERNA
TITLE:
VIRTE
AN1707.0
October 21, 2011
ISL70002SRH Schematic
VIN
R12
VIN
EN2
PVIN6
ISL70002SRHVF
PVIN7
SS
LX8
NC
ISHEN
38
37
36
LX2
33
D
GND
LX2
0
R35
1UF
C33
C28
4700PF
P7
LED2
1V0
PVIN8
32
PGOOD2
1
Q2
2N7002
2
31
P5
VIN
30
29
LX2 27
VIN 28
25
GND 26
22
VIN 23
LX2 24
GND
21
20
19
18
17
DVDD2
0
1K
1.5K
VIN
LX2
D
R17
R19
VIN
35
34
C32
R18
GND
3
PORSEL
FSEL
PGND8
M/S
ISHSL
LX9
15
PVIN9
PGND7
PGND10
PGND9
LX7
ISHCOM
LX10
PGOOD
14
SYNC
PVIN10
13
39
47UF
LX6
TP4
D2
MBRS320T3
FB2
DGND
40
LX2
C31
10
41
VIN
TP3
47UF
PGND6
42
P6
1K
PGND5
AGND
43
LX2
C30
AVDD
9
LX5
44
GND
330UF
8
U2
45
1V0
0.52UH
744 310 055
WURTH ELEKTRONIK
R28
ISHREFC
46
LX2
C29
7
47
330UF
PVIN5
L2
48
1
PVIN4
ISHC
LX4
DVDD
C27
VIN
49
50
NC
51
52
SC1
SC0
ISHREFB
6
11
0.01UF
R13
SC1
SC0
LX2
53
PVIN2
GND
55
54
LX2
57
56
PGND1
PGND2
59
58
PVIN1
LX1
60
61
5
16
D
62
PGND4
ISHB
ZAP
GND
1UF
C26
C25
0.01UF
ISHREFA
TDI
1UF
C24
0.1UF
PGND3
TDO
1
R16
1K
R15
1
R14
C23
D
ISHA
4
12
PGOOD2
LX3
DVDD2
SYNC
DVDD2
DNP
R31
DNP
R29
R33
0
SC1
DRAWN BY:
R34
DNP
0
R32
0
R30
SC0
DATE:
KIRAN BERNARD
RELEASED BY:
06/22/2011
DATE:
UPDATED BY:
ENGINEER:
VIRTEX5MEZPWREV1ZA
DATE:
TIM KLEMANN
EVALUATION BOARD
07/08/2011
TESTER
SCHEMATIC
MASK#
FILENAME:
DATE:
KIRAN BERNARD
TITLE:
REV.
HRDWR ID
SHEET
2
A
3
Application Note 1707
D
DVDD2
PVIN3
2
3
VIN
OCSSB
EN
2
FB
OCB
1
OCA
REF
FB2
OCSSA
C22
0.22UF
63
R11
4.02K
64
R10
19.6K
OCB
R9
19.6K
OCSSB
R8
4.02K
OCSSA
C21
6800PF
OCA
7
C20
6800PF
OCA
OCSSA
OCB
OCSSB
EN2
VIN
LX2
GND
10.2K
1UF
1UF
C19
C44
C43
47UF
C42
47UF
C18
47UF
C17
47UF
C16
150UF
56.2K
AN1707.0
October 21, 2011
ISL75051RH Schematic
VIN
R26
1K
LED3
3
3V3
8
PGOOD3
Q3
1
2N7002
2
P10
U3
R36
7
8
4.32K
9
100PF
C36
768
R22
C37
R21
0
5.49K
16
15
14
13
12
VIN
11
10
ISL75051SRH
PGOOD1
0.1UF
6
0.18UF
P9
TP6
TP5
5
17
C39
4
220UF
C35
0.1UF
C34
P8
VOUT
3 VOUT
4 VOUT
5 VOUT
6 VOUT
7 VOUT
8 ADJ
9 BYP
VIN
220UF
2
3
R25
18
C38
2
PGOOD 18
VIN 17
VIN 16
VIN 15
VIN 14
VIN 13
VIN 12
OCP 11
EN 10
511
1 GND
Application Note 1707
3V3
1
R24
GND
AN1707.0
October 21, 2011
Application Note 1707
VIRTEX5MEZPWREV1Z Bill of Materials
REF DES.
Q1
Q2, Q3
TP1-TP6
LED1-LED3
PART NUMBER
QTY
MANUFACTURER
DESCRIPTION
2N7002-7-F
1
FAIRCHILD
N-Channel EMF Effect Transistor (Pb-Free)
2N7002L
2
ON Semi
N-Channel 60V 115mA MOSFET
5002
6
KEYSTONE
Miniature White Test Point 0.100 Pad 0.040 Thole
597-3311-407
3
Dialight
Surface Mount Green LED
8
PANASONIC
Thick Film Chip Resistor
R17, R20, R23, R30, R32, R33, ERJ3GEY0R00V
R35, R36
C37
GRM188R71E184KA88
1
GENERIC
Multilayer Cap
C36
H1045-00101-50V5
1
GENERIC
Multilayer Cap
C5, C10
H1045-00103-16V10
2
GENERIC
Multilayer Cap
C25, C27
H1045-00103-25V10
2
GENERIC
Multilayer Cap
C6
H1045-00104-16V10
1
GENERIC
Multilayer Cap
C24, C34, C39
H1045-00104-25V10
3
GENERIC
Multilayer Cap
C7, C8
H1045-00105-16V20
2
GENERIC
Ceramic Cap
C9, C22
H1045-00224-16V10
2
GENERIC
Multilayer Cap
C11, C28
H1045-00472-50V10
2
GENERIC
Multilayer Cap
C20, C21
H1045-00682-50V10
2
GENERIC
Multilayer Cap
C2, C3, C13, C14, C17, C18,
C31, C32, C40, C42, C43
H1046-00476-16V20
11
GENERIC
Multilayer Cap
H2505-DNP-DNP-1
3
GENERIC
Metal Film Chip Resistor (Do Not Populate)
R2, R3, R14, R16
H2511-00010-1/10W1
4
GENERIC
Thick Film Chip Resistor
R1, R5, R6, R27
H2511-01001-1/16W1
4
GENERIC
Thick Film Chip Resistor
R21
H2511-04321-1/16W1
1
GENERIC
Thick Film Chip Resistor
R24
H2511-05110-1/16W1
1
GENERIC
Thick Film Chip Resistor
R25
H2511-05491-1/16W1
1
GENERIC
Thick Film Chip Resistor
R12
H2511-05622-1/16W1
1
GENERIC
Thick Film Chip Resistor
R22
H2511-07680-1/16W1
1
GENERIC
Thick Film Chip Resistor
U1
ISL70001SRHF
1
INTERSIL
4.2A/6A Synchronous Buck Regulator
U2
ISL70002SRHVF
1
INTERSIL
12A Synchronous Buck Regulator w/MOSFET
MBRS320T3
2
ON-SEMI
3A 20V Schottky Power Rectifier
MCR03EZPFX1001
1
ROHM
Metal Film Chip Resistor
PJ-002AH
1
CUI-INC
DC Power Jack
R13
RG1608P-1022-B-T5
1
SUSUMU
Thick Film Chip Resistor
R18
S0603CA1001BEB
1
State of the Art
Thick Film Chip Resistor
R29, R31, R34
D1, D2
R26
J1
9
AN1707.0
October 21, 2011
Application Note 1707
VIRTEX5MEZPWREV1Z Bill of Materials
REF DES.
PART NUMBER
QTY
(Continued)
MANUFACTURER
DESCRIPTION
R19
S0603CA1501BEZ
1
State of the Art
25ppm Thin Film Chip Resistor
R9, R10
S0603CA1962BEZ
2
State of the Art
25ppm Thin Film Chip Resistor
R7
S0603CA3160BEB
1
State of the Art
Thick Film Chip Resistor
R8, R11
S0603CA4021BEZ
2
State of the Art
25ppm Thin Film Chip Resistor
R15, R28
S0603CPX1001F10
2
State of the Art
Thick Film Chip Resistor
R4
S0603CPX4990F10
1
State of the Art
Thick Film Chip Resistor
C35, C38
T525D227M010ATE025
2
KEMET
Ripple 3000mA ESR 25mΩ Polymer Tantalum
Capacitor
C1, C16
T530X157M016ATE015
2
KEMET
High Capacitance Ultra-Low ESR Tantalum SMD Cap
C12, C29, C30
T530X337M010ATE005
3
KEMET
High Capacitance Ultra-Low ESR Tantalum SMD Cap
8
Taiyo Yuden
Ceramic Cap
1
INTERSIL
18 Pin Flat-Pack Package K18.A
PAD_80
10
GENERIC
0.080 Pad with .037 Plated Thru Hole
L1
744311100
1
Wurth Elektronik
SMT Power Inductor
L2
744310055
1
Wurth Elektronik
SMT Power Inductor
C4, C15, C19, C23, C26, C33, TMK107BJ105KA-T
C41, C44
U3
P1-P10
ISL75051SRH
10
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Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
FIGURE 14. TOP COMPONENTS
11
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Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
(Continued)
FIGURE 15. BOTTOM LAYER (MIRRORED)
12
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Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
(Continued)
FIGURE 16. 1 ST LAYER
13
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Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
(Continued)
FIGURE 17. 2 ND LAYER
14
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Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
(Continued)
FIGURE 18. 3 RD LAYER
15
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Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
(Continued)
FIGURE 19. 4 TH LAYER
16
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Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
(Continued)
FIGURE 20. 5 TH LAYER
17
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October 21, 2011
Application Note 1707
VIRTEX5MEZPWREV1Z Board Layout
(Continued)
FIGURE 21. 6 TH LAYER
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
AN1707.0
October 21, 2011
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