Data Sheet

HEF4043B-Q100
Quad R/S latch with 3-state outputs
Rev. 1 — 15 July 2013
Product data sheet
1. General description
The HEF4043B-Q100 is a quad R/S latch with 3-state outputs with a common output
enable input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH
reset input (1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
The nR and nS inputs determine the latch output (nQ) when OE is HIGH (see Table 3).
When OE is LOW, the latch outputs are in the high impedance OFF-state. OE does not
affect the state of the latch. The high impedance off-state feature allows common bussing
of the outputs.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 ESD protection:
 MIL-STD-833, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
3. Applications
 Four-bit storage with output enable
HEF4043B-Q100
NXP Semiconductors
Quad R/S latch with 3-state outputs
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
HEF4043BT-Q100 SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
5. Functional diagram
4 1S
1Q 2
3 1R
6 2S
2Q 9
7 2R
12 3S
3-STATE
OUTPUTS
nS
nQ
3Q 10
11 3R
nR
14 4S
4Q 1
15 4R
OE
5 OE
to other latches
001aae618
001aae616
Fig 1.
Functional diagram
HEF4043B_Q100
Product data sheet
Fig 2.
Logic diagram for one latch
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Quad R/S latch with 3-state outputs
6. Pinning information
6.1 Pinning
+()%4
4
9''
4
5
5
6
6
QF
2(
6
6
5
5
4
966
4
DDD
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1Q to 4Q
2, 9, 10, 1
3-state buffered latch output
1R to 4R
3, 7, 11, 15
reset input (active HIGH)
1S to 4S
4, 6, 12, 14
set input (active HIGH)
OE
5
common output enable input
VSS
8
ground supply voltage
n.c.
13
not connected
VDD
16
supply voltage
7. Functional description
Table 3.
Function table[1]
Inputs
Output
OE
nS
nR
nQ
L
X
X
Z
H
L
H
L
H
H
X
H
H
L
L
latched
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.
HEF4043B_Q100
Product data sheet
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Quad R/S latch with 3-state outputs
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Max
Unit
0.5
+18
V
-
10
mA
0.5
VDD + 0.5
V
-
10
mA
input/output current
-
10
mA
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
VI < 0.5 V or VI > VDD + 0.5 V
Min
VO < 0.5 V or VO > VDD + 0.5 V
IDD
supply current
-
50
mA
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+85
C
-
500
mW
-
100
mW
Ptot
total power dissipation
Tamb 40 C to +85 C
P
power dissipation
per output
[1]
[1]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
supply voltage
3
-
15
V
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
HEF4043B_Q100
Product data sheet
Conditions
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Quad R/S latch with 3-state outputs
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
LOW-level output current
II
input leakage current
IOZ
OFF-state output current
IDD
CI
supply current
Conditions
IO < 1 A
VDD
Tamb = 40 C Tamb = 25 C
Product data sheet
Min
Max
Min
Max
Min
Max
5V
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
mA
VO = 4.6 V
5V
-
0.52
-
0.44
-
0.36 mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
VO = 1.5 V
15 V
3.6
-
3.0
-
2.4
-
mA
15 V
-
0.3
-
0.3
-
1.0
A
nQ output HIGH;
returned to VDD
15 V
-
1.6
-
1.6
-
12.0
A
nQ output LOW;
returned to VSS
15 V
-
1.6
-
1.6
-
12.0
A
IO < 1 A
IO < 1 A
IO < 1 A
IO = 0 A
5V
-
20
-
20
-
150
A
10 V
-
40
-
40
-
300
A
15 V
-
80
-
80
-
600
A
-
-
-
7.5
-
-
pF
input capacitance
HEF4043B_Q100
Tamb = 85 C Unit
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NXP Semiconductors
Quad R/S latch with 3-state outputs
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; For waveforms and test circuit see Section 12; unless otherwise specified.
Symbol
Parameter
HIGH to LOW
propagation delay
tPHL
tPLH
Conditions
nR nQ;
see Figure 4
LOW to HIGH
propagation delay
nS nQ;
see Figure 4
transition time
nQ output;
see Figure 4
VDD
Extrapolation formula
Min
Typ
Max
Unit
63 ns + (0.55 ns/pF)CL
-
90
180
ns
10 V
24 ns + (0.23 ns/pF)CL
-
35
70
ns
15 V
17 ns + (0.16 ns/pF)CL
-
25
50
ns
38 ns + (0.55 ns/pF)CL
-
65
135
ns
14 ns + (0.23 ns/pF)CL
-
25
50
ns
5V
5V
[1]
[1]
10 V
7 ns + (0.16 ns/pF)CL
-
15
35
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
15 V
tt
HIGH to OFF-state
propagation delay
tPHZ
LOW to OFF-state
propagation delay
tPLZ
tPZH
tPZL
OE nQ;
see Figure 5
OFF-state to HIGH
propagation delay
OE nQ;
see Figure 5
OFF-state to LOW
propagation delay
OE nQ;
see Figure 5
pulse width
tW
OE nQ;
see Figure 5
5V
[1] [2]
5V
-
45
90
ns
10 V
-
20
35
ns
15 V
-
10
25
ns
5V
-
50
100
ns
10 V
-
20
40
ns
15 V
-
10
25
ns
5V
-
25
50
ns
10 V
-
15
30
ns
15 V
-
10
25
ns
5V
-
40
80
ns
10 V
-
20
45
ns
15 V
-
15
35
ns
30
15
-
ns
20
10
-
ns
16
8
-
ns
30
15
-
ns
nS input HIGH;
5V
minimum width; 10 V
see Figure 4
15 V
nR input HIGH; 5 V
minimum width; 10 V
see Figure 4
15 V
20
10
-
ns
16
8
-
ns
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
tt is the same as tTHL and tTLH.
HEF4043B_Q100
Product data sheet
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Quad R/S latch with 3-state outputs
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
Typical formula for PD (W)
where:
5V
PD = 1100  fi + (fo  CL)  VDD
10 V
PD = 4400  fi + (fo  CL)  VDD2
fo = output frequency in MHz;
15 V
PD = 11400  fi + (fo  CL) 
CL = output load capacitance in pF;
2
fi = input frequency in MHz;
VDD2
VDD = supply voltage in V;
(fo  CL) = sum of the outputs.
12. Waveforms
tr
VI
tf
90 %
input nS
VM
0V
10 %
tW
VI
input nR
VM
0V
tW
tPLH
VOH
tPHL
90 %
output nQ
VM
VOL
10 %
tTLH
tTHL
001aai286
tr and tf are the input rise and fall times.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.
Measurement points are given in Table 9 and test data is given in Table 10.
Fig 4.
Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation
delay and nQ transition time
HEF4043B_Q100
Product data sheet
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NXP Semiconductors
Quad R/S latch with 3-state outputs
VDD
OE input
VSS
tPLZ
output
LOW-to-OFF
OFF-to-LOW
tPZL
VDD
VY
VX
VSS
tPHZ
VDD
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VX
VSS
outputs on
outputs off
outputs on
001aag355
Measurement points are given in Table 9.
Fig 5.
Output enable (OE) to latch output (nQ) enable time (tPZL and tPZH) and disable time (tPLZ and tPHZ)
Table 9.
Measurement points
Supply voltage
Input
VDD
VI
VM
VM
VX
VY
5 V to 15 V
VDD or 0 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
HEF4043B_Q100
Product data sheet
Output
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Quad R/S latch with 3-state outputs
VI
tW
90 %
90 %
negative
pulse
VM
0V
10 %
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
90 %
VM
VM
10 %
10 %
tW
001aaj781
a. Input waveform
VEXT
VDD
VI
RL
VO
G
DUT
RT
CL
001aaj915
b. Test circuit
Test and measurement data is given in Table 10.
Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 6.
Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
5 V to 15 V
HEF4043B_Q100
Product data sheet
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
VDD
 20 ns
50 pF
1 k
open
VDD
GND
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Quad R/S latch with 3-state outputs
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 7.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4043B_Q100
Product data sheet
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Quad R/S latch with 3-state outputs
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4043B_Q100 v.1
20130715
Product data sheet
-
-
HEF4043B_Q100
Product data sheet
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NXP Semiconductors
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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data sheet shall define the specification of the product as agreed between
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customer have explicitly agreed otherwise in writing. In no event however,
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deemed to offer functions and qualities beyond those described in the
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changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4043B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
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authorized or warranted to be suitable for use in life support, life-critical or
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
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purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 July 2013
© NXP B.V. 2013. All rights reserved.
12 of 14
HEF4043B-Q100
NXP Semiconductors
Quad R/S latch with 3-state outputs
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4043B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 July 2013
© NXP B.V. 2013. All rights reserved.
13 of 14
HEF4043B-Q100
NXP Semiconductors
Quad R/S latch with 3-state outputs
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 July 2013
Document identifier: HEF4043B_Q100