DATASHEET

DATASHEET
Dual Channel/Dual Phase PMBus™ ChargeMode™
Control DC/DC Digital Controller
ZL8802
Features
The ZL8802 is a dual output or dual phase digital DC/DC
controller. Each output can operate independently or be used
together in a dual phase configuration for high current
applications supporting 2-, 4-, 6- and 8-phase operation with
up to four ZL8802s.
• Unique compensation-free design – always stable
The ZL8802 supports a wide range of output voltages
(0.54V to 5.5V) operating from input voltages as low as 4.5V
up to 14V.
• ChargeMode control achieves fast transient response,
reduced output capacitance and provides output stability
without compensation.
With the fully digital ChargeMode control, the ZL8802 will
respond to a transient load step within a single switching cycle.
This unique compensation-free modulation technique allows
designs to meet transient specifications with minimum output
capacitance, thus saving cost and board space.
• 2-channel output, 2-, 4-, 6- or 8-phase output with 2, 3 or 4
devices
Intersil’s proprietary single-wire DDC (Digital-DC™) serial bus
enables the ZL8802 to communicate between other Intersil
digital power ICs. By using the DDC, the ZL8802 achieves
complex functions such as inter-IC phase current balancing,
sequencing and fault spreading. This eliminates complicated
power supply managers with numerous external discrete
components.
The ZL8802 features fast output overcurrent protection. The
input voltage, output voltages and DrMOS/MOSFET driver
supply voltages are overvoltage and undervoltage protected.
Two external and one internal temperature sensors are
available for temperature monitoring, one of which can be
configured for under- and over-temperature protection. A
snapshot parametric capture feature allows users to take a
snapshot of operating and fault data during normal or fault
conditions.
Integrated Low Dropout (LDO) regulators allow the ZL8802 to
operate from a single input supply eliminating the need for
additional linear regulators. The VDRV LDO output can be used
to power external drivers or DrMOS devices.
• Output voltage range: 0.54V to 5.5V
• Input voltage range: 4.5V to 14V
• 1% output voltage accuracy over line, load and temperature
• Switching frequency range 200kHz to 1.33MHz
• Proprietary single-wire DDC (Digital-DC) serial bus enables
voltage sequencing and fault spreading with other Intersil
digital power ICs
• Inductor peak and averaged over and undercurrent
protection
• Digital fault protection for output voltage UV/OV, input
voltage UV/OV, temperature and MOSFET driver voltage
• Accurate average output current measurement with
adjustable gain settings for sensing with SPS current
monitor outputs or high current, low DCR inductors
• Monitor ADC measures input voltage, input current, output
voltage, driver voltage, internal and external temperature
• Nonvolatile memory for storing operating parameters and
fault events
• PMBus™ compliant
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
With full PMBus™ compliance, the ZL8802 is capable of
measuring and reporting input voltage, input current, output
voltage, output current as well as the device’s internal
temperature, 2 external temperatures and an auxiliary voltage
or temperature input.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
DUAL OUTPUT
DUAL PHASE
ZL8800
Yes
ZL8801
No
ZL8802
Yes
December 11, 2015
FN8760.1
1
DDC CURRENT SHARE
SPS SUPPORT
Yes
No
No
Yes
Yes
No
Yes
Yes
Yes
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design), ChargeMode, Digital-DC and PowerNavigator are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ZL8802
Table of Contents
Two-Phase Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ZL8802 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin-Strap Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configurable Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage and VOUT_MAX Selection (VSET0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency Setting (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Undervoltage Lockout Setting (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Setting (CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ChargeMode Control (ASCR) Setting (ASCRCFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up and Shutdown Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ton-Delay and Rise Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Pin Operation and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
11
12
12
12
12
13
13
14
14
14
15
15
16
16
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Limit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring Using XTEMP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonvolatile Memory and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
17
18
18
18
18
19
19
19
20
20
20
20
21
21
21
PMBus™ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMBus™ Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMBus™ Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMBus™ Command Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MFR_SMBALERT_MASK (DBh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
25
26
27
70
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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2
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VIN
VDD
V25
V6
VCC
10µF
3
ZL880 2
VIN
V5
VDRV
PVCC
IINP
10µF
2 x 22µF
1µF
1mΩ
(OPTIONAL)
IINN
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Two-Phase Application
BOOT
PHASE
CGND
0.22µF
ISL992 26
IMON
SYNC
ISENA0
ISENB0
PWM0
VSWH
REFIN
PWM
PGND
CFG
ASCRCFG
TMON
UVLO
VOUT
VSET1
VSET0
SA
2 x 22µF
10µF
VCC
PG
VIN
PVCC
EN
CONTROL AND
STATUS
BOOT
0.22µF
PHASE
CGND
ISL992 26
V5
10kΩ
INTER-DEVICE
COORDINATION
(OPTIONAL)
DDC
PMBUS
(OPTIONAL)
SDA
ISENB1
PWM1
REFIN
TMON
TMON
SYNC
SCL
VSWH
PWM
PGND
ISENA1
IMON
VSEN0N
VSEN0P
DGND SGND
FN8760.1
December 11, 2015
FIGURE 1. TWO-PHASE APPLICATION
ZL8802
VIN
VDRV
ZL8802
Block Diagram
VSE N0P/N
ADC
PGA
ASCR
DIG ITAL PWM
MODULATOR
PWM+
DEAD TIME
ASCR
DIG ITAL PWM
MODULATOR
PWM+
DEAD TIME
PWMH0
PWMEN0
DAC
VSE N1P/N
ADC
PGA
PWMH1
PWMEN1
DAC
XTEMP0P/N
MUX
XTEMP1P/N
MONITOR
ADC
VMON/TMO N
DIG ITAL LOGIC
+
OV/UV/OC/UC
COMPARATORS
VDD
VTRKP/N
EN0/1
PG0/1
OSC
ISENA0
CLK GEN
Ipea k/IAV G
ADC
PLL
PGA
SYNC
ISENB0
PGA
ISENB1
IIN
ADC
LDO s
IINN
GAIN
VDRVEN
VDD
UVLO
VSE T1
VSE T0
SA
CFG
ASCRCFG
PIN-STRAP RESISTOR
DETECTION
IINP
2
I C AND SMBus
SERIAL
INTERFACE
VR6
SALRT
ISENA1
Ipea k/IAV G
ADC
VDRV
SCL
MICROCONTROLLER
AND
NONVOLATILE
MEMORY
V25
SDA
Digital-DC
INTER-DEVICE
COMMUNICATIO NS
VR5
DDC
FIGURE 2. BLOCK DIAGRAM
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ZL8802
Pin Configuration
ZL8802
(44 LD QFN)
TOP VIEW
(PAD)
Pin Description
PIN
#
TYPE
PIN NAME (Note 1)
DESCRIPTION
1
SCL
I/O
Serial clock. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V (recommend
VR5, do not use V25) source. Pull-up supply must be from an “always on” source or VR5.
2
SDA
I/O
Serial data. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V (recommend
VR5, do not use V25) source. Pull-up supply must be from an “always on” source or VR5.
3
SALRT
O
Serial alert. Connect to external host if desired. Requires a pull-up resistor to a 2.5V to 5.5V (recommend VR5, do not use
V25) source. Leave floating if not used.
4
SGND
PWR
Connect to low impedance ground plane. Internal connection to SGND. All pin-strap resistors should be connected to SGND.
SGND must be connected to DGND and PGND using a single point connection.
5
SA
M
Serial address select pin. Used to assign unique address for each individual device. See Table 3 for PMBus address options.
Connect resistor to SGND.
6
VMON/
TMON
I
Smart power stage temperature monitoring or general purpose voltage monitoring pin. Requires an external 2:1 resistor
divider network to correctly read temperature. Requires an external 16:1 resistor divider network to read voltage. Connect
bottom of resistor divider network to SGND. Connect VMON/TMON pin to SGND if not used.
7
DGND
PWR
8
ASCRCFG
M
Selects ChargeMode control (ASCR) configuration settings. See “Configurable Pins” on page 12 and Table 8 on page 14
for details.
9
CFG
M
Selects current sense, current limit and operating mode. See “Configurable Pins” on page 12 and Table 8 on page 14 for
details.
10
VSET0
M
Channel 0 output voltage selection pin. Used to set VOUT0 and VOUT0 max. See Table 4 on page 12 for VOUT pin-strap
options. Default VOUT max is 115% of VOUT setting, but this can be overridden via the PMBus interface with the VOUT_MAX
command. Connect resistor to SGND.
11
VSET1
M
Channel 1 output voltage selection pin. Used to set VOUT1 and VOUT1 max. See Table 4 on page 12 for VOUT pin-strap
options. Default VOUT max is 115% of VOUT setting, but this can be overridden via the PMBus interface with the VOUT_MAX
command. Connect resistor to SGND. NOT USED IN 2-PHASE MODE. Leave floating in 2-phase mode.
12
PG0
O
Channel 0 power-good output. Can be configured as open drain or push-pull using the PMBus interface. Default setting is
open drain.
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Digital ground. Must connect to SGND and PGND using a single point connection.
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ZL8802
Pin Description
PIN
#
(Continued)
TYPE
PIN NAME (Note 1)
DESCRIPTION
13
UVLO
M
Undervoltage lockout selection. Sets the minimum value for VDD voltage to enable VOUT. See Table 6 on page 13 for UVLO
setting options. Pin-strapped (configured) values can be overridden by the PMBus interface. Connect resistor to SGND. If
enabling the device by tying the EN0 and or EN1 pins high (self-enabling), set the UVLO level to 16V with a 100k resistor
so the device will not turn on until after a configuration file has been loaded.
14
DDC
I/O
Single-wire DDC bus (current sharing, interdevice communication). Requires a pull-up resistor to a 2.5V to 5.5V
(recommend VR5, no not use V25) source. Pull-up voltage must be present when the device is powered. Pull-up supply
must be from an “always on” source or VR5.
15
XTEMP0P
I
External temperature sensor input for Channel 0. Connect to external 2N3904 (base emitter junction) or equivalent
embedded thermal diode. If not used connect to SGND.
16
XTEMP0N
I
External temperature sensor input for Channel 0 return. If not used connect to SGND.
17
VTRKP
-
Tracking sense positive input. Used to track an external voltage source. Tracking is only possible in 2-phase operation, or
with a single channel in a 2-channel configuration. Tracking is disabled in 4-, 6- and 8-phase operation. If not used connect
to SGND.
18
VTRKN
-
Tracking sense negative input (return). If not used connect to SGND.
19
VSEN0P
I
Differential output Channel 0 voltage sense feedback. Connect to positive output regulation point.
20
VSEN0N
I
Differential output Channel 0 voltage sense feedback. Connect to negative output regulation point.
21
VDRVEN
I
VDRV (MOSFET Driver Bias Supply) enable. Leave unconnected (float) or pull up to VR5 to enable, tie to ground to disable.
22
ISENA0
I
Positive differential voltage input for Channel 0 DCR current sensing. Should be routed as a pair with ISENB0. Should
connect to resistor located close to output inductor. See “SPS Current Sensing” on page 17.
23
ISENB0
I
Negative differential voltage input for Channel 0 DCR current sensing. Should be routed as a pair with ISENA0. Should be
connected to output inductor terminal. See “SPS Current Sensing” on page 17.
24
PWMEN0
O
Used to drive DrMOS enable where applicable. Leave unconnected when not used.
25
PWMH0
O
PWM0 high signal.
26
PWMH1
O
PWM1 high signal.
27
PWMEN1
O
Used to drive DrMOS enable where applicable. Leave unconnected when not used.
28
ISENB1
I
Negative differential voltage input for Channel 1 DCR current sensing. Should be routed as a pair with ISENA1. Should be
connected to output inductor terminal. See “SPS Current Sensing” on page 17 for details.
29
ISENA1
I
Positive differential voltage input for Channel 1 DCR current sensing. Should be routed as a pair with ISENB1. Should
connect to resistor located close to output inductor. See “SPS Current Sensing” on page 17 for details.
30
VDRV
PWR
MOSFET driver bias supply regulator output. If disabled, this pin can be left floating. Decouple with a high quality 4.7µF
X7R or better ceramic capacitor placed close to this pin.
31
VR6
PWR
Bypass for internal 6V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better ceramic
capacitor placed close to this pin. Keep this net as small as possible. Do not route near switching signals.
32
VR5
PWR
Bypass for internal 5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better ceramic
capacitor placed close to this pin.
33
VDD
PWR
Supply voltage. Decouple with a high quality 1µF X7R or better ceramic capacitor placed close to this pin.
34
IINN
I
Input current monitor negative input. If not used connect to VDD.
35
IINP
I
Input current monitor positive input. If not used connect to VDD.
36
V25
PWR
Internal 2.5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better ceramic capacitor
placed close to this pin.
37
PG1
O
Channel 1 power-good output. Can be configured as open drain or push-pull using the PMBus interface. Default setting is
open drain.
38
VSEN1N
I
Differential output Channel 1 voltage sense feedback. Connect to negative output regulation point. NOT USED IN 2-PHASE
MODE. Leave floating in 2-phase mode.
39
VSEN1P
I
Differential output Channel 1 voltage sense feedback. Connect to positive output regulation point. NOT USED IN 2-PHASE
MODE. Leave floating in 2-phase mode.
40
XTEMP1N
I
External temperature sensor input for Channel 1 return. If not used connect to SGND.
I
External temperature sensor input for Channel/Phase 1. Connect to external 2N3904 (base emitter junction) or equivalent
embedded thermal diode. If not used connect to SGND.
41
XTEMP1P
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FN8760.1
December 11, 2015
ZL8802
Pin Description
PIN
#
(Continued)
TYPE
PIN NAME (Note 1)
DESCRIPTION
42
EN0
I
Enable Channel 0. Active signal enables PWM0 switching. Recommended to be tied low during device configuration. Refer
to “Enable Pin Operation and Timing” on page 16 for additional information.
43
EN1
I
Enable Channel 1. Active signal enables PWM1 switching. Recommended to be tied low during device configuration. Refer
to “Enable Pin Operation and Timing” on page 16 for additional information. NOT USED IN 2-PHASE MODE. Leave floating
in 2-phase mode.
44
SYNC
M/I/O
Clock synchronization input. Used to set the frequency of the internal clock, to sync to an external clock or to output internal
clock. When configured as an output this pin is push-pull and does not require a pull-up. See ““Switching Frequency Setting
(SYNC)” on page 12 and Table 5 on page 12 for additional information.
PAD
SGND
PWR
Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.
NOTE:
1. I = Input, O = Output, PWR = Power or Ground, M = Multimode pins.
Ordering Information
PART
MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
QUANTITY
(Units)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ZL8802ALAFT
8802
-40 to +85
4k
44 Ld QFN
L44.7x7B
ZL8802ALAFT7A
8802
-40 to +85
250
44 Ld QFN
L44.7x7B
ZL8802ALAFTK
8802
-40 to +85
1k
44 Ld QFN
L44.7x7B
PART
NUMBER
(Notes 2, 3, 4)
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ZL8802 For more information on MSL please see techbrief TB363.
ZL8802
A L A F T
Product Designator
Shipping Option
T = Tape and Reel - 4000 pcs
Contact factory for other options
Lead Finish
F = Lead-free matte tin
Firmware Revision
Alpha character
Operating Temperature Range
L = -40°C to +85°C
Package Designator
A = QFN package
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FN8760.1
December 11, 2015
ZL8802
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage: VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic I/O voltage: DDC, EN0, EN1, PG0, PG1, SA, VDRVEN,
SALRT, SCL, SDA, SYNC, UVLO, VMON/TMON, VSET0,
VSET1, CFG, ASCRCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Analog Input Voltages: VSEN0P, VSEN0N, VSEN1P, VSEN1N,
ISENA0, ISENA1, ISENB0, ISENB1 . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
XTEMP0P, XTEMP1P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
XTEMP0N, XTEMP1N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
IINN, IINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic Reference: V25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Bias Supplies: VR5, VR6, VDRV. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
PWM Logic Outputs, PWMH0, PWMH1, PWML0, PWML1 . . . .-0.3V to 6.5V
Ground Voltage Differential (VDGND-VSGND), . . . . . . . . . . . . . . .-0.3V to +0.3V
ESD Ratings
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . 3000V
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C1010-D) . . . . . . . . . . 1000V
Latch-Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
44 Ld QFN Package (Notes 6, 7) . . . . . . . .
25
1.5
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Input Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Output Voltage Range, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
5V (VR5) Supply Total Supplied Current (Note 8) . . . . . . . . . . . . . . . . . 5mA
5V LDO Supply (VDRV) (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 80mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. Output current is limited by device thermal dissipation.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Total of current used by pull-ups to SDA, SCL, SALRT, DDC, EN, PG (including push-pull configuration).
Electrical Specifications
range, TA -40°C to +85°C
VDD = 12V. Typical values are at TA = +25°C. Boldface limits apply across the operating ambient temperature
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
MAX
(Note 14)
UNIT
IC INPUT AND BIAS SUPPLY CHARACTERISTICS
IDD Supply Current
fSW = 200kHz
-
26
50
mA
fSW = 1.33MHz
-
50
80
mA
IDD Device Disabled Current
EN = 0V, SMBus inactive, VDD = 12V, fSW = 1.33MHz
-
20
40
mA
VR5 Reference Output Voltage
VDD > 6V, I < 5mA
4.5
5.0
5.5
V
V25 Reference Output Voltage
For reference only, VR > 3V
2.25
2.5
2.75
V
VR6 Reference Output Voltage
For reference only, VDD = 12V
5.5
6.1
6.6
V
VDRV 5V Output Voltage (Note 9)
VDD > 6.0V; 0 to 80mA
4.5
5.25
5.5
V
0.54
-
5.5
V
-1
-
1
% VOUT
OUTPUT CHARACTERISTICS
Output Voltage Adjustment Range
VIN > VOUT + 1.1V
Output Voltage Set-point Accuracy (Note 11)
Across line, load, temperature variation 0.72 < VOUT < 5.50
Output Voltage Set-point Resolution (Note 10)
Set using PMBus™ command
Output Voltage Positive Sensing Bias Current
VSEN[0,1] P = 4V (negative = sinking)
Output Voltage Negative Sensing Bias Current
VSEN[0,1] N = 0V
-
±0.025
-
% VOUT
-100
20
100
µA
-
20
-
µA
-100
-
100
nA
-
-
0.8
V
LOGIC INPUT/OUTPUT CHARACTERISTICS
Logic Input Leakage Current
Logic I/O - multimode pins
Logic Input Low, VIL
2
-
-
V
Logic Output Low, VOL
2mA sinking
-
-
0.5
V
Logic Output High, VOH
2mA sourcing
2.25
-
-
V
Logic Input High, VIH
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FN8760.1
December 11, 2015
ZL8802
Electrical Specifications
range, TA -40°C to +85°C (Continued)
VDD = 12V. Typical values are at TA = +25°C. Boldface limits apply across the operating ambient temperature
MIN
(Note 14)
TYP
MAX
(Note 14)
UNIT
2mA sinking
-
-
0.5
V
PWM Output High
2mA sourcing
4.25
-
-
V
PWM Tri-State Input Bias Current (PWMH0, 1)
VPWM = 2.5V
-
-
10
µA
PARAMETER
TEST CONDITIONS
PWM OUTPUT CHARACTERISTICS
PWM Output Low
PWM Tri-State transition (always starts from LOW) 10pF maximum load
1
µs
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
Switching Frequency Set-point Accuracy
200
-
1334
kHz
-5
-
5
%
Minimum SYNC Pulse Width
50% to 50%
150
-
-
ns
Input Clock Frequency Drift Tolerance
Maximum allowed drift of external clock
-10
-
10
%
100
-
400
kHz
5000
ms
PMBus™ Clock Frequency (Note 12)
POWER MANAGEMENT
SOFT START/RAMP CHARACTERISTICS
Ton-delay/Toff-Delay Range
Set using PMBus™ command
0
Ton-Delay Accuracy
2-phase Ton-delay > 4ms
-
Toff-Delay Accuracy
Set to immediate off
Ton-Rise/Toff-Fall Duration Range
Set using PMBus™ command (2-phase or 2-channel only)
Ton-Rise/Toff-Fall Duration Accuracy
2-phase or 2-channel only
+/-1
-
-0/+1
0.0
ms
ms
100
ms
±250
-
µs
2.85
-
16
V
-
±2
-
% FS
-
MONITORING AND FAULT MANAGEMENT
INPUT VOLTAGE MONITOR AND FAULT DETECTION
VDD/VIN UVLO Threshold Range
VDD/VIN Monitor Accuracy
Full Scale (FS) = 14V
VDD/VIN Monitor Resolution
Full Scale (FS) = 14V
-
±0.15
-
% FS
-
100
-
µs
VIINP-VIINN
0
-
20
mV
Input Current Sense Input Offset Voltage
VIINP-VIINN
-
±100
-
µV
Input Current Sense Accuracy
% of full scale (20mV)
-
±5
-
% FS
VIN UV Fault Response delay
INPUT CURRENT
Input Current Sense Differential Input Voltage
OUTPUT VOLTAGE MONITOR AND FAULT DETECTION
VOUT Monitor Accuracy
FS = VSET voltage (VOUT)
-2
-
2
% FS
VOUT Monitor Resolution
FS = VSET voltage (VOUT)
-
± 0.15
-
% FS
-
10
-
µs
VOUT UV Fault Response Delay
OUTPUT CURRENT
OUTPUT CURRENT SENSE RESOLUTION
Low Range
±25mV Full Scale
-
37.5
-
µV
Medium Range
±35mV Full Scale
-
56.25
-
µV
High Range
±50mV Full Scale
-
75.0
-
µV
ISENA0 or ISENA1
-100
-
100
nA
ISENB0 or ISENB1
-25
-
25
µA
12700
ppm/°C
OUTPUT CURRENT SENSE INPUT BIAS CURRENT
VOUT Referenced
OUTPUT CURRENT SENSE MONITOR AND FAULT DETECTION
Output Current DCR Monitor Temperature
Compensation
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9
Configurable via PMBus™
0
FN8760.1
December 11, 2015
ZL8802
Electrical Specifications
range, TA -40°C to +85°C (Continued)
VDD = 12V. Typical values are at TA = +25°C. Boldface limits apply across the operating ambient temperature
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
MAX
(Note 14)
UNIT
2.85
–
5
V
TMON BIAS MONITOR AND FAULT DETECTION
TMON UVLO Threshold Range
Using TMON pin with 16:1 resistor divider
TMON Accuracy (Note 13)
Full Scale (FS) = 1.15V
-2
–
2
% FS
TMON Resolution
Full Scale (FS) = 1.15V
–
±0.15
–
% FS
–
200
–
µs
-5
–
5
°C
–
1
–
°C
–
125
–
°C
-40
–
125
°C
TMON UV/OV Fault Response Delay
TEMPERATURE SENSING
INTERNAL TEMPERATURE SENSOR
Internal Temperature Accuracy
Tested at +100°C
Internal Temperature Resolution
Thermal Protection Threshold
(Junction temperature)
Factory default
Configurable via PMBus™
EXTERNAL TEMPERATURE SENSOR: XTEMP0 AND XTEMP1
External Temperature Accuracy
Filter capacitance <100pF
External Temperature Resolution
Thermal Protection Threshold
Factory default
Configurable via PMBus™
-
±5
-
°C
–
1
–
°C
–
125
–
°C
-40
–
125
°C
NOTES:
9. Output current is limited by device thermal dissipation.
10. Percentage of Full Scale (FS) with temperature compensation applied.
11. VOUT measured at the termination of the VSENxP and VSENxN sense points.
12. For operation at 400kHz, see PMBus™ Power System Management Protocol Specification Part 1, Section 5.2.6.2 for timing parameter limits.
13. Does not include errors due to resistor divider tolerances.
14. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
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FN8760.1
December 11, 2015
ZL8802
ZL8802 Overview
Digital-DC Architecture Overview
The ZL8802 is an innovative mixed-signal power conversion and
power management IC based on Intersil patented Digital-DC
technology that provides an integrated, high performance
step-down converter for a wide variety of power supply
applications.
The ZL8802 DC/DC controller is a dual channel, dual phase
controller based on an architecture that does not require loop
compensation.
The ZL8802s full digital loop achieves precise control of the
entire power conversion process with no software required
resulting in a very flexible device that is also very easy to use. The
ChargeMode control algorithm is implemented to respond to
output current changes within a single PWM switching cycle. This
achieves a smaller total output voltage variation with less output
capacitance than traditional PWM controllers. An extensive set of
power management functions are fully integrated and can be
configured using simple pin connections. The user configuration
can be saved in an internal Nonvolatile Memory (NVRAM).
Additionally, all functions can be configured and monitored via
the SMBus hardware interface using standard PMBus™
commands, allowing ultimate flexibility. The ZL8802 is compliant
with the PMBus™ Power System Management Protocol
Specification Part I and II version 1.2.
Once enabled, the ZL8802 is immediately ready to regulate
power and perform power management tasks with no
programming required. Advanced configuration options and
real-time configuration changes are available via PMBus™
commands if desired and continuous monitoring of multiple
operating parameters is possible with minimal interaction from a
host controller. Integrated subregulation circuitry enables single
supply operation from any supply between 4.5V and 14V with no
bias supplies needed.
The ZL8802 can be configured by simply connecting its pins
according to the tables provided in the following sections.
Additionally, a comprehensive set of online tools and application
notes are available to help simplify the design process. An
evaluation board is also available to help the user become
familiar with the device. This board can be evaluated as a
standalone platform using pin configuration settings.
PowerNavigator™, a Windows based GUI is also provided to
enable full configuration and monitoring capability via the
PMBus interface and the included USB cable.
Power Management Overview
The ZL8802 incorporates a wide range of configurable power
management features that are simple to implement with no
external components. Additionally, the ZL8802 includes circuit
protection features that continuously safeguard the device and
load from damage due to unexpected system faults. The ZL8802
can continuously monitor input voltage and current, output
voltage and current, internal temperature and the temperature of
2 external thermal diodes. A power-good output signal is also
included to enable power-on reset functionality for an external
processor.
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11
All power management functions can be configured using either
pin configuration techniques described in this document or via
the SMBus interface using PMBus™ commands. Monitoring
parameters can also be preconfigured to provide alerts for
specific conditions. The “PMBus™ Command Summary” on
page 22 contains a listing of all the PMBus™ commands
supported by the ZL8802 and a detailed description of the use of
each of these commands.
Pin-Strap Pins
In order to simplify circuit design, the ZL8802 incorporates
patented pin-strap pins that allow the user to easily configure
many aspects of the device with no programming. Most power
management features can be configured using these pins. The
pin-strap pins will read the value of the resistor connected to
those pins when power is applied to the device and set certain
device configuration settings as specified by those resistor
values.
V25
LOGIC
HIGH
MULTIMODE
PIN
OPEN
MULTIMODE
PIN
LOGIC
LOW
PIN-STRAP
SETTINGS
RESISTOR
SETTINGS
FIGURE 3. PIN-STRAP AND RESISTOR SETTINGS
TABLE 2.
PIN TIED TO
VALUE
LOW (Logic LOW)
<0.8 VDC
OPEN (N/C)
No connection
HIGH (Logic HIGH)
>2.0 VDC
Resistor to SGND
Set by resistor value
Device configuration settings are made when connecting a finite
value resistor (in a specified range) between the pin-strap pin and
SGND. Standard 1% resistor values are used, and only every
fourth E96 resistor value is used so the device can reliably
recognize the value of resistance connected to the pin while
eliminating the error associated with the resistor accuracy. Up to
31 unique selections are available using a single resistor.
SMBus: Almost any ZL8802 function can be configured via the
SMBus interface using standard PMBus™ commands.
Additionally, any value that has been configured using the
pin-strap setting method can also be reconfigured and/or verified
via the SMBus. “PMBus™ Command Detail” on page 27 explains
the use of the PMBus™ commands in detail.
FN8760.1
December 11, 2015
ZL8802
Configurable Pins
Numerous operating parameters can be set using the pin-strap
resistor setting method: SMBus address (pin 5, SA), output
voltage (pins 10 and 11, VSET0, 1), switching frequency (pin 44,
SYNC), input voltage undervoltage lockout (pin 13, UVLO). ASCR
gain is set by ASCRCFG (pin 8). CFG (pin 9) sets the power stage
settings such as over and undercurrent limits.
The SMBus device address is the only parameter that must be
set by a pin-strap setting pin. All other device parameters can be
set via the PMBus™. The device address is set using the SA pin.
Output Voltage and VOUT_MAX Selection
(VSET0, 1)
The output voltage may be set to any voltage between 0.54V and
5.5V provided that the input voltage is higher than the desired
output voltage by at least 1.1V. Using the pin-strap method, VOUT
can be set to any of the voltages shown in Table 4. VOUT can also
be set using a PMBus™ command. VOUT_MAX is also
determined by this pin-strap setting, and is 15% greater than the
VSET0 and VSET1 voltage settings by default, however,
VOUT_MAX can be changed via the PMBus.
TABLE 4.
SMBus Device Address Selection (SA)
When communicating with multiple SMBus devices using the
SMBus interface, each device must have its own unique address
so the host can distinguish between the devices. The device
address can be set according to the pin-strap options listed in
Table 3. When operating in 2-channel mode, care must be taken
when using sequential PMBus addresses. Since DDC addresses
are automatically set using the PMBus address, it is possible for
a device with a PMBus address immediately after a 2-channel
ZL8802 to be automatically configured with the same DDC
address as one of the ZL8802 channels, which could cause
unintended operating modes. For this reason, do not use the next
higher PMBus address when using the ZL8802 as a 2-channel
device. See PMBus command “DDC_CONFIG (D3h)” on page 65
for details. The SMBus address cannot be changed with a
PMBus™ command.
TABLE 3. SMBus DEVICE ADDRESS SELECTION
RVSET (kΩ)
VOUT (V)
RVSET (kΩ)
VOUT (V)
LOW
1.00
38.3
1.30
OPEN
1.20
42.2
1.40
HIGH
0.90
46.4
1.50
10
0.60
51.1
1.60
11
0.65
56.2
1.70
12.1
0.70
61.9
1.80
13.3
0.75
68.1
1.90
14.7
0.80
75
2.00
16.2
0.85
82.5
2.10
17.8
0.90
90.9
2.20
19.6
0.95
100
2.30
21.5
1.00
110
2.50
23.7
1.05
121
2.80
26.1
1.10
133
3.00
28.7
1.15
147
3.30
31.6
1.20
162
4.00
34.8
1.25
178
5.00
RSA
(kΩ)
SMBus
ADDRESS
RSA
(kΩ)
SMBus
ADDRESS
LOW
40h
42.2
51h
OPEN
42h
46.4
52h
10
41h
51.1
53h
11
43h
56.2
54h
12.1
44h
61.9
55h
13.3
45h
68.1
56h
Switching Frequency Setting (SYNC)
14.7
46h
75
57h
16.2
47h
82.5
58h
17.8
48h
90.9
59h
19.6
49h
100
5Ah
21.5
4Ah
110
5Bh
The device’s switching frequency is set from 200kHz to 1333kHz
using the pin-strap method as shown in Table 5, or by using a
PMBus™ command. The ZL8802 generates the device switching
frequency by dividing an internal precision 16MHz clock by
integers from 11 to 80. 500kHz (n = 32) and 1000kHz (n = 16)
are not recommended operating frequencies; use 533kHz and
1067kHz for best performance.
23.7
61h
121
5Ch
TABLE 5. SWITCHING FREQUENCY SETTINGS
26.1
4Ch
133
5Dh
RSYNC (kΩ)
FREQ (kHz)
RSYNC (kΩ)
FREQ (kHz)
28.7
4Dh
147
5Eh
LOW
302
23.7
457
31.6
4Eh
162
5Fh
OPEN
400
26.1
533
34.8
4Fh
178
60h
HIGH
485
28.7
571
38.3
50h
10
200
31.6
615
11
222
34.8
727
12.1
242
38.3
800
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FN8760.1
December 11, 2015
ZL8802
TABLE 5. SWITCHING FREQUENCY SETTINGS (Continued)
TABLE 6. INPUT VOLTAGE UNDERVOLTAGE LOCKOUT SETTING
RSYNC (kΩ)
FREQ (kHz)
RSYNC (kΩ)
FREQ (kHz)
13.3
267
42.2
842
LOW
5.50
46.4
7.42
OPEN
4.50
51.1
8.18
HIGH
10.80
56.2
8.99
26.1
4.18
61.9
9.90
28.7
4.59
68.1
10.90
31.6
5.06
75
12.00
14.7
286
46.4
889
16.2
320
51.1
1067
17.8
364
56.2
1143
19.6
381
61.9
1231
21.5
432
68.1
1333
The ZL8802 incorporates an internal Phase-Locked Loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin. When using the internal
oscillator, the SYNC pin can be configured as a clock source for
other Intersil digital power devices.
By default, the SYNC pin is configured as an input. The device will
automatically check for a clock signal on the SYNC pin each time
EN is asserted. The ZL8802’s oscillator will then synchronize with
the rising edge of the external clock.
The incoming clock signal must be in the range of 200kHz to
1.33MHz and must be stable when the enable pin (EN0, EN1) is
asserted. When using an external clock, the frequencies are not
limited to discrete values as when using the internal clock. The
external clock signal must not vary more than 10% from its initial
value and should have a minimum pulse width of 150ns. In the
event of a loss of the external clock signal, the output voltage
may show transient overshoot or undershoot.
If loss of synchronization occurs, the ZL8802 will automatically
switch to its internal oscillator and switch at its programmed
frequency.
When used in a multiphase (4-, 6- and 8-phase) application, the
SYNC pin of one of the devices must be configured as an output.
The device will run from its internal oscillator and will drive the
SYNC pin so other devices can be synchronized to it. The SYNC
pin will not be checked for an incoming clock signal while in this
mode.
The switching frequency can be set to any value between 200kHz
and 1.33MHz using a PMBus™ command. The available
frequencies below 1.33MHz are defined by fSW = 16MHz/N,
where 12 ≤ N ≤ 80.
If a value other than fSW = 16MHz/N is entered using a PMBus™
command, the internal circuitry will select the switching
frequency value using N as a whole number to achieve a value
close to the entered value. For example, if 810kHz is entered, the
device will select 800kHz (N = 20).
RUVLO (kΩ)
UVLO (V)
RUVLO (kΩ)
UVLO (V)
34.8
5.57
82.5
13.20
38.3
6.13
90.9
14.54
42.2
6.75
100
16.00
Once an input undervoltage fault condition occurs, the user may
determine the desired response to the fault condition. The
following input undervoltage protection response options are
available:
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
Refer to “PMBus™ Command Detail” on page 27 for details on
how to select specific overvoltage fault response options using
the VIN_UV_FAULT_RESPONSE command.
When controlling the ZL8802 exclusively through the PMBus™, a
high voltage setting for UVLO can be used to prevent the ZL8802
from being enabled until a lower voltage for UVLO is set using the
VIN_UV_FAULT_LIMIT command.
Configuration Setting (CFG)
The Configuration pin (CFG) sets several device configuration
settings allowing the device to be used in applications without the
need for loading configuration files. The settings are shown in
Table 7. When using the ZL8802 in a 4-phase application, the
master device address must be 1 higher than the slave address.
This must be done in order for the 2 devices to be recognized as
part of a current sharing group. See PMBus command
“DDC_CONFIG (D3h)” on page 65 for details.
TABLE 7.
CONFIGURATION SETTINGS
Page 0
Page 1
RCFG AVERAGE OC PEAK OC AVERAGE OC PEAK OC
(kΩ)
LIMIT (A)
LIMIT (A)
LIMIT (A)
LIMIT (A)
CIRCUIT
10
25
28
25
28
2 Output
11
35
37.5
35
37.5
2 Output
12.1
45
48
45
48
2 Output
Input Voltage Undervoltage Lockout Setting
(UVLO)
13.3
55
60
55
60
2 Output
14.7
60
65
60
65
2 Output
The input Undervoltage Lockout (UVLO) prevents the ZL8802 from
operating when the input falls below a preset threshold, indicating
the input supply is out of its specified range. The input voltage
undervoltage lockout threshold can be set between 4.18V and 16V
using the pin-strap method as shown in Table 6. UVLO can also be
set or changed using the VIN_UV_FAULT_LIMIT command.
16.2
65
70
65
70
2 Output
17.8
35
37.5
25
28
2 Output
19.6
45
48
25
28
2 Output
21.5
55
60
25
28
2 Output
23.7
45
48
35
37.5
2 Output
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FN8760.1
December 11, 2015
ZL8802
TABLE 7.
(Continued)CONFIGURATION SETTINGS
Page 0
TABLE 8. ChargeMode CONTROL (ASCR) SETTINGS (Continued)
Page 1
RCFG AVERAGE OC PEAK OC AVERAGE OC PEAK OC
(kΩ)
LIMIT (A)
LIMIT (A)
LIMIT (A)
LIMIT (A)
CIRCUIT
ASCRCFG
kΩ)
GAIN P0
GAIN P1
ASCRCFG
(kΩ)
GAIN P0
GAIN P1
16.2
400
200
82.5
1000
600
26.1
55
60
35
37.5
2 Output
17.8
400
400
90.9
1000
800
28.7
55
60
45
48
2 Output
19.6
400
600
100
1000
1000
31.6
25
28
35
37.5
2 Output
21.5
400
800
110
100
100
34.8
25
28
45
48
2 Output
23.7
400
1000
121
300
300
38.3
25
28
55
60
2 Output
26.1
600
200
133
500
500
42.2
35
37.5
45
48
2 Output
28.7
600
400
147
700
700
46.4
35
37.5
55
60
2 Output
31.6
600
600
162
900
900
51.1
45
48
55
60
2 Output
34.8
600
800
178
1100
1100
56.2
25
28
25
28
2-Phase
38.3
600
1000
LOW
300
300
61.9
35
37.5
35
37.5
2-Phase
42.2
800
200
OPEN
500
500
68.1
45
48
45
48
2-Phase
46.4
800
400
HIGH
700
700
75
55
60
55
60
2-Phase
82.5
65
70
65
70
2-Phase
90.9
35
37.5
35
37.5
4-PH Master
100
35
37.5
35
37.5
4-PH Slave
110
45
48
45
48
4-PH Master
121
45
48
45
48
4-PH Slave
133
55
60
55
60
4-PH Master
147
55
60
55
60
4-PH Slave
162
65
70
65
70
4-PH Master
178
65
70
65
70
4-PH Slave
LOW
20
22.5
20
22.5
2-Phase
OPEN
20
22.5
20
22.5
2 Output
HIGH
35
37.5
35
37.5
2 Output
ChargeMode Control (ASCR) Setting
(ASCRCFG)
The device’s ChargeMode response can be optimized by
adjusting the ASCR gain and residual settings, either by using the
ASCRCFG pin-strap resistor method as shown in Table 8, or by
using the ASCR_CONFIG PMBus™ command. When using
Table 8, the ASCR Residual is fixed at 90.
TABLE 8. ChargeMode CONTROL (ASCR) SETTINGS
ASCRCFG
kΩ)
GAIN P1
ASCRCFG
(kΩ)
GAIN P0
GAIN P0
GAIN P1
10
200
200
51.1
800
600
11
200
400
56.2
800
800
12.1
200
600
61.9
800
1000
13.3
200
800
68.1
1000
200
14.7
200
1000
75
1000
400
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Start-Up and Shutdown Settings
The device’s start-up and shutdown settings can be set by using
the following PMBus Commands:
TON_DELAY: Sets the time from a low to high EN0 or EN1
transition, or the receipt of an OPERATION command via the
PMBus, to the start of an output voltage ramp.
TON_RISE: Sets the time from the end of the TON_DELAY to the
output voltage reaching regulation.
TOFF_DELAY: Sets the time from a high to low EN0 or EN1
transition, or the receipt of an OPERATION command via the
PMBus, to the start of an output voltage ramp down.
TOFF_FALL: Sets the time from the end of the TOFF_DELAY to the
output voltage reaching 0V.
Note that in the case of 2-channel operation, these settings will
apply to both channels. Each channel can be configured to have
different settings by using the TON_DELAY, TON_RISE,
TOFF_DELAY and TOFF_FALL PMBus commands.
Internal Bias Regulators and Input Supply
Connections
The ZL8802 employs internal Low Dropout (LDO) regulators to
supply bias voltages for internal circuitry, allowing it to operate
from a single input supply. The internal bias regulators are as
follows:
VR6: The VR6 LDO provides a regulated 6.1V bias supply for
internal circuitry. It is powered from the VDD pin. A 4.7µF
ceramic X7R filter capacitor to SGND is required at the VR6 pin.
Keep this net as small as possible and avoid routing this trace
near any switching signals.
VR5: The VR5 LDO provides a regulated 5.1V bias supply for
internal circuitry. It is powered from the VDD pin. A 4.7µF
ceramic X7R filter capacitor to SGND is required at the VR5 pin.
This supply may be used for to provide a pull-up supply as long as
load current does not exceed 5mA.
FN8760.1
December 11, 2015
ZL8802
V25: The V25 LDO provides a regulated 2.5V bias supply for the
main controller circuitry. It is powered from an internal 5V node.
A 4.7µF ceramic X7R filter capacitor to SGND is required at the
V25 pin. This voltage should only be used to set pin-strap pins to
the HIGH state.
VDRV: The VDRV LDO provides a regulated 5.25V bias supply for
external MOSFET driver ICs or DrMOS integrated drivers/FETs. A
4.7µF ceramic X7R filter capacitor to PGND is required, however,
additional capacitance will be needed as specified by the
MOSFET driver or DrMOS device selected. The maximum rated
output current is 80mA, but device thermal limits must be
considered. The power dissipated by the VDRV supply will be
(VIN-5.25V) X IDRV, where IDRV is the current supplied by the
VDRV bias supply. VDRV is enabled by leaving the VDRVEN
unconnected (floating) or connecting it to VR5, and is disabled by
connecting VDRVEN to ground.
NOTE: The internal bias regulators, VR6, VR5 and V25, are not
designed to be outputs for powering other circuitry. The
multimode pins may be connected to the V25 pin for logic HIGH
settings, and the VR5 supply can be used to provide up to 5mA of
pull-up current for the SDA, SCL, SALRT, DDC and PG pins.
Operation with 5V VDD: When operating the ZL8802 at voltages
below 5.5V, the VR6 and VR5 supplies should be connected
directly to VDD for best performance. The VDRV supply should
not be used; the 5V VDD supply should be used instead for
powering DrMOS and MOSFET driver ICs.
VIN
VIN
VDD
VDD
VR6
VR6
VR5
VR5
4.5V < VIN < 5.5V
5.5V < VIN < 14V
FIGURE 4. VR SUPPLY CONNECTIONS
Start-Up Procedure
The ZL8802 follows a specific internal start-up procedure after
power is applied to the VDD pin, as shown in Figure 5.
The device requires approximately 60ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded.
Once this process is completed, the device is ready to accept
commands via the serial interface and the device is ready to be
enabled. If the device is to be synchronized to an external clock
source, the clock frequency must be stable prior to asserting the
EN pin. Once enabled, the device requires approximately 2ms
before its output voltage may be allowed to start its ramp-up
process.
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After the Ton-delay period has expired, the output will begin to
ramp towards its target voltage according to the preconfigured
Ton-rise time.
Input Power Applied
Pre-ramp delay
minimum 2ms
delay between enable
signal and start of output
ramp. Additional delay may
be added with PMBusTM
command
Internal Memory Check
50ms – 70ms
Device will ignore an
enable signal or PMBusTM
commands
Device Ready
FIGURE 5. ZL8802 INTERNAL START-UP PROCEDURE
VIN should be above the ZL8802’s UVLO limit
(VIN_UV_FAULT_LIMIT) before the Enable pin is driven high.
Following this sequence will result in the most consistent turn-on
delays. If a configuration file is needed to ensure proper circuit
operation, when VIN is first applied to the ZL8802, for example,
during initial PCB turn-on and test, the Enable pin must be held
low by some means until the ZL8802 configuration file can be
loaded. If the Enable pin is not held low, then the ZL8802 may
attempt to turn on with incorrect configuration settings, possibly
causing circuit failure.
In those cases where a configuration file is needed to ensure
proper circuit operation and the Enable pin cannot be held low
during the initial application of power, two options are available:
1. Limit VIN to 3.0V during initial testing. The ZL8802
configuration file can be loaded when VIN is as low as 3.0V.
Once the configuration file is loaded VIN can be increased to
the normal input voltage range.
2. Use a 100kΩ pin-strap resistor to set UVLO to 16V. This will
keep the ZL8802 disabled while the configuration file is
loaded. Ensure that the VIN_UV_FAULT_LIMIT command is the
last command in the configuration file.
Ton-Delay and Rise Times
Ton- and Toff-delay and Ramp times are initially set to 5ms. In
some applications, it may be necessary to set a delay from when
an enable signal is received until the output voltage starts to
ramp to its target value. In addition, the designer may wish to
precisely set the time required for VOUT to ramp to its target
value after the delay period has expired. These features may be
used as part of an overall inrush current management strategy or
to precisely control how fast a load IC is turned on. The ZL8802
gives the system designer several options for precisely and
independently controlling both the delay and ramp time periods.
The Ton-delay time begins when the EN pin is asserted. The
Ton-delay time is set using the PMBus™ command TON_DELAY.
The Ton-rise time enables a precisely controlled ramp to the
nominal VOUT value that begins once the Ton-delay time has
expired. The ramp-up is monotonic and its slope may be precisely
set using the PMBus™ command TON_RISE.
FN8760.1
December 11, 2015
ZL8802
The Ton-delay and Ton-ramp times can be set using PMBus™
commands TON_DELAY and TON_RISE over the serial bus
interface. When the Ton-delay time is set to 0ms, the device will
begin its ramp after the internal circuitry has initialized
The Ton-delay and Ton-ramp times can be set using PMBus™
commands TON_DELAY and TON_RISE over the serial bus
interface. When the Ton-delay time is set to 0ms, the device will
begin its ramp after the internal circuitry has initialized which takes
approximately 2ms to complete. The Ton-rise time may be set to
values less than 2ms, however the Ton-rise time should be set to a
value greater than 500µs to prevent inadvertent fault conditions
due to excessive inrush current. A lower Ton-rise time limit can be
estimated using the formula: Ton-rise = COUT*VOUT/ILIMIT where
COUT is the total output capacitance, VOUT is the output voltage
and ILIMIT is the current limit setting for the ZL8802.
When interdevice current sharing is used (4 phases), the output
voltage rise time will vary by application. The rise time in this
case can be adjusted using the PMBus command
MULTI_PHASE_RAMP_GAIN. Higher gain values produce faster
turn-on ramps. Typical MULTI_PHASE_RAMP_GAIN values range
between 1 and 10; the default value is 3. The slew rate of the
output voltage during ramp-up is directly proportional to this
gain, as well as the input voltage (VIN) and the device switching
frequency (FREQUENCY_SWITCH). The slew rate of the output
voltage during turn-on can be calculated with the following
formula:
Slew Rate (mV/ms) = 14*(VIN)*(MULTI_PHASE_RAMP_GAIN) *
(FREQUENCY_SWITCH in MHz)
The resulting total rise time can then be calculated:
Rise Time = Output Voltage/Slew Rate
Enable Pin Operation and Timing
The enable pins (EN0 and EN1) are used to enable and disable
each channel of the ZL8802. When operated as a 2-phase
converter, use EN0 and ground EN1. The enable pins should be
held low whenever a configuration file or script is used to
configure the ZL8802, or a PMBus™ command is sent that could
potentially damage the application circuit. When the ZL8802 is
used in a self-enabled mode, for example, when EN0 or EN1 is
tied to VR5, or to a resistor divider to VIN, the user must consider
the ZL8802's default factory settings. When a configuration file
is used to configure the ZL8802, the factory default settings are
restored to both the user and default stores in order to set the
ZL8802 to an initialized state. Since the default state of the
ZL8802 is to be enabled when the enable pin is high, it is
possible for the ZL8802 to be enabled while the PMBus™
commands are sent to the ZL8802 during the configuration
process.
The Enable pin is edge triggered to achieve fast turn-off times. As
a result, minimum Enable high and Enable low pulse widths must
be observed to ensure correct operation. The minimum high and
low pulse widths are dependent on the configured rise, fall and
delay times and can be calculated using Equations 1 and 2:
EN low  TOFF_DELAY + TOFF_FALL + 10.5ms
(EQ. 1)
EN high  TON_DELAY + TON_RISE +
POWER_GOOD_DELAY + 5.5ms
(EQ. 2)
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EN low and EN high times shorter than these minimums may
result in the device not responding to the trailing edge of the
pulse. For example, a EN low pulse below the EN low minimum
pulse width may stay in the OFF state until a valid EN low pulse is
applied to the EN pin.
Power-Good
The ZL8802 provides a power-good (PG0, PG1) signal for each
channel that indicates the output voltage is within a specified
tolerance of its target level and no fault condition exists. By
default, the PG pin will assert if the output is within 10% of the
target voltage. These limits and the polarity of the pin may be
changed using PMBus™ commands.
A PG delay period is defined as the time from when all conditions
within the ZL8802 for asserting PG are met to when the PG pin is
actually asserted. This feature is commonly used instead of using
an external reset controller to control external digital logic. By
default, the ZL8802 PG delay is set equal to 1ms. The PG delay
may be set using a PMBus™ command as described in
“POWER_GOOD_DELAY (D4h)” on page 66.
Power Management Functional
Description
Output Overvoltage Protection
The ZL8802 offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the VSEN pin) to a programmable threshold set
to 10% higher than the target output voltage (the default setting).
If the VSEN voltage exceeds this threshold, the PG pin will
deassert and the device can then respond in the following ways:
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down, and when the fault is no longer present, attempt
to restart.
Refer to “VOUT_OV_FAULT_RESPONSE (41h)” on page 37 for
details on how to select specific overvoltage fault response
options using the VOUT_OV_FAULT_RESPONSE command.
Output Prebias Protection
The ZL8802 provides prebiased start-up operation in 2-channel
and single device 2-phase operation. Prebias protection is not
provided when operating in current sharing 4-, 6- or 8-phase
configurations. An output prebias condition exists when an
externally applied voltage is present on a power supply's output
before the power supply's control IC is enabled. Certain
applications require that the converter not be allowed to sink
current during start up if a prebias condition exists at the output.
The ZL8802 provides prebias protection by sampling the output
voltage prior to initiating an output ramp.
If a prebias voltage lower than the desired output voltage is
present after the Ton-delay time the ZL8802 starts switching
with a duty cycle that matches the prebias voltage. This ensures
that the ramp-up from the prebias voltage is monotonic. The
FN8760.1
December 11, 2015
ZL8802
output voltage is then ramped to the desired output voltage at
the ramp rate set by the TON_RISE command.
The resulting output voltage rise time will vary depending on the
prebias voltage, but the total time elapsed from the end of the
Ton-delay time to when the Ton-rise time is complete and the
output is at the desired value will match the preconfigured ramp
time (see Figure 6).
VOUT
SPS CURRENT SENSING
By default, the ZL8802 senses current by utilizing the IMON
output from the ISL9922X Smart Power Stage (SPS). A 6:1
resistor divider is needed between the SPS IMON output and the
ISENA and ISENB inputs of the ZL8802, as shown in Figure 7.
Using an ISL9922x device will provide the best current sense
accuracy with no action needed from the user.
VIN
DESIRED OUTPUT
VOLTAGE
VIN
VDRV
PREBIAS
VOLTAGE
ZL8802
VDD VIN
PWMH
PWM
6*R
Ton
DELAY
Ton
RISE
TIME
ISENA
SW
VOUT
SPS
IMON
ISL99226
R
VPREBIAS < VTARGET
ISENB
REFIN
VOUT
PREBIAS
VOLTAGE
DESIRED OUTPUT
VOLTAGE
FIGURE 7. SPS CURRENT SENSING
DRMOS CURRENT SENSING
If a DrMOS device must be used, the ZL8802 can also use the
inductor DCR current sensing technique. Current sensing is
achieved with an R/C network as shown in Figure 8.
Ton
DELAY
Ton
RISE
TIME
VPREBIAS > VTARGET
FIGURE 6. OUTPUT RESPONSES TO PREBIAS VOLTAGES
If a prebias voltage higher than the target voltage exists after the
preconfigured Ton-delay time and Ton-rise time have completed,
the ZL8802 starts switching with a duty cycle that matches the
prebias voltage. This ensures that the ramp-down from the
prebias voltage is monotonic. The output voltage is then ramped
down to the desired output voltage
V IN
VIN
ZL8802
L
PWMH
ISENA
ISENB
If a prebias voltage higher than the overvoltage limit exists, the
device will not initiate a turn-on sequence and will stay off.
Output Overcurrent Protection
The ZL8802 can protect the power supply from damage from an
overloaded or shorted output. Once the current limit threshold
has been selected (see “Current Limit Configuration” on
page 18), the user may determine the desired response to the
fault condition. The following overcurrent protection response
options are available:
1. Shut down and stay off until the device has been disabled and
reenabled.
2. Shut down and restart continuously after a delay.
Refer to the “PMBus™ Command Detail” on page 27 for details
on how to select specific overvoltage fault response options
using the IOUT_OC_FAULT_RESPONSE command.
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17
DRMOS
V OUT
R1
C1
FIGURE 8. DCR CURRENT SENSING
For the voltage across C1 to reflect the voltage across the DCR of
the inductor, the time constant of the inductor must match the
time constant of the RC network.
 RC   L / DCR
R1  C1 
L
DCR
This capacitor, shown as C1 in Figure 8, should be an X7R or better
dielectric, and C1 should be placed as close to the ZL8802 as
possible for the best noise performance. The L and DCR values
should be set using the INDUCTOR and IOUT(0/1)_CAL_GAIN
commands. For L, use the average of the nominal value and the
minimum value. Include the effects of tolerance, DC bias and
switching frequency on the inductance when determining the
minimum value of L. Use the typical room temperature value for DCR.
FN8760.1
December 11, 2015
ZL8802
Current Limit Configuration
Thermal Overload Protection
The ZL8802 gives the power supply designer several choices for
the fault response during over or undercurrent condition. The
user can select the number of violations allowed before declaring
fault, a blanking time and the action taken when a fault is
detected. These parameters can be configured using the
ISENSE_CONFIG command.
The ZL8802 includes an on-chip thermal sensor that continuously
measures the internal temperature of the die. This thermal sensor
is used to provide both over-temperature and under-temperature
protection. If the over-temperature limit is exceeded, or the
temperature falls below the under-temperature limit, the ZL8802
is shut down. The over-temperature and under-temperature limits
are set by the OT_FAULT_LIMIT and UT_FAULT_LIMIT respectively.
The ZL8802 will not attempt to restart until the temperature has
fallen below the OT_WARN_LIMIT for over-temperature faults or
has risen above the UT_WARN_LIMIT for under-temperature faults.
The default temperature limits are +125°C and -45°C, but the
user may set the limits to different values if desired. Note that
setting a higher over-temperature or under-temperature limit may
result in permanent damage to the device. Once the device has
been disabled due to an internal temperature fault, the user may
select one of several fault response options as follows:
The blanking time represents the time when no current
measurement is taken. This is to avoid taking a reading just after
a current load step (less accurate due to potential ringing). It is a
configurable parameter from 0 to 832ns.
ZL8802 provides an adjustable maximum full scale sensing
range. Three ranges are available: ±25mV, ±35mV and ±50mV
maximum input voltage.
By default, current sensing is enabled during the inductor current
down-slope period of the switching period (D’). In applications
where the steady state duty cycle is >0.5, for example, a 5V to
3.3V converter, the ZL8802 can be configured to sense current
during the inductor up-slope period of the switching cycle (D).
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The user has the option of selecting how many consecutive
overcurrent readings must occur before an overcurrent fault and
subsequent shutdown are initiated. Either 1, 3, 5, 7, 9, 11 or 13
consecutive faults can be selected.
Refer to “PMBus™ Command Detail” on page 27 for details on
how to select specific overvoltage fault response options using
the OT_FAULT_RESPONSE and UT_FAULT_ RESPONSE
commands.
The current limit thresholds are set with 4 commands:
Voltage Tracking
1. IOUT_OC_FAULT_LIMIT – This sets the overcurrent threshold
that must be exceeded by the number of consecutive times
chosen in ISENSE_CONFIG.
2. IOUT_UC_FAULT_LIMIT – This is the same as
IOUT_OC_FAULT_LIMIT, but represents the negative current
that flows lower FET during the D’ interval. Large negative
currents can flow during faults such as a higher voltage rail
being shorted to a lower voltage rail.
3. IOUT_AVG_OC_FAULT_LIMIT – This limit is similar to
IOUT_OC_FAULT_LIMIT, but the limit represents an average
reading over several switching cycles. Since it is an average,
the response time is slower, but the limit can be set closer to
the maximum average expected output current.
4. IOUT_AVG_UC_FAULT_LIMIT – This limit is similar to
IOUT_AVG_OC_FAULT_LIMIT, but represents the negative
current that flows lower FET during the D’ interval.
Input Current Monitor
The input current can be monitored through the IINN and IINP
pins. The input current monitor input should be connected across
a current sensing resistor in series with the input supply. The IINP
pin is connected to the input supply side of the current sense
resistor and the IINN pin is connected to the ZL8802 VDD side of
the current sense resistor. Using the IIN_SCALE command, set
the current sense resistor value. Select the current sense resistor
value such that the maximum expected input current times the
current sense resistor value does not exceed the maximum
current sensing input voltage of 20mV.
If this feature is not used, IINN and IINP should be tied to VDD.
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Numerous high performance systems place stringent demands
on the order in which the power supply voltages are turned on.
This is particularly true when powering FPGAs, ASICs and other
advanced processor devices that require multiple supply voltages
to power a single die. In most cases, the I/O interface operates at
a higher voltage than the core and therefore the core supply
voltage must not exceed the I/O supply voltage according to the
manufacturers' specifications.
The ZL8802 integrates a tracking scheme that allows one of its
outputs (Channel 0 or Channel 1), or the single output in a dual
phase application, to track a voltage that is applied to the VTRK
pin with no external components required. The VTRK pin is an
analog input that, when tracking mode is enabled, configures the
voltage applied to the VTRK pin to act as a reference for the
device’s output regulation.
Coincident. This mode configures the ZL8802 to ramp its output
voltage at the same rate as the voltage applied to the VTRK pin
until it reaches its desired output voltage. The device that is
tracking another output voltage (slave) must be set to its desired
steady state output voltage, i.e., VOUT_COMMAND is set to the
final output voltage.
Ratiometric. This mode configures the ZL8802 to ramp its output
voltage at a rate that is a percentage of the voltage applied to the
VTRK pin. The default setting is 50%, but an external resistor
string may be used to configure a different tracking ratio. The
device that is tracking another output voltage (slave) must be set
to its desired steady-state output voltage, i.e., VOUT_COMMAND
is set to the final output voltage.
The master ZL8802 device in a tracking group is defined as the
device that has the highest target output voltage within the
group. This master device will control the ramp rate of all
FN8760.1
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ZL8802
tracking devices and is not configured for tracking mode. The
maximum tracking rise time is 1V/ms. The slave device must be
enabled before the master.
Any device that is configured for tracking mode will ignore its
Ton-delay and Ton-rise settings and its output will take on the
turn-on/turn-off characteristics of the reference voltage present
at the VTRK pin.
Tracking mode can be configured by using the TRACK_CONFIG
command.
Note that current sharing groups that are also configured to track
another voltage do not offer prebias protection; a minimum load
should therefore be enforced to avoid the output voltage from
being held up by an outside force.
V OUT
Vo1
Vo2
TIME
COINCIDENT
V OUT
Vo1
Vo2
TIME
RATIOMETRIC
FIGURE 9. TRACKING MODES
External Voltage Monitoring
The voltage monitoring (TMON) pin is available to monitor the
voltage supply for the external driver IC. The TMON input must be
scaled by a 16:1 ratio in order to read-back the TMON voltage
correctly. A 100kΩ and 6.65kΩ resistor divider is recommended.
Overvoltage and undervoltage fault thresholds can be set using
MFR_TMON_OV_FAULT_LIMIT and MFR_ TMON_UV_FAULT_LIMIT
commands. The response to these limits are set using the
TMON_OV_FAULT_RESPONSE and TMON_ UV_FAULT_RESPONSE
commands. To ignore the TMON input, set the TMON_OV and
_UV_FAULT_RESPONSEs to 00h.
Once the device has been disabled due to TMON fault, the user
may select one of several fault response options as follows:
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
SMBus Communications
The ZL8802 provides a SMBus digital interface. The ZL8802 can
be used with any standard 2-wire SMBus host device. In addition,
the device is compatible with SMBus version 2.0 and includes an
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19
SALRT line to help mitigate bandwidth limitations related to
continuous fault monitoring. Pull-up resistors are required on the
SMBus. The pull-up resistor may be tied to VR5 or to an external
3.3V or 5V supply as long as this voltage is present prior to or
during device power-up. The ideal design will use a central pull-up
resistor that is well-matched to the total load capacitance. The
minimum pull-up resistance should be limited to a value that
enables any device to assert the bus to a voltage that will ensure
a logic 0 (typically 0.8V at the device monitoring point) given the
pull-up voltage (5V if tied to VR5) and the pull-down current
capability of the ZL8802 (nominally 4mA). A pull-up resistor of
10kΩ is a good value for most applications.
SMBus data and clock lines should be routed with a closely
coupled return or ground plane to minimize coupled interference
(noise). Excessive noise on the data and clock lines that cause
the voltage on these lines to cross the high and low logic
thresholds of 2.0V and 0.8V respectively will cause command
transmissions to be interrupted and result in slow bus operation
or missed commands. For less than 10 devices on an SMBus a
10kΩ resistor on each line provides good performance.
The ZL8802 accepts most standard PMBus™ commands. When
enabling the device with ON_OFF_CONFIG command, it is
recommended that the enable pin is tied to SGND.
In addition to bus noise considerations, it is important to ensure
that user connections to the SMBus are compliant to the
PMBus™ command standards. Any device that can malfunction
in a way that permanently shorts SMBus lines will disable
PMBus™ communications. Incomplete PMBus™ commands can
also cause the ZL8802 to halt PMBus™ communications. This
can be corrected by disabling, then reenabling the device.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Intersil Digital-DC devices, and within the
ZL8802 itself. This dedicated bus provides the communication
channel between devices for features such as sequencing, fault
spreading and current sharing. The DDC pin must be pulled-up to
an external 2.5V to 5.0V supply, (or configured as a push-pull
output using the USER_GLOBAL_CONFIG command) even if the
ZL8802 is operating stand-alone. In addition, the DDC pin must
be pulled up or configured as a push-pull output before the
Enable pin is set high. Push-pull mode can only be used when the
ZL8802 is operating stand-alone. The DDC pin on all Digital-DC
devices that utilize sequencing, fault spreading or current sharing
must be connected together. The DDC pin on all Digital-DC
devices in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the rise
time as follows:
Riset time = R PU  C LOAD  1s
(EQ. 3)
Where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to VR5 or to an
external 3.3V or 5V supply as long as this voltage is present prior
to or during device power-up. As a rule of thumb, each device
connected to the DDC bus presents approximately 12pF of
capacitive loading. The ideal design will use a central pull-up
resistor that is well-matched to the total load capacitance. In
power module applications, the user should consider whether to
FN8760.1
December 11, 2015
ZL8802
place the pull-up resistor on the module or on the PCB of the end
application. The minimum pull-up resistance should be limited to
a value that enables any device to assert the bus to a voltage that
will ensure a logic 0 (typically 0.8V at the device monitoring
point) given the pull-up voltage (5V if tied to VR5) and the
pull-down current capability of the ZL8802 (nominally 4mA). As
with SMBus data and clock lines, the DDC data line should be
routed with a closely coupled return or ground plane to minimize
coupled interference (noise). Excessive noise on the DDC signal
can cause the voltage on this line to cross the high and low logic
thresholds of 2.0V and 0.8V respectively and will cause
command transmissions to be interrupted and result in slow bus
operation or missed commands. For less than 10 devices on the
DDC bus a 10kΩ resistor provides good performance.
called the “sequel” when the prequel’s Power-Good (PG) signal is
driven high.
Phase Spreading
Fault Spreading
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices have coincident rising
edges. Setting each converter to start its switching cycle at a
different point in time can dramatically reduce input capacitance
requirements. Since the peak current drawn from the input
supply is effectively spread out over a period of time, the peak
current drawn at any given moment is reduced and the power
losses proportional to IRMS2 are reduced.
Digital-DC devices can be configured to broadcast a fault event
over the DDC bus to the other devices in the group. When a fault
occurs and the device is configured to shut down on a fault, the
device will shut down and broadcast the fault event over the DDC
bus. The other devices on the DDC bus will shut down together if
configured to do so, and will attempt to restart in their prescribed
order if configured to do so.
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. Configuring the SYNC
pin is described in “Configurable Pins” on page 12. Selecting the
phase offset for the device is accomplished by selecting a device
address according to Equation 4:
The PWM outputs of the ZL8802 are used in parallel to create a
dual phase power rail. The device outputs will share the current
equally within a few percent, assuming all external sensing
element variations and tolerances are negligible. Current sensing
element tolerances must be taken into account, or adjusted for
using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands in
any application.
(EQ. 4)
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments using the
INTERLEAVE PMBus™ command.
Output Sequencing
A group of Intersil digital power devices may be configured to
power up in a predetermined sequence. This feature is especially
useful when powering advanced processors, FPGAs and ASICs
that require one supply to reach its operating voltage prior to
another supply reaching its operating voltage in order to avoid
latch-up from occurring. Multidevice sequencing can be achieved
by configuring each device using the SEQUENCE PMBus™
command.
Multiple device sequencing is achieved by issuing PMBus™
commands to assign the preceding device in the sequencing
chain as well as the device that will follow in the sequencing
chain.
The enable (EN) pins of all devices in a sequencing group must be
tied together and driven high to initiate a sequenced turn-on of
the group. Enable must be driven low to initiate a sequenced
turn-off of the group. In order to achieve sequenced turn-off of a
group of sequenced devices, all the devices should be configured
to turn off using the “soft-off”, or ramped down behavior, in the
ON_OFF_CONFIG PMBus command.
When sequencing on, the first device to ramp up, called the
“prequel”, sends a message via the DDC bus to the next device,
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20
Sequencing can also be accomplished by connecting the enable
pin of a sequel device to the power-good pin of a prequel device.
Sequencing is also achieved by using the TON_DELAY and
TON_RISE commands and choosing appropriate delay and rise
durations such that sequel devices start after their associated
prequel devices. The drawback to this method is that if a prequel
device fails to start properly, its sequel device will still start and
ramp on according to its delay and rise time settings.
Active Current Sharing
The ZL8802 will current share between phases without utilizing
output voltage droop.
Droop resistance is used in 4-phase current sharing to add
artificial resistance in the output voltage path to control the slope
of the load line curve, calibrating out the physical parasitic
mismatches due to power train components and PCB layout.
VREFERENCE
-R
VOUT
Phase offset = device address  45
When sequencing off, the sequel will send a message to the
prequel to begin the prequel’s ramp down after the sequel has
completed it’s own ramp down.
VMEMBER
-R
I MEMBER
I OUT
I REFERENCE
FIGURE 10. ACTIVE CURRENT SHARING
When current sharing up to 2 ZL8802s (4 phases total), the
ZL8802 uses a low-bandwidth, first-order digital current sharing
technique to balance the unequal device output loading by
aligning the load lines of member devices to a reference device.
Upon system start-up, the lowest numbered phase is defined as
the reference phase and all other phases are member phases.
FN8760.1
December 11, 2015
ZL8802
The reference phase broadcasts its current over the DDC bus. The
member phases use the reference current information to trim
their reference voltages (VMEMBER) to balance the current
loading of each device in the system.
Figure 10 shows that, for load lines with identical slopes, the
member reference voltage is increased towards the reference
voltage which closes the gap between the inductor currents.
User Store: The user store is the most commonly used store. It
provides the ability to modify certain power supply settings while
still protecting the equipment from modifying values that can
lead to a system level fault. The equipment manufacturer would
use the user store to achieve this goal.
Where R is the value of the droop resistance. The VOUT_DROOP
command is used to set the device output voltage droop to
achieve 4-, 6- or 8-phase current sharing.
Default Store: The default store is less commonly used. It
provides a means to protect the circuit from damage by
preventing the user from modifying certain values that are
related to the physical construction of the circuit. In this case, the
Original Equipment Manufacturer (OEM) would use the default
store in a protected mode and allow the user to restore the
device to its default settings. In this case the user store would be
available to the end-user for making changes, but would restrict
the user from restoring the device to the factory settings or
modifying the default store.
4-, 6- and 8-phase current sharing groups must have their DDC and
SYNC pins tied together in order to achieve current sensing and
ensure accurate phase offsets between current sharing phases.
The user store takes priority over the Default Store. If there are
no values set in the user or default store, then the device will use
the pin-strap setting value.
Temperature Monitoring Using XTEMP Pin
For details regarding protection of the user and default stores,
see the PASSWORD PMBus command.
The relation between reference and member current and voltage
is given by the following Equation 5:
VMEMBER  VOUT  R  I REFERENCE  I MEMBER 
(EQ. 5)
Each channel of the ZL8802 supports measurement of an external
device temperature using either a thermal diode integrated in a
processor, FPGA or ASIC, or using a discrete diode-connected
2N3904 NPN transistor. Figure 11 illustrates the typical
connections required. A noise filtering capacitor, not exceeding
100pF, should be connected across the external temperature
sensing device. The external temperature sensors can be used to
provide the temperature reading for over-temperature and
under-temperature faults. The external sensors can also be used
to provide more accurate temperature compensation for inductor
DCR current sensing by being placed close to the inductor. These
options for the external temperature sensors are selected using
the User_config PMBus™ command.
XTEMPxP
ZL8802
100pF
2N3904
XTEMPxN
DISCRETE NPN
100pF
ASIC
XTEMPxN
EMBEDDED THERMAL DIODE
FIGURE 11. EXTERNAL TEMPERATURE MONITORING
Nonvolatile Memory and Security Features
The ZL8802 has internal nonvolatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the device to a level that has been
made available to them. During the initialization process, the
ZL8802 checks for stored values contained in its internal
nonvolatile memory. The ZL8802 offers two internal memory
storage units that are accessible by the user as follows:
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A system controller can monitor a wide variety of different
ZL8802 parameters through the SMBus interface. The device
can monitor for fault conditions by monitoring the SALRT pin,
which will be asserted when any number of preconfigured fault
conditions occur.
The device can also be monitored continuously for any number of
power conversion parameters including, but not limited to, the
following:
•
•
•
•
•
•
•
•
•
Input voltage
Output voltage
Input current
Output current
Internal junction temperature
Temperature of an external device
Switching frequency
Duty cycle
Fault status information
The PMBus™ Host should respond to SALRT as follows:
XTEMPxP
ZL8802
Monitoring via SMBus
21
1. ZL device pulls SALRT low.
2. PMBus™ host detects that SALRT is now low, performs
transmission with Alert Response Address to find which ZL
device is pulling SALRT low.
3. PMBus™ host talks to the ZL device that has pulled SALRT
low. The actions that the host performs are up to the system
designer.
If multiple devices are faulting, SALRT will still be low after doing
the above steps and will require transmission with the Alert
Response Address repeatedly until all faults are cleared.
Please refer to “PMBus™ Command Detail” on page 27 for details
on how to monitor specific parameters via the SMBus interface.
FN8760.1
December 11, 2015
ZL8802
PMBus™ Command Summary
CODE
COMMAND NAME
DESCRIPTION
DATA
TYPE FORMAT
DEFAULT
VALUE
DEFAULT SETTING
00h PAGE
Selects Controller 0, 1, or both
R/W
BIT
00h
Page 0 Controller addressed
01h OPERATION
Enable/disable, margin settings
R/W
BIT
00h
Immediate off, nominal margin
02h ON_OFF_CONFIG
On/off configuration settings
R/W
BIT
17h
ENABLE pin control, active high
03h CLEAR_FAULTS
Clears faults
Write
N/A
N/A
N/A
11h STORE_DEFAULT_ALL
Stores values to default store
Write
N/A
N/A
N/A
12h RESTORE_DEFAULT_ALL
Restores values from default store
Write
N/A
N/A
N/A
15h STORE_USER_ALL
Stores values to user store
Write
N/A
N/A
N/A
16h RESTORE_USER_ALL
Restores values from user store
Write
N/A
N/A
N/A
20h VOUT_MODE
Reports VOUT mode and exponent
Read
BIT
13h
Linear mode, exponent = -13
21h VOUT_COMMAND
Sets nominal VOUT set-point
R/W
L16u
N/A
Pin-strap setting
22h VOUT_TRIM
Applies offset voltage to VOUT set-point
R/W
L16s
0000h
0V
23h VOUT_CAL_OFFSET
Applies offset voltage to VOUT set-point
R/W
L16s
0000h
0V
24h VOUT_MAX
Sets maximum VOUT set-point
R/W
L16u
N/A
1.15 x VSET pin-strap setting
25h VOUT_MARGIN_HIGH
Sets VOUT set-point during margin high
R/W
L16u
N/A
1.05 x VSET pin-strap setting
26h VOUT_MARGIN_LOW
Sets VOUT set-point during margin low
R/W
L16u
N/A
0.95 x VSET pin-strap setting
27h VOUT_TRANSITION_RATE
Sets VOUT transition rate during margin
commands
R/W
L11
BA00h
28h VOUT_DROOP
Sets V/I slope for total rail output current
(all phases combined)
R/W
L11
N/A
CFG pin-strap setting
33h FREQUENCY_SWITCH
Sets switching frequency
R/W
L11
N/A
SYNC pin-strap setting
37h INTERLEAVE
Configures phase offset during group
operation
R/W
BIT
N/A
CFG pin-strap setting
38h IOUT_CAL_GAIN
Sets impedance of current sense circuit
R/W
L11
B2AEh
0.67mΩ
39h IOUT_CAL_OFFSET
Sets an offset to IOUT sense circuit
R/W
L11
BD00h
-1.5A
40h VOUT_OV_FAULT_LIMIT
Sets the VOUT overvoltage fault threshold
R/W
L16u
N/A
1.10 x VSET pin-strap setting
41h VOUT_OV_FAULT_RESPONSE
Sets the VOUT overvoltage fault response
R/W
BIT
80h
Disable, no retry
44h VOUT_UV_FAULT_LIMIT
Sets the VOUT undervoltage fault threshold R/W
L16u
N/A
0.85 x VSET pin-strap setting
45h VOUT_UV_FAULT_RESPONSE
Sets the VOUT undervoltage fault response R/W
BIT
80h
Disable, no retry
46h IOUT_OC_FAULT_LIMIT
Sets the IOUT peak overcurrent fault
threshold for each phase
R/W
L11
N/A
CFG pin-strap setting
4Bh IOUT_UC_FAULT_LIMIT
Sets the IOUT valley undercurrent fault
threshold for each phase
R/W
L11
N/A
-1*IOUT_OC_FAULT_LIMIT from
CFG pin-strap setting
4Fh OT_FAULT_LIMIT
Sets the over-temperature fault limit
R/W
L11
EBE8h
50h OT_FAULT_RESPONSE
Sets the over-temperature fault response
R/W
BIT
BFh
51h OT_WARN_LIMIT
Sets the over-temperature warning limit
R/W
L11
EB70h
+110°C
52h UT_WARN_LIMIT
Sets the under-temperature warning limit
R/W
L11
DC40h
-30°C
53h UT_FAULT_LIMIT
Sets the under-temperature fault limit
R/W
L11
E530h
-45°C
54h UT_FAULT_RESPONSE
Sets the under-temperature fault response R/W
BIT
BFh
55h VIN_OV_FAULT_LIMIT
Sets the VIN overvoltage fault threshold
L11
D380h
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22
R/W
1V/ms
+125°C
Continuous retry, 280ms retry
delay
Continuous retry, 280ms retry
delay
14V
FN8760.1
December 11, 2015
ZL8802
PMBus™ Command Summary
CODE
COMMAND NAME
(Continued)
DESCRIPTION
DATA
TYPE FORMAT
DEFAULT
VALUE
DEFAULT SETTING
56h VIN_OV_FAULT_RESPONSE
Sets the VIN overvoltage fault response
R/W
BIT
80h
57h VIN_OV_WARN_LIMIT
Sets the VIN overvoltage warning threshold R/W
L11
D360h
58h VIN_UV_WARN_LIMIT
Sets the VIN undervoltage warning
threshold
R/W
L11
N/A
1.1 x UVLO pin-strap setting
59h VIN_UV_FAULT_LIMIT
Sets the VIN undervoltage fault threshold
R/W
L11
N/A
UVLO pin-strap setting
5Ah VIN_UV_FAULT_RESPONSE
Sets the VIN undervoltage fault response
R/W
BIT
BFh
Continuous retries, 280ms retry
delay
5Eh POWER_GOOD_ON
Sets the voltage threshold for power-good
indication
R/W
L16u
N/A
0.9 x VSET pin-strap setting
60h TON_DELAY
Sets the delay time from enable to VOUT
rise
R/W
L11
CA80h
5ms
61h TON_RISE
Sets the rise time of VOUT after ENABLE
and TON_DELAY
R/W
L11
CA80h
5ms
64h TOFF_DELAY
Sets the delay time from DISABLE to start
of VOUT fall
R/W
L11
CA80h
5ms
65h TOFF_FALL
Sets the fall time for VOUT after DISABLE
and TOFF_DELAY
R/W
L11
CA80h
5ms
78h STATUS_BYTE
First byte of STATUS_WORD
Read
BIT
00h
No faults
79h STATUS_WORD
Summary of critical faults
Read
BIT
0000h
No faults
7Ah STATUS_VOUT
Reports VOUT warnings/faults
Read
BIT
00h
No faults
7Bh STATUS_IOUT
Reports IOUT warnings/faults
Read
BIT
00h
No faults
7Ch STATUS_INPUT
Reports input warnings/faults
Read
BIT
00h
No faults
7Dh STATUS_TEMP
Reports temperature warnings/faults
Read
BIT
00h
No faults
7Eh STATUS_CML
Reports communication, memory, logic
errors
Read
BIT
00h
No faults
80h STATUS_MFR_SPECIFIC
Reports voltage monitoring/clock
synchronization faults
Read
BIT
00h
no faults
88h READ_VIN
Reports input voltage measurement
Read
L11
N/A
N/A
89h READ_IIN
Reports input current measurement
Read
L11
N/A
N/A
8Bh READ_VOUT
Reports output voltage measurement
Read
L16u
N/A
N/A
8Ch READ_IOUT
Reports output current measurement
Read
L11
N/A
N/A
8Dh READ_TEMPERATURE_1
Reports internal temperature
measurement
Read
L11
N/A
N/A
8Eh READ_TEMPERATURE_2
Reports external temperature
measurement from XTEMP pins
Read
L11
N/A
N/A
8Fh READ_TEMPERATURE_3
Reports external temperature
measurement from VMON/TMON pin.
Read
L11
N/A
N/A
94h READ_DUTY_CYCLE
Reports actual duty cycle
Read
L11
N/A
N/A
95h READ_FREQUENCY
Reports actual switching frequency
Read
L11
N/A
N/A
98h PMBUS_REVISION
Reports the PMBUS revision used
Read
BIT
22h
P1 R1.2, P2 R1.2
99h MFR_ID
Sets a user defined identification
R/W
ASC
N/A
<null>
9Ah MFR_MODEL
Sets a user defined model
R/W
ASC
N/A
<null>
9Bh MFR_REVISION
Sets a user defined revision
R/W
ASC
N/A
<null>
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Disable, no retry
13.5V
FN8760.1
December 11, 2015
ZL8802
PMBus™ Command Summary
CODE
COMMAND NAME
(Continued)
DESCRIPTION
DATA
TYPE FORMAT
DEFAULT
VALUE
DEFAULT SETTING
9Ch MFR_LOCATION
Sets a user defined location identifier
R/W
ASC
N/A
<null>
9Dh MFR_DATE
Sets a user defined date
R/W
ASC
N/A
<null>
9Eh MFR_SERIAL
Sets a user defined serialized identifier
R/W
ASC
N/A
<null>
ADh IC_DEVICE_ID
Reports device identification information
Read
CUS
49A02D00h Intersil ZL8802
AEh IC_DEVICE_REV
Reports device revision information
Read
CUS
01000000h Initial Release
B0h USER_DATA_00
Sets user defined data
R/W
ASC
N/A
CEh MIN_VOUT_REG
Sets a minimum start-up voltage
R/W
L11
0000h
0mV
D0h ISENSE_CONFIG
Configures current sensing circuitry
R/W
BIT
620Eh
Downslope, 5 fault count, 384ns
blanking, high range
D1h USER_CONFIG
Configures several user-level features
R/W
BIT
N/A
D2h IIN_CAL_GAIN
Sets the resistance of the input current
sensing resistor
R/W
L11
C200h
D3h DDC_CONFIG
Configures the DDC addressing and current
R/W
sharing
BIT
N/A
D4h POWER_GOOD_DELAY
Sets the delay between PG threshold and
PG assertion
R/W
L11
BA00h
D5h MULTI_PHASE_RAMP_GAIN
Adjusts the ramp-up and ramp-down rate
by setting the feedback gain
R/W
CUS
03h
D6h INDUCTOR
Sets the inductor value
R/W
L11
B133h
0.3µH
D7h SNAPSHOT_FAULT_MASK
Masks faults that cause a snapshot to be
taken
R/W
BIT
0000h
No faults masked
D8h OVUV_CONFIG
Configures output voltage OV/UV fault
detection
R/W
BIT
00h
D9h XTEMP_SCALE
Calibrates external temperature sensor
R/W
L11
BA00h
1/degree C
DAh XTEMP_OFFSET
Offset calibration for external temperature
R/W
sensor
L11
0000h
No offset
DBh MFR_SMBALERT_MASK
Identifies which fault limits will not assert
SALRT
R/W Custom
00..00h
N/A
DCh TEMPCO_CONFIG
Sets tempco settings
R/W
BIT
00h
0ppm/°C
DDh PINSTRAP_READ_STATUS
Reads pin-strap settings
Read
BIT
N/A
Set by pin-straps
DFh ASCR_CONFIG
Configures the ASCR settings
R/W
BIT
N/A
ASCRCFG pin-strap setting
E0h SEQUENCE
DDC rail sequencing configuration
R/W
BIT
00h
Prequel and sequel disabled
E1h TRACK_CONFIG
Configures voltage tracking.
R/W
BIT
00h
Tracking disabled
E2h DDC_GROUP
Configures group ID, fault spreading,
OPERATION and VOUT
R/W
BIT
N/A
Set by CFG pin-strap
E4h DEVICE_ID
Returns the device identifier string
Read
ASC
TBD
ZL8802, current revisions
E5h MFR_IOUT_OC_FAULT_RESPONSE
Configures the IOUT overcurrent fault
response
R/W
BIT
80h
Disable, no retry
E6h MFR_IOUT_UC_FAULT_RESPONSE
Configures the IOUT undercurrent fault
response
R/W
BIT
80h
Disable, no retry
E7h IOUT_AVG_OC_FAULT_LIMIT
Sets the IOUT average overcurrent fault
threshold
R/W
L11
N/A
Set by CFG pin-strap
E8h IOUT_AVG_UC_FAULT_LIMIT
Sets the IOUT average undercurrent fault
threshold
R/W
L11
N/A
-1* IOUT_AVG_OC_FAULT_LIMIT
from CFG pin-strap setting
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24
<null>
Set by CFG pin-strap setting
2mΩ
Set by pin-strapped PMBus™
address and CFG pin-strap setting
1ms
3
Low side FET off on fault, 1
violation triggers fault.
FN8760.1
December 11, 2015
ZL8802
PMBus™ Command Summary
CODE
COMMAND NAME
(Continued)
DESCRIPTION
DATA
TYPE FORMAT
DEFAULT
VALUE
DEFAULT SETTING
E9h USER_GLOBAL_CONFIG
Sets options pertaining to advanced
features
R/W
BIT
N/A
Set by CFG pin-strap setting
EAh SNAPSHOT
32-byte read-back of parametric and
status values
Read
BIT
N/A
<null>
F0h LEGACY_FAULT_GROUP
Configures fault group compatibility with
older Intersil digital power devices
R/W
BIT
F3h SNAPSHOT_CONTROL
Snapshot feature control command
R/W
BIT
00h
N/A
F4h RESTORE_FACTORY
Restores device to the hard-coded default
Write
values
N/A
N/A
N/A
F5h MFR_VMON_OV_FAULT_LIMIT
Sets the VMON overvoltage fault threshold R/W
L11
C266h
2.4V, SPS OT trip voltage
F6h MFR_VMON_UV_FAULT_LIMIT
Sets the VMON undervoltage fault
threshold
R/W
L11
B0CCh
0.2V, corresponds to -50°C
F7h MFR_READ_VMON
Reads the VMON voltage
Read
L11
N/A
N/A
F8h VMON_OV_FAULT_RESPONSE
Configures the VMON overvoltage fault
response
R/W
BIT
BFh
Continuous retry
F9h VMON_UV_FAULT_RESPONSE
Configures the VMON undervoltage fault
response
R/W
BIT
BFh
Continuous retry
FAh SECURITY_LEVEL
Reports the security level
Read
Hex
01h
Public security level
FBh PRIVATE_PASSWORD
Sets the private password string
R/W
ASC
00…00h
<null>
FCh PUBLIC_PASSWORD
Sets the public password string
R/W
ASC
00…00h
<null>
FDh UNPROTECT
Identifies which commands are protected
R/W Custom
FF…FFh
No commands are protected
00000000h <null>
PMBus™ Use Guidelines
The PMBus is a powerful tool that allows the user to optimize circuit performance by configuring the ZL8802 for their application. When
configuring the ZL8802 in a circuit, the ZL8802 should be disabled whenever most settings are changed with PMBus commands. Some
exceptions to this recommendation are OPERATION, ON_OFF_CONFIG, CLEAR_FAULTS, VOUT_COMMAND, VOUT_MARGIN_HIGH,
VOUT_MARGIN_LOW and ASCCR_CONFIG. While the device is enabled any command can be read. Many commands do not take effect
until after the device has been reenabled, hence the recommendation that commands that change device settings are written while
the device is disabled.
When sending the STORE_DEFAULT_ALL, STORE_USER_ALL, RESTORE_DEFAULT_ALL and RESTORE_USER_ALL commands, it is
recommended that no other commands are sent to the device for 100ms after sending STORE or RESTORE commands.
In addition, there should be a 2ms delay between repeated READ commands sent to the same device. When sending any other
command, a 5ms delay is recommended between repeated commands sent to the same device.
SUMMARY:
All commands can be read at any time.
Always disable the ZL8802 when writing commands that change device settings. Exceptions to this rule are commands intended to be
written while the device is enabled, for example, VOUT_MARGIN_HIGH.
To be sure a change to a device setting has taken effect, write the STORE_USER_ALL command, then cycle input power and reenable
the device.
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FN8760.1
December 11, 2015
ZL8802
PMBus™ Data Formats
Linear-11 (L11)
L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world decimal
value (X).
Data Byte High
7 6 5 4 3 2 1 0
Exponent (N)
Data Byte Low
7 6 5 4 3 2 1 0
Mantissa (Y)
Relation between real world decimal value (X), N and Y is: X = Y·2N
Linear-16 Unsigned (L16u)
L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world
decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y·2-13
Linear-16 Signed (L16s)
L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real world
decimal value (X).
Relation between real world decimal value (X), N and Y is: X = Y·2-13
Bit Field (BIT)
Breakdown of Bit Field is provided in “PMBus™ Command Detail” starting on page 27.
Custom (CUS)
Breakdown of Custom data format is provided in “PMBus™ Command Detail”. A combination of Bit Field and integer are common type
of Custom data format.
ASCII (ASC)
A variable length string of text characters uses ASCII data format.
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FN8760.1
December 11, 2015
ZL8802
PMBus™ Command Detail
PAGE (00h)
Definition: Selects Controller 0, Controller 1 or both Controllers 0 and 1 to receive commands. All commands following this command
will be received and acted on by the selected controller or controllers.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: No
Default Value: 00h (Page 0)
Units: N/A
COMMAND
PAGE (00h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
BITS 7:4
BITS 3:0
PAGE
0000
0000
0
0000
0001
1
1111
1111
Both
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FN8760.1
December 11, 2015
ZL8802
OPERATION (01h)
Definition: Sets Enable, Disable and VOUT Margin settings. This command can also be monitored to read the operating state of the
device on bits 7:6. Writing Immediate off will turn off the output and ignore TOFF_DELAY and TOFF_FALL settings. This command is not
stored like other PMBus commands. The value read reflects the current state of the device. When this command is written the
command takes effect, but if a STORE _USER_ALL written and the device is reenabled, the OPERATION settings may not be the same
settings that were written before the device was reenabled.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h (immediate off)
Units: N/A
COMMAND
OPERATION (01h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
BITS 7:6
BITS 5:4
BITS 3:0
(NOT USED)
UNIT ON OR OFF
MARGIN STATE
00
00
0000
Immediate off (No sequencing)
N/A
01
00
0000
Soft off (With sequencing)
N/A
10
00
0000
On
Nominal
10
01
0000
On
Margin Low
10
10
0000
On
Margin High
NOTE: Bit combinations not listed above may cause command errors.
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FN8760.1
December 11, 2015
ZL8802
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN). When bit 0 is set to 1
(turn off the output immediately), the TOFF_FALL setting is ignored.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 17h (ENABLE pin control, active high, turn off output immediately – no ramp down)
Units: N/A
COMMAND
ON_OFF_CONFIG (02h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
Function
See Following Table
Default Value
0
BIT NUMBER
0
PURPOSE
0
1
BIT VALUE
0
MEANING
7:5
Not Used
000
Not used
000
Not used
4:2
Sets the default to either operate any time
power is present or for the on/off to be
controlled by ENABLE pin or OPERATION
command
101
Device starts from ENABLE pin only.
110
Device starts from OPERATION command only.
1
(Polarity of ENABLE pin - not used)
1
Active high only.
0
ENABLE pin action when commanding the unit
to turn off
0
Use the configured ramp-down settings (“soft-off”)
1
Turn off the output immediately.
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the
bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Paged or Global: Global
Data Length in Bytes: 0 Byte
Data Format: N/A
Type: Write only
Protectable: Yes
Default Value: N/A
Units: N/A
STORE_DEFAULT_ALL (11h)
Definition: Stores all current PMBus™ values from the operating memory into the nonvolatile DEFAULT Store memory. To clear the
DEFAULT store, perform a RESTORE_FACTORY then STORE_DEFAULT_ALL. To add to the DEFAULT store, perform a
RESTORE_DEFAULT_ALL, write commands to be added, then STORE_DEFAULT_ALL. This command should not be used during device
operation, the device will be unresponsive for 100ms while storing values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
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FN8760.1
December 11, 2015
ZL8802
RESTORE_DEFAULT_ALL (12h)
Definition: Restores PMBus™ settings from the nonvolatile DEFAULT store memory into the operating memory. These settings are
loaded during at power-up if not superseded by settings in USER store. Security level is changed to level 1 following this command. This
command should not be used during device operation, the device will be unresponsive for 100ms while storing values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
STORE_USER_ALL (15h)
Definition: Stores all PMBus™ settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,
perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to
be added, then STORE_USER_ALL. This command should not be used during device operation, the device will be unresponsive for
100ms while storing values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
RESTORE_USER_ALL (16h)
Definition: Restores all PMBus™ settings from the USER store memory to the operating memory. Command performed at power-up.
Security level is changed to Level 1 following this command. This command should not be used during device operation, the device will
be unresponsive for 100ms while restoring values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
VOUT_MODE (20H)
Definition: Reports the VOUT mode and provides the exponent used in calculating several VOUT settings.
Data Length in Bytes: 1
Data Format: BIT
Type: Read Only
Default Value: 13h (Linear Mode, Exponent = -13)
Units: N/A
COMMAND
VOUT_MODE (20h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
1
1
Function
See Following Table
Default Value
0
MODE
BITS 7:5
Linear
000
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30
0
0
1
0
BITS 4:0 (PARAMETER)
5-bit two’s complement exponent for the mantissa delivered as the data bytes for an output
voltage related command.
FN8760.1
December 11, 2015
ZL8802
VOUT_COMMAND (21h)
Definition: This command sets or reports the target output voltage. The integer value is multiplied by 2 raised to the power of -13h. This
command cannot be set to be higher than 115% of the pin-strap VSET setting, or VOUT_MAX if VOUT_MAX is set higher than 115% of
the pin-strap VSET setting.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned
Type: R/W
Protectable: Yes
Default Value: VSET pin-strap setting
Units: Volts
Equation: VOUT = VOUT_COMMAND × 2-13
Range: 0 to VOUT_MAX
Example: VOUT_COMMAND = 699Ah = 27,034
Target voltage equals 27034 × 2-13 = 3.3V
COMMAND
VOUT_COMMAND (21h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
VSET Pin-strap Setting
VOUT_TRIM (22h)
Definition: The VOUT_TRIM command is used to apply a fixed trim voltage to the output voltage command value. This command is
typically used by the manufacturer of a power supply subassembly to calibrate a device in the subassembly circuit. The two bytes are
formatted as a two’s complement binary mantissa, used in conjunction with the exponent of -13h.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Signed
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: Volts
Equation: VOUT trim = VOUT_TRIM×2-13
Range: ±150mV
COMMAND
VOUT_TRIM (22h)
Format
Linear-16 Signed
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Submit Document Feedback
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FN8760.1
December 11, 2015
ZL8802
VOUT_CAL_OFFSET (23h)
Definition: The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the output voltage command value. This
command is typically used by the user to calibrate a device in the application circuit. The two bytes are formatted as a two’s
complement binary mantissa, used in conjunction with the exponent of -13h.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Signed
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: Volts
Equation: VOUT calibration offset = VOUT_CAL_OFFSET×2-13
Range: ±150mVV
COMMAND
VOUT_CAL_OFFSET (23h)
Format
Linear-16 Signed
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VOUT_MAX (24h)
Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output
voltage to a possibly destructive level rather than to be the primary output overprotection. If a VOUT_COMMAND is sent with a value
higher than VOUT_MAX, the device will set the output voltage to VOUT_MAX. Note that this command setting does not automatically
scale with a stored VOUT_COMMAND setting.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 1.15 x VSET pin-strap setting
Units: Volts
Equation: VOUT max = VOUT_MAX × 2-13
Range: 0V to 5.5V
COMMAND
VOUT_MAX (24h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
Submit Document Feedback
1.15 x VSET Pin-strap Setting
32
FN8760.1
December 11, 2015
ZL8802
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the VOUT during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to
which the output is to be changed when the OPERATION command is set to “Margin High”.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W word
Protectable: Yes
Default Value: 1.05 x VSET pin-strap setting.
Units: V
Equation: VOUT margin high = VOUT_MARGIN_HIGH x 2-13
Range: 0V to VOUT_MAX
COMMAND
VOUT_MARGIN_HIGH (25h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
1.05 x VSET Pin-strap Setting
VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the VOUT during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which
the output is to be changed when the OPERATION command is set to “Margin Low”.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned.
Type: R/W
Protectable: Yes
Default Value: 0.95 x VSET pin-strap setting.
Units: V
Equation: VOUT margin low = VOUT_MARGIN_LOW
Range: 0V to VOUT_MAX
COMMAND
VOUT_MARGIN_LOW (26h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
Access
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
Submit Document Feedback
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0.95 x VSET Pin-strap Setting
33
FN8760.1
December 11, 2015
ZL8802
VOUT_TRANSITION_RATE (27h)
Definition: This command sets the rate at which the output should change voltage when the device receives an OPERATION command
(Margin High, Margin Low) that causes the output voltage to change. The maximum possible positive value of the two data bytes
indicates that the device should make the transition as quickly as possible. This commanded rate does not apply when the device is
commanded to turn on or to turn off.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h (1.0V/ms)
Units: V/ms
Equation: VOUT_TRANSITION_RATE = Y×2N
Range: 0.1 to 4V/ms
COMMAND
VOUT_TRANSITION_RATE (27h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Signed Exponent, N
Default Value
1
0
1
Signed Mantissa, Y
1
1
0
1
0
0
0
0
0
VOUT_DROOP (28h)
Definition: The VOUT_DROOP sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A at
which the output voltage decreases with increasing output current for use with passive current sharing schemes. For devices that are
set to sink output current (negative output current), the output voltage continues to increase as the output current is negative.
VOUT_DROOP is not needed with a single (2-phase) ZL8802. VOUT_DROOP is needed when multiple ZL8802s are operated in current
sharing mode, i.e., 4-, 6- and 8-phase configurations. In this case, VOUT_DROOP is calculated based on the combined output current of
all phases as applicable.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: mV/A
Equation: VOUT_DROOP = Y×2N
Range: 0 to 40mV/A
COMMAND
VOUT_DROOP (28h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Default Value
Submit Document Feedback
Signed Mantissa, Y
Set by CFG Pin-strap Setting
34
FN8760.1
December 11, 2015
ZL8802
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin-strap and this value can be overridden by
writing this command. If an external SYNC is utilized, this value should be set as close as possible to the external clock value. The
output must be disabled when writing this command. Available frequencies are defined by the equation fSW = 16MHz/n where
12 ≤ n ≤ 80.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: SYNC pin-strap setting
Units: kHz
Equation: FREQUENCY_SWITCH = Y×2N
Range: 200kHz-1.33MHz
COMMAND
FREQUENCY_SWITCH (33h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
SYNC Pin-strapped Value
INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. A desired phase position is
specified. Interleave is used for setting the phase offset between individual devices, current sharing groups, and/or combinations of
devices and current sharing groups. For devices within single current sharing group the phase offset is set automatically. In a
multiphase current share group the same interleave settings must be stored in all devices in the current sharing group in order to
phase spread properly. Interleave Offset refers to the phase offset of Phase 0 of the device; Phase 1 is always Phase 0 + 180 degrees.
INTERLEAVE Phase offset is calculated with Equation 6:
Phase Offset (in degrees) =  Rounded  Position  16  Number    22.5
(EQ. 6)
Phase offsets greater than 360 degrees are “wrapped around” by subtracting 360 degrees.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting.
Units: N/A
COMMAND
INTERLEAVE (37h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
Set by CFG Pin-strap Setting
BITS
PURPOSE
VALUE
15:8
Not Used
0
7:4
Number In Group
0 to 15d Sets the number of devices in the interleave group. A value of 0 is interpreted as 16.
3:0
Position in Group
(Interleave Order)
0 to 15d
Submit Document Feedback
35
DESCRIPTION
Not used
Sets position of the device’s rail within the group. A value of 0 is interpreted as 16. Position
1 will have a 22.5 degree offset.
FN8760.1
December 11, 2015
ZL8802
IOUT_CAL_GAIN (38h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: B2AEh (0.67mΩ)
Units: mΩ
Equation: IOUT_CAL_GAIN = Y×2N
COMMAND
IOUT_CAL_GAIN (38h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
Function
Default Value
Signed Exponent, N
1
0
1
1
Signed Mantissa, Y
0
0
1
0
1
0
1
0
IOUT_CAL_OFFSET (39h)
Definition: Used to null out any offsets in the output current sensing circuit, and to compensate for delayed measurements of current
ramp due to the current sense blanking time (see “ISENSE_CONFIG (D0h)” on page 62).
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BD00h (-1.5A)
Units: A
Equation: IOUT_CAL_OFFSET = Y×2N
COMMAND
IOUT_CAL_OFFSET (39h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
Submit Document Feedback
0
1
36
1
Signed Mantissa, Y
1
1
0
1
0
0
0
0
FN8760.1
December 11, 2015
ZL8802
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the VOUT overvoltage fault threshold.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 1.10 x VSET pin-strap setting.
Units: V
Equation: VOUT OV fault limit = VOUT_OV_FAULT_LIMIT×2-13
Range: 0V to 7.99V
COMMAND
VOUT_OV_FAULT_LIMIT (40h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
1.10 x VSET Pin-strap Setting
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the VOUT overvoltage fault response. The retry time is the time between restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (shut down immediately, no retries)
Units: Retry time = 35ms increments
COMMAND
VOUT_OV_FAULT_RESPONSE (41h)
Format
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
BIT
1
FIELD NAME
VALUE
Response behavior, the device:
• Pulls SALRT low
7:6
0
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
CLEAR_FAULTS command.
00-01
0
0
0
DESCRIPTION
Not used
Disable and retry according to the setting in bits [5:3].
10-11
000
No retry. The output remains disabled until the device is restarted.
001-110 Not used
5:3
2:0
Retry Setting
Retry Delay
Submit Document Feedback
37
111
Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION
command or both), bias power is removed, or another fault condition causes the unit to shut
down. The time between the start of each attempt to restart is set by the value in bits [2:0]
multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range
is 35ms to 280ms.
FN8760.1
December 11, 2015
ZL8802
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp, before power-good is asserted or when the
device is disabled. VOUT_UV_FAULT_LIMIT should be set to a value below POWER_GOOD
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned.
Type: R/W
Protectable: Yes
Default Value: 0.85 x VSET pin-strap setting.
Units: V
Equation: VOUT UV fault limit = VOUT_UV_FAULT_LIMIT×2-13
Range: 0V to 7.99V
COMMAND
VOUT_UV_FAULT_LIMIT (44h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0.85 x VSET Pin-strap Setting
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the VOUT undervoltage fault response. Note that VOUT UV faults can only occur after Power-good (PG) has been
asserted. Under some circumstances this will cause the output to stay fixed below the power-good threshold indefinitely. If this behavior
is undesired, use setting 80h. The retry time is the time between restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (shut down immediately, no retries)
Units: Retry time unit = 35ms
COMMAND
VOUT_UV_FAULT_RESPONSE (45h)
Format
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
BIT
1
FIELD NAME
Response Behavior: the device:
• Pulls SALRT low
7:6
• Sets the related fault bit in the status
registers. Fault bits are only cleared by
the CLEAR_FAULTS command.
0
0
VALUE
00-01
0
0
DESCRIPTION
Not used
Disable and Retry according to the setting in bits [5:3].
10-11
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
Retry Setting
111
2:0
Retry Delay
Submit Document Feedback
38
000-111
Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or
OPERATION command or both), bias power is removed, or another fault condition
causes the unit to shut down. The time between the start of each attempt to restart is
set by the value in bits [2:0] multiplied by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms
increments. Range is 35ms to 280ms.
FN8760.1
December 11, 2015
ZL8802
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the IOUT peak overcurrent fault threshold. This limit is applied to current measurement samples taken after the Current
Sense Blanking Time has expired (see “ISENSE_CONFIG (D0h)” on page 62)). A fault occurs after this limit is exceeded for the number of
consecutive samples as defined in ISENSE_CONFIG. This feature shares the OC fault bit operation (in STATUS_IOUT) and OC fault response
with IOUT_AVG_OC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CFG pin-strap setting
Units: A
Equation: IOUT_OC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_OC_FAULT_LIMIT (46h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
CFG Pin-strap Setting
IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the IOUT valley undercurrent fault threshold. This limit is applied to current measurement samples taken after the Current
Sense Blanking Time has expired. A fault occurs after this limit is exceeded for the number of consecutive sample as defined in
ISENSE_CONFIG. This feature shares the UC fault bit operation (in STATUS_IOUT) and UC fault response with IOUT_AVG_UC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: -1 * IOUT_OC_FAULT_LIMIT from CFG pin-strap setting
Units: A
Equation: IOUT_OC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_UC_FAULT_LIMIT (4Bh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Default Value
Submit Document Feedback
Signed Mantissa, Y
-1 * IOUT_OC_FAULT_LIMIT from CFG Pin-strap Setting
39
FN8760.1
December 11, 2015
ZL8802
OT_FAULT_LIMIT (4Fh)
Definition: The OT_FAULT_LIMIT command sets the temperature at which the device should indicate an over-temperature fault.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: EBE8h (+125°C)
Units: Celsius
Equation: OT_FAULT_LIMIT = Y×2N
Range: 0 to 175°C
COMMAND
OT_FAULT_LIMIT (4Fh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
Function
Signed Exponent, N
Default Value
1
1
1
Signed Mantissa, Y
0
1
0
1
1
1
1
1
0
OT_FAULT_RESPONSE (50h)
Definition: The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an over-temperature fault.
The retry time is the time between restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (Continuous retries, retry delay 280ms)
Units: Retry time unit = 35ms
COMMAND
OT_FAULT_RESPONSE (50h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
1
FIELD NAME
0
VALUE
Response behavior, the device:
• Pulls SALRT low
7:6
3
2
1
0
R/W
R/W
R/W
R/W
R/W
1
1
1
See Following Table
Default Value
BIT
4
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
CLEAR_FAULTS command.
00-01
1
1
1
DESCRIPTION
Not used
10
Disable and Retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and the output is enabled when
the temperature falls below the OT_WARN_LIMIT.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
111
Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION
command or both), bias power is removed, or another fault condition causes the unit to shut
down. A retry is attempted after the temperature falls below the OT_WARN_LIMIT. The time
between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range
is 35ms to 280ms.
Retry Setting
Retry Delay
Submit Document Feedback
40
FN8760.1
December 11, 2015
ZL8802
OT_WARN_LIMIT (51h)
Definition: The OT_WARN_LIMIT command sets the temperature at which the device should indicate an over-temperature warning
alarm. In response to the OT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, sets the
OT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: EB70h (+110°C)
Units: Celsius
Equation: OT_WARN_LIMIT = Y×2N
Range: 0 to 175°C
COMMAND
OT_WARN_LIMIT (51h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
1
0
Signed Mantissa, Y
1
0
1
1
0
1
1
1
UT_WARN_LIMIT (52h)
Definition: The UT_WARN_LIMIT command set the temperature at which the device should indicate an under-temperature warning
alarm. In response to the UT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, sets the
UT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: DC40h (-30°C)
Units: Celsius
Equation: UT_WARN_LIMIT = Y×2N
Range: -55°C to +25°C
COMMAND
UT_WARN_LIMIT (52h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
Submit Document Feedback
41
0
1
Signed Mantissa, Y
1
1
0
0
0
1
0
0
FN8760.1
December 11, 2015
ZL8802
UT_FAULT_LIMIT (53h)
Definition: The UT_FAULT_LIMIT command sets the temperature, in degrees Celsius, of the unit at which it should indicate an
under-temperature fault.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: E530h (-45°C)
Units: Celsius
Equation: UT_FAULT_LIMIT = Y×2N
Range: -55°C to +25°C
COMMAND
UT_FAULT_LIMIT (53h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
1
0
0
0
0
0
Function
Signed Exponent, N
Default Value
1
1
1
Signed Mantissa, Y
0
0
1
1
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response as defined by the table below. The retry time is the time between restart
attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (Continuous retries, 280ms retry delay)
Units: Retry time unit = 35ms
COMMAND
UT_FAULT_RESPONSE (54h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
3
2
1
0
R/W
R/W
R/W
R/W
R/W
1
1
1
See Following Table
Default Value
BIT
4
1
FIELD NAME
0
VALUE
Response behavior, the device:
• Pulls SALRT low
7:6 • Sets the related fault bit in the status
registers. Fault bits are only cleared
by the CLEAR_FAULTS command.
00-01
1
1
1
DESCRIPTION
Not used
10
Disable and Retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and the output is enabled when
the temperature rises above the UT_WARN_LIMIT.
000
No retry. The output remains disabled until the device is restarted.
001-110 Not used
5:3
2:0
Retry Setting
Retry Delay
Submit Document Feedback
42
111
Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION
command or both), bias power is removed, or another fault condition causes the unit to shut
down. A retry is attempted after the temperature rises above UT_WARN_LIMIT. The time
between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range
is 35ms to 280ms.
FN8760.1
December 11, 2015
ZL8802
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the VIN overvoltage fault threshold.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D380h (14V)
Units: V
Equation: VIN_OV_FAULT_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_OV_FAULT_LIMIT (55h)
Format
Linear-11
Bit Position
15
14
13
Access
R/W
R/W
R/W
Function
12
11
10
9
8
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Exponent, N
Default Value
1
1
0
1
0
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
Signed Mantissa, Y
0
1
1
1
0
0
0
0
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the VIN overvoltage fault response as defined by the table below.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (Disable, no retry)
Units: N/A
COMMAND
VIN_OV_FAULT_RESPONSE (56h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
BIT
1
FIELD NAME
VALUE
Response behavior, the device:
• Pulls SALRT low
7:6
0
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
CLEAR_FAULTS command.
00-01
0
0
0
DESCRIPTION
Not used
10
Disable and Retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and the output is enabled when
VIN falls below the VIN_OV_WARN_LIMIT.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
111
Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION
command or both), bias power is removed, or another fault condition causes the unit to shut
down. A retry is attempted after the output falls below the VIN_OV_WARN_LIMIT. The time
between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range
is 35ms to 280ms.
Retry Setting
Retry Delay
Submit Document Feedback
43
FN8760.1
December 11, 2015
ZL8802
VIN_OV_WARN_LIMIT (57h)
Definition: Sets the VIN overvoltage warning threshold as defined by the table below. In response to the OV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, sets the VIN_OV_WARNING bit in STATUS_INPUT
and notifies the host.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D360h (13.5V)
Units: V
Equation: VIN_OV_FAULT_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_OV_WARN_LIMIT (57h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
0
1
Signed Mantissa, Y
1
1
0
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above
VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_UV_WARNING bit in STATUS_INPUT,
and notifies the host.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 1.10 x UVLO pin-strap setting
Units: V
Equation: VIN_UV_WARN_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_UV_WARN_LIMIT (58h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Default Value
Submit Document Feedback
Signed Mantissa, Y
1.10 x UVLO Pin-strap Setting
44
FN8760.1
December 11, 2015
ZL8802
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: UVLO pin-strap setting
Units: V
Equation: VIN_UV_FAULT_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_UV_FAULT_LIMIT (59h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
UVLO pin-strapped value
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the VIN undervoltage fault response as defined by the table below. The retry time is the time between restart
attempts.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (continuous retries, 280ms retry delay)
Units: Retry time unit = 35ms
COMMAND
VIN_UV_FAULT_RESPONSE (5Ah)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
BIT
1
FIELD NAME
0
VALUE
Response behavior, the device:
• Pulls SALRT low
7:6 • Sets the related fault bit in the status
registers. Fault bits are only cleared
by the CLEAR_FAULTS command.
00-01
0
0
0
DESCRIPTION
Not used
10
Disable and retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and the output is enabled when
VIN rises above the VIN_UV_WARN_LIMIT.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
Retry Setting
Retry Delay
Submit Document Feedback
45
111
Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION
command or both), bias power is removed, or another fault condition causes the unit to shut
down. A retry is attempted after the input voltage rises above the VIN_UV_WARN_LIMIT. The time
between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range
is 35ms to 280ms.
FN8760.1
December 11, 2015
ZL8802
POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for power-good indication. Power-good asserts when the output voltage exceeds
POWER_GOOD_ON and deasserts when the output voltage is less than VOUT_UV_FAULT_LIMIT. POWER_GOOD_ON should be set to a
value above VOUT_UV_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 0.9 x VSET pin-strap setting.
Units: V
COMMAND
POWER_GOOD_ON (5Eh)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0.9 x VSET Pin-strap Setting
TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of VOUT rise.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TON_DELAY = Y×2N
Range: 0 to 5 seconds
COMMAND
TON_DELAY (60h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
Submit Document Feedback
46
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
FN8760.1
December 11, 2015
ZL8802
TON_RISE (61h)
Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY for single and dual channel operation. To adjust the rise time in 4-,
6- or 8-phase operation, use MULTI_PHASE_RAMP_GAIN (D5h).
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TON_RISE = Y×2N
Range: 0 to 100ms. Although values can be set below 0.50ms, rise time accuracy cannot be guaranteed. In addition, short rise times
may cause excessive input and output currents to flow, thus triggering overcurrent faults at start-up.
COMMAND
TON_RISE (61h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
Signed Exponent, N
1
1
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
0
0
0
0
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of VOUT fall.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TON_DELAY = Y×2N
Range: 0 to 5 seconds
COMMAND
TOFF_DELAY (64h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
Submit Document Feedback
47
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
FN8760.1
December 11, 2015
ZL8802
TOFF_FALL (65h)
Definition: Sets the fall time for VOUT after DISABLE and TOFF_DELAY. This setting is only valid in single or 2-phase operation. Setting
the TOFF_FALL to values less than 0.5ms will cause the ZL8802 to turn-off both the high and low-side FETs (or disable the DrMOS
device) immediately after the expiration of the TOFF_DELAY time. In 4-, 6- or 8-phase operation, the ZL8802 will always turn-off both
the high and low-side FETs (or disable the DrMOS device) immediately after the expiration of the TOFF_DELAY time.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TOFF_FALL = Y×2N
Range: 0 to 100ms. Values less than 0.5ms will cause the ZL8802 to tri-state the PWM signal (turn-off both the high and low-side FETs)
immediately after the expiration of the TOFF_DELAY time.
COMMAND
TOFF_FALL (65h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
Submit Document Feedback
48
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
FN8760.1
December 11, 2015
ZL8802
STATUS_BYTE (78h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the
information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the
STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_BYTE (78h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
BIT NUMBER
STATUS BIT
NAME
7
BUSY
6
OFF
0
0
0
A fault was declared because the device was busy and unable to respond.
This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being
enabled.
VOUT_OV_FAULT An output overvoltage fault has occurred.
4
IOUT_OC_FAULT An output overcurrent fault has occurred.
3
VIN_UV_FAULT An input undervoltage fault has occurred.
2
TEMPERATURE A temperature fault or warning has occurred.
CML
0
None of the
above
Submit Document Feedback
0
MEANING
5
1
0
A communications, memory or logic fault has occurred.
A fault other than the faults listed in bits 7:1 above has occurred. The source of the fault will be in bits 15:8 of the
STATUS_WORD
49
FN8760.1
December 11, 2015
ZL8802
STATUS_WORD (79h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the
information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the
STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 0000h
Units: N/A
COMMAND
STATUS_WORD (79h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
15
VOUT
An output voltage fault or warning has occurred.
14
IOUT
An output current fault has occurred.
13
INPUT
12
MFG_SPECIFIC
11
POWER_GOOD #
10
NOT USED
9
OTHER
8
Not Used
7
BUSY
A fault was declared because the device was busy and unable to
respond.
6
OFF
This bit is asserted if the unit is not providing power to the output,
regardless of the reason, including simply not being enabled.
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
0
None of the above
An input voltage fault or warning has occurred.
A manufacturer specific fault or warning has occurred.
The POWER_GOOD signal, if present, is negated. (Note 15)
Not used
A bit in STATUS_VOUT, STATUS_IOUT, STATUS_INPUT,
STATUS_TEMPERATURE, STATUS_CML, or STATUS_MFR_SPECIFIC is
set.
Not used
A communications, memory or logic fault has occurred.
A fault other than the faults listed in bits 7:1 above has occurred. The
source of the fault will be in bits 15:8 of the STATUS_WORD
NOTE:
15. If the POWER_GOOD# bit is set, this indicates that the POWER_GOOD signal, if present, is signaling that the output power is not good.
Submit Document Feedback
50
FN8760.1
December 11, 2015
ZL8802
STATUS_VOUT (7Ah)
Definition: The STATUS_VOUT command returns one data byte with the status of the output voltage.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_VOUT (7Ah)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
7
VOUT_OV_FAULT
6
VOUT_OV_WARNING
Not used
5
VOUT_UV_WARNING
Not used
4
VOUT_UV_FAULT
3:0
Not Used
Indicates an output overvoltage fault.
Indicates an output undervoltage fault.
Not used
STATUS_IOUT (7Bh)
Definition: The STATUS_IOUT command returns one data byte with the status of the output current.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_IOUT (7Bh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
0
0
0
BIT NUMBER
STATUS BIT NAME
7
IOUT_OC_FAULT
6
Not Used
Not used
5
Not Used
Not used
4
IOUT_UC_FAULT
3:0
Not Used
Submit Document Feedback
51
0
0
MEANING
An output overcurrent fault has occurred.
An output undercurrent fault has occurred.
Not used
FN8760.1
December 11, 2015
ZL8802
STATUS_INPUT (7Ch)
Definition: The STATUS_INPUT command returns input voltage and input current status information.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read-only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_INPUT (7Ch)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
7
VIN_OV_FAULT
6
VIN_OV_WARNING
An input overvoltage warning has occurred.
5
VIN_UV_WARNING
An input undervoltage warning has occurred.
4
VIN_UV_FAULT
3:0
Not Used
An input overvoltage fault has occurred.
An input undervoltage fault has occurred.
Not used
STATUS_TEMPERATURE (7Dh)
Definition: The STATUS_TEMPERATURE command returns one byte of information with a summary of any temperature related faults or
warnings.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read-only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_TEMP (7Dh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
7
OT_FAULT
6
OT_WARNING
An over-temperature warning has occurred.
5
UT_WARNING
An under-temperature warning has occurred.
4
UT_FAULT
An under-temperature fault has occurred.
3:0
Not Used
Not used
Submit Document Feedback
52
MEANING
An over-temperature fault has occurred.
FN8760.1
December 11, 2015
ZL8802
STATUS_CML (7Eh)
Definition: The STATUS_WORD command returns one byte of information with a summary of any communications, logic and/or
memory errors.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_CML (7Eh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
0
0
0
BIT NUMBER
0
MEANING
7
Invalid or unsupported PMBus™ command was received.
6
The PMBus™ command was sent with invalid or unsupported data.
5
A packet error was detected in the PMBus™ command.
4:2
0
Not used
1
A PMBus™ command tried to write to a read-only or protected command, or a communication fault other than the ones listed in
this table has occurred.
0
Not used
Submit Document Feedback
53
FN8760.1
December 11, 2015
ZL8802
STATUS_MFR_SPECIFIC (80h)
Definition: The STATUS_MFR_SPECIFIC command returns one byte of information providing the status of the device’s voltage
monitoring and clock synchronization faults.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_MFR_SPECIFIC (80h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
BIT
FIELD NAME
MEANING
7
Not Used
6
DDC Warning
5
VMON UV Warning
The voltage on the VMON pin has dropped 10% below the level set by MFR_VMON_UV_FAULT.
4
VMON OV Warning
The voltage on the VMON pin has risen 10% above the level set by MFR_VMON_OV_FAULT.
3
External Switching Period Fault
2
Not Used
1
VMON UV Fault
The voltage on the VMON pin has dropped below the level set by MFR_VMON_UV_FAULT.
0
VMON OV Fault
The voltage on the VMON pin has risen above the level set by MFR_VMON_OV_FAULT.
Not used
An error was detected on the DDC bus.
Loss of external clock synchronization has occurred.
Not used
READ_VIN (88h)
Definition: Returns the input voltage reading.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: V
Equation: READ_VIN = Y×2N
Range: N/A
COMMAND
READ_VIN (88h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
Submit Document Feedback
N/A
54
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FN8760.1
December 11, 2015
ZL8802
READ_IIN (89h)
Definition: Returns the input current reading.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IIN = Y×2N
Range: N/A
COMMAND
READ_IIN (89h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: Read Only
Protectable: No
Default Value: N/A
Equation: READ_VOUT = READ_VOUT × 2-13
Units: V
COMMAND
READ_VOUT (8Bh)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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55
FN8760.1
December 11, 2015
ZL8802
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IOUT = Y×2N
Range: N/A
COMMAND
READ_IOUT (8Ch)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Default Value
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_TEMPERATURE_1 (8Dh)
Definition: Returns the temperature reading internal to the device.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_1 = Y×2N
Range: N/A
COMMAND
READ_TEMPERATURE_1 (8Dh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
Submit Document Feedback
N/A
56
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FN8760.1
December 11, 2015
ZL8802
READ_TEMPERATURE_2 (8Eh)
Definition: Returns the temperature reading from the external temperature device connected to XTEMP.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_2 = Y×2N
Range: N/A
COMMAND
READ_TEMPERATURE_2 (8Eh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_TEMPERATURE_3 (8Fh)
Definition: Returns the temperature reading from the VMON/TMON pin when the device is configured to read temperature on the
VMON/TMON pin by setting bit 12 in the USER_GLOBAL_CONFIG command to 1. The voltage on the VMON/TMON pin is converted to °C
by the equation TEMPERTATURE 3 = (VMON voltage - 0.6V)/0.008. See MFR_VMON commands starting on page 85 (F5h, F6h, F8h,
F9H) for fault limits when reading temperature on the VMON/TMON pin. When using the Intersil ISL9922X smart power stage, a 2:1
voltage divider is needed between the TMON pin of the ISL9922X and the VMON/TMON pin of the ZL8802.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_3 = Y×2N
Range: N/A
COMMAND
READ_TEMPERATURE_3 (8Fh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
Submit Document Feedback
N/A
57
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FN8760.1
December 11, 2015
ZL8802
READ_DUTY_CYCLE (94h)
Definition: Reports the actual duty cycle of the converter during the enable state.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: %
Equation: READ_DUTY_CYCLE = Y×2N
Range: 0 to 100%
COMMAND
READ_DUTY_CYCLE (94h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Default Value
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Default Value: N/A
Units: kHz
Equation: READ_FREQUENCY = Y×2N
Range: N/A
COMMAND
READ_FREQUENCY (95h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
Submit Document Feedback
N/A
58
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FN8760.1
December 11, 2015
ZL8802
PMBUS_REVISION (98h)
Definition: The PMBUS_REVISION command returns the revision of the PBus Specification to which the device is compliant.
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: N/A
Default Value: 22h (Part 1 Revision 1.2, Part 2 Revision 1.2)
Units: N/A
COMMAND
PMBUS_REVISION (98h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
1
0
Function
See Following Table
Default Value
0
0
1
0
0
BITS 7:4
PART 1 REVISION
BITS 3:0
PART 2 REVISION
0000
1.0
0000
1.0
0001
1.1
0001
1.1
0010
1.2
0010
1.2
MFR_ID (99h)
Definition: MFR_ID sets a user defined identification string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot
exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform
a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII, ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_MODEL (9Ah)
Definition: MFR_MODEL sets a user defined model string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,
MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128bytes.
This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write
this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII, ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
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59
FN8760.1
December 11, 2015
ZL8802
MFR_REVISION (9Bh)
Definition: MFR_REVISION sets a user defined revision string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot
exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform
a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_LOCATION (9Ch)
Definition: MFR_LOCATION sets a user defined location identifier string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot
exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform
a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_DATE (9Dh)
Definition: MFR_DATE sets a user defined date string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,
MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128bytes.
This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write
this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_SERIAL (9Eh)
Definition: MFR_SERIAL sets a user defined serialized identifier string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot
exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform
a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
Submit Document Feedback
60
FN8760.1
December 11, 2015
ZL8802
IC_DEVICE_ID (ADh)
Definition: Reports device identification information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Protectable: No
Default Value: 49A02D00h (ZL8802)
Units: N/A
COMMAND
IC_DEVICE_ID (ADh)
Format
Block Read
Byte Position
3
2
1
0
Function
MFR code
ID High Byte
ID Low Byte
Reserved
Default Value
49h
A0h
2Ah
00h
IC_DEVICE_REV (AEh)
Definition: Reports device revision information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Protectable: No
Default Value: 01000000h (initial release)
Units: N/A
COMMAND
IC_DEVICE_REV (AEh)
Format
Block Read
Byte Position
3
2
1
0
Function
Firmware Major
Firmware Minor
Factory Configuration
Reserved
Default Value
01h
00h
00h
00h
USER_DATA_00 (B0h)
Definition: USER_DATA_00 sets a user defined data string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,
MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128bytes
This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write
this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
Submit Document Feedback
61
FN8760.1
December 11, 2015
ZL8802
MIN_VOUT_REG (CEh)
Definition: Sets the minimum output voltage in millivolts (mV) that the device will attempt to regulate to during start-up and shutdown
ramps.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0mV)
Units: A
Equation: MIN_VOUT_REG = Y x 2N
COMMAND
MIN_VOUT_REG (CEh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
Signed Exponent, N
1
1
1
1
Signed Mantissa, Y
0
0
1
0
0
1
0
1
1
0
0
0
ISENSE_CONFIG (D0h)
Definition: Configures current sense circuitry.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W word
Protectable: Yes
Default Value: 620Eh (384ns blanking, SPS sensing, high range)
Units: N/A
Range: N/A
COMMAND
ISENSE_CONFIG (D0h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
1
0
Function
Default Value
See Following Table
0
Submit Document Feedback
1
1
62
0
0
0
1
0
0
FN8760.1
December 11, 2015
ZL8802
BIT
15:11
10:8
7:4
3:2
1:0
FIELD NAME
VALUE
Current Sense Blanking
Time
Current Sense Fault Count
Not Used
Current Sense Control
Current Sense Range
Submit Document Feedback
63
SETTING
00000
0
00001
32
00010
64
00011
96
00100
128
00101
160
00110
192
00111
224
01000
256
01001
288
01010
320
01011
352
01100
384
01101
416
01110
448
01111
480
10000
512
10001
544
10010
576
10011
608
10100
640
10101
672
10110
704
10111
736
11000
768
11001
800
11010
832
000
1
001
3
010
5
011
7
100
9
101
11
110
13
111
15
0000
Not Used
00
Not Used
01
DCR (Down Slope)
10
DCR (Up Slope)
11
SPS
00
Low Range
01
Medium Range
10
High Range
11
Not Used
DESCRIPTION
Sets the blanking time current sense blanking time in increments of 32ns
Sets the number of consecutive overcurrent (OC) or undercurrent (UC) events
required for a fault. An event can occur once during each switching cycle. For
example, if 5 is selected, an OC or UC event must occur for 5 consecutive
switching cycles, resulting in a delay of at least 5 switching periods.
Not used
Selection of current sensing method (SPS IMON)
Low range ±25mV, medium range ±35mV, high range ±50mV
FN8760.1
December 11, 2015
ZL8802
USER_CONFIG (D1h)
Definition: Configures several user-level features. This command should be saved immediately after being written to the desired user or
default store. This is recommended when written as an individual command or as part of a series of commands in a configuration file
or script.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: N/A
COMMAND
USER_CONFIG (D1h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
CFG Pin-strap Setting
BIT
FIELD NAME
15:11 Minimum Duty Cycle
VALUE
SETTING
00000
0-31d
DESCRIPTION
Sets the minimum duty-cycle to 2X(VALUE+1)/512. Must be enabled with Bit 7
10
Not Used
1
Not Used
Not used
9:8
Not Used
00
Not Used
Not used
7
Minimum Duty Cycle
Control
0
Disable
1
Enable
6
Not Used
0
Not Used
5
VSET Select
0
VSET0
0 = Uses only VSET0 to set the pin-strapped output voltage
1
VSET1
1 = Uses only VSET1 to set the pin-strapped output voltage
4
Not Used
0
Not Used
3
PWML disabled state
0
Low when disabled
1
High when disabled
2
Power-good
Configuration
0
Open Drain
1
Push-Pull
1
XTEMP Enable
0
Disable
1
Enable
0
XTEMP Fault Select
0
Disable
1
Enable
Submit Document Feedback
64
Control for minimum duty cycle
Not used
Not used
PWML is low (off) when device is disabled (bit 3 set to 0), or high (on) when device
is disabled (bit 3 set to 1)
0 = PG is open-drain output
1 = PG is push-pull output
Enable external temperature sensor
Selects external temperature sensor to determine temperature faults
FN8760.1
December 11, 2015
ZL8802
IIN_CAL_GAIN (D2h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating input current at +25°C.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: C200h (2mΩ)
Units: mΩ
Equation: IIN_CAL_GAIN = Y×2N
COMMAND
IIN_CAL_GAIN (D2h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Signed Exponent, N
Default Value
1
1
0
Signed Mantissa, Y
0
0
0
1
0
0
0
0
0
DDC_CONFIG (D3h)
Definition: Configures DDC addressing and current sharing for up to 8 phases. To operate as a 2-phase controller, set both phases to the
same rail ID, set phases in rail to 2, then set each phase ID sequentially as 0 and 1. To operate as a 4-phase controller, set all phases to
the same rail ID, set phases in rail to 4, then set each phase ID alternately, for example, the first ZL8802 will be set to 0 and 2, the
second ZL8802 will be set to 1 and 3. The ZL8802 will automatically equally offset the phases in the rail. Phase spreading is done
automatically as part of the DDC_CONFIG command. When using CFG pin-strap settings, the DDC_CONFIG command is set
automatically.
NOTE: The output MUST be connected to VSEN0P and VSEN0N when operating as a 2-phase controller.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: PMBus™ address pin-strap dependent.
Units: N/A
COMMAND
DDC_CONFIG (D3h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
0
Lower 5 bits of device address
0
BIT
FIELD NAME
VALUE
SETTING
15:13
Phase ID
0 to 7
0
Sets the output's phase position within the rail
12:8
Rail ID
0 to 31d
0
Identifies the device as part of a current sharing rail (Shared output)
7:3
Not Used
00
00
Not used
2:0
Phases In Rail
0 to 7
0
Identifies the number of phases on the same rail (+1)
Submit Document Feedback
65
DESCRIPTION
FN8760.1
December 11, 2015
ZL8802
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The
delay time can range from 0ms up to 500ms, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper
debounce to this signal.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h, 1ms
Units: ms
Equation: POWER_GOOD_DELAY = Y×2N
Range: 0 to 500ms
COMMAND
POWER_GOOD_DELAY (D4h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Signed Exponent, N
Default Value
1
0
1
1
Signed Mantissa, Y
1
0
1
0
0
0
0
0
MULTI_PHASE_RAMP_GAIN (D5h)
Definition: MULTI_PHASE_RAMP_GAIN command value indirectly determines the output voltage rise time during the turn-on ramp.
Typical gain values range from 1 to 10. Lower gain values produce longer ramp times.
MULTI_PHASE_RAMP_GAIN mode is automatically selected when the ZLS8802 is configured to operate in a 4-phase current sharing
group. When in MULTI_PHASE_RAMP_GAIN mode, the turn-on ramp up is done with the high bandwidth ASCR control circuitry disabled,
resulting in a lower loop bandwidth during start-up ramps. Once POWER_GOOD has been asserted, ASCR circuitry is enabled and the
ZLS8802 operates normally. When MULTI_PHASE_RAMP_GAIN mode is enabled, soft-off ramps are not allowed (TOFF_FALL is
ignored). When the ZL8802 is commanded to shutdown, the PWMHO/1 output is tri-stated, turning both the high-side and low-side
MOSFETs off, and the PWML0/1 pin is pulled low (DrMOS disabled). Large load current transitions during multphase ramp-ups will
cause output voltage discontinuities.
When the phase count is 2; i.e., when the ZL8802 is operating standalone, ASCR is enabled at all times and all commands associated
with turn-on and turn-off (TON_RISE, TOFF_FALL, Soft-Off) operate normally.
Rise time can be calculated using Equation 7:
RiseTime = VOUT_COMMAND   14  Input Voltage  FREQUENCY_SWITCH (in MHz)  MULTI_PHASE_RAMP_GAIN 
(EQ. 7)
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Custom
Type: R/W
Protectable: Yes
Default Value: 03h
Units: N/A
COMMAND
MULTI_PHASE_RAMP_GAIN (D5h)
Format
1 Byte Binary
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0
0
0
0
0
0
1
1
BIT
FIELD NAME
VALUE
7:0
Gain
00-FF
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66
DESCRIPTION
Start-up ramp gain
FN8760.1
December 11, 2015
ZL8802
INDUCTOR (D6h)
Definition: Informs the device of the circuit’s inductor value. This is used in adaptive algorithm calculations relating to the inductor
ripple current.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: B133h (0.3µH)
Units: µH
Equation: INDUCTOR = Y×2N
Range: 0 to 100µH
COMMAND
INDUCTOR (D6h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
Function
Signed Exponent, N
Default Value
1
0
1
Signed Mantissa, Y
1
0
0
0
1
0
0
1
1
SNAPSHOT_FAULT_MASK (D7h)
Definition: Prevents faults from causing a SNAPSHOT event (and store) from occurring.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: NA
Range: NA
COMMAND
SNAPSHOT_FAULT_MASK (D7h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
15:14
Not Used
13
Group
Ignore Fault Spreading faults
12
Phase
Ignore Other Phase faults
11
CPU
Not used
Ignore CPU faults
10
CRC
9
Not Used
Not used
Ignore CRC Memory faults
8
Not Used
Not used
7
IOUT_UC_FAULT
6
IOUT_OC_FAULT
Ignore output undercurrent faults
Ignore output overcurrent faults
5
VIN_UV_FAULT
Ignore input undervoltage faults
Ignore Input undervoltage faults
4
VIN_OV_FAULT
3
UT_FAULT
Ignore under-temperature faults
2
OT_FAULT
Ignore over-temperature faults
1
VOUT_UV_FAULT
Ignore output undervoltage faults
0
VOUT_OV_FAULT
Ignore output overvoltage faults
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67
FN8760.1
December 11, 2015
ZL8802
OVUV_CONFIG (D8h)
Definition: Configures the output voltage OV and UV fault detection feature
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
OVUV_CONFIG (D8h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
0
BITS
0
0
0
PURPOSE
0
VALUE
DESCRIPTION
Controls how an OV fault response shutdown sets the output
driver state
0
An OV fault does not enable low-side power device
1
An OV fault enables the low-side power device
6:4
Not Used
0
Not used
3:0
Defines the number of consecutive limit violations required to
declare an OV or UV fault
N
N+1 consecutive OV or UV violations initiate a fault response
7
XTEMP_SCALE (D9h)
Definition: Sets a scalar value that is used for calibrating the external temperature. The constant is applied in the equation below to
produce the read value of XTEMP via the PMBus™ command READ_TEMPERATURE_2.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h (1.0)
Units: 1/°C

1
Equation: READ_TEMPERATURE_2   ExternalTemperature 
  XTEMP_OFFSET
XTEMP_SCALE 

Range: 0.1 to 10
COMMAND
XTEMP_SCALE (D9h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
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0
1
68
1
Signed Mantissa, Y
1
0
1
0
0
0
0
0
FN8760.1
December 11, 2015
ZL8802
XTEMP_OFFSET (DAh)
Definition: Sets an offset value that is used for calibrating the external temperature. The constant is applied in the equation below to
produce the read value of XTEMP via the PMBus™ command READ_TEMPERATURE_2.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0)
Units: °C

1
Equation: READ_TEMPERATURE_2  ExternalTemperature 
  XTEMP_OFFSET
XTEMP_SCALE 

Range: -100°C to +100°C
COMMAND
XTEMP_OFFSET (DAh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
0
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0
0
69
0
Signed Mantissa, Y
0
0
0
0
0
0
0
0
FN8760.1
December 11, 2015
ZL8802
MFR_SMBALERT_MASK (DBh)
Definition: The MFR_SMBALERT_MASK command is used to prevent faults from activating the SALRT pin. The bits in each byte
correspond to a specific fault type as defined in the STATUS command.
Data Length in Bytes: 7
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00 00 00 00 00 00 00h (No faults masked)
Units: N/A
COMMAND
MFR_SMBALT_MASK (DBh)
Format
Bit Field
Access
R/W
R/W
R/W
Function
R/W
R/W
R/W
R/W
R/W
See following table
Bit Position
55
54
53
52
51
50
49
48
Default Value Byte 6
0
0
0
0
0
0
0
0
Bit Position
47
46
45
44
43
42
41
40
Default Value Byte 5
0
0
0
0
0
0
0
0
Bit Position
39
38
37
36
35
34
33
32
Default Value Byte 4
0
0
0
0
0
0
0
0
Bit Position
31
30
29
28
27
26
25
24
Default Value Byte 3
0
0
0
0
0
0
0
0
Bit Position
23
22
21
20
19
18
17
16
Default Value Byte 2
0
0
0
0
0
0
0
0
Bit Position
15
14
13
12
11
10
9
8
Default Value Byte 1
0
0
0
0
0
0
0
0
Bit Position
7
6
5
4
3
2
1
0
Default Value Byte 0
0
0
0
0
0
0
0
0
BYTE
STATUS BYTE NAME
6
STATUS_MFR_SPECIFIC
5
STATUS_OTHER
4
STATUS_CML
3
STATUS_TEMPERATURE
2
STATUS_INPUT
1
STATUS_IOUT
Mask output current specific faults as identified in the STATUS_IOUT byte
0
STATUS_VOUT
Mask output voltage specific faults as identified in the STATUS_VOUT byte
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70
MEANING
Mask manufacturer specific faults as identified in the STATUS_MFR_SPECIFIC byte.
Not used
Mask communications, memory or logic specific faults as identified in the STATUS_CML
byte.
Mask temperature specific faults as identified in the STATUS_TEMPERATURE byte
Mask input specific faults as identified in the STATUS_INPUT byte
FN8760.1
December 11, 2015
ZL8802
TEMPCO_CONFIG (DCh)
Definition: Configures the correction factor and temperature measurement source when performing temperature coefficient correction
for current sense. TEMPCO_CONFIG values are applied as negative correction to a positive temperature coefficient. TEMPCO_CONFIG
should be set to 3900ppm (27h) when using inductor DCR current sensing in order to compensate for the variation in inductor
resistance due to the temperature coefficient of copper. When using the ISL9922X Smart Power Stage, TEMPCO_CONFIG should be set
to 0ppm (00h) since the IMON signal from the ISL9922X is internally compensated for temperature.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h (0ppm/°C, copper)
Equation: To determine the hex value of the Tempco Correction factor (TC) for current scale of a power stage current sensing, first
determine the temperature coefficient of resistance for the sensing element, α. This is found with Equation 8:
RREF  R

(EQ. 8)
RREF (TREF  T )
Where:
R = Sensing element resistance at temperature “T”
RREF = Sensing element resistance at reference temperature TREF
α = Temperature coefficient of resistance for the sensing element material
T = Temperature measured by temperature sensor, in degrees Celsius
TREF = Reference temperature that α is specified at for the sensing element material
After α is determined, convert the value in units of 100ppm/°C. This value is then converted to a hex value with Equation 9:
TC 
 106
(EQ. 9)
100
Range: 0 to 12700ppm/˚C
COMMAND
TEMPCO_CONFIG (DCh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
0
0
BITS
PURPOSE
7
Selects the temp sensor source for tempco correction
6:0
Sets the tempco correction in units of 100ppm/˚C for
IOUT_CAL_GAIN
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71
0
VALUE
0
0
DESCRIPTION
0
Selects the internal temperature sensor
1
Selects the XTEMP pin for temperature measurements (2N3904 Junction)
Note that XTEMP must be enabled in USER_CONFIG, bit 1.
TC
RSEN (DCR) = IOUT_CAL_GAIN x (1+TC x (T-25))
Where RSEN = resistance of sense element
FN8760.1
December 11, 2015
ZL8802
PINSTRAP_READ_STATUS (DDh)
Definition: Reads back 7 bytes of 8 bit values that represent the pin-strap settings of each of the device’s pin-strap pins. This value
corresponds to a resistor value, a high, a low or an open condition. The pin decode values correspond to pin-strap settings according to
Table 9:
TABLE 9.
R (kΩ)
DECODE
R (kΩ)
DECODE
10
00
51.1
11
11
01
56.2
12
12.1
02
61.9
13
13.3
03
68.1
14
14.7
04
75
15
16.2
05
82.5
16
17.8
06
90.9
17
19.6
07
100
18
21.5
08
110
19
23.7
09
121
1A
26.1
0A
133
1B
28.7
0B
147
1C
31.6
0C
162
1D
34.8
0D
178
1E
38.3
0E
LOW
F1
42.2
0F
OPEN
F2
46.4
10
HIGH
F3
Unmeasured
F4
Paged or Global: Global
Data Length in Bytes: 7
Data Format: Bit Field
Type: Read Only
Protectable: Yes
Default Value: Pin-strap settings
Units: N/A
COMMAND
READ_PINSTRAP (DDh)
Format
Bit Field
Bit Position
55
54
53
52
51
50
49
48
Access
R
R
R
R
R
R
R
R
Function
ASCRCFG Pin Decode
Default Value
ASCRCFG Pin-strap Setting
Format
Bit Field
Bit Position
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
CFG Pin Decode
SYNC Pin Decode
Default Value
CFG Pin-strap Setting
SYNC Pin-strap Setting
Format
Submit Document Feedback
Bit Field
72
FN8760.1
December 11, 2015
ZL8802
COMMAND
READ_PINSTRAP (DDh) (Continued)
Bit Position
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
UVLO Pin Decode
VSET0 Pin Decode
Default Value
UVLO Pin-strap Setting
VSET0 Pin-strap Setting
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
VSET1 Pin Decode
Reserved
Default Value
VSET1 Pin-strap Setting
N/A
BITS
PURPOSE
VALUE
55:48
ASCRCFG Pin Decode
00-F4h
Decode value of ASCRCFG pin-strap setting
47:40
CFG Pin Decode
00-F4h
Decode value of CFG pin-strap setting
39:32
SYNC Pin Decode
00-F4h
Decode value of SYNC pin-strap setting
31:24
UVLO Pin Decode
00-F4h
Decode value of UVLO pin-strap setting
23:16
VSET0 Pin Decode
00-F4h
Decode value of VSET0 pin-strap setting
15:8
VSET1 Pin Decode
00-F4h
Decode value of VSET1 pin-strap setting
7:0
Not Used
FF
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73
DESCRIPTION
Not used
FN8760.1
December 11, 2015
ZL8802
ASCR_CONFIG (DFh)
Definition: Allows user configuration of ASCR settings. ASCR gain and residual value are automatically set by the ZL8802 based on
input voltage and output voltage. ASCR gain is analogous to bandwidth, ASCR residual is analogous to damping. To improve load
transient response performance, increase ASCR gain. To lower transient response overshoot, increase ASCR residual. Increasing ASCR
gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain can lead to excessive
output voltage ripple. Increasing ASCR residual to improve transient response damping can result in slower recovery times, but will not
affect the peak output voltage deviation. Typical ASCR gain settings range from 100 to 1000, and ASCR residual settings range from
10 to 90.
Paged or Global: Paged
Data Length in Bytes: 4
Data Format: Bit Field and nonsigned binary
Type: R/W
Protectable: Yes
Default Value: ASCRCFG pin-strap setting
Units: N/A
COMMAND
ASCR_CONFIG (DFh)
Format
Bit Field/Linear-8 Unsigned
Bit Position
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
See Following Table
0
0
0
0
0
0
0
1
Format
ASCRCFG Pin-strap Setting (residual)
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
ASCRCFG Pin-strap Setting (gain)
BITS
PURPOSE
VALUE
31:25
Not Used
0000000h
24
ASCR Enable
23:16
ASCR Residual Setting
0 - 7Fh
ASCR residual
15:0
ASCR Gain Setting
0-FFh
ASCR gain
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DESCRIPTION
Not used
1
Enable
0
Disable
FN8760.1
December 11, 2015
ZL8802
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multirail sequencing. The device will enable its
output when its EN or OPERATION enable state, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a power-good
event on the DDC bus as a result of the prequel’s Power-good (PG) signal going high. The device will disable its output (using the
programmed delay values) when the sequel device has issued a power-down event on the DDC bus at the completion of its ramp-down
(its output voltage is 0V).
The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant
byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or
sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h (prequel and sequel disabled)
Units: N/A
COMMAND
SEQUENCE (E0h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Function
See Following Table
Default Value
0
BIT
FIELD NAME
15
Prequel Enable
14:13
0
0
0
0
0
0
0
0
VALUE
SETTING
0
Disable
Disable, no prequel preceding this rail
1
Enable
Enable, prequel to this rail is defined by bits 12:8
Not Used
0
Not Used
12:8
Prequel Rail DDC ID
0-31d
DDC ID
Set to the DDC ID of the prequel rail
7
Sequel Enable
0
Disable
Disable, no sequel following this rail
1
Enable
Enable, sequel to this rail is defined by bits 4:0
6:5
Not Used
0
Not Used
4:0
Sequel Rail DDC ID
0-31d
DDC ID
Submit Document Feedback
75
DESCRIPTION
Not used
Not used
Set to the DDC ID of the sequel rail
FN8760.1
December 11, 2015
ZL8802
TRACK_CONFIG (E1h)
Definition: Configures the voltage tracking modes of the device. Single device (Channel 0, Channel 1 or 2-phase) tracking is supported.
Tracking as part of a 4-, 6- or 8-phase current sharing group is not supported. When tracking, the TOFF_DELAY in the tracking device
must be greater than TOFF_DELAY + TOFF_FALL in the device being tracked. When configured to track, VOUT_COMMAND must be set to
the desired steady state output voltage.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
TRACK_CONFIG (E1h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
0
BIT
FIELD NAME
7
Voltage Tracking Control
6:3
Not Used
2
Tracking Ratio Control
1
Tracking Upper Limit
0
Not Used
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76
0
0
0
0
VALUE
SETTING
DESCRIPTION
0
Disable
Tracking is Disabled.
1
Enable
Tracking is Enabled.
0000
Not Used
0
100%
Output Tracks at 100% ratio of VTRK input.
1
50%
Output Tracks at 50% ratio of VTRK input.
0
Target Voltage
Output Voltage is Limited by Target Voltage.
1
VTRK Voltage
Output Voltage is Limited by VTRK Voltage.
0
Not Used
Not used
Not used
FN8760.1
December 11, 2015
ZL8802
DDC_GROUP (E2h)
Definition: Rails (output voltages) are assigned Group numbers in order to share specified behaviors. The DDC_GROUP command
configures fault spreading group ID and enable, broadcast OPERATION group ID and enable, and broadcast VOUT_COMMAND group ID
and enable. Note that DDC Groups are separate and unique from DDC Rail IDs (see “DDC_CONFIG (D3h)” on page 65). Current sharing
rails need to be in the same DDC Group in order to respond to broadcast VOUT_COMMAND and OPERATION commands. Power fail
event responses (and phases) are automatically spread in Phase 0 and 1 when the ZL8802 is operating in 2-phase current sharing
mode when it is configured using DDC_CONFIG, regardless of its setting in DDC_GROUP.
Paged or Global: Paged
Data Length in Bytes: 34
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: N/A
COMMAND
DDC_GROUP (E2h)
Format
Bit Field
Bit Position
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Not Used
EN>
Default Value
Set by CFG Pin-strap Setting
Format
Bit Field
VOUT_COMMAND Group ID
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Not Used
EN>
OPERATION Group ID
Default Value
Not Used
EN>
Power Fail Group ID
Set by CFG Pin-strap Setting
BITS
PURPOSE
VALUE
31:22
Not Used
00
Not used
21
BROADCAST_VOUT_COMMAND response
1
Responds to broadcast VOUT_COMMAND with same Group ID
0
Ignores broadcast VOUT_COMMAND
20:16
BROADCAST_VOUT_COMMAND group ID
0-31d
15:14
Not Used
00
Not used
13
BROADCAST_OPERATION response
1
Responds to broadcast OPERATION with same Group ID
0
Ignores broadcast OPERATION
12:8
BROADCAST_OPERATION group ID
0-31d
7:6
Not Used
00
Not used
5
POWER_FAIL response
1
Responds to POWER_FAIL events with same Group ID by shutting down immediately
0
Responds to POWER_FAIL events with same Group ID with sequenced shutdown
4:0
POWER_FAIL group ID
Submit Document Feedback
77
0-31d
DESCRIPTION
Group ID sent as data for broadcast VOUT_COMMAND events
Group ID sent as data for broadcast OPERATION events
Group ID sent as data for broadcast POWER_FAIL events
FN8760.1
December 11, 2015
ZL8802
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string. The format is: Part number, Major Revision, (period), Minor Revision,
Engineering version letter
Paged or Global: Global
Data Length in Bytes: 16
Data Format: ASCII. ISO/IEC 8859-1
Type: Block Read
Protectable: Read Only
Default Value: ZL8802, current major revision, (period), current minor revision, current engineering version letter
Units: N/A
COMMAND
DEVICE_ID (E4h)
Format
Characters (Bytes)
Characters
15
14
13
12
Access
R
R
R
R
Function
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
Part Number
Default Value
Z
L
8
8
0
0
Maj. Rev.
.
Min. Rev
*
*
*
*
Engr.
*
*
* Current revision at time of manufacture
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the IOUT overcurrent fault response as defined by the table below. The command format is the same as the
PMBus™ standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT. The retry time is the time between
restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (immediate shutdown, no retries)
Units: Retry time unit = 35ms
COMMAND
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
See Following Table
Default Value
1
0
0
0
0
BIT
FIELD NAME
VALUE
DESCRIPTION
00
Not used
01
Not used
7:6
Response behavior, for all modes, the
device:
• Pulls SALRT low
• Sets the related fault bit in the
status registers. Fault bits are only
cleared by the CLEAR_FAULTS
command.
10
Disable without delay and retry according to the setting in bits 5:3.
11
Output is disabled while the fault is present. Operation resumes and the output is enabled
when the fault is no longer present.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
Retry Setting
Retry Delay
Submit Document Feedback
78
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down. The time between the
start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
FN8760.1
December 11, 2015
ZL8802
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the IOUT undercurrent fault response as defined by the table below. The command format is the same as the
PMBus™ standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT. The retry time is the time between
restart attempts.
Data Length in Bytes: 1
Paged or Global: Paged
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shutdown, no retries)
Units: Retry time unit = 35ms
COMMAND
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
1
0
0
0
0
BIT
FIELD NAME
VALUE
DESCRIPTION
7:6
Response behavior, for all modes, the device:
• Pulls SALRT low
• Sets the related fault bit in the status
registers. Fault bits are only cleared by the
CLEAR_FAULTS command.
00
Not used
01
Not used
10
Disable without delay and retry according to the setting in bits 5:3.
11
Output is disabled while the fault is present. Operation resumes and the output is
enabled when the fault is no longer present.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
Retry Setting
111
2:0
Retry Delay
Submit Document Feedback
79
000-111
Attempts to restart continuously, without checking if the fault is still present, until it
is commanded OFF (by the CONTROL pin or OPERATION command or both), bias
power is removed, or another fault condition causes the unit to shut down. The time
between the start of each attempt to restart is set by the value in bits [2:0] multiplied
by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms
increments. Range is 35ms to 280ms.
FN8760.1
December 11, 2015
ZL8802
IOUT_AVG_OC_FAULT_LIMIT (E7h)
Definition: Sets the IOUT average overcurrent fault threshold. For down-slope sensing, this corresponds to the average of all the current
samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the beginning of the 1-D
interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval, excluding the
current sense blanking time (which occurs at the beginning of the D interval). This feature shares the OC fault bit operation (in
STATUS_IOUT) and OC fault response with IOUT_ OC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CFG pin-strap setting
Units: Amperes
Equation: IOUT_AVG_OC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_AVG_OC_FAULT_LIMIT (E7h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
CFG Pin-strap Setting
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Definition: Sets the IOUT average undercurrent fault threshold. For down-slope sensing, this corresponds to the average of all the current
samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the beginning of the 1-D
interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval, excluding the
current sense blanking time (which occurs at the beginning of the D interval). This feature shares the UC fault bit operation (in
STATUS_IOUT) and UC fault response with IOUT_ UC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: -1 X IOUT_AVG_OC_FAULT_LIMIT as set by CFG pin-strap setting
Units: Amperes
Equation: IOUT_AVG_UC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Default Value
Submit Document Feedback
Signed Mantissa, Y
-1 X IOUT_AVG_OC_FAULT_LIMIT as set by CFG Pin-strap Setting
80
FN8760.1
December 11, 2015
ZL8802
USER_GLOBAL_CONFIG (E9h)
Definition: This command is used to set options for output voltage sensing, VMON/TMON pin configuration, SMBus time-out and DDC
and SYNC output configurations.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: N/A
COMMAND
USER_GLOBAL_CONFIG (E9h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
Set by CFG Pin-strap Setting
BITS
PURPOSE
VALUE
15:13
Not Used
000000
12
VMON/TMON Config
0
MFR_READ_VMON returns voltage on VMON pin in Volts. External 16:1
voltage divider needed on VMON/TMON pin (pin 6) to voltage being
monitored.
1
READ_TEMPERATURE_3 returns TMON in °C. External 2:1 voltage divider
needed on VMON/TMON pin (pin 6) to SPS TMON pin.
11:10
Not Used
9:8
VSENSE Select for monitoring and fault
detection
7
Not Used
6
DDC output Configuration
5
Not Used
4
Disable SMBus Time-Outs
3
Not Used
2:1
0
Submit Document Feedback
Sync I/O Control
Not Used
81
DESCRIPTION
Not used
00
Not used
00
Output 0 uses VSEN0, Output 1 uses VSEN1
01
Both outputs use VSEN0
10-11
Not used
0
Not used
0
DDC output open drain
1
DDC output push-pull
0
Not used
0
SMBus time-outs enabled
1
SMBus time-outs disabled
0
Not used
00
Use internal clock (frequency initially set with pin-strap)
01
Use internal clock and output internal clock (not for use with pin-strap)
10
Use external clock
11
Not used
0
Not used
FN8760.1
December 11, 2015
ZL8802
SNAPSHOT (EAh)
Definition: The SNAPSHOT command is a 32-byte read-back of parametric and status values. It allows monitoring and status data to be
stored to flash either during a fault condition or via a system-defined time using the SNAPSHOT_CONTROL command. Snapshot is
continuously updated in RAM and can be read using the SNAPSHOT command. When a fault occurs, the latest snapshot in RAM is
stored to flash. Snapshot data can read back by writing a 01h to the SNAPSHOT_CONTROL command, then reading SNAPSHOT.
Paged or Global: Paged
Data Length in Bytes: 32
Data Format: Bit Field
Type: Block Read
Protectable: No
Default Value: N/A
Units: N/A
BYTE NUMBER
VALUE
PMBus™ COMMAND
FORMAT
31:23
Not Used
Not Used
0000h
22
Flash Memory Status Byte
N/A
Bit Field
21
Manufacturer Specific Status Byte
STATUS_MFR_SPECIFIC (80h)
1 Byte Bit Field
20
CML Status Byte
STATUS_CML (7Eh)
1 Byte Bit Field
19
Temperature Status Byte
STATUS_TEMPERATURE (7Dh)
1 Byte Bit Field
18
Input Status Byte
STATUS_INPUT (7Ch)
1 Byte Bit Field
17
IOUT Status Byte
STATUS_IOUT (7Bh)
1 Byte Bit Field
16
VOUT Status Byte
STATUS_VOUT (7Ah)
1 Byte Bit Field
15:14
Switching Frequency
READ_FREQUENCY (95h)
2 Byte Linear-11
13:12
External Temperature
READ_TEMPERATURE_2 (8Eh)
2 Byte Linear-11
11:10
Internal Temperature
READ_TEMPERATURE_1 (8Dh)
2 Byte Linear-11
9:8
Duty Cycle
READ_DUTY_CYCLE (94h)
2 Byte Linear-11
7:6
Highest Measured Output Current
N/A
2 Byte Linear-11
5:4
Output Current
READ_IOUT (8Ch)
2 Byte Linear-11
3:2
Output Voltage
READ_VOUT (8Bh)
2 Byte Linear-16 Unsigned
1:0
Input Voltage
READ_VIN (88h)
2 Byte Linear-11
Submit Document Feedback
82
FN8760.1
December 11, 2015
ZL8802
LEGACY_FAULT_GROUP (F0h)
Definition: This command allows the ZL8802 to sequence and fault spread with devices other than the ZL8800 family of ICs. This
command sets which rail DDC IDs should be listened to for fault spreading information. The data sent is a 4-byte, 32-bit bit vector
where every bit represents a rail’s DDC ID. A bit set to 1 indicates a device DDC ID to which the configured device will respond upon
receiving a fault spreading event. In this vector, bit 0 of byte 0 corresponds to the rail with DDC ID 0. Following through, Bit 7 of byte 3
corresponds to the rail with DDC ID 31.
NOTE: The device/rail’s own DDC ID should not be set within the LEGACY_FAULT_GROUP command for that device/rail.
All devices in a current share rail (devices other than the ZL8800 family ICs) must shut down for the rail to report a shutdown.
If fault spread mode is enabled in USER_CONFIG, the device will immediately shut down if on of its DDC_GROUP members fail. The
device/rail will attempt its configured restart only after all devices/rails within the DDC_GROUP have cleared their faults.
If fault spread mode is disabled in USER_CONFIG, the device will perform a sequenced shutdown as defined by the SEQUENCE
command setting. The rails/devices in a sequencing set only attempt their configured restart after all faults have cleared within the
DDC_GROUP. If fault spread mode is disabled and sequencing is also disabled, the device will ignore faults from other devices and stay
enabled.
Paged or Global: Paged
Data Length in Bytes: 4
Data Format: Bit field
Type: Block R/W
Protectable: Yes
Default Value: 00000000h
Units: N/A
COMMAND
LEGACY_FAULT_GROUP (F0h)
Format
Bit Field
Bit Position
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
0
0
Format
0
0
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
SETTING
31:0
Fault Group
NA
00000000h
Submit Document Feedback
83
0
0
0
DESCRIPTION
Identifies the devices in the fault spreading group.
FN8760.1
December 11, 2015
ZL8802
SNAPSHOT_CONTROL (F3h)
Definition: Writing a 01h will cause the device to copy the current SNAPSHOT values from NVRAM to the 32-byte SNAPSHOT command
parameter. Writing a 02h will cause the device to write the current SNAPSHOT values to NVRAM, 03h will erase all SNAPSHOT values
from NVRAM. Write (02h) and Erase (03h) may only be used when the device is disabled. All other values will be ignored. SNAPSHOT
03h must be written to the device when the device is DISABLED. Data will not be updated, or written to NVRAM after a fault occurs until
the SNAPSHOT 03h command has been written.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W Byte
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
SNAPSHOT_CONTROL (F3h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Function
See Following Table
Default Value
VALUE
0
0
DESCRIPTION
01
Read SNAPSHOT values from NVRAM
02
Write SNAPSHOT values to NVRAM
03
Erase SNAPSHOT values from NVRAM
RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard-coded factory default values and pin-strap definitions. The device retains the DEFAULT and
USER stores for restoring. Security level is changed to Level 1 following this command.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Protectable: Yes
Default Value: N/A
Units: N/A
Submit Document Feedback
84
FN8760.1
December 11, 2015
ZL8802
MFR_VMON_OV_FAULT_LIMIT (F5h)
Definition: Sets the VMON over-temperature fault threshold. The VMON overvoltage warn limit is automatically set to 90% of this fault
value. If VMON is not used, set VMON_OV_FAULT_RESPONSE to 00h, which will disable VMON OV faults entirely.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: C266h (2.4V)
Units: Volts
Equation: MFR_VMON_OV_FAULT_LIMIT = Y×2N
Range: 0 to 20V
COMMAND
MFR_VMON_OV_FAULT_LIMIT (F5h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
0
Function
Default Value
Signed Exponent, N
1
1
1
0
Signed Mantissa, Y
0
0
1
0
0
1
1
0
MFR_VMON_UV_FAULT_LIMIT (F6h)
Definition: Sets the VMON undervoltage fault threshold. The VMON undervoltage warn limit is automatically set to 110% of this fault
value. If VMON is not used, set VMON_UV_FAULT_RESPONSE to 00h, which will disable VMON UV faults entirely.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: B0CCh (0.2V)
Units: Volts
Equation: MFR_VMON_UV_FAULT_LIMIT = Y x 2N
Range: 0 to 20V
COMMAND
MFR_VMON_UV_FAULT_LIMIT (F6h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
Function
Default Value
Signed Exponent, N
1
Submit Document Feedback
0
1
85
1
Signed Mantissa, Y
0
0
0
0
1
1
0
0
FN8760.1
December 11, 2015
ZL8802
MFR_READ_VMON (F7h)
Definition: Reads the voltage on the VMON pin.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: MFR_READ_VMON = Y x 2N
Range: -200°C to +200°C
COMMAND
MFR_READ_VMON (F7h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
N/A
N/A
Function
Signed Exponent, N
Default Value
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VMON_OV_FAULT_RESPONSE (F8h)
Definition: Configures the VMON overvoltage fault response as defined by the table below. Note: The retry time is the time between
restart attempts. If VMON is not used, set this response to 00h, which will disable VMON OV faults entirely
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (continuous retries)
Units: N/A
COMMAND
VMON_OV_FAULT_RESPONSE (F8h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
Function
See Following Table
Default Value
BIT
1
FIELD NAME
0
1
VALUE
Response behavior, the device:
• Pulls SALRT low
7:6 • Sets the related fault bit in the status
registers. Fault bits are only cleared by the
CLEAR_FAULTS command.
1
1
DESCRIPTION
00
Ignore faults
01
Not used
10
Disable without delay and retry according to the setting in bits 5:3.
11
Output is disabled while the fault is present. Operation resumes and the output is enabled
when VMON falls below 95% of the VMON_OV_FAULT_LIMIT setting.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down. A retry is attempted after
VMON falls below 95% of the VMON_OV_FAULT_LIMIT. The time between the start of each
attempt to restart is set by the value in bits [2:0] multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
Retry Setting
Retry Delay
Submit Document Feedback
86
FN8760.1
December 11, 2015
ZL8802
VMON_UV_FAULT_RESPONSE (F9h)
Definition: Configures the VMON undervoltage fault response as defined by the table below. Note: The retry time is the time between
restart attempts. If VMON is not used, set this response to 00h, which will disable VMON UV faults entirely
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field.
Type: R/W
Protectable: Yes
Default Value: BFh (continuous retries)
Units: Retry time unit = 35ms
COMMAND
VMON_UV_FAULT_RESPONSE (F9h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
Function
See Following Table
Default Value
BIT
7:6
FIELD NAME
Response behavior, the device:
• Pulls SALRT low
• Sets the related fault bit in the
status registers. Fault bits are only
cleared by the CLEAR_FAULTS
command.
VALUE
1
1
DESCRIPTION
00
Fault ignored
01
Not used
10
Disable without delay and retry according to the setting in bits 5:3.
11
Output is disabled while the fault is present. Operation resumes and the output is enabled
when VMON rises above 105% of the VMON_UV_FAULT_LIMIT setting.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down. A retry is attempted after
VMON has risen above 105% of VMON_UV_FAULT_LIMIT. The time between the start of
each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.
000-111
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
Retry Setting
Retry Delay
SECURITY_LEVEL (FAh)
Definition: The device provides write protection for individual commands. Each bit in the UNPROTECT parameter controls whether its
corresponding command is writeable (commands are always readable). If a command is not writeable, a password must be entered in
order to change its parameter (i.e., to enable writes to that command). There are two types of passwords, public and private. The public
password provides a simple lock-and-key protection against accidental changes to the device. It would typically be sent to the device in the
application prior to making changes. Private passwords allow commands marked as nonwriteable in the UNPROTECT parameter to be
changed. Private passwords are intended for protecting default-installed configurations and would not typically be used in the application.
Each store (USER and DEFAULT) can have its own UNPROTECT string and private password. If a command is marked as nonwriteable in the
DEFAULT UNPROTECT parameter (its corresponding bit is cleared), the private password in the DEFAULT store must be sent in order to
change that command. If a command is writeable according to the default UNPROTECT parameter, it may still be marked as nonwriteable
in the user store UNPROTECT parameter. In this case, the user private password can be sent to make the command writeable.
The device supports four levels of security. Each level is designed to be used by a particular class of users, ranging from module
manufacturers to end users, as discussed below. Levels 0 and 1 correspond to the public password. All other levels require a private
password. Writing a private password can only raise the security level. Writing a public password will reset the level down to 0 or 1.
Figure 12 on page 88 shows the algorithm used by the device to determine if a particular command write is allowed.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Hex
Type: Read Byte
Protectable: No
Default Value: 01h
Units: N/A
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Write
Attempted
Always
Writeable
?
Y
N
Read
Only
?
Y
N
Security
Level == 3
?
Y
N
Default
UNPROTECT
== 0
?
Y
N
Security
Level == 2
?
Y
N
User
UNPROTECT
== 0
?
Y
N
Write
Prohibited
N
Security
Level == 1
?
Y
Write
Allowed
FIGURE 12. ALGORITHM USED TO DETERMINE WHEN A COMMAND IS WRITEABLE
Security Level 3 – Module Vendor
Level 3 is intended primarily for use by module vendors to protect device configurations in the default store. Clearing a UNPROTECT bit
in the default store implies that a command is writeable only at Level 3 and above. The device’s security level is raised to Level 3 by
writing the private password value previously stored in the default store. To be effective, the module vendor must clear the UNPROTECT
bit corresponding to the STORE_DEFAULT_ALL and RESTORE_DEFAULT commands. Otherwise, Level 3 protection is ineffective since
the entire store could be replaced by the user, including the enclosed private password.
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Security Level 2 – User
Level 2 is intended for use by the end user of the device. Clearing a UNPROTECT bit in the user store implies that a command is
writeable only at Level 2 and above. The device’s security level is raised to Level 2 by writing the private password value previously
stored in the User Store. To be effective, the user must clear the UNPROTECT bit corresponding to the STORE_USER_ALL,
RESTORE_DEFAULT_ALL, STORE_DEFAULT_ALL and RESTORE_DEFAULT commands. Otherwise, Level 2 protection is ineffective since
the entire store could be replaced, including the enclosed private password.
Security Level 1 – Public
Level 1 is intended to protect against accidental changes to ordinary commands by providing a global write-enable. It can be used to
protect the device from erroneous bus operations. It provides access to commands whose UNPROTECT bit is set in both the default and
User Store. Security is raised to Level 1 by writing the public password stored in the user store using the PUBLIC_PASSWORD command.
The public password stored in the default store has no effect.
Security Level 0 - Unprotected
Level 0 implies that only commands which are always writeable (e.g., PUBLIC_PASSWORD) are available. This represents the lowest
authority level and hence the most protected state of the device. The level can be reduced to 0 by using PUBLIC_PASSWORD to write
any value which does not match the stored public password.
PRIVATE_PASSWORD (FBh)
Definition: Sets the private password string.
Paged or Global: Global
Data Length in Bytes: 9
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: No
Default Value: 000000000000000000h
Units: N/A
PUBLIC_PASSWORD (FCh)
Definition: Sets the public password string.
Paged or Global: Global
Data Length in Bytes: 4
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: No
Default Value: 00000000h
Units: N/A
UNPROTECT (FDh)
Definition: Sets a 256-bit (32-byte) parameter which identifies which commands are to be protected against write-access at lower
security levels. Each bit in this parameter corresponds to a command according to the command’s code. The command with a code of
00h (PAGE) is protected by the least-significant bit of the least-significant byte, followed by the command with a code of 01h and so
forth. Note that all possible commands have a corresponding bit regardless of whether they are protectable or supported by the device.
Clearing a command’s UNPROTECT bit indicates that write-access to that command is only allowed if the device’s security level has
been raised to an appropriate level. The UNPROTECT bits in the default store require a security level 3 or greater to be writeable. The
UNPROTECT bits in the user store require a security level of 2 or higher.
Data Length in Bytes: 32
Paged or Global: Global
Data Format: Custom
Type: Block R/W
Protectable: No
Default Value: FF…FFh
Units: N/A
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
December 11, 2015
FN8760.1
Added Junction Temperature to the “Thermal Information” on page 8.
Added ZL8802ALAFT7A to the ordering information table on page 7.
August 6, 2015
FN8760.0
Initial Release
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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Package Outline Drawing
L44.7x7B
44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 10/09
7.00
A
5.00 TYP
40X 0.50
B
6
PIN 1
INDEX
AREA
6
PIN #1
INDEX
1 AREA
44
34
7.00
33
5.20 ±0.1
EXP. DAP
23
(4X)
44X 0.25 4
0.10 M C A B
0.15
TOP VIEW
11
22
SIDE VIEW
12
5.20 ±0.1 EXP. DAP
44X 0.55 ±0.1
BOTTOM VIEW
( 6.65 )
SEE DETAIL "X"
( 5.20)
0.10 C
1.00 MAX
C
0.08 C
SIDE VIEW
( 6.65 )
( 5.20 )
( 40X 0.50)
C
(44X .25)
0.2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 44 X 0.75)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Complies to JEDEC MO220 VKKD-1.
either a mold or mark feature.
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