HD74AC165 Parallel-Load 8-bit Shift Register REJ03D0254–0200Z (Previous ADE-205-374 (Z)) Rev.2.00 Jul.16.2004 Description This 8-bit serial shift register shifts data from QA to QH when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock. Features • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC165FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74AC165RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement Parallel Inputs SL 1 16 VCC CP 2 Clock 15 Inhibit E 3 14 D F 4 13 C G 5 12 B H 6 11 A QH 7 10 SI GND 8 9 QH (Top view) Rev.2.00, Jul.16.2004, page 1 of 6 Parallel Inputs HD74AC165 Logic Symbol 15 1 Clock Inhibit SL 2 CP 10 SI 11 12 13 14 3 4 5 A F G H B C D E QH QH 9 7 6 Pin Names A to H SI CP SL Clock Inhibit QH, QH Parallel Inputs Serial Input Clock Input Shift Load Clock Inhibit Outputs Truth Table Inputs Clock Inhibit SL L H H H H X L L L H H : L : X : : CP X L X High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Rev.2.00, Jul.16.2004, page 2 of 6 SI X X H L X Parallel A ······ H a ······ h X X X X Internal Outputs QA QB a QAD H L QAD b QBO QAn QAn QBO Outputs QH h QHO QGn QCn QHO HD74AC165 Logic Diagram Parallel Inputs A B Preset QA S Clock QA R Clear SI Preset QB S Clock QB R Clear SL CP C D Preset QC S Clock QC R Clear E Preset QD S Clock QD R Clear F Preset QE S Clock QE R Clear Preset QF S Clock QF R Clear G Preset QG S Clock QG R Clear H Preset QH S Clock QH R Clear Output QH Output QH Clock Inhibit Absolute Maximum Ratings Item Symbol Ratings –0.5 to 7 Unit V Condition Supply voltage VCC DC input diode current IIK –20 20 mA mA VI = –0.5V VI = Vcc+0.5V DC input voltage DC output diode current VI IOK –0.5 to Vcc+0.5 –50 V mA VO = –0.5V DC output voltage VO 50 –0.5 to Vcc+0.5 mA V DC output source or sink current DC VCC or ground current per output pin IO ICC, IGND ±50 ±50 mA mA Storage temperature Tstg –65 to +150 °C VO = Vcc+0.5V Recommended Operating Conditions Item Symbol Ratings Unit Supply voltage VCC 2 to 6 V Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC VI, VO Ta 0 to VCC –40 to +85 V °C tr, tf 8 ns/V Rev.2.00, Jul.16.2004, page 3 of 6 Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC165 DC Characteristics Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics Item Symbol VCC (V)*1 Ta = +25°C CL = 50 pF Min Typ Max Ta = –40°C to +85°C CL = 50 pF Min Max Unit Maximum count frequency fmax 3.3 5.0 85 100 — — — — 70 90 — — MHz Propagation delay CP to QH or QH tPLH 3.3 5.0 1.0 1.0 11.0 8.0 17.5 11.5 1.0 1.0 20.5 13.5 ns Propagation delay CP to QH or QH tPHL 3.3 5.0 1.0 1.0 12.0 8.5 18.0 12.5 1.0 1.0 21.5 14.5 ns Propagation delay H to QH or QH tPLH 3.3 5.0 1.0 1.0 13.5 9.5 19.5 13.5 1.0 1.0 22.5 15.5 ns Propagation delay H to QH or QH tPHL 3.3 5.0 1.0 1.0 9.0 6.5 14.0 9.5 1.0 1.0 16.5 11.0 ns Propagation delay SL to QH or QH tPLH 3.3 5.0 1.0 1.0 11.5 8.5 20.5 14.0 1.0 1.0 23.5 16.0 ns Propagation delay SL to QH or QH tPHL 3.3 5.0 1.0 1.0 10.0 7.5 16.5 11.0 1.0 1.0 19.5 12.5 ns Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 4 of 6 HD74AC165 AC Operating Requirements Ta = +25°C CL = 50 pF Item Setup time, HIGH or LOW Symbol VCC (V)*1 Typ tsu 3.3 3.5 H to SL Hold time, HIGH or LOW th 5.0 3.3 H to SL Setup time, HIGH or LOW Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.0 6.0 ns Unit 2.5 –1.0 4.0 0.5 4.5 0.5 ns –0.5 1.0 0.5 3.5 0.5 4.0 ns tsu 5.0 3.3 Sin to CP Hold time, HIGH or LOW th 5.0 3.3 0.5 1.5 3.0 2.0 3.5 2.0 ns Sin to CP Setup time, HIGH or LOW tsu 5.0 3.3 1.0 3.0 2.0 5.0 2.0 6.0 ns SL to CP Hold time, HIGH or LOW th 5.0 3.3 2.0 –2.0 4.0 0.0 4.5 0.0 ns trec 5.0 3.3 –1.0 2.5 0.0 3.5 0.0 3.5 ns tw 5.0 3.3 2.0 3.0 3.0 5.5 3.0 7.0 ns 5.0 3.0 4.5 5.0 SL to CP Recovery time clock inhibit to CP Clock pulse width Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 5 of 6 Symbol CIN CPD Typ 4.5 50 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC165 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 6 of 6 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g Sales Strategic Planning Div. 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