RENESAS 3806_03

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
3806
Group
User’s Manual
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable, but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi
Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party’s rights, originating in the use of any
product data, diagrams, charts or circuit application examples contained in
these materials.
All information contained in these materials, including product data,
diagrams and charts, represent information on products at the time of
publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for any specific purposes, such as apparatus or systems for transportation,
vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export
control restrictions, they must be exported under a license from the
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the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 3806 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3806 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “SERIES MELPS
740 <SOFTWARE> USER’S MANUAL.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such
as hardware design or software development. Chapter 3 also includes necessary information for systems denelopment.
Be sure to refer to this chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting examples
of related registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, electric
characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which
are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B16]
B
0
Name
Function
b1 b0
Processor mode bits
1
0 0 : Single-chip mode
01:
1 0 : Not available
11:
0 : 0 page
1 : 1 page
At reset
R W
0
0
2
Stack page selection bit
3
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
0
✕
Fix this bit to “0.”
1
4
5
6
Main clock (XIN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN-XOUT selected
1 : XCIN-XCOUT selected
0
✻
✻
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
✻ ••••••Contents determined by option at reset release
Note 2. Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS
3806 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user’s manual is provided with
standard functions.
The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the
detailed functions of each group, refer to the related data book and user’s manual.
List of groups having the same functions
Group
As of September 1995
3800 group
3802 group
3806 group
3807 group
Pin
(Package type)
64 pin
• 64P4B
• 64P6N-A
• 64P6D-A
64 pin
• 64P4B
• 64P6N-A
80 pin
• 80P6N-A
• 80P6S-A
• 80P6D-A
80 pin
• 80P6N-A
Clock generating circuit
1 circuit
1 circuit
1 circuit
2 circuits
Timer
<8-bit>
Prescaler : 3
Timer : 4
<8-bit>
Prescaler : 3
Timer : 4
<8-bit>
Prescaler : 3
Timer : 4
Timer : 3
<16-bit>
Timer X/Y : 2
Timer A/B : 2
UART or
Clock synchronous ✕ 1
UART or
Clock synchronous ✕ 1
UART or
Clock synchronous ✕ 1
UART or
Clock synchronous ✕ 1
—
Clock synchronous ✕ 1
Clock synchronous ✕ 1
Clock synchronous ✕ 1
A-D converter
—
8-bit ✕ 8-channel
8-bit ✕ 8-channel
8-bit ✕ 13-channel
D-A converter
—
8-bit ✕ 2-channel
8-bit ✕ 2-channel
8-bit ✕ 4-channel
Function
<8-bit>
Serial I/O
Mask
ROM
Memory
type
One Time
PROM
EPROM
RAM
8K 16K 24K 32K
(Note 1)
(Note 1)
✽
(Note 1)
16K —
8K (Note
1)
8K
16K
(Note 1)
(Note 1)
24K
—
32K 12K 16K 24K 32K 48K
(Note 1)
32K
(Note 1)
(Note 1)
—
—
—
(Note 3)
(Note 3)
24K —
(Note 3)
48K
32K —
—
—
— 16K — 32K —
—
—
—
48K
— 24K — (Note
2)
16K
384
640 1024 384 384 512 1024 1024
512
384 384 512 640 384 384
(Note 1)
32K
(Note 2)
(Note 3)
PWM output
Remarks
Notes 1:
2:
3:
✽.
16K
Extended operating temperature version available
High-speed version available
Extended operating temperature version and High-speed version available
ROM expansion
16K
Real time port output
Analog comparator
Watchdog timer
Table of contents
Table of contents
CHAPTER 1. HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES ...................................................................................................................................... 1-2
APPLICATIONS .............................................................................................................................. 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK................................................................................................................... 1-4
PIN DESCRIPTION ........................................................................................................................ 1-5
PART NUMBERING ....................................................................................................................... 1-7
GROUP EXPANSION .................................................................................................................... 1-8
GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) ................. 1-10
GROUP EXPANSION (HIGH-SPEED VERSION) .................................................................... 1-11
FUNCTIONAL DESCRIPTION .................................................................................................... 1-12
Central Processing Unit (CPU) ............................................................................................ 1-12
Memory .................................................................................................................................... 1-16
I/O Ports .................................................................................................................................. 1-18
Interrupts ................................................................................................................................. 1-21
Timers ...................................................................................................................................... 1-23
Serial I/O ................................................................................................................................. 1-25
A-D Converter ......................................................................................................................... 1-31
D-A Converter ......................................................................................................................... 1-32
Reset Circuit ........................................................................................................................... 1-31
Clock Generating Circuit ....................................................................................................... 1-35
Processor Modes .................................................................................................................... 1-36
NOTES ON PROGRAMMING ..................................................................................................... 1-38
Processor Status Register .................................................................................................... 1-38
Interrupts ................................................................................................................................. 1-38
Decimal Calculations .............................................................................................................. 1-38
Timers ...................................................................................................................................... 1-38
Multiplication and Division Instructions ............................................................................... 1-38
Ports ......................................................................................................................................... 1-38
Serial I/O ................................................................................................................................. 1-38
A-D Converter ......................................................................................................................... 1-38
D-A Converter ......................................................................................................................... 1-38
Instruction Execution Time .................................................................................................... 1-38
Memory Expansion Mode and Microprocessor Mode ....................................................... 1-38
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-39
3806 GROUP USER'S MANUAL
i
Table of contents
ROM PROGRAMMING METHOD .............................................................................................. 1-39
FUNCTIONAL DESCRIPTION SUPPLEMENT .........................................................................
Interrupt ...................................................................................................................................
Timing After Interrupt .............................................................................................................
A-D Converter .........................................................................................................................
1-40
1-40
1-41
1-42
CHAPTER 2. APPLICATION
2.1 I/O port .....................................................................................................................................
2.1.1 Memory map of I/O port ...............................................................................................
2.1.2 Related registers ............................................................................................................
2.1.3 Handling of unused pins ...............................................................................................
2-2
2-2
2-3
2-4
2.2 Timer ......................................................................................................................................... 2-5
2.2.1 Memory map of timer .................................................................................................... 2-5
2.2.2 Related registers ............................................................................................................ 2-6
2.2.3 Timer application examples ........................................................................................ 2-11
2.3 Serial I/O ................................................................................................................................
2.3.1 Memory map of serial I/O ...........................................................................................
2.3.2 Related registers ..........................................................................................................
2.3.3 Serial I/O connection examples .................................................................................
2.3.4 Setting of serial I/O transfer data format .................................................................
2.3.5 Serial I/O application examples .................................................................................
2-23
2-23
2-24
2-30
2-32
2-33
2.4 A-D converter .......................................................................................................................
2.4.1 Memory map of A-D conversion ................................................................................
2.4.2 Related registers ..........................................................................................................
2.4.3 A-D conversion application example .........................................................................
2-53
2-53
2-54
2-56
2.5 Processor mode ...................................................................................................................
2.5.1 Memory map of processor mode ...............................................................................
2.5.2 Related register ............................................................................................................
2.5.3 Processor mode application examples ......................................................................
2-58
2-58
2-58
2-59
2.6 Reset ....................................................................................................................................... 2-66
2.6.1 Connection example of reset IC ................................................................................ 2-66
CHAPTER 3. APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-3
3.1.3 Electrical characteristics ................................................................................................ 3-4
3.1.4 A-D converter characteristics ....................................................................................... 3-4
3.1.5 D-A converter characteristics ....................................................................................... 3-5
3.1.6 Timing requirements and Switching characteristics .................................................. 3-6
3.1.7 Absolute maximum ratings (Extended operating temperature version) ................ 3-10
3.1.8 Recommended operating conditions(Extended operating temperature version) .. 3-10
ii
3806 GROUP USER'S MANUAL
Table of contents
3.1.9 Electrical characteristics (Extended operating temperature version) .................... 3-11
3.1.10 A-D converter characteristics (Extended operating temperature version) ........ 3-11
3.1.11 D-A converter characteristics (Extended operating temperature version) ........ 3-12
3.1.12 Timing requirements and Switching characteristics
(Extended operating temperature version) .......................................................... 3-13
3.1.13 Absolute maximum ratings (High-speed version) .................................................. 3-15
3.1.14 Recommended operating conditions(High-speed version) .................................... 3-15
3.1.15 Electrical characteristics (High-speed version) ...................................................... 3-16
3.1.16 A-D converter characteristics (High-speed version) ............................................ 3-16
3.1.17 D-A converter characteristics (High-speed version) ............................................ 3-17
3.1.18 Timing requirements and Switching characteristics (High-speed version) ......... 3-18
3.1.19 Timing diagram ........................................................................................................... 3-22
3.2 Standard characteristics .................................................................................................... 3-25
3.2.1 Power source current characteristic examples ........................................................ 3-25
3.2.2 Port standard characteristic examples ...................................................................... 3-26
3.2.3 A-D conversion standard characteristics ................................................................... 3-28
3.2.4 D-A conversion standard characteristics ................................................................... 3-29
3.3 Notes on use ........................................................................................................................ 3-30
3.3.1 Notes on interrupts ...................................................................................................... 3-30
3.3.2 Notes on the serial I/O1 ............................................................................................. 3-30
3.3.3 Notes on the A-D converter ....................................................................................... 3-31
3.3.4 Notes on the RESET pin ............................................................................................ 3-32
3.3.5 Notes on input and output pins ................................................................................. 3-32
3.3.6 Notes on memory expansion mode and microprocessor mode ............................ 3-33
3.3.7 Notes on built-in PROM .............................................................................................. 3-34
3.4 Countermeasures against noise ...................................................................................... 3-36
3.4.1 Shortest wiring length .................................................................................................. 3-36
3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line ............ 3-37
3.4.3 Wiring to analog input pins ........................................................................................ 3-38
3.4.4 Consideration for oscillator ......................................................................................... 3-38
3.4.5 Setup for I/O ports ....................................................................................................... 3-39
3.4.6 Providing of watchdog timer function by software .................................................. 3-39
3.5 List of registers ................................................................................................................... 3-41
3.6 Mask ROM ordering method ............................................................................................. 3-53
3.7 Mark specification form ..................................................................................................... 3-79
3.8 Package outline ................................................................................................................... 3-81
3.9 List of instruction codes ................................................................................................... 3-83
3.10 Machine Instructions ........................................................................................................ 3-84
3.11 SFR memory map .............................................................................................................. 3-94
3.12 Pin configuration ............................................................................................................... 3-95
3806 GROUP USER'S MANUAL
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig.
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Fig.
Fig.
1 Pin configuration of M38063M6-XXXFP .......................................................................... 1-2
2 Pin configuration of M38063M6-XXXGP and M38063M6AXXXHP ............................. 1-3
3 Functional block diagram .................................................................................................. 1-4
4 Part numbering ................................................................................................................... 1-7
5 Memory expansion plan .................................................................................................... 1-8
6 Memory expansion plan (Extended operating temperature version) ........................ 1-10
7 Memory expansion plan (High-speed version) ............................................................ 1-11
8 740 Family CPU register structure ................................................................................ 1-12
9 Register push and pop at interrupt generation and subroutine call ........................ 1-13
10 Structure of CPU mode register .................................................................................. 1-15
11 Memory map diagram .................................................................................................... 1-16
12 Memory map of special function register (SFR) ....................................................... 1-17
13 Port block diagram (single-chip mode) (1)................................................................. 1-19
14 Port block diagram (single-chip mode) (2)................................................................. 1-20
15 Interrupt control .............................................................................................................. 1-22
16 Structure of interrupt-related registers ........................................................................ 1-22
17 Structure of timer XY register ...................................................................................... 1-23
18 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-24
19 Block diagram of clock synchronous serial I/O1 ....................................................... 1-25
20 Operation of clock synchronous serial I/O1 function ............................................... 1-25
21 Block diagram of UART serial I/O ............................................................................... 1-26
22 Operation of UART serial I/O function ....................................................................... 1-27
23 Structure of serial I/O control registers ...................................................................... 1-28
24 Structure of serial I/O2 control register ...................................................................... 1-29
25 Block diagram of serial I/O2 function ......................................................................... 1-29
26 Timing of serial I/O2 function....................................................................................... 1-30
27 Structure of AD/DA control register ............................................................................ 1-31
28 Block diagram of A-D converter .................................................................................. 1-31
29 Block diagram of D-A converter .................................................................................. 1-32
30 Equivalent connection circuit of D-A converter ......................................................... 1-32
31 Example of reset circuit ................................................................................................ 1-33
32 Internal status of microcomputer after reset .............................................................. 1-33
33 Timing of reset ............................................................................................................... 1-34
34 Ceramic resonator circuit .............................................................................................. 1-35
35 External clock input circuit ........................................................................................... 1-35
36 Block diagram of clock generating circuit .................................................................................. 1-35
37 Memory maps in various processor modes ............................................................... 1-36
38 Structure of CPU mode register .................................................................................. 1-36
39 ONW function timing ...................................................................................................... 1-37
40 Programming and testing of One Time PROM version ........................................... 1-39
41 Timing chart after an interrupt occurs ........................................................................ 1-41
42 Time up to execution of the interrupt processing routine ....................................... 1-41
43 A-D conversion equivalent circuit ................................................................................ 1-43
44 A-D conversion timing chart ......................................................................................... 1-43
3806 GROUP USER’S MANUAL
i
List of figures
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port related registers ................................................................ 2-2
Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ...................................................... 2-3
Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ....................... 2-3
Fig.
Fig.
Fig.
Fig.
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Fig.
Fig.
Fig.
Fig.
Fig.
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Fig.
Fig.
Fig.
Fig.
2.2.1 Memory map of timer related registers ..................................................................... 2-5
2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y .............................................. 2-6
2.2.3 Structure of Timer 1 .................................................................................................... 2-6
2.2.4 Structure of Timer 2, Timer X, Timer Y ................................................................... 2-7
2.2.5 Structure of Timer XY mode register ........................................................................ 2-8
2.2.6 Structure of Interrupt request register 1 ................................................................... 2-9
2.2.7 Structure of Interrupt request register 2 ................................................................... 2-9
2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10
2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10
2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12
2.2.11 Setting of related registers [Clock function] ......................................................... 2-13
2.2.12 Control procedure [Clock function] ........................................................................ 2-14
2.2.13 Example of a peripheral circuit .............................................................................. 2-15
2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] .......... 2-15
2.2.15 Setting of related registers [Piezoelectric buzzer output] ................................... 2-16
2.2.16 Control procedure [Piezoelectric buzzer output] .................................................. 2-16
2.2.17 A method for judging if input pulse exists ........................................................... 2-17
2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18
2.2.19 Control procedure [Measurement of frequency]................................................... 2-19
2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] ........... 2-20
2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21
2.2.22 Control procedure [Measurement of pulse width] ................................................ 2-22
Fig.
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2.3.1 Memory map of serial I/O related registers ........................................................... 2-23
2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24
2.3.3 Structure of Serial I/O1 status register ................................................................... 2-24
2.3.4 Structure of Serial I/O1 control register .................................................................. 2-25
2.3.5 Structure of UART control register .......................................................................... 2-25
2.3.6 Structure of Baud rate generator ............................................................................. 2-26
2.3.7 Structure of Serial I/O2 control register .................................................................. 2-26
2.3.8 Structure of Serial I/O2 register ............................................................................... 2-27
2.3.9 Structure of Interrupt edge selection register ........................................................ 2-27
2.3.10 Structure of Interrupt request register 1 ............................................................... 2-28
2.3.11 Structure of Interrupt request register 2 ............................................................... 2-28
2.3.12 Structure of Interrupt control register 1 ................................................................ 2-29
2.3.13 Structure of Interrupt control register 2 ................................................................ 2-29
2.3.14 Serial I/O connection examples (1) ....................................................................... 2-30
2.3.15 Serial I/O connection examples (2) ....................................................................... 2-31
2.3.16 Setting of Serial I/O transfer data format ............................................................. 2-32
2.3.17 Connection diagram [Communication using a clock synchronous serial I/O] .. 2-33
2.3.18 Timing chart [Communication using a clock synchronous serial I/O] ............... 2-33
2.3.19 Setting of related registers at a transmitting side
[Communication using a clock synchronous serial I/O] ................................ 2-34
Fig. 2.3.20 Setting of related registers at a receiving side
[Communication using a clock synchronous serial I/O] ................................ 2-35
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3806 GROUP USER’S MANUAL
List of figures
Fig. 2.3.21 Control procedure at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-36
Fig. 2.3.22 Control procedure at a receiving side[Communication using a clock synchronous serial I/O] . 2-37
Fig. 2.3.23 Connection diagram [Output of serial data] ......................................................... 2-38
Fig. 2.3.24 Timing chart [Output of serial data] ...................................................................... 2-38
Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data] .......................... 2-39
Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data] ....................... 2-39
Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data] .................................... 2-40
Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data] .......................... 2-41
Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data] ....................... 2-41
Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data] .................................... 2-42
Fig. 2.3.31 Connection diagram
[Cyclic transmission or reception of block data between microcomputers] . 2-43
Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers] .......... 2-44
Fig. 2.3.33 Setting of related registers
[Cyclic transmission or reception of block data between microcomputers] . 2-44
Fig. 2.3.34 Control in the master unit ....................................................................................... 2-45
Fig. 2.3.35 Control in the slave unit ......................................................................................... 2-46
Fig. 2.3.36 Connection diagram [Communication using UART] ............................................ 2-47
Fig. 2.3.37 Timing chart [Communication using UART] ......................................................... 2-47
Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-49
Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART] ............................ 2-50
Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART] ......... 2-51
Fig. 2.3.41 Control procedure at a receiving side [Communication using UART] .............. 2-52
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
Memory map of A-D conversion related registers ................................................. 2-53
Structure of AD/DA control register ......................................................................... 2-54
Structure of A-D conversion register ....................................................................... 2-54
Structure of Interrupt request register 2 ................................................................. 2-55
Structure of Interrupt control register 2 .................................................................. 2-55
Connection diagram [Conversion of Analog input voltage] .................................. 2-56
Setting of related registers [Conversion of Analog input voltage] ...................... 2-56
Control procedure [Conversion of Analog input voltage] ...................................... 2-57
Fig.
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Fig.
Fig.
2.5.1 Memory map of processor mode related register ................................................. 2-58
2.5.2 Structure of CPU mode register .............................................................................. 2-58
2.5.3 Expansion example of ROM and RAM ................................................................... 2-59
2.5.4 Read-cycle (OE access, SRAM) .............................................................................. 2-60
2.5.5 Read-cycle (OE access, EPROM) ........................................................................... 2-60
2.5.6 Write-cycle (W control, SRAM)................................................................................. 2-61
2.5.7 Application example of the ONW function .............................................................. 2-62
2.5.8 Expansion example of ROM and RAM [High-speed version] .............................. 2-63
2.5.9 Read-cycle (OE access, SRAM) [High-speed version] ......................................... 2-64
2.5.10 Read-cycle (OE access, EPROM) [High-speed version] .................................... 2-64
2.5.11 Write-cycle (W control, SRAM) [High-speed version] ......................................... 2-65
Fig. 2.6.1 Example of Poweron reset circuit ............................................................................ 2-66
Fig. 2.6.2 RAM back-up system ................................................................................................. 2-66
3806 GROUP USER’S MANUAL
iii
List of figures
CHAPTER 3 APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
Circuit for measuring output switching characteristics (1) ................................... 3-21
Circuit for measuring output switching characteristics (2) ................................... 3-21
Timing diagram (in single-chip mode) ..................................................................... 3-22
Timing diagram (in memory expansion mode and microprocessor mode) (1) .. 3-23
Timing diagram (in memory expansion mode and microprocessor mode) (2) .. 3-24
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
Power source current characteristic example ........................................................
Power source current characteristic example (in wait mode) ..............................
Standard characteristic example of CMOS output port at P-channel drive(1) ..
Standard characteristic example of CMOS output port at P-channel drive(2) ..
Standard characteristic example of CMOS output port at N-channel drive(1) ..
Standard characteristic example of CMOS output port at N-channel drive(2) ..
A-D conversion standard characteristics .................................................................
D-A conversion standard characteristics .................................................................
3-25
3-25
3-26
3-26
3-27
3-27
3-28
3-29
Fig. 3.3.1 Structure of interrupt control register 2 .................................................................. 3-30
iv
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
Wiring for the RESET pin .........................................................................................
Wiring for clock I/O pins ...........................................................................................
Wiring for the VPP pin of the One Time PROM and the EPROM version ........
Bypass capacitor across the V SS line and the V CC line ......................................
Analog signal line and a resistor and a capacitor ................................................
Wiring for a large current signal line ......................................................................
Wiring to a signal line where potential levels change frequently .......................
Stepup for I/O ports ...................................................................................................
Watchdog timer by software .....................................................................................
3-36
3-37
3-37
3-37
3-38
3-38
3-38
3-39
3-39
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ....................................................
3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7, 8) .....................
3.5.3 Structure of Transmit/Receive buffer register ........................................................
3.5.4 Structure of Serial I/O1 status register ...................................................................
3.5.5 Structure of Serial I/O1 control register ..................................................................
3.5.6 Structure of UART control register ..........................................................................
3.5.7 Structure of Baud rate generator .............................................................................
3.5.8 Structure of Serial I/O2 control register ..................................................................
3.5.9 Structure of Serial I/O2 register ...............................................................................
3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y ..........................................
3.5.11 Structure of Timer 1 ................................................................................................
3.5.12 Structure of Timer 2, Timer X, Timer Y ...............................................................
3.5.13 Structure of Timer XY mode register ....................................................................
3.5.14 Structure of AD/DA control register .......................................................................
3.5.15 Structure of A-D conversion register .....................................................................
3.5.16 Structure of D-A 1 conversion, D-A 2 conversion register ................................
3.5.17 Structure of Interrupt edge selection register ......................................................
3.5.18 Structure of CPU mode register ............................................................................
3.5.19 Structure of Interrupt request register 1 ...............................................................
3.5.20 Structure of Interrupt request register 2 ...............................................................
3.5.21 Structure of Interrupt control register 1 ................................................................
3.5.22 Structure of Interrupt control register 2 ................................................................
3-41
3-41
3-42
3-42
3-43
3-43
3-44
3-44
3-45
3-45
3-46
3-46
3-47
3-48
3-48
3-49
3-49
3-50
3-51
3-51
3-52
3-52
3806 GROUP USER’S MANUAL
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description (1) ........................................................................................................... 1-5
2 Pin description (2) ........................................................................................................... 1-6
3 List of supported products ............................................................................................. 1-9
4 List of supported products (Extended operating temperature version) .................. 1-10
5 List of supported products (High-speed version) ...................................................... 1-11
6 Push and pop instructions of accumulator or processor status register ............... 1-13
7 Set and clear instructions of each bit of processor status register ....................... 1-14
8 List of I/O port functions .............................................................................................. 1-18
9 Interrupt vector addresses and priority ...................................................................... 1-21
10 Functions of ports in memory expansion mode and microprocessor mode ....... 1-36
11 Programming adapter .................................................................................................. 1-39
12 Interrupt sources, vector addresses and interrupt priority ..................................... 1-40
13 Change of A-D conversion register during A-D conversion .................................. 1-42
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins (in single-chip mode) .................................................... 2-4
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) ........ 2-4
Table 2.2.1 Function of CNTR 0/CNTR 1 edge switch bit .......................................................... 2-8
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values ...................... 2-48
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions ....................................................................... 3-3
3.1.3 Electrical characteristics ........................................................................................... 3-4
3.1.4 A-D converter characteristics .................................................................................. 3-4
3.1.5 D-A converter characteristics .................................................................................. 3-5
3.1.6 Timing requirements (1) ........................................................................................... 3-6
3.1.7 Timing requirements (2) ........................................................................................... 3-6
3.1.8 Switching characteristics (1) .................................................................................... 3-7
3.1.9 Switching characteristics (2) .................................................................................... 3-7
3.1.10 Timing requirements in memory expansion mode and microprocessor mode (1) ...................... 3-8
3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (1) .............. 3-8
3.1.12 Timing requirements in memory expansion mode and microprocessor mode (2) ...................... 3-9
3.1.13 Switching characteristics in memory expansion mode and microprocessor mode (2) .............. 3-9
3.1.14 Absolute maximum ratings (Extended operating temperature version) ......... 3-10
3.1.15 Recommended operating conditions (Extended operating temperature version) ..... 3-10
3.1.16 Electrical characteristics (Extended operating temperature version) ............. 3-11
3.1.17 A-D converter characteristics (Extended operating temperature version) ..... 3-11
3.1.18 D-A converter characteristics (Extended operating temperature version) ..... 3-12
3.1.19 Timing requirements (Extended operating temperature version) .................... 3-13
3.1.20 Switching characteristics (Extended operating temperature version) ............ 3-13
3806 GROUP USER’S MANUAL
i
List of tables
Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode
(Extended operating temperature version) ................................................... 3-14
Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode
(Extended operating temperature version) ................................................... 3-14
Table 3.1.23 Absolute maximum ratings (High-speed version) ............................................. 3-15
Table 3.1.24 Recommended operating conditions (High-speed version) ............................. 3-15
Table 3.1.25 Electrical characteristics (High-speed version) ................................................. 3-16
Table 3.1.26 A-D converter characteristics (High-speed version) ......................................... 3-16
Table 3.1.27 D-A converter characteristics (High-speed version) ......................................... 3-17
Table 3.1.28 Timing requirements (1) (High-speed version) ................................................. 3-18
Table 3.1.29 Timing requirements (2) (High-speed version) ................................................. 3-18
Table 3.1.30 Switching characteristics (1) (High-speed version) .......................................... 3-19
Table 3.1.31 Switching characteristics (2) (High-speed version) .......................................... 3-19
Table 3.1.32 Timing requirements in memory expansion mode and microprocessor mode (1)
(High-speed version) ....................................................................................... 3-20
Table 3.1.33 Switching characteristics in memory expansion mode and microprocessor mode (1)
(High-speed version) ....................................................................................... 3-20
Table 3.1.34 Timing requirements in memory expansion mode and microprocessor mode (2)
(High-speed version) ....................................................................................... 3-21
Table 3.1.35 Switching characteristics in memory expansion mode and microprocessor mode (2)
(High-speed version) ....................................................................................... 3-21
Table 3.3.1 Programming adapter ............................................................................................. 3-34
Table 3.3.2 Setting of programming adapter switch ............................................................... 3-34
Table 3.3.3 Setting of PROM programmer address ................................................................ 3-35
Table 3.5.1 Function of CNTR 0/CNTR 1 edge switch bit ........................................................ 3-47
ii
3806 GROUP USER’S MANUAL
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATIONS
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
DATA REQUIRED FOR MASK
ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION
DESCRIPTION
• Clock generating circuit ....................... Internal feedback resistor
The 3806 group is 8-bit microcomputer based on the 740 family
core technology.
The 3806 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, and D-A converters.
The various microcomputers in the 3806 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3806 group, refer to the section on group expansion.
(connect to external ceramic resonator or quartz-crystal)
• Memory expansion possible
Specification
Standard
(unit)
• Basic machine-language instructions ....................................... 71
• Memory size
•
•
•
•
•
•
•
0.5
0.5
0.4
Oscillation frequency
(MHz)
8
8
10
4.0 to 5.5
2.7 to 5.5
32
40
–40 to 85
–20 to 85
Power dissipation
(mW)
ROM ................................................................ 12 K to 48 K bytes
RAM ................................................................. 384 to 1024 bytes
Programmable input/output ports ............................................. 72
Interrupts .................................................. 16 sources, 16 vectors
Timers ............................................................................. 8 bit ✕ 4
Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized)
Serial I/O2 .................................... 8-bit ✕ 1 (Clock-synchronized)
A-D converter .................................................. 8-bit ✕ 8 channels
D-A converter .................................................. 8-bit ✕ 2 channels
High-speed
version
Minimum instruction
execution time
(µs)
Power source voltage 3.0 to 5.5
(V)
FEATURES
Extended operating
temperature version
32
Operating temperature –20 to 85
range
(°C)
APPLICATIONS
Office automation, VCRs, tuners, musical instruments, cameras,
air conditioners, etc.
41
42
43
45
44
47
46
50
49
48
53
52
51
54
55
57
58
56
59
60
61
62
65
40
66
39
67
38
68
37
69
36
70
35
71
34
33
72
M38063M6-XXXFP
73
74
32
31
75
30
76
29
77
28
78
27
79
80
26
24
21
22
23
19
20
18
17
15
16
14
13
11
12
10
9
8
7
6
5
3
4
P62/AN2
P61/AN1
P60/AN0
P77
P76
P75
P74
P73/SRDY2
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/INT4
P52/INT3
P51/INT2
P50
P47/SRDY1
P46/SCLK1
P45/TXD
P44/RXD
P43/INT1
1
25
2
P87
P86
P85
P84
P83
P82
P81
P80
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63 /AN3
63
64
P30
P31
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
PIN CONFIGURATION (TOP VIEW)
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 Pin configuration of M38063M6-XXXFP
1-2
3806 GROUP USER’S MANUAL
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40
P41
RESET
CNVSS
P42/INT0
HARDWARE
PIN CONFIGURATION
41
43
42
45
44
46
47
48
50
49
52
51
53
55
54
57
56
58
60
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
32
69
70
31
M38063M6-XXXGP
M38063M6AXXXHP
71
72
30
29
28
73
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
Vss
XOUT
XIN
P40
P41
20
18
19
17
16
15
14
13
P60/AN0
P77
P76
P75
P74
P73/SRDY2
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2
P56/DA1
P55/CNTR 1
P54/CNTR 0
P53/INT4
P52/INT3
P51/INT2
P50
P47/SRDY1
P46/SCLK1
P45/TXD
12
21
11
22
80
10
79
CNVSS
P42/INT0
P43/INT1
P44/RXD
9
23
8
78
7
RESET
24
6
25
77
5
76
4
26
3
27
75
1
74
2
P31
P30
P87
P86
P85
P84
P83
P82
P81
P80
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
59
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
PIN CONFIGURATION (TOP VIEW)
Package type : 80P6S-A/80P6D-A
80-pin plastic-molded QFP
Fig. 2 Pin configuration of M38063M6-XXXGP and M38063M6AXXXHP
3806 GROUP USER’S MANUAL
1-3
1-4
31
Fig. 3 Functional block diagram
3806 GROUP USER’S MANUAL
AV SS
VREF
I/O port P7
I/O port P8
I/O port P6
76 77 78 79 80 1 2 3
4 5 6 7 8 9 10 11
65 66 67 68 69 70 71 72
74 75
P6(8)
D-A
converter 2
(8)
ROM
P7(8)
(8)
A-D
converter
RAM
P8(8)
Serial I/O2
(8)
Clock output
XOUT
Clock generating circuit
30
Clock input
XIN
I/O port P5
12 13 14 15 16 17 18 19
P5(8)
D-A
converter 1
(8)
73
32
INT2
to
INT4
P4(8)
INT0
to
INT1
I/O port P4
20 21 22 23 24 25 28 29
Serial I/O1
(8)
PS
PC L
S
Y
X
A
Data bus
CPU
VCC
VSS
PC H
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)
I/O port P3
57 58 59 60 61 62 63 64
P1(8)
I/O port P2
I/O port P1
P0(8)
I/O port P0
49 50 51 52 53 54 55 56
Timer Y (8)
Timer X (8)
Timer 2 (8)
Timer 1 (8)
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
P2(8)
CNTR1
Prescaler Y (8)
Prescaler X (8)
Prescaler 12 (8)
26
CNVSS
CNTR0
P3(8)
27
RESET
Reset input
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1. Pin description (1)
Pin
Function
Name
Function except a port function
Power source
• Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)
(High-speed version : 2.7 V to 5.5 V)
CNVSS
CNVSS
• This pin controls the operation mode of the chip.
• Normally connected to VSS.
• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.
VREF
Analog reference
voltage
• Reference voltage input pin for A-D and D-A converters
AVSS
Analog power
source
• GND input pin for A-D and D-A converters
• Connect to VSS.
RESET
Reset input
• Reset input pin for active “L”
XIN
Clock input
XOUT
Clock output
• Input and output signals for the internal clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00 – P07
I/O port P0
P10 – P17
I/O port P1
P20 – P27
I/O port P2
P30 – P37
I/O port P3
P40, P41
I/O port P4
VCC
VSS
______
P42/INT0,
P43/INT1
•
•
•
•
•
•
8 bit CMOS I/O port
I/O direction register allows each pin to be individually programmed as either input or output.
At reset this port is set to input mode.
In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
CMOS compatible input level
CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• External interrupt input pin
P44/RXD,
P45/TXD,
P46/S
CLK1,
_____
P47/SRDY1
P50
• Serial I/O1 I/O pins
I/O port P5
P51/INT2 –
P53/INT4
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• External interrupt input pin
P54/CNTR0,
P55/CNTR1
• Timer X and Timer Y I/O pins
P56/DA1,
P57/DA2
• D-A conversion output pins
P60/AN0 –
P67/AN7
I/O port P6
• 8-bit CMOS I/O port with the same function as
port P0
• CMOS compatible input level
• CMOS 3-state output structure
3806 GROUP USER’S MANUAL
• A-D conversion input pins
1-5
HARDWARE
PIN DESCRIPTION
Table 2. Pin description (2)
Pin
Name
Function
Function except a port function
P70/SIN2,
P71/SOUT2,
P72/S
CLK2,
_____
P73/SRDY2
I/O port P7
• 8-bit I/O port with the same function as port P0
• CMOS compatible input level
• N-channel open-drain output structure
• Serial I/O2 I/O pins
I/O port P8
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
P74 – P77
P80 – P87
1-6
3806 GROUP USER’S MANUAL
HARDWARE
PART NUMBERING
PART NUMBERING
Product M3806 3 M 6 - XXX FP
Package type
FP : 80P6N-A package
GP : 80P6S-A package
FS : 80D0 package
ROM number
Omitted in some types.
Normally, using hyphen
When electrical characteristic, or division of quality
identification code using alphanumeric character
– : standard
D : Extended operating temperature version
A : High-speed version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
Fig. 4 Part numbering
3806 GROUP USER’S MANUAL
1-7
HARDWARE
GROUP EXPANSION
Currently supported products are listed below.
Table 3. List of supported products
As of September 1995
Product name
(P) ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
M38062M3-XXXFP
M38062M3-XXXGP
M38062M4-XXXFP
M38062M4-XXXGP
M38063M6-XXXFP
M38063E6-XXXFP
M38063E6FP
M38063M6-XXXGP
M38063E6-XXXGP
M38063E6GP
M38063E6FS
M38067M8-XXXFP
M38067M8-XXXGP
M38067MC-XXXFP
M38067EC-XXXFP
M38067ECFP
M38067MC-XXXGP
M38067EC-XXXGP
M38067ECGP
12288
(12158)
384
16384
(16254)
384
1-8
Package
80P6N-A
80P6S-A
80P6N-A
80P6S-A
80P6N-A
24576
(24446)
512
80P6S-A
32768
(32638)
1024
80D0
80P6N-A
80P6S-A
80P6N-A
49152
(49022)
1024
80P6S-A
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version
Mask ROM version
One Time PROM version
One Time PROM version
EPROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version
Mask ROM version
One Time PROM version
One Time PROM version
3806 GROUP USER’S MANUAL
(blank)
(blank)
(blank)
(blank)
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(2) Packages
80P6N-A ............................. 0.8 mm-pitch plastic molded QFP
80P6S-A ........................... 0.65 mm-pitch plastic molded QFP
80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
Mitsubishi plans to expand the 3806 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM
versions
ROM/PROM capacity ................................ 12 K to 48 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
Mass product
ROM size (bytes)
48K
M38067MC/EC
Mass product
32K
M38067M8
28K
Mass product
24K
M38063M6/E6
20K
Mass product
16K
M38062M4
Mass product
12K
M38062M3
8K
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Fig. 5 Memory expansion plan
3806 GROUP USER’S MANUAL
1-9
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(EXTENDED OPERATING TEMPERATURE VERSION)
(2) Packages
80P6N-A ............................. 0.8 mm-pitch plastic molded QFP
Mitsubishi plans to expand the 3806 group (extended operating
temperature version) as follows:
(1) Support for mask ROM version
ROM/PROM capacity ................................ 12 K to 48 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
New product
M38067ECD
Mass product
ROM size (bytes)
48K
M38067MCD
Mass product
32K
M38067M8D
28K
Mass product
24K
M38063M6D
20K
Mass product
16K
M38062M4D
Mass product
12K
M38062M3D
8K
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Fig. 6 Memory expansion plan (Extended operating temperature version)
Currently supported products are listed below.
Table 4. List of supported products (Extended operating temperature version)
Product name
(P) ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
M38062M3DXXXFP
M38062M4DXXXFP
M38063M6DXXXFP
M38067M8DXXXFP
M38067MCDXXXFP
M38067ECDXXXFP
M38067ECDFP
12288(12158)
16384(16254)
24576(24446)
32768(32638)
384
384
512
1024
49152(49022)
1024
1-10
As of September 1995
Package
80P6N-A
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
3806 GROUP USER’S MANUAL
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(HIGH-SPEED VERSION)
(2) Packages
80P6N-A ............................. 0.8 mm-pitch plastic molded QFP
80P6S-A ........................... 0.65 mm-pitch plastic molded QFP
80P6D-A ............................. 0.5 mm-pitch plastic molded QFP
80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
Mitsubishi plans to expand the 3806 group (high-speed version)
as follows:
(1) Support for mask ROM, One Time PROM, and EPROM
versions
ROM/PROM capacity ................................ 24 K to 48 K bytes
RAM capacity .............................................. 512 to 1024 bytes
Memory Expansion Plan
New product
ROM size (bytes)
48K
M38067MCA/ECA
New product
M38067M8A
32K
28K
New product
24K
M38063M6A
20K
16K
12K
8K
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Fig. 7 Memory expansion plan (High-speed version)
Currently supported products are listed below.
Table 5. List of supported products (High-speed version)
Product name
M38063M6AXXXFP
M38063M6AXXXGP
M38063M6AXXXHP
M38067M8AXXXFP
M38067M8AXXXGP
M38067MCAXXXFP
M38067ECAXXXFP
M38067ECAFP
M38067MCAXXXGP
M38067ECAXXXGP
M38067ECAGP
M38067ECAFS
(P) ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
24576
(24446)
512
32768
(32638)
1024
As of September 1995
Package
80P6N-A
80P6S-A
80P6D-A
80P6N-A
80P6S-A
80P6N-A
49152
(49022)
1024
80P6S-A
80D0
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
3806 GROUP USER’S MANUAL
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
Stack pointer (S)
The 3806 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
b7
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Fig. 9.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b0
Accumulator
A
b7
b0
Index Register X
X
b7
b0
Index Register Y
Y
b7
b0
Stack Pointer
S
b15
b7
PCH
b0
Program Counter
PCL
b7
b0
N V T B D I Z C
Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 8 740 Family CPU register structure
1-12
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt Request
(Note 1)
M(S) ← (PCH)
Execute JSR
(S) ← (S – 1)
M(S) ← (PCH)
Store Return Address
on Stack (Note 2)
M(S) ← (PCL)
(S) ← (S – 1)
(S) ← (S – 1)
M(S) ← (PC L)
M(S) ← (PS)
(S) ← (S – 1)
(S) ← (S – 1)
Subroutine
Store Contents of
Processor Status
Register on Stack
Interrupt
Service Routine
Execute RTS
Restore Return
Address
Store Return Address
on Stack (Note 2)
I Flag “0” to “1”
Fetch the Jump
Vector
Execute RTI
(S) ← (S + 1)
(S) ← (S + 1)
(PCL ) ← M(S)
(PS) ← M(S)
(S) ← (S + 1)
Restore Contents of
Processor Status
Register
(S) ← (S + 1)
(PCH) ← M(S)
(PC L) ← M(S)
(S) ← (S + 1)
Restore Return
Address
(PCH) ← M(S)
Notes 1 : The condition to enable the interrup t → Interrupt enable bit is “1”
Interrupt disable flag is “0”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Fig. 9 Register push and pop at interrupt generation and subroutine call
Table 6. Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
3806 GROUP USER’S MANUAL
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry
(C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should be
initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1”
to prevent other interrupts from interfering until the current interrupt is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”. Decimal correction is automatic in decimal mode. Only
the ADC and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status
register is pushed onto the stack with the break flag set to “1”.
The saved processor status is the only place where the break
flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O,
and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory
location 2 is stored in memory location 1. The address of
memory location 1 is specified by index register X, and the
address of memory location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds + 127 to
–128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit
7 of the memory location operated on by the BIT instruction is
stored in the negative flag.
Table 7. Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
—
SEI
SED
—
SET
—
—
Clear instruction
CLC
—
CLI
CLD
—
CLT
CLV
—
1-14
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
CPU mode register
The CPU mode register is allocated at address 003B16.
The CPU mode register contains the stack page selection bit.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (return “0” when read)
Fig. 10 Structure of CPU mode register
3806 GROUP USER’S MANUAL
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area
Zero page
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
The 256 bytes from addresses 000016 to 00FF 16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt vector area
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity
(bytes)
192
256
384
512
640
768
896
1024
Address
XXXX16
000016
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
SFR area
004016
RAM
Zero page
010016
XXXX16
Reserved area
044016
ROM area
Not used
ROM capacity
(bytes)
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
Address
YYYY16
Address
ZZZZ16
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ16
ROM
FF0016
FFDC16
FFFE16
FFFF16
Fig. 11 Memory map diagram
1-16
Special page
Interrupt vector area
3806 GROUP USER’S MANUAL
Reserved ROM area
HARDWARE
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
000916
Port P4 direction register (P4D)
002916
000A16
Port P5 (P5)
002A16
000B16
Port P5 direction register (P5D)
002B16
000C16
Port P6 (P6)
002C16
000D16
Port P6 direction register (P6D)
002D16
000E16
Port P7 (P7)
002E16
000F16
Port P7 direction register (P7D)
002F16
001016
Port P8 (P8)
003016
001116
Port P8 direction register (P8D)
003116
001216
003216
001316
003316
001416
003416
AD/DA control register (ADCON)
001516
003516
A-D conversion register (AD)
001616
003616
D-A1 conversion register (DA1)
001716
003716
D-A2 conversion register (DA2)
001816
Transmit/Receive buffer register (TB/RB)
003816
001916
Serial I/O1 status register (SIO1STS)
003916
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2(IREQ2)
001E16
001F16
Serial I/O2 register (SIO2)
(INTEDGE)
003E16
Interrupt control register 1(ICON1)
003F16
Interrupt control register 2(ICON2)
Fig. 12 Memory map of special function register (SFR)
3806 GROUP USER’S MANUAL
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
Direction registers
The 3806 group has 72 programmable I/O pins arranged in nine
I/O ports (ports P0 to P8). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 8. List of I/O port functions
Pin
Name
Input/Output
P00 – P07
Port P0
Input/output,
individual bits
P10 – P17
Port P1
Input/output,
individual bits
P20 – P27
Port P2
Input/output,
individual bits
P30 – P37
Port P3
Input/output,
individual bits
P40,P41
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK1,
_____
P47/SRDY1
P50
P51/INT2,
P52/INT3,
P53/INT4
P54/CNTR0,
P55/CNTR1
P56/DA1,
P57/DA2
P60/AN0 –
P67/AN7
Port P4
Port P5
Port P6
Input/output,
individual bits
Input/output,
individual bits
I/O Format
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
CMOS 3-state output
CMOS compatible
input level
P70/SIN2,
P71/SOUT2,
P72/SCLK2,
_____
P73/SRDY2
P74 – P77
Port P7
Input/output,
individual bits
N-channel open-drain output
CMOS compatible
input level
P80 – P87
Port P8
Input/output,
individual bits
CMOS 3-state output
CMOS compatible
input level
Non-Port Function
Related SFRs
Address low-order byte
output
CPU mode register
Address high-order
byte output
CPU mode register
Ref.No.
(1)
Data bus I/O
CPU mode register
Control signal I/O
CPU mode register
External interrupt input
Interrupt edge selection
register
Serial I/O1 function I/O
Serial I/O1 control
register
UART control register
External interrupt input
Interrupt edge selection
register
(2)
Timer X and Timer Y
function I/O
Timer XY mode register
(7)
D-A conversion output
AD/DA control register
(8)
A-D conversion input
Serial I/O2 function I/O
(2)
(3)
(4)
(5)
(6)
(1)
(9)
Serial I/O2 control
register
(10)
(11)
(12)
(13)
(14)
(1)
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
1-18
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
(1) Ports P0, P1, P2, P3, P40, P41, P50, P8
(2) Ports P42, P43, P51, P52, P53
Direction register
Data bus
Direction register
Port latch
Port latch
Data bus
Interrupt input
(3) Port P44
(4) Port P45
Serial I/O1 enable bit
Receive enable bit
P45/TXD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction register
Direction register
Data bus
Port latch
Port latch
Data bus
Serial I/O1 input
Serial I/O1output
(5) Port P46
(6) Port P47
Serial I/O1
synchronous clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction register
Data bus
Direction register
Port latch
Port latch
Data bus
Serial I/O1
external
clock input
Serial I/O1 clock output
(7) Ports P54, P55
Serial I/O1 ready output
(8) Ports P56, P57
Direction register
Data bus
Direction register
Port latch
Data bus
Pulse output mode
Timer output
Port latch
D-A conversion output
DA1 output enable bit (P5 6)
DA2 output enable bit (P5 7)
Counter input
Interrupt input
Fig. 13 Port block diagram (single-chip mode) (1)
3806 GROUP USER’S MANUAL
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
(9) Port P6
(10) Port P70
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O2 input
A-D conversion input
Analog input pin selection bit
(11) Port P71
(12) Port P72
Serial I/O2
transmit completion signal
Serial I/O2 port selection bit
Serial I/O2
synchronous clock selection bit
Serial I/O2 port selection bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O2 clock output
Serial I/O2 output
(13) Port P73
(14) Ports P74 – Port P77
Direction register
SRDY2 output enable bit
Data bus
Direction register
Data bus
Port latch
Serial I/O2 ready output
Fig. 14 Port block diagram (single-chip mode) (2)
1-20
3806 GROUP USER’S MANUAL
Port latch
Serial I/O2
external
clock input
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupts
Interrupt operation
Interrupts occur by sixteen sources: seven external, eight internal,
and one software.
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
Notes on use
When the active edge of an external interrupt (INT 0 to INT 4 ,
CNTR 0, or CNTR 1 ) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 9. Interrupt vector addresses and priority
Interrupt Source
Priority
Vector Addresses (Note 1)
Low
High
FFFC16
FFFD16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
Reset (Note 2)
1
INT0
2
FFFB16
FFFA16
INT1
3
FFF916
FFF816
Serial I/O1
reception
4
FFF716
FFF616
Serial I/O1
transmission
5
FFF516
FFF416
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
CNTR0
10
FFEB16
FFEA16
CNTR1
11
FFE916
FFE816
Serial I/O2
12
FFE716
FFE616
INT2
13
FFE516
FFE416
INT3
14
FFE316
FFE216
INT4
15
FFE116
FFE016
A-D converter
16
FFDF16
FFDE16
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1
data reception
At completion of serial I/O1
transfer shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O2
data transfer
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3806 GROUP USER’S MANUAL
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 15 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
Not used (returns “0” when read)
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
Not used (returns “0” when read)
b7
0 : Falling edge active
1 : Rising edge active
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16)
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Serial I/O2 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16)
b7
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
b0 Interrupt control register 2
(ICON2 : address 003F16)
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Serial I/O2 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers
1-22
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Timers
Timer 1 and Timer 2
The 3806 group has four timers: timer X, timer Y, timer 1, and
timer 2.
All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
b7
b0
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bit
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
Timer X and Timer Y
Timer X and Timer Y can each be selected in one of four operating
modes by setting the timer XY mode register.
Timer Mode
The timer counts f(XIN)/16 in timer mode.
Pulse Output Mode
Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of
the timer reach “00 16 ”, the signal output from the CNTR 0 (or
CNTR 1 ) pin is inverted. If the CNTR 0 (or CNTR 1 ) active edge
switch bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P54 ( or port P55) direction register to output mode.
Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except the timer counts signals input through the CNTR 0 or
CNTR1 pin.
Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts at the oscillation frequency divided by 16 while the CNTR0
(or CNTR 1) pin is at “H”. If the CNTR0 (or CNTR1 ) active edge
switch bit is “1”, the count continues during the time that the
CNTR0 (or CNTR1) pin is at “L”.
In all of these modes, the count can be stopped by setting the
timer X (timer Y) count stop bit to “1”. Ever y time a timer
underflows, the corresponding interrupt request bit is set.
Fig. 17 Structure of timer XY register
3806 GROUP USER’S MANUAL
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
Oscillator
Divider
f(XIN )
1/16
Pulse width
measurement
mode
P54/CNTR0 pin
CNTR0 active
edge switch bit
“0”
Timer X latch (8)
Prescaler X (8)
Timer X (8)
Timer mode
Pulse output
mode
Event
counter
mode
Timer X count stop bit
CNTR0 active
edge switch
bit
Q
“1”
“0”
Port P5 4
latch
Toggle flip- flop
Q
Timer X latch write pulse
Pulse output mode
Data bus
Pulse width
measurement
mode
CNTR1 active
edge switch bit
“0”
Prescaler Y latch (8)
Timer Y latch (8)
Prescaler Y (8)
Timer Y (8)
Timer mode
Pulse output
mode
Event
counter
mode
To timer Y interrupt
request bit
Timer Y count stop bit
To CNTR 1 interrupt
request bit
“1”
CNTR1 active
edge switch
bit
Q
“1”
Port P55
direction register
T
R
Pulse output
mode
P55/CNTR1 pin
To timer X interrupt
request bit
To CNTR 0 interrupt
request bit
“1”
Port P54
direction register
Prescaler X latch (8)
Port P5 5
latch
“0”
Toggle flip- flop
Q
T
R
Timer Y latch write pulse
Pulse output mode
Pulse output
mode
Data bus
Prescaler
12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt
request bit
To timer 1 interrupt
request bit
Fig. 18 Block diagram of timer X, timer Y, timer 1, and timer 2
1-24
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O
Serial I/O1
Clock synchronous serial I/O mode
Clock synchronous serial I/O1 mode can be selected by setting
the mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O1 control register
Address 0018 16
Receive buffer
Receive interrupt request (RI)
Receive shift register
P44/RXD
Address 001A 16
Receive buffer full flag (RBF)
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(X
IN)
XIN
Baud rate generator
P47/SRDY1
F/F
1/4
Address 001C 16
1/4
Clock control circuit
Falling-edge detector
Shift clock
P45/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 0019 16
Address 0018 16
Data bus
Fig. 19 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer (address 0018 16)
TBE = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 1
TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 20 Operation of clock synchronous serial I/O1 function
3806 GROUP USER’S MANUAL
1-25
HARDWARE
FUNCTIONAL DESCRIPTION
Asynchronous serial I/O (UART) mode
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can hold a character while the next character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
Data bus
Address 0018 16
Serial I/O1 control register Address 001A16
Receive buffer
OE
Character length selection bit
P44/RXD
STdetector
7 bits
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
1/16
8 bits
PE FE
SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronous clock selection bit
P46/SCLK1
f(XIN)
BRG count source selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C 16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
Transmit shift register
P45/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 21 Block diagram of UART serial I/O
1-26
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
Receive buffer read
signal
SP
D1
✽
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 22 Operation of UART serial I/O function
Serial I/O1 control register (SIO1CON) 001A16
The serial I/O control register consists of eight control bits for the
serial I/O function.
UART control register (UARTCON) 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
Serial I/O1 status register (SIO1STS) 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer, and
the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-
spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of
the Serial I/O Control Register) also clears all the status flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
Transmit buffer/Receive buffer register (TB/
RB) 001816
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
Baud rate generator (BRG) 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
3806 GROUP USER’S MANUAL
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b7
Serial I/O1 status register
(SIO1STS : address 0019 16)
b0
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
SRDY1 output enable bit (SRDY)
0: P4 7 pin operates as ordinaly I/O pin
1: P4 7 pin operates as S RDY1 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns "1" when read)
b7
b0
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P4 4 to P4 7 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P4 4 to P4 7 operate as serial I/O pins)
UART control register
(UARTCON : address 001B 16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return "1" when read)
Fig. 23 Structure of serial I/O control registers
1-28
Serial I/O1 control register
(SIO1CON : address 001A 16)
BRG count source selection bit (CSS)
0: f(X IN)
1: f(X IN)/4
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O2
b7
b0
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
Serial I/O2 control register
(SIO2CON : address 001D16)
Internal synchronous clock selection bits
b2 b1 b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
Serial I/O2 control register (SIO2CON) 001D16
The serial I/O2 control register contains seven bits which control
various serial I/O functions.
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
Not used (returns “0” when read)
Fig. 24 Structure of serial I/O2 control register
1/8
Divider
1/16
XIN
Internal synchronous
clock selection bits
1/32
Data bus
1/64
1/128
1/256
P73 latch
Serial I/O2 synchronous
clock selection bit
P73/SRDY2
SRDY2
"1"
Synchronization circuit
"1"
SRDY2 output enable bit
SCLK2
"0"
"0"
External clock
P72 latch
"0"
P72/SCLK2
"1"
Serial I/O2 port selection bit
Serial I/O counter 2 (3)
Serial I/O2
interrupt request
P71 latch
"0"
P71/SOUT2
"1"
Serial I/O2 port selection bit
P70/SIN2
Serial I/O shift register 2 (8)
Fig. 25 Block diagram of serial I/O2 function
3806 GROUP USER’S MANUAL
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output S OUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input S IN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the S OUT2 pin goes to high impedance after transfer completion.
Fig. 26 Timing of serial I/O2 function
1-30
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
[Comparator and Control circuit]
The functional blocks of the A-D converter are described below.
The comparator and control circuit compares an analog input voltage with the comparison voltage, then stores the result in the A-D
conversion register. When an A-D conversion is complete, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to 500 kHz or more during an A-D conversion.
[A-D conversion register]
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
[AD/DA control register]
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Bits 6 and 7 are used to control the output of the D-A converter.
b7
b0
AD/DA control register
(ADCON : address 0034 16)
Analog input pin selection bits
b2 b1 b0
0
0
0
0
1
1
1
1
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF into 256, and outputs the divided voltages.
[Channel selector]
0
0
1
1
0
0
1
1
0: P60/AN0
1: P61/AN1
0: P62/AN2
1: P63/AN3
0: P64/AN4
1: P65/AN5
0: P66/AN6
1: P67/AN7
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
The channel selector selects one of the ports P60/AN0 to P67/AN7,
and inputs the voltage to the comparator.
Not used (return "0" When read)
DA1 output enable bit
0: DA1 output disabled
1: DA1 output enabled
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
Fig. 27 Structure of AD/DA control register
Data bus
AD/DA control register
(Address 0034 16)
b7
b0
3
A-D control circuit
Channel selector
P60/AN0
P61/AN 1
P62/AN 2
P63/AN 3
P64/AN 4
P65/AN 5
P66/AN 6
P67/AN 7
Comparator
A-D interrupt request
A-D conversion register (Address 0035 16)
8
Resistor ladder
VREF AV SS
Fig. 28 Block diagram of A-D converter
3806 GROUP USER’S MANUAL
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
D-A Converter
The 3806 group has two internal D-A converters (DA1 and DA2)
with 8-bit resolutions.
The D-A converter is performed by setting the value in the D-A
conversion register. The result of D-A converter is output from the
DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (DA 1/P56 or DA2/P57) should be set to “0” (input status).
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
D-A1 conversion register (8)
Data bus
R-2R resistor ladder
V = VREF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
DA1 output enable bit
P56/DA1
D-A2 conversion register (8)
At reset, the D-A conversion registers are cleared to “00 16”, the DA
output enable bits are cleared to “0”, and the P56/DA1 and P5 7/
DA2 pins are set to input (high impedance).
The D-A output is not buffered, so connect an external buffer when
driving a low-impedance load.
Set VCC to 4.0 V or more when using the D-A converter.
R-2R resistor ladder
DA2 output enable bit
P57/DA2
Fig. 29 Block diagram of D-A converter
"0" DA1 output enable bit
R
P56/DA1
"1"
2R
R
2R
R
2R
R
2R
MSB
D-A1 conversion
register
"0"
2R
R
2R
R
2R
2R
2R
LSB
"1"
AV SS
VREF
Fig. 30 Equivalent connection circuit of D-A converter
1-32
R
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
______
To reset the microcomputer, the RESET
pin should be held at an
______
“L” level for 2 µs or more. Then the RESET pin is returned to an
“H” level (Note 1), reset is released. Internal operation does not
begin until after 8 to 13 XIN clock cycles are completed. After the
reset is completed, the program starts from the address contained
in address FFFD16 (high-order byte) and address FFFC16 (low-order byte).
Make sure that the reset input voltage is less than 0.8 V for VCC of
4.0 V (Note 2).
Note 1. The power source voltage should be between the following voltage.
• Between 3.0 V and 5.5 V for standard version
• Between 4.0 V and 5.5 V for extended operating temperature version
• Between 2.7 V and 5.5 V for high-speed version
Note 2. Reset input voltage is less than the following voltage.
• 0.6 V for VCC = 3.0 V
• 0.8 V for VCC = 4.0 V
• 0.54 V for VCC = 2.7 V
4.0V
Power source
0V
voltage
0.8V
Reset input
0V
voltage
VCC
1
5
M51953AL
3
RESET
4
0.1 µ F
VSS
3806 group
Address
(000116) • • •
0016
(2) Port P1 direction register
(000316) • • •
0016
(3) Port P2 direction register
(000516) • • •
0016
(4) Port P3 direction register
(000716) • • •
0016
(5) Port P4 direction register
(000916) • • •
0016
(6) Port P5 direction register
(000B16) • • •
0016
(7) Port P6 direction register
(000D16) • • •
0016
(8) Port P7 direction register
(000F16) • • •
0016
(9) Port P8 direction register
(001116) • • •
0016
(10) Serial I/O1 status register
(001916) • • • 1 0 0 0 0 0 0 0
(11) Serial I/O1 control register
(001A16) • • •
(12) UART control register
(001B16) • • • 1 1 1 0 0 0 0 0
(13) Serial I/O2 control register
(001D16) • • •
0016
(14) Prescaler 12
(002016) • • •
FF16
(15) Timer 1
(002116) • • •
0116
(16) Timer 2
(002216) • • •
FF16
(17) Timer XY mode register
(002316) • • •
0016
(18) Prescaler X
(002416) • • •
FF16
(19) Timer X
(002516) • • •
FF16
(20) Prescaler Y
(002616) • • •
FF16
(21) Timer Y
(002716) • • •
FF16
(22) AD/DA control register
(003416) • • • 0 0 0 0 1 0 0 0
(23) D-A1 conversion register
(003616) • • •
0016
(24) D-A2 conversion register
(003716) • • •
0016
(25) Interrupt edge selection register (003A16) • • •
0016
0016
(26) CPU mode register
(003B16) • • • 0 0 0 0 0 0 ✽ 0
(27) Interrupt request register 1
(003C16) • • •
0016
(28) Interrupt request register 2
(003D16) • • •
0016
(29) Interrupt control register 1
(003E16) • • •
0016
(30) Interrupt control register 2
(003F16) • • •
0016
(31) Processor status register
Fig. 31 Example of reset circuit
Register contents
(1) Port P0 direction register
(32) Program counter
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH) Contents of address FFFD 16
(PCL) Contents of address FFFC 16
Note. ✕ : Undefined
✽ : The initial values of CM 1 are determined by the level at the
CNVSS pin.
The contents of all other registers and RAM are undefined
after a reset, so they must be initialized by software.
Fig. 32 Internal status of microcomputer after reset
3806 GROUP USER’S MANUAL
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
XIN
φ
RESET
RESETOUT
(internal reset)
SYNC
Address
?
?
?
?
?
FFFC
FFFD
ADH, ADL
Reset address from the vector table
?
Data
XIN: 8 to 13 clock cycles
?
?
?
?
ADH
Notes 1: f(XIN) and f(φ) are in the relationship: f(X IN)=2 • f(φ).
2: A question mark (?) indicates an undefined status that depends on the previous status.
Fig. 33 Timing of reset
1-34
ADL
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. To supply a clock signal externally, input it to
the XIN pin and make the XOUT pin open.
When the STP status is released, prescaler 12 and timer 1 will
start counting and reset will not be released until timer 1
underflows, so set the timer 1 interrupt enable bit to “0” before the
STP instruction is executed.
Oscillation control
Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H”. Timer 1 is set to “0116” and prescaler 12 is set to “FF16”.
Oscillator restarts when an external interrupt is received, but the
internal clock φ remains at an “H” until timer 1 underflow.
This allows time for the clock circuit oscillation to stabilize.
If oscillator
is restarted by a reset, no wait time is generated, so
______
keep the RESET pin at an “L” level until oscillation has stabilized.
Wait Mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator itself does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or
WIT state, interrupt enable bits must be set to “1” before the STP
or WIT instruction is executed.
XIN
XOUT
CIN
COUT
Fig. 34 Ceramic resonator circuit
X IN
XOUT
Open
Vcc
External oscillation
circuit
Vss
Fig. 35 External clock input circuit
Interrupt request
Interrupt disable
flag (I)
S
Q
S
Q
Q
Reset
S
Reset
R
STP instruction
WIT
instruction
R
STP instruction
R
φ output
Internal clock φ
ONW pin
Single-chip mode
ONW
control
1/2
1/8
Prescaler 12
Timer 1
Rd
FF16
0116
Reset or STP instruction
Rf
XIN
X OUT
Fig. 36 Block diagram of clock generating circuit
3806 GROUP USER’S MANUAL
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
Processor Modes
Single-chip mode, memory expansion mode, and microprocessor
mode can be selected by changing the contents of the processor
mode bits CM 0 and CM 1 (bits 0 and 1 of address 003B 16 ). In
memory expansion mode and microprocessor mode, memory can
be expanded externally through ports P0 to P3. In these modes,
ports P0 to P3 lose their I/O port functions and become bus pins.
Table 10. Functions of ports in memory expansion mode and
microprocessor mode
Port Name
Function
Port P0
Outputs low-order byte of address.
Port P1
Outputs high-order byte of address.
Operates as I/O pins for data D7 to D0
Port P2
(including instruction codes).
P30 and P31 function only as output pins
(except that the port latch cannot be read).
_____
P32 is the ONW input pin.
_________
P33 is the RESETOUT output pin. (Note)
Port P3
P34 is the φ output pin.
P35 is the SYNC output pin.
___
P36 is the WR output pin, and P3 7 is the
___
RD output pin.
Note: If CNVSS is connected to V SS, the microcomputer goes to
single-chip
mode after a reset, so this pin cannot be used
_________
as the RESETOUT output pin.
000016
000816
000016
000816
SFR area
004016
SFR area
004016
Internal RAM
reserved area
044016
Internal RAM
reserved area
044016
✽
YYYY16
Internal ROM
FFFF16
FFFF16
Memory expansion mode
Microprocessor mode
The shaded areas are external memory areas.
✽ : YYYY16 is the start address of internal ROM.
Fig. 37 Memory maps in various processor modes
b7
b0
CPU mode register
(CPUM : address 003B 16)
Processor mode bits
b1 b0
Single-Chip Mode
Select this mode by resetting the microcomputer with CNVSS connected to VSS.
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available
Memory Expansion Mode
Select this mode by setting the processor mode bits to “01” in software with CNV SS connected to VSS. This mode enables external
memory expansion while maintaining the validity of the internal
ROM. Internal ROM will take precedence over external memory if
addresses conflict.
Microprocessor Mode
Select this mode by resetting the microcomputer with CNVSS connected to V CC, or by setting the processor mode bits to “10” in
software with CNVSS connected to VSS. In microprocessor mode,
the internal ROM is no longer valid and external memory must be
used.
1-36
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (return “0” when read)
Fig. 38 Structure of CPU mode register
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Bus control with memory expansion
_____
The 3806 group has a built-in ONW function to facilitate access to
external memory and I/O devices in memory expansion mode or
microprocessor mode.
_____
If an “L” level signal is input to the ONW pin when the CPU is in a
read or write state, the corresponding read or write cycle ___
is extended
by
one
cycle
of
φ.
During
this
extended
period,
the
RD
or
___
WR signal remains at “L”. This extension period is valid only for
writing to and reading from addresses 0000 16 to 0007 16 and
044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in
memory expansion mode, and only read and write cycles are extended.
Read cycle
Dummy cycle Write cycle
Read cycle Dummy cycle
Write cycle
φ
AD15 to AD0
RD
WR
ONW
✽
✽
✽
✽ : Period during which ONW input signal is received
During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations.
The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal
is received.
_____
Fig. 39 ONW function timing
3806 GROUP USER’S MANUAL
1-37
HARDWARE
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Processor Status Register
Serial I/O
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
In clock synchronous serial I/O, if the
receive side is using an ex_____
ternal clock and it is to output the SRDY1 _____
signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed. The SOUT2 pin from serial I/O2 goes to
high impedance after transmission is completed.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a
BBC or BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
The carry flag can be used to indicate whether a carry or borrow
has occurred. Initialize the carry flag before each calculation.
Clear the carry flag before an ADC and set the flag before an
SBC.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direction registers.
1-38
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that
f(XIN ) is at least 500 kHz during an A-D conver____
sion. (If the ONW pin has been set to “L”, the A-D conversion will
take twice as long to match the longer bus cycle, and so f(X IN)
must be at least 1 MHz.)
Do not execute the STP or WIT instruction during an A-D conversion.
D-A Converter
The accuracy of the D-A converter becomes poor rapidly under
the VCC = 4.0 V or less condition.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency
of the internal clock φ is half of the XIN frequency.
_____
When the ONW function is used in modes other than single-chip
mode, the frequency of the internal clock φ may be one fourth the
XIN frequency.
Memory Expansion Mode and Microprocessor Mode
Execute the LDM or STA instruction for writing to port P3 (address
000616) in memory expansion mode and microprocessor mode.
Set areas which can be read out and write to port P3 (address
0006 16 ) in a memory, using the read-modify-write instruction
(SEB, CLB).
3806 GROUP USER’S MANUAL
HARDWARE
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical
copies)
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Table 11. Programming adapter
Package
Name of Programming Adapter
80P6N-A
PCA4738F-80A
80P6S-A
PCA4738G-80A
80D0
PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 40 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 40 Programming and testing of One Time PROM version
3806 GROUP USER’S MANUAL
1-39
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
3806 group permits interrupts on the basis of 16
sources. It is vector interrupts with a fixed priority
system. Accordingly, when two or more interrupt
requests occur during the same sampling, the higherpriority interrupt is accepted first. This priority is
determined by hardware, but variety of priority
processing can be performed by software, using an
interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to “Table 12.”
Table 12. Interrupt sources, vector addresses and interrupt priority
Vector addresses
Priority
Interrupt sources
Remarks
High-order Low-order
1
2
Reset (Note)
INT0 interrupt
FFFD16
FFFB 16
FFFC 16
FFFA 16
3
INT1 interrupt
FFF916
FFF8 16
4
5
6
7
8
9
10
Serial I/O1 receive interrupt
Serial I/O1 transmit interrupt
Timer X interrupt
Timer Y interrupt
Timer 1 interrupt
Timer 2 interrupt
CNTR0 interrupt
FFF716
FFF516
FFF316
FFF116
FFEF 16
FFED16
FFEB16
FFF6 16
FFF4 16
FFF2 16
FFF0 16
FFEE 16
FFEC16
FFEA 16
11
CNTR1 interrupt
FFE9 16
FFE816
12
13
Serial I/O2 interrupt
INT2 interrupt
FFE7 16
FFE5 16
FFE616
FFE416
14
INT3 interrupt
FFE3 16
FFE216
15
INT4 interrupt
FFE1 16
FFE016
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
FFDE16
16
A-D conversion interrupt
FFDF16
FFDC16
17
BRK instruction interrupt
FFDD 16
Non-maskable software interrupt
Note: Reset functions in the same way as an interrupt with the highest priority.
1-40
3806 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
Figure 41 shows a timing chart after an interrupt
occurs, and Figure 42 shows the time up to execution of the interrupt processing routine.
The interrupt processing routine begins with the
machine cycle following the completion of the instruction that is currently in execution.
SYNC
RD
WR
Address bus
PC
Not used
Data bus
SYNC
BL, BH
AL, AH
SPS
S, SPS
S-1, SPS S-2, SPS
PCH PCL
BL
PS
BH
AL
AL, AH
AH
: CPU operation code fetch cycle
: Vector address of each interrupt
: Jump destination address of each interrupt
: “0016” or “0116”
Fig. 41 Timing chart after an interrupt occurs
Generation of interrupt request
Main routine
0 to 16 ✻ cycles
Start of interrupt processing
Waiting time for
post-processing
of pipeline
Stack push and
Vector fetch
2 cycles
Interrupt processing routine
5 cycles
7 to 23 cycles
(At performing 8.0 MHz, 1.75 µs to 5.75 µs)
✻ : at execution of DIV instruction (16 cycles)
Fig. 42 Time up to execution of the interrupt processing routine
3806 GROUP USER’S MANUAL
1-41
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowestorder bit of the A-D conversion register, an analog
value converts into a digital value.
A-D conversion completes at 50 clock cycles (12.5
µs at f(XIN) = 8.0 MHz) after it is started, and the
result of the conversion is stored into the A-D conversion register.
Concurrently with the completion of A-D conversion,
A-D conversion interrupt request occurs, so that the
AD conversion interrupt request bit is set to “1.”
A-D conversion is started by setting AD conversion
completion bit to “0.” During A-D conversion, internal operations are performed as follows.
1. After the start of A-D conversion, A-D conversion
register goes to “0016 .”
2. The highest-order bit of A-D conversion register
is set to “1,” and the comparison voltage Vref is
input to the comparator. Then, Vref is compared
with analog input voltage VIN.
3. As a result of comparison, when Vref < V IN, the
highest-order bit of A-D conversion register becomes “1.” When Vref > V IN, the highest-order
bit becomes “0.”
Relative formula for a reference voltage VREF of A-D converter and Vref
When n = 0
Vref = 0
Vref = VREF ✕ (n – 0.5)
256
n : the value of A-D converter (decimal numeral)
When n = 1 to 255
Table 13. Change of A-D conversion register during A-D conversion
Change of A-D conversion register
At start of conversion
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
Second comparison
✽
Third comparison
✽
1
1
✽
2
Value of comparison voltage (Vref)
0
VREF
2
VREF
2
VREF
2
✽1:
✽3:
✽5:
✽7:
1-42
A
A
A
A
result
result
result
result
of
of
of
of
the
the
the
the
VREF
512
±
VREF
±
VREF
4
4
~
~
~
~
After completion of eighth
comparison
–
A result of A-D conversion
✽
1
✽
2
✽
first comparison
third comparison
fifth comparison
seventh comparison
3
✽
4
✽
✽2:
✽4:
✽6:
✽8:
5
A
A
A
A
✽
6
✽
result
result
result
result
7
✽
of
of
of
of
8
the
the
the
the
second comparison
fourth comparison
sixth comparison
eighth comparison
3806 GROUP USER’S MANUAL
–
VREF
512
VREF
±
8
–
VREF
512
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 43 shows A-D conversion equivalent circuit, and Figure 44 shows A-D conversion timing
chart.
VCC
VSS
about 2 k
VCC AVSS
VIN
AN0
Sampling
clock
AN1
C
AN2
Chopper amplifier
AN3
AN4
AN5
AN6
A-D conversion register
AN7
b2 b1 b0
A-D conversion interrupt request
AD/DA control register
Vref
VREF
Build-in
D-A converter
Reference
clock
AVSS
Fig. 43 A-D conversion equivalent circuit
Write signal for AD/DA control register
50 cycles
AD conversion completion bit
Sampling clock
Fig. 44 A-D conversion timing chart
3806 GROUP USER’S MANUAL
1-43
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
MEMORANDUM
1-44
3806 GROUP USER’S MANUAL
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
I/O port
Timer
Serial I/O
A-D converter
Processor mode
Reset
APPLICATION
2.1 I/O port
2.1 I/O port
2.1.1 Memory map of I/O port
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
Port P3 direction register (P3D)
000816
Port P4 (P4)
000916
Port P4 direction register (P4D)
000A16
Port P5 (P5)
000B16
Port P5 direction register (P5D)
000C16
Port P6 (P6)
000D16
Port P6 direction register (P6D)
000E16
Port P7 (P7)
000F16
Port P7 direction register (P7D)
001016
Port P8 (P8)
001116
Port P8 direction register (P8D)
Fig. 2.1.1 Memory map of I/O port related registers
2-2
3806 GROUP USER’S MANUAL
APPLICATION
2.1 I/O port
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016]
B
Name
0 Port Pi0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16, 1116]
B
Function
Name
At reset
R W
0 Port Pi direction register
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0
✕
1
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0
✕
0
✕
0
✕
0
✕
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
✕
0
✕
0
✕
2
3
4
5
6
7
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
3806 GROUP USER’S MANUAL
2-3
APPLICATION
2.1 I/O port
2.1.3 Handling of unused pins
Table 2.1.1 Handling of unused pins (in single-chip mode)
Handling
Name of Pins/Ports
P0, P1, P2, P3, P4, P5, P6, P7, P8
VREF
AV SS
XOUT
• Set to the input mode and connect to V CC or V SS through a
resistor of 1 k to 10 k .
• Set to the output mode and open at “L” or “H.”
Connect to V SS(GND) or open.
Connect to V SS(GND).
Open (only when using external clock).
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode)
Name of Pins/Ports
P3 0, P31
P4, P5, P6, P7, P8
VREF
____
ONW
_________
RESET OUT
SYNC
AV SS
XOUT
2-4
Handling
Open
• Set to the input mode and connect to V CC or V SS through a
resistor of 1 k to 10 k .
• Set to the output mode and open at “L” or “H.”
Connect to V SS(GND) or open.
Connect to V CC through a resistor of 1 k to 10 k .
Open
Open
Open
Connect to V SS(GND).
Open (only when using external clock).
3806 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
2.2 Timer
2.2.1 Memory map of timer
002016
Prescaler 12 (PRE12)
002116
Timer 1 (T1)
002216
Timer 2 (T2)
002316
Timer XY mode register (TM)
002416
Prescaler X (PREX)
002516
Timer X (TX)
002616
Prescaler Y (PREY)
002716
Timer Y (TY)
~
~
~
~
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of timer related registers
3806 GROUP USER’S MANUAL
2-5
APPLICATION
2.2 Timer
2.2.2 Related registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
[Address : 2016, 2416, 2616]
B
0
1
Function
●
●
●
2
The count value of each prescaler is set.
The value set in this register is written to both the prescaler and
the prescaler latch at the same time.
When the prescaler is read out, the value (count value) of the
prescaler is read out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116]
B
0
●
●
1
2
●
Function
At reset
The count value of the Timer 1 is set.
The value set in this register is written to both the Timer 1 and
the Timer 1 latch at the same time.
When the Timer 1 is read out, the value (count value) of the
Timer 1 is read out.
1
0
3
0
4
0
5
0
6
0
7
0
Fig. 2.2.3 Structure of Timer 1
2-6
0
3806 GROUP USER’S MANUAL
R W
APPLICATION
2.2 Timer
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX), Timer Y (TY)
[Address : 2216, 2516, 2716]
B
0
Function
●
●
1
2
●
The count value of each timer is set.
The value set in this register is written to both the Timer and the
Timer latch at the same time.
When the Timer is read out, the value (count value) of the Timer
is read out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y
3806 GROUP USER’S MANUAL
2-7
APPLICATION
2.2 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 23 16]
Name
B
0 Timer X operating mode
1
2 CNTR 0 active edge switch
bit
Timer
X count stop bit
3
4 Timer Y operating mode
5
6 CNTR 1 active edge switch
bit
7 Timer Y count stop bit
Function
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer X (refer to Table 2.2.1).
0 : Count start
1 : Count stop
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer Y (refer to Table 2.2.1).
0 : Count start
1 : Count stop
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.5 Structure of Timer XY mode register
Table. 2.2.1 Function of CNTR 0/CNTR 1 edge switch bit
Operating mode of
Timer X/Timer Y
Timer mode
Function of CNTR 0 /CNTR1 edge switch bit (bits 2 and 6)
“0”
“1”
Pulse output mode
“0”
“1”
Event counter mode
“0”
“1”
Pulse width measurement mode
“0”
“1”
2-8
• Generation of CNTR0/CNTR 1 interrupt request : Falling
(No effect on timer count)
• Generation of CNTR0/CNTR1 interrupt request : Rising
(No effect on timer count)
• Start of pulse output : From “H” level
• Generation of CNTR0/CNTR 1 interrupt request : Falling
• Start of pulse output : From “L” level
• Generation of CNTR0/CNTR1 interrupt request : Rising
• Timer X/Timer Y : Count of rising edge
• Generation of CNTR0/CNTR 1 interrupt request : Falling
•
•
•
•
•
•
edge
edge
edge
edge
edge
Timer X/Timer Y : Count of falling edge
Generation of CNTR0/CNTR1 interrupt request : Rising edge
Timer X/Timer Y : Measurement of “H” level width
Generation of CNTR0/CNTR 1 interrupt request : Falling edge
Timer X/Timer Y : Measurement of “L” level width
Generation of CNTR0/CNTR1 interrupt request : Rising edge
3806 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C 16]
Function
Name
B
At reset
R W
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0
✻
3 Serial I/O1 transmit interrupt
0 : No interrupt request
1 : Interrupt request
0
✻
4 Timer X interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
✻ “0” is set by software, but not “1.”
0
✻
0 INT0 interrupt request bit
1 INT 1 interrupt request bit
2 Serial I/O1 receive interrupt
request bit
request bit
bit
5 Timer Y interrupt request
bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
Fig. 2.2.6 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D 16]
Name
B
0 CNTR 0 interrupt request bit
1 CNTR 1 interrupt request bit
2 Serial I/O2 interrupt request
bit
3 INT 2 interrupt request bit
4 INT 3 interrupt request bit
5 INT 4 interrupt request bit
6 AD conversion interrupt
request bit
Function
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
At reset
R W
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✕
✻ “0” is set by software, but not “1.”
Fig. 2.2.7 Structure of Interrupt request register 2
3806 GROUP USER’S MANUAL
2-9
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
Name
B
0 INT0 interrupt enable bit
1 INT 1 interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
Serial
I/O1 transmit interrupt
3
enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.8 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name
B
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
2 Serial I/O2 interrupt enable bit 0 : Interrupt disabled
0
3 INT 2 interrupt enable bit
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
4 INT 3 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
5 INT 4 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 CNTR 0 interrupt enable bit
1 CNTR 1 interrupt enable bit
6 AD conversion interrupt
enable bit
7 Fix this bit to “0.”
Fig. 2.2.9 Structure of Interrupt control register 2
2-10
At reset
3806 GROUP USER’S MANUAL
0
0
0
R W
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2)
The Timer count stop bit is set to “0” after setting a count value to a timer. Then a timer interrupt
request occurs after a certain period.
[Use] • Generation of an output signal timing
• Generation of a waiting time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2)
The value of a timer latch is automatically written to a corresponding timer every time a timer
underflows, and each cyclic timer interrupt request occurs.
[Use] • Generation of cyclic interrupts
• Clock function (measurement of 250m second) → Application example 1
• Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X, Timer Y)
The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode).
[Use] • A piezoelectric buzzer output → Application example 2
• Generation of the remote-control carrier waveforms
[Function 4] Count of External pulse (Timer X, Timer Y)
External pulses input to the CNTR pin are selected as a timer count source (Event counter
mode).
[Use] • Measurement of frequency → Application example 3
• Division of external pulses.
• Generation of interrupts in a cycle based on an external pulse.
(count of a reel pulse)
[Function 5] Measurement of External pulse width (Timer X, Timer Y)
The “H” or “L” level width of external pulses input to CNTR pin is measured (Pulse width
measurement mode).
[Use] • Measurement of external pulse frequency (Measurement of pulse width of FG pulse✽ generated by motor) → Application example 4
• Measurement of external pulse duty (when the frequency is fixed)
✽FG pulse : Pulse used for detecting the motor speed to control the motor speed.
3806 GROUP USER’S MANUAL
2-11
APPLICATION
2.2 Timer
(2) Timer application example 1 : Clock function (measurement of 250 ms)
Outline : The input clock is divided by a timer so that the clock counts up every 250 ms.
Specifications : • The clock f(X IN ) = 4.19 MHz (222 Hz) is divided by a timer.
• The clock is counted at intervals of 250 ms by the Timer X interrupt.
Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figure 2.2.11 shows a
setting of related registers, and Figure 2.2.12 shows a control procedure.
f(XIN) =
4.19 MHz
Fixed
Prescaler X
Timer X
1/16
1/256
1/256
Timer X interrupt request bit
The clock is divided by 4 by software.
0 or 1
1/4
250 ms
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function]
2-12
3806 GROUP USER’S MANUAL
1 second
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316)
b7
b0
1
TM
0 0
Timer X operating mode bits : Timer mode
Timer X count stop bit : Count stop
Set to “0” at starting count.
Prescaler X (Address : 2416)
b7
PREX
b0
255
Timer X (Address : 2516)
b7
TX
b0
Set “division ratio – 1”
255
Interrupt control register 1 (Address : 3E16)
b7
b0
1
ICON1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7
IREQ1
b0
0
Timer X interrupt request bit
(becomes “1” every 250 ms)
Fig. 2.2.11 Setting of related registers [Clock function]
3806 GROUP USER’S MANUAL
2-13
APPLICATION
2.2 Timer
Control procedure :
Figure 2.2.12 shows a control procedure.
●
RESET
Initialization
SEI
X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
●
....
XXXX1X002
(Address : 2316)
TM
1
ICON1 (Address : 3E16), bit4
....
PREX (Address : 2416)
(Address : 2516)
TX
●
256 – 1
256 – 1
....
TM
●
(Address : 2316), bit3
0
All interrupts : Disabled
Timer X : Timer mode
Timer X interrupt : Enabled
....
●
Set “division ratio – 1” to the Prescaler X
and Timer X.
●
Timer X count : Operating
Interrupts : Enabled
●
CLI
●
Main processing
....
[Processing for completion of setting clock]
(Note 1)
PREX (Address : 2416)
(Address : 2516)
TX
IREQ1 (Address : 3C16), bit4
When restarting the clock from zero
second after completing to set the
clock, reset timers.
Note 1: This processing is performed only
at completing to set the clock.
256 – 1
256 – 1
0
~
~
Timer X interrupt processing routine
Note 2: When using the Index X mode flag (T).
Note 3: When using the Decimal mode flag (D).
CLT (Note 2)
CLD (Note 3)
Push register to stack
●
Y
Clock stop?
Push the register used in the interrupt
processing routine into the stack.
●
Check if the clock has already been set.
●
Count up the clock.
●
Pop registers which is pushed to stack
N
Clock count up (1/4 second-year)
Pop registers
RTI
Fig. 2.2.12 Control procedure [Clock function]
2-14
3806 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
(3) Timer application example 2 : Piezoelectric buzzer output
Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer
output.
Specifications : • The rectangular waveform resulting from dividing clock f(XIN) = 4.19 MHz into about
2 kHz (2048 Hz) is output from the P5 4/CNTR 0 pin.
• The level of the P5 4/CNTR0 pin fixes to “H” while a piezoelectric buzzer output is
stopped.
Figure 2.2.13 shows an example of a peripheral circuit, and Figure 2.2.14 shows a connection of the
timer and setting of the division ratio.
The “H” level is output while a piezoelectric buzzer output is stopped.
CNTR0 output
3806 group
P54/CNTR0
PiPiPi....
244 µs
244 µs
Set a division ratio so that the underflow output cycle of the Timer X becomes this value.
Fig. 2.2.13 Example of a peripheral circuit
f(XIN) = 4.19 MHz
Fixed
Prescaler X
Timer X
Fixed
1/16
1
1/64
1/2
CNTR0
Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
3806 GROUP USER’S MANUAL
2-15
APPLICATION
2.2 Timer
Timer XY mode register (Address : 23 16)
b7
b0
TM
1 0 0 1
Timer X operating mode bits : Pulse output mode
CNTR 0 active edge switch bit : Output from the “H” level
Timer X count stop bit : Count stop
Set to “0” at starting to count.
Timer X (Address : 25 16)
b7
TX
b0
63
Set “division ratio – 1”
Prescaler X (Address : 24 16)
b7
PREX
b0
0
Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]
Control procedure :
Figure 2.2.16 shows a control procedure.
RESET
●X
....
Initialization
P5
P5D
: This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
1
(Address : 0A 16), bit4
XXX1XXXX 2
(Address : 0B 16)
....
0
ICON1 (Address : 3E 16), bit4
XXXX10012
(Address : 23 16)
TM
TX
(Address : 25 16)
PREX (Address : 24 16)
●
●
....
64 – 1
1–1
●
Timer X interrupts : Disabled
The CNTR 0 output is stopped at this point (stop
outputting a piezoelectric buzzer).
Set “division ratio – 1” to the Prescaler X and
Timer X.
Main processing
●
Output unit
A piezoelectric buzzer
is requested?
Y
The piezoelectric buzzer request occured in the
main processing is processed in the output unit.
N
TM (Address : 23 16), bit3
TX (Address : 25 16)
1
64 –1
During stopping outputting a piezoelectric buzzer
TM (Address : 23 16), bit3
During outputting a piezoelectric buzzer
Fig. 2.2.16 Control procedure [Piezoelectric buzzer output]
2-16
0
3806 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
(4) Timer application example 3 : Measurement of frequency
Outline : The following two values are compared for judging if the frequency is within a certain range.
• A value counted a pulse which is input to P55 /CNTR 1 pin by a timer.
• A referance value
Specifications : • The pulse is input to the P5 5 /CNTR1 pin and counted by the Timer Y.
• A count value is read out at the interval of about 2 ms (Timer 1 interrupt interval
: 244 µs ✕ 8). When the count value is 28 to 40, it is regarded the input pulse
as a valid.
• Because the timer is a down-counter, the count value is compared with 227 to 215✽ .
✽ 227 to 215 = 255 (initialized value of counter) – 28 to 40 (the number of valid
value).
Figure 2.2.17 shows a method for judging if input pulse exists, and Figure 2.2.18 shows a setting of
related registers.
Input pulse
••••
71.4 µs or more
(14 kHz or less)
••••
71.4 µs
(14 kHz)
Invalid
2 ms
71.4 µs
••••
50 µs
(20 kHz)
Valid
= 28 counts
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
Fig 2.2.17 A method for judging if input pulse exists
3806 GROUP USER’S MANUAL
2-17
APPLICATION
2.2 Timer
Timer XY mode register (Address : 23 16)
b7
TM
b0
1 1 1 0
Timer Y operating mode bit : Event counter mode.
CNTR 1 active edge switch bit : Count at falling edge
Timer Y count stop bit : Count stop
Set to “0” at starting to count.
Prescaler 12 (Address : 20 16)
b7
b0
PRE12
63
Timer 1 (Address : 21 16)
b7
b0
T1
Set “division ratio – 1”
7
Prescaler Y (Address : 26 16)
b7
b0
0
PREY
Timer Y (Address : 27 16)
b7
b0
255
TY
Set “255” to this register immediately before
counting pulse.
(After a certain time, this value is decreased by
the number of input pulses)
Interrupt control register 1 (Address : 3E 16)
b7
ICON1
b0
1 0
Timer Y interrupt enable bit : Interrupt disabled
Timer 1 interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C 16)
b7
IREQ1
b0
0
Judgment of Timer Y interrupt request bit
(When this bit is set to “1” at reading out
the count value of the Timer Y (address : 27 16),
256 pulses or more are input (at setting 255 to
the Timer Y).)
Fig. 2.2.18 Setting of related registers [Measurement of frequency]
2-18
3806 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Control procedure :
Figure 2.2.19 shows a control procedure.
● X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
●
All interrupts : Disabled
SEI
....
(Address : 23 16)
1110XXXX 2
TM
PRE12 (Address : 20 16)
64–1
(Address : 21 16)
T1
8–1
PREY (Address : 26 16)
1–1
(Address : 27 16)
TY
256–1
ICON1 (Address : 3E 16), bit6
1
●
●
●
....
TM
(Address : 23 16), bit7
0
●
....
●
Timer Y : Event counter mode
(Count at falling edge of pulse input from CNTR 1 pin)
Set the division ratio so that the Timer 1 interrupt
occurs every 2 ms.
Timer 1 interrupt : Enabled
Timer Y count : Start
Interrupts : Enabled
CLI
~
~
Timer 1 interrupt processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
1
●
IREQ1 (Address : 3C 16), bit5?
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Push the register used in the interrupt
processing routine into the stack
When the count value is 256 or more, the
processing is performed as out of range.
0
●
(A)
TY (Address : 27 16)
●
Read the count value.
Store the count value in the accumulator (A).
In range
214 < (A) < 228?
●
Out of range
Fpulse
●
Fpulse
0
●
(Address : 27 16)
TY
IREQ1 (Address : 3C 16), bit5
256 – 1
0
●
Compare the count value read with the
reference value.
Store the comparison result in flag Fpulse.
1
Initialize the count value.
Set the Timer Y interrupt request bit to “0.”
Processing for a result of judgment
Pop registers
●
Pop registers which is pushed to stack.
RTI
Fig. 2.2.19 Control procedure [Measurement of frequency]
3806 GROUP USER’S MANUAL
2-19
APPLICATION
2.2 Timer
(5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor
Outline : The “H” level width of a pulse input to the P5 4 /CNTR 0 pin is counted by Timer X. An
underflow is detected by Timer X interrupt and an end of the input pulse “H” level is
detected by CNTR 0 interrupt.
Specifications : • The “H” level width of FG pulse input to the P54/CNTR0 pin is counted by Timer
X.
(Example : When the clock frequency is 4.19 MHz, the count source would be 3.8
µs that is obtained by dividing the clock frequency by 16. Measurement can be made up to 250 ms in the range of FFFF16 to 0000 16.)
Figure 2.2.20 shows a connection of the timer and a setting of the division ratio, and Figure 2.2.21
shows a setting of related registers.
f(XIN) = 4.19 MHz
Fixed
Prescaler X
Timer X
1/16
1/256
1/256
Timer X interrupt request bit
0 or 1
250 ms
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width]
2-20
3806 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Timer XY mode register (Address : 23 16)
b7
b0
TM
1 0
1 1
Timer X operating mode bits : Pulse width
measurement mode
CNTR 0 active edge switch bit : Count “H” level width
Timer X count stop bit : Count stop
Set to “0” at starting to count.
Prescaler X (Address : 24 16)
b7
PREX
b0
255
Timer X (Address : 25 16)
b7
TX
Set “division ratio – 1”
b0
255
Interrupt control register 1 (Address : 3E 16)
b7
b0
1
ICON1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register (Address : 3C 16)
b7
b0
0
IREQ1
Timer X interrupt request bit
(This bit is set to “1” at underflow of Timer X.)
Interrupt control register 2 (Address : 3F 16)
b7
b0
1
ICON2
CNTR 0 interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D 16)
b7
IREQ2
b0
0
CNTR 0 interrupt request bit
(This bit is set to “1” at completion of inputting
“H” level signal.)
Fig. 2.2.21 Setting of related registers [Measurement of pulse width]
3806 GROUP USER’S MANUAL
2-21
APPLICATION
2.2 Timer
Figure 2.2.22 shows a control procedure.
● X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SEI
●
....
●
●
●
●
CNTR 0 interrupt : Enabled
....
XXXX10112
(Address : 23 16)
TM
256–1
PREX (Address : 24 16)
256–1
(Address : 25 16)
TX
1
ICON1 (Address : 3E 16), bit4
0
IREQ1 (Address : 3C 16), bit4
1
ICON2 (Address : 3F 16), bit0
0
IREQ2 (Address : 3D 16), bit0
All interrupts : Disabled
Timer X : Pulse width measurement mode
(Count “H” level width of pulse input from CNTR 0 pin.)
Set the division ratio so that the Timer X interrupt
occurs every 250 ms.
Timer X interrupt : Enabled
0
(Address : 23 16), bit3
●
....
TM
●
CLI
Timer X count : Start
Interrupts : Enabled
~
~
Timer X interrupt processing routine
Processing for error
●
Error occurs
RTI
CNTR 0 interrupt processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
(A)
Result of pulse width measurement
low–order 8-bit
(A)
Result of pulse width measurement
high–order 8-bit
PREX (Address : 24 16)
TX
(Address : 25 16)
Pop registers
●
PREX
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Push the register used in the interrupt
processing routine into the stack.
●
A count value is read out and stored to RAM.
●
Set the division ratio so that the Timer X
interrupt occurs every 250 ms.
Inversion of (A)
TX
Inversion of (A)
256 – 1
256–1
●
Pop registers which is pushed to stack .
RTI
Fig. 2.2.22 Control procedure [Measurement of pulse width]
2-22
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
2.3.1 Memory map of serial I/O
001816
Transmit/Receive buffer register (TB/RB)
001916
Serial I/O1 status register (SIO1STS)
001A16
Serial I/O1 control register (SIO1CON)
001B16
UART control register (UARTCON)
001C16
Baud rate generator (BRG)
001D16
Serial I/O2 control register (SIO2CON)
~
Serial I/O2 register (SIO2)
001F
~
Interrupt edge selection register (INTEDGE)
003A
~
~
16
16
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
~
~
~
~
~
Fig. 2.3.1 Memory map of serial I/O related registers
3806 GROUP USER’S MANUAL
2-23
APPLICATION
2.3 Serial I/O
2.3.2 Related registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816]
Function
B
At reset
0 A transmission data is written to or a receive data is read out
?
1
?
from this buffer register.
• At writing : a data is written to the Transmit buffer register.
• At reading : a content of the Receive buffer register is read out.
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 2.3.2 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status reigster (SIO1STS) [Address : 1916]
Name
B
Transmit
buffer
empty flag
0
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE)
4 Parity error flag (PE)
5 Framing error flag (FE)
6 Summing error flag (SE)
Function
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0
R W
✕
0
✕
0
✕
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
0
✕
0
✕
0 : No error
1 : Framing error
0 : (OE) (PE) (FE) = 0
1 : (OE) (PE) (FE) = 1
0
✕
0
✕
1
✕
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is “0.”
Fig. 2.3.3 Structure of Serial I/O1 status register
2-24
3806 GROUP USER’S MANUAL
At reset
APPLICATION
2.3 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
0
1
Name
BRG count source
selection bit (CSS)
Serial I/O1
synchronous clock
selection bit (SCS)
Function
At reset
0 : f(XIN)
1 : f(XIN)/4
0
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
0
R W
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
2
SRDY1 output enable bit
3
(SRDY)
Transmit interrupt
source selection bit
(TIC)
4
Transmit enable bit (TE)
5
Receive enable bit (RE)
6
Serial I/O1 mode
selection bit (SIOM)
7
Serial I/O1 enable bit
(SIOE)
0 : I/O port (P47)
1 : SRDY1 output pin
0 : Transmit buffer empty
1 : Transmit shift operating
completion
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : UART
1 : Clock synchronous serial I/O
0
0 : Serial I/O1 disabled
(P44–P47 : I/O port)
1 : Serial I/O1 enabled
(P44–P47 : Serial I/O function pin)
0
0
0
0
0
Fig. 2.3.4 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
Name
B
0 Character length
1
2
3
4
5
6
7
Function
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length selection
bit (STPS)
P45/TxD P-channel
output disable bit
(POFF)
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
At reset
R W
0
0
0
0
0
1
1
1
✕
✕
✕
Fig. 2.3.5 Structure of UART control register
3806 GROUP USER’S MANUAL
2-25
APPLICATION
2.3 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16]
Function
B
At reset
0 A count value of Baud rate generator is set.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 2.3.6 Structure of Baud rate generator
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 1D16]
Name
B
0 Internal synchronous
clock selection bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8
1 : f(XIN)/16
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
0 : I/O port (P71, P72)
1 : SOUT2, SCLK2 output pin
0 : I/O port (P73)
SRDY2 output enable bit
1 : SRDY2 output pin
0 : LSB first
Transfer direction
1 : MSB first
selection bit
Serial I/O2 synchronous clock 0 : External clock
1 : Internal clock
selection bit
Nothing is allocated for this bit. This is write disabled bit. When
this bit is read out, the value is “0.”
0
0
0
4
0
6
7
Fig. 2.3.7 Structure of Serial I/O2 control register
3806 GROUP USER’S MANUAL
R W
0
3 Serial I/O2 port selection bit
5
2-26
At reset
0
0
0
✕
APPLICATION
2.3 Serial I/O
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
Function
B
At reset
0 A shift register for serial transmission and reception.
?
At transmitting : Set a transmission data.
● At receiving : Store a reception data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
●
Fig. 2.3.8 Structure of Serial I/O2 register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name
B
0 INT0 interrupt edge
selection bit
1 INT1 interrupt edge
Function
0 : Falling edge active
1 : Rising edge active
0
0 : Falling edge active
0
1 : Rising edge active
selection bit
2 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
0 : Falling edge active
3 INT2 interrupt edge
1 : Rising edge active
selection bit
4 INT3 interrupt edge
At reset
0 : Falling edge active
1 : Rising edge active
selection bit
0 : Falling edge active
INT
4
interrupt
edge
5
1 : Rising edge active
selection bit
6 Nothing is allocated for these bits. These are write disabled
7 bits. When these bits are read out, the values are “0.”
0
R W
✕
0
0
0
0
0
✕
✕
Fig. 2.3.9 Structure of Interrupt edge selection register
3806 GROUP USER’S MANUAL
2-27
APPLICATION
2.3 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
Function
Name
B
At reset
R W
0 INT0 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0
✻
1 INT1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0
✻
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit interrupt
request bit
4 Timer X interrupt request bit
bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
✻ “0” is set by software, but not “1.”
Fig. 2.3.10 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name
B
CNTR
0
interrupt
request bit
0
At reset
R W
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
CNTR1 interrupt request bit
1 : Interrupt request
Serial I/O2 interrupt request bit 0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
INT2 interrupt request bit
1 : Interrupt request
0 : No interrupt request
INT3 interrupt request bit
1 : Interrupt request
0 : No interrupt request
INT4 interrupt request bit
1 : Interrupt request
0 : No interrupt request
AD conversion interrupt
1 :Interrupt request
request bit
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
7 Nothing is allocated for this bit. This is a write disabled bit.
0
✕
1
2
3
4
5
6
When this bit is read out, the value is “0.”
✻ “0” is set by software, but not “1.”
Fig. 2.3.11 Structure of Interrupt request register 2
2-28
Function
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Function
Name
0 INT0 interrupt enable bit
1 INT1 interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
3 Serial I/O1 transmit interrupt
enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
0
0
0
0
0
Fig. 2.3.12 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name
B
CNTR
0
interrupt
enable bit
0
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 CNTR1 interrupt enable bit
1 : Interrupt enabled
0
: Interrupt disabled
2 Serial I/O2 interrupt enable bit
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 INT2 interrupt enable bit
4 INT3 interrupt enable bit
5 INT4 interrupt enable bit
6 AD conversion interrupt
enable bit
7 Fix this bit to “0.”
R W
0
0
0
0
0
0
Fig. 2.3.13 Structure of Interrupt control register 2
3806 GROUP USER’S MANUAL
2-29
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
There are connection examples using a clock synchronous serial I/O mode.
Figure 2.3.14 shows connection examples of a peripheral IC equipped with the CS pin.
(1) Only transmission
(using the RXD pin as an I/O port)
Port
CS
SCLK
CLK
TXD
DATA
3806 group
Peripheral IC
(OSD controller etc.)
(3) Transmission and reception
(Pins RXD and TXD are connected)
(Pins IN and OUT in peripheral IC
are connected)
(2) Transmission and reception
Port
CS
SCLK
CLK
TXD
RXD
IN
3806 group
OUT
Peripheral IC
(E2 PROM etc.)
(4) Connecting ICs
Port
CS
Port
CS
SCLK
CLK
SCLK
CLK
TXD
RXD
IN
TXD
IN
OUT
R XD
OUT
3806 group ✻1 Peripheral IC ✻2
2
(E PROM etc.)
Port
Peripheral IC 1
3806 group
✻1:
Select an N-channel open-drain output control of TXD pin.
2: Use such OUT pin of peripheral IC as an N-channel opendrain output in high impedance during receiving data.
Notes1: “Port” is an output port controlled by software.
2: Use SOUT and SIN instead of TXD and RXD in the
serial I/O2.
Fig. 2.3.14 Serial I/O connection examples (1)
2-30
3806 GROUP USER’S MANUAL
CS
CLK
IN
OUT
Peripheral IC 2
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.15 shows connection examples of the other microcomputers.
(2) Selecting an external clock
(1) Selecting an internal clock
SCLK
CLK
TXD
RXD
3806 group
SCLK
CLK
IN
TXD
IN
OUT
R XD
OUT
3806 group
Microcomputer
(3) Using the SRDY signal output function
(Selecting an external clock)
Microcomputer
(4) Using UART✻
SRDY
RDY
SCLK
CLK
TXD
RXD
TXD
IN
R XD
T XD
RXD
OUT
3806 group
Microcomputer
3806 group
Microcomputer
✻: UART can not be used in the serial I/O2.
Note: Use SOUT and SIN instead of TXD and RXD in the serial I/O2.
Fig. 2.3.15 Serial I/O connection examples (2)
3806 GROUP USER’S MANUAL
2-31
APPLICATION
2.3 Serial I/O
2.3.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O1. The
serial I/O2 operates in a clock synchronous.
Figure 2.3.16 shows a setting of serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
Serial
I/O1
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
1ST-7DATA-1PAR-2SP
ST
Clock synchronous
Serial I/O
Serial
I/O2
Clock synchronous
Serial I/O
LSB
LSB first
LSB first
MSB first
Fig. 2.3.16 Setting of Serial I/O transfer data format
2-32
MSB
3806 GROUP USER’S MANUAL
ST : Start bit
SP : Stop bit
PAR : Parity bit
2SP
APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O application examples
(1) Communication using a clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The
signal is used for communication control.
____
SRDY
Figure 2.3.17 shows a connection diagram, and Figure 2.3.18 shows a timing chart.
Transmitting side
Receiving side
P42/INT0
SRDY1
SCLK1
SCLK
TXD
RXD
3806 group
3806 group
Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O]
Specifications : •
•
•
•
The Serial I/O1 is used (clock synchronous serial I/O is selected)
Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
The S RDY1 (receivable signal) is used.
The receiving side outputs the S RDY1 signal at intervals of 2 ms (generated by
timer), and 2-byte data is transferred from the transmitting side to the receiving
side.
_____
_____
••••
SRDY1
SCLK1
TXD
••••
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
••••
2 ms
Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O]
3806 GROUP USER’S MANUAL
2-33
APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 19 16)
b7
b0
SIO1STS
Transmit buffer empty flag
• Check to be transferred data from the Transmit buffer register to
Transmit shift register.
• Writable the next transmission data to the Transmit buffer register
at being set to “1.”
Transmit shift register shift completion flag
Check a completion of transmitting 1-byte data with this flag
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A 16)
b7
SIO1CON
b0
1 1 0 1
0 0
BRG counter source selection bit : f(X IN)
Serial I/O1 synchronous clock selection bit : BRG/4
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
Baud rate generator (Address : 1C 16)
b7
BRG
b0
7
Set “division radio – 1”
Interrupt edge selection register (Address : 3A
b7
INTEDGE
16)
b0
0
INT 0 active edge selection bit : Select INT 0 falling edge
Fig. 2.3.19 Setting of related registers at a transmitting side [Communication using a clock
synchronous serial I/O]
2-34
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 19 16)
b7
b0
SIO1STS
Receive buffer full flag
Check a completion of receiving 1-byte data with this flag.
“1” : At completing to receive
“0” : At reading out a receive buffer
Serial I/O1 control register (Address : 1A 16)
b7
SIO1CON
1 1 1 1
b0
1 1
Serial I/O1 synchronous clock selection bit : External clock
SRDY1 output enable bit : Use the S RDY1 output
Transmit enable bit : Transmit enabled
Set this bit to “1,” using S RDY1 output.
Receive enable bit : Receive enabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
Fig. 2.3.20 Setting of related registers at a receiving side [Communication using a clock
synchronous serial I/O]
3806 GROUP USER’S MANUAL
2-35
APPLICATION
2.3 Serial I/O
Control procedure : Figure 2.3.21 shows a control procedure at a transmitting side, and Figure
2.3.22 shows a control procedure at a receiving side.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
.....
1101XX002
SIO1CON (Address : 1A 16)
(Address : 1C 16)
BRG
8—1
INTEDGE (Address : 3A 16), bit0
0
0
IREQ1 (Address:3C 16), bit0?
• Detect INT 0 falling edge
1
IREQ1 (Address : 3C 16), bit0
TB/RB (Address : 18 16)
0
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
0
SIO1STS (Address : 19 16), bit0?
1
TB/RB (Address : 18 16)
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
SIO1STS (Address : 19 16), bit0?
• Check to be transfered data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
0
• Check to be transfered data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
0
• Check a shift completion of the Transmit shift register
(Transmit shift register shift completion flag)
1
SIO1STS (Address : 19 16), bit2?
1
Fig. 2.3.21 Control procedure at a transmitting side [Communication using a clock synchronous
serial I/O]
2-36
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
.....
SIO1CON (Address : 1A 16)
1111X11X2
N
Pass 2 ms?
• An interval of 2 ms is generated by a timer.
Y
TB/RB (Address : 18 16)
• SRDY1 output
SRDY1 signal is output by writing data to
the TB/RB.
Using the S RDY1 , the transmit enabled bit
(bit4) of the SIO1CON is set to “1.”
Dummy data
0
SIO1STS (Address : 19 16), bit1?
• Check a completion of receiving
(Receive buffer full flag)
1
• Receive the first byte data.
A Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 18 16)
SIO1STS (Address : 19 16), bit1?
0
• Check a completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (Address : 18 16)
• Receive the second byte data.
A Receive buffer full flag is set to “0” by reading data.
Fig. 2.3.22 Control procedure at a receiving side [Communication using a clock synchronous
serial I/O]
3806 GROUP USER’S MANUAL
2-37
APPLICATION
2.3 Serial I/O
(2) Output of serial data (control of a peripheral IC)
Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS
signal is output to a peripheral IC through the port P53.
P53
SCLK1
TXD
3806 group
CS
P53
CS
CLK
DATA
CS
CLK
SCLK2
CLK
DATA
SOUT2
DATA
Peripheral IC
(1) Example for using Serial I/O1
3806 group
CS
CLK
DATA
Peripheral IC
(2) Example for using Serial I/O2
Fig. 2.3.23 Connection diagram [Output of serial data]
Specifications : •
•
•
•
•
The Serial I/O is used. (clock synchronous serial I/O is selected)
Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
Transfer direction : LSB first
The Serial I/O1 interrupt is not used. ___
The Port P5 3 is connected to the CS pin (“L” active) of the peripheral IC for a
transmission control (the output level of the port P5 3 is controlled by software).
Figre 2.3.24 shows an output timing chart of serial data.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Note: The SOUT2 pin is in high impedance after completing to transfer data, using the serial I/O2.
Fig. 2.3.24 Timing chart [Output of serial data]
2-38
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Figure 2.3.25 shows a setting of serial I/O1 related registers, and Figure 2.3.26 shows a setting of
serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A 16)
b7
SIO1CON
b0
1 1 0 1 1 0 0 0
BRG count source selection bit : f(X IN)
Serial I/O1 synchronous clock selection bit : BRG/4
SRDY1 output enable bit : Not use the SRDY1 signal output function
Transmit interrupt source selection bit : Transmit shift operating completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B 16)
b7
b0
0
UARTCON
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C 16)
b7
b0
7
BRG
Set “division ratio – 1”
Interrupt control register 1 (Address : 3E 16)
b7
b0
ICON1
0
Serial I/O1 transmit interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C 16)
b7
b0
IREQ1
0
Serial I/O1 transmit interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit shift completion
Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data]
Transmit/Receive buffer register (Address : 1816)
b7
TB/RB
b0
Set a transmission data.
Check that transmission of the previous data is
completed before writing data (bit 3 of the
Interrupt request register 1 is set to “1”).
Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]
3806 GROUP USER’S MANUAL
2-39
APPLICATION
2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.25, the Serial I/O1 can transmit
1-byte data simply by writing data to the Transmit buffer register.
Thus, after setting the CS signal to “L,” write the transmission data to the
Receive buffer register on a 1-byte base, and return the CS signal to “H” when
the desired number of bytes have been transmitted.
Figure 2.3.27 shows a control procedure of serial I/O1.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
....
Initialization
SIO1CON (Address : 1A16)
110110002
UARTCON (Address : 1B16), bit4
0
8–1
BRG (Address : 1C16)
0
ICON1 (Address : 3E16), bit3
1
(Address : 0A16), bit3
P5
XXXX1XXX2
P5D (Address : 0B16)
●
Set the Serial I/O1.
●
Serial I/O1 transmit interrupt : Disabled
●
Set the CS signal output port.
(“H” level output)
....
P5 (Address : 0A16), bit3
0
IREQ1 (Address : 3C16), bit3
TB/RB (Address : 1816)
●
●
0
a transmission
data
0
IREQ1 (Address : 3C16), bit3?
Set the CS signal output level to “L.”
Set the Serial I/O1 transmit interrupt
request bit to “0.”
●
Write a transmission data.
(start to transmit 1-byte data)
●
Check the completion of transmitting 1byte data.
1
N
●
Complete to transmit data?
●
Y
●
P5 (Address : 0A16), bit3
1
Use any of RAM area as a counter for
counting the number of transmitted bytes.
Check that transmission of the target
number of bytes has been completed.
Return the CS signal output level to “H”
when transmission of the target number of
bytes is completed.
Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data]
2-40
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Figure 2.3.28 shows a setting of serial I/O2 related registers, and Figure 2.3.29 shows a setting of
serial I/O2 transmission data.
Serial I/O2 control register (Address : 1D16)
b7
SIO2CON
b0
1 0 0 1 0 1 0
Internal synchronous clock selection bits : f(XIN)/32
Serial I/O2 port selection bit :Use the Serial I/O2
SRDY2 output enable bit : Not use the SRDY2 signal output function
Transfer direction selection bit : LSB first
Serial I/O2 synchronous clock selection bit : Internal clock
Interrupt control register 2 (Address : 3F16)
b7
b0
ICON2
0
Serial I/O2 interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16)
b7
b0
IREQ2
0
Serial I/O2 interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit completion
Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data]
Serial I/O2 register (Address : 1F16)
b7
SIO2
b0
Set a transmission data.
Check that transmission of the previous data is
completed before writing data (bit 2 of the Interrupt
request register 2 is set to “1”).
Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data]
3806 GROUP USER’S MANUAL
2-41
APPLICATION
2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.28, the Serial I/O2 can transmit
1-byte data simply by writing data to the Serial I/O2 register.
Thus, after setting the CS signal to “L,” write the transmission data to the Serial
I/O1 register on a 1-byte base, and return the CS signal to “H” when the desired
number of bytes have been transmitted.
Figure 2.3.30 shows a control procedure of serial I/O2.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
....
SIO2CON (Address : 1D16)
X10010102
ICON2
(Address : 3F16), bit2
0
P5
(Address : 0A16), bit3
1
P5D
(Address : 0B16)
XXXX1XXX2
●
●
●
Set the Serial I/O2 control register.
Serial I/O2 interrupt : Disabled
Set the CS signal output port.
(“H” level output)
....
P5 (Address : 0A16), bit3
●
0
●
IREQ2 (Address : 3D16), bit2
0
a transmission
data
SIO2 (Address : 1F16)
IREQ2 (Address : 3D16), bit2?
0
Set the CS signal output level to “L.”
Set the Serial I/O2 interrupt
request bit to “0.”
●
Write a transmission data.
(start to transmit 1-byte data)
●
Check the completion of transmitting 1byte data.
●
Use any of RAM area as a counter for
counting the number of transmitted bytes.
Check that transmission of the target
number of bytes has been completed.
1
N
Complete to transmit data?
●
Y
●
P5 (Address : 0A16), bit3
1
Return the CS signal output level to “H”
when transmission of the target number of
bytes is completed.
Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data]
2-42
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of a specified number of bytes)
between microcomputers
[without using an automatic transfer]
Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock
and the data between the transmitting and receiving sides may be lost because of noise
included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This
“heading adjustment” is carried out by using the interval between blocks in this example.
SCLK
SCLK
RXD
TXD
TXD
RXD
Master unit
Slave unit
Note: Use SOUT and SIN instead of TXD and RXD in the serial I/O2.
Fig. 2.3.31 Connection diagram [Cyclic transmission or reception of block data between
microcomputers]
Specifications : •
•
•
•
•
•
•
•
The serial I/O1 is used (clock synchronous serial I/O is selected).
Synchronous clock frequency : 131 kHz (f(X IN) = 4.19 MHz is divided by 32)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 byte/block
Block transfer cycle : 16 ms
Block transfer period : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustive time : 8 ms
Limitations of the specifications
1. Reading of the reception data and setting of the next transmission data must be completed
within the time obtained from “byte cycle – time for transferring 1-byte data” (in this example,
the time taken from generating of the Serial I/O1 receive interrupt request to generating of the
next synchronizing clock is 431 µs).
2. “Heading adjustive time < interval between blocks” must be satisfied.
3806 GROUP USER’S MANUAL
2-43
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a
synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is
processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.33 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle
Block transfer period
Interval between blocks
Block transfer cycle
Heading adjustive time
Processing for heading adjustment
Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Slave unit
Serial I/O1 control register (Address : 1A16)
b7
b0
Serial I/O1 control register (Address : 1A16)
b7
b0
SIO1CON 1 1 1 1 1 0 0 0
SIO1CON 1 1 1 1
BRG count source : f(XIN)
Synchronous
clock : BRG/4
Not use the SRDY1 output
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Receive enabled
0 1
Not be effected by
external clock
Synchronous clock : External clock
Not use the SRDY1 output
Not use the serial I/O1 transmit interrupt
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Clock synchronous serial I/O
Serial I/O1 enabled
Serial I/O1 enabled
Both of units
UART control register (Address : 1B16)
b7
b0
UARTCON
0
P45/TXD pin : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
BRG
7
Set “division ratio – 1”
Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between
microcomputers]
2-44
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Control procedure :
Control in the master unit
After a setting of the related registers is completed as shown in Figure 2.3.33, in the master unit
transmission or reception of 1-byte data is started simply by writing transmission data to the
Transmit buffer register.
To perform the communication in the timing shown in Figure 2.3.32, therefore, take the timing into
account and write transmission data. Read out the reception data when the Serial I/O1 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the Transmit
buffer register.
A processing example in the master unit using timer interrupts is shown below.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block transfer period?
●
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Push the register used in the interrupt
processing routine into the stack.
N
●
Y
Generate a certain block interval by
using a timer or other functions.
●
Count a block interval counter
Read a reception data
Complete to transfer a block?
Y
Start a block transfer?
N
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
Pop registers
Check the block interval counter and
determine to start of a block transfer.
●
Pop registers which is pushed to stack.
RTI
Fig. 2.3.34 Control in the master unit
3806 GROUP USER’S MANUAL
2-45
APPLICATION
2.3 Serial I/O
Control in the slave unit
After a setting of the related registers is completed as shown in Figure 2.3.33, the slave unit becomes the
state which is received a synchronizing clock at all times, and the Serial I/O1 receive interrupt request bit
is set to “1” every time an 8-bit synchronous clock is received.
By the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the
Transmit buffer register after received data is read out.
However, if no serial I/O1 receive interrupt occurs for more than a certain time (head adjustive time), the
following processing will be performed.
1. The first 1 byte data of the transmission data in the block is written into the Transmission buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.35 shows the control in the slave unit using a serial I/O1 receive interrupt and any timer interrupt
(for head adjustive).
Serial I/O1 receive interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
N
Within a block transfer period?
Push the register used in
the interrupt processing
routine into the stack.
Check the received byte
counter to judge if a block
has been transfered.
Y
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Heading adjustive counter – 1
N
Heading adjustive
counter = 0?
Read a reception data
Push the register used in
the interrupt processing
routine into the stack.
Y
Write the first transmission data
(first byte) in a block
A received byte counter +1
A received byte counter ≥ 8?
A received byte counter
Y
0
N
Pop registers
Write any data (FF16)
Write a transmission data
●
Pop registers which is
pushed to stack.
RTI
Heading adjustive
counter
Initialized
value (Note 3)
Pop registers
●
Pop registers which is
pushed to stack.
RTI
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustive time divided by the timer interrupt
cycle as the initialized value of the heading adjustive
counter.
For example: When the heading adjustive time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initialized value.
Fig. 2.3.35 Control in the slave unit
2-46
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
(4) Communication (transmit/receive) using an asynchronous serial I/O (UART)
Point : 2-byte data is transmitted and received through an asynchronous serial I/O.
The port P4 0 is used for communication control.
Figure 2.3.36 shows a connection diagram, and Figure 2.3.37 shows a timing chart.
Transmitting side
Receiving side
P40
P40
TXD
R XD
3806 group
3806 group
Fig. 2.3.36 Connection diagram [Communication using UART]
Specifications : • The Serial I/O1 is used (UART is selected).
• Transfer bit rate : 9600 bps (f(XIN ) = 4.9152 MHz is divided by 512)
• Communication control using port P4 0
(The output level of the port P4 0 is controlled by softoware.)
• 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms (generated by timer).
P40
TXD
…
ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2)
ST D0
…
10 ms
Fig. 2.3.37 Timing chart [Communication using UART]
3806 GROUP USER’S MANUAL
2-47
APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values,
Figure 2.3.38 shows a setting of related registers at a transmitting side, and Figure 2.3.39 shows a
setting of related registers at a receiving side.
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values
Transfer bit BRG count
at f(XIN) = 4.9152 MHZ
at f(X IN) = 7.3728 MHZ
at f(XIN) = 8 MHZ
rate(bps)
source
(Note 1)
(Note 2) BRG setting value Actual time (bps) BRG setting value Actual time (bps) BRG setting value Actual time (bps)
600
f(X IN)/4
127(7F16)
600.00
191(BF16)
600.00
207(CF16)
600.96
1200
f(X IN)/4
63(3F16)
1200.00
95(5F16)
1200.00
103(67 16)
1201.92
2400
f(X IN)/4
31(1F16)
2400.00
47(2F16)
2400.00
51(33 16)
2403.85
4800
f(X IN)/4
15(0F16)
4800.00
23(17 16)
4800.00
25(19 16)
4807.69
9600
f(X IN)/4
7(0716)
9600.00
11(0B16)
9600.00
12(0C 16)
9615.38
19200
f(X IN)/4
3(0316)
19200.00
5(0516)
19200.00
5(0516)
20833.33
38400
f(X IN)/4
1(0116)
38400.00
2(0216)
38400.00
2(0216)
41666.67
76800
f(XIN)
3(0316)
76800.00
5(0516)
76800.00
5(0516)
83333.33
31250
f(XIN)
15(0F16)
31250.00
62500
f(XIN)
7(0716)
62500.00
Notes 1: Equation of transfer bit rate
Transfer bit rate (bps) =
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m
m: when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,” a value
of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1,” a value
of m is 4.
2: A BRG count source is selected by bit 0 of the Serial I/O1 control register (Address : 1A 16).
2-48
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 19 16)
b7
b0
SIO1STS
Transmit buffer empty flag
• Check to be transferred data from the Transmit buffer
register to the Transmit shift register.
• Writable the next transmission data to the Transmit buffer
register at being set to “1.”
Transmit shift register shift completion flag
Check a completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A 16)
b7
SIO1CON
b0
1 0 0 1
0 0 1
BRG count source selection bit : f(XIN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit : Not use S RDY1 output
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B 16)
b7
b0
0 1
UARTCON
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C 16)
b7
BRG
b0
7
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✻
–1
✻ when bit 0 of the Serial I/O1 control register (Address : 1A
16)
is set to
16)
is set to
“0,” a value of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A
“1,” a value of m is 4.
Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART]
3806 GROUP USER’S MANUAL
2-49
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 19 16)
b0
b7
SIO1STS
Receive buffer full flag
Check a completion of receiving 1-byte data with this flag.
“1” : at completing to receive
“0” : at reading out a content of the Receive buffer register
Overrun error flag
“1” : when data are ready to be transferred to the
Receive shift register in the state of storing data
into the Receive buffer register.
Parity error flag
“1” : when parity error occurs at enabled parity.
Framing error flag
“1” : when data can not be received at the timing of
setting a stop bit.
Summing error flag
“1” : when even one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O1 control register (Address : 1A 16)
b0
b7
SIO1CON
1 0 1 0
0 0 1
BRG count source selection bit : f(X IN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit : Not use S RDY1 out
Transmit enable bit : Transmit disabled
Receive enable bit : Receive enabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B 16)
b0
b7
1
UARTCON
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C 16)
b7
BRG
b0
7
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✻
–1
✻ when bit 0 of the Serial I/O1 control register (Address : 1A
16)
is set to
16)
is set to
“0,” a value of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A
“1,” a value of m is 4.
Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART]
2-50
3806 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Control procedure : Figure 2.3.40 shows a control procedure at a transmitting side, and Figure 2.3.41
shows a control procedure at a receiving side.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
.....
SIO1CON (Address : 1A 16) 1001X001 2
UARTCON(Address : 1B 16) 00001000 2
BRG
(Address : 1C 16) 8 –1
P4
(Address : 08 16), bit0 0
P4D
(Address : 09 16) XXXXXXX12
• Set port P4 0 for a communication control.
N
Pass 10 ms?
• An interval of 10 ms is generated by a timer.
Y
P4 (Address : 08 16), bit0
• Start of communication.
1
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
TB/RB (Address : 18 16)
SIO1STS (Address : 19 16), bit0?
0
• Check to be transferred data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
1
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
TB/RB (Address : 18 16)
0
• Check to be transferred data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
0
• Check a shift completion of the Transmit shift register.
(Transmit shift register shift completion flag)
SIO1STS (Address : 19 16), bit0?
1
SIO1STS (Address : 19 16), bit2?
1
P4 (Address : 08 16), bit0
0
• End of communication
Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART]
3806 GROUP USER’S MANUAL
2-51
APPLICATION
2.3 Serial I/O
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
.....
SIO1CON (Address : 1A 16)
UARTCON (Address : 1B 16)
BRG
(Address : 1C 16)
P4D
(Address : 09 16)
1010X0012
00001000 2
8–1
XXXXXXX02
SIO1STS (Address : 19 16), bit1?
0
• Check a completion of receiving.
(Receive buffer full flag)
1
• Receive the first 1 byte data
A Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 18 16)
SIO1STS (Address : 19 16), bit6?
1
• Check an error flag.
0
• Check a completion of receiving.
(Receive buffer full flag)
0
SIO1STS (Address : 19 16), bit1?
1
• Receive the second byte data
A Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 18 16)
SIO1STS (Address : 19 16), bit6?
1
• Check an error flag.
Processing for error
0
1
P4 (Address : 08 16), bit0?
0
SIO1CON (Address : 1A 16)
SIO1CON (Address : 1A 16)
0000X001 2
1010X001 2
• Countermeasure for a bit slippage
Fig. 2.3.41 Control procedure at a receiving side [Communication using UART]
2-52
3806 GROUP USER’S MANUAL
APPLICATION
2.4 A-D converter
2.4 A-D converter
2.4.1 Memory map of A-D conversion
003416
AD/DA control register (ADCON)
003516
A-D conversion register (AD)
~
~
Interrupt request register 2 (IREQ2)
003D
~
~
16
003F16
~
~
~
~
Interrupt control register 2 (ICON2)
Fig. 2.4.1 Memory map of A-D conversion related registers
3806 GROUP USER’S MANUAL
2-53
APPLICATION
2.4 A-D converter
2.4.2 Related registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register (ADCON) [Address : 34 16]
B
Function
Name
0 Analog input pin selection bits
1
2
3
4
5
6
7
b2 b1 b0
0 0 0 : P6 0/AN0
0 0 1 : P6 1/AN1
0 1 0 : P6 2/AN2
0 1 1 : P6 3/AN3
1 0 0 : P6 4/AN4
1 0 1 : P6 5/AN5
1 1 0 : P6 6/AN6
1 1 1 : P6 7/AN7
0
: Conversion in progress
AD conversion completion bit
1 : Conversion completed
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
0 : DA 1 output disable
DA1 output enable bit
1 : DA 1 output enable
0
: DA 2 output disabled
DA2 output enable bit
1 : DA 2 output enabled
At reset
R W
0
0
0
1
0
0
0
✕
✕
0
Fig. 2.4.2 Structure of AD/DA control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address : 35 16]
B
0
1
2
3
4
5
6
7
Function
The read-only register which A-D conversion results are stored.
Fig. 2.4.3 Structure of A-D conversion register
2-54
3806 GROUP USER’S MANUAL
At reset
?
?
?
?
?
?
?
?
R W
✕
✕
✕
✕
✕
✕
✕
✕
APPLICATION
2.4 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D
B
Name
0 CNTR 0 interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 CNTR 1 interrupt request bit
1 : Interrupt request
Serial
I/O2
interrupt
request
bit
0 : No interrupt request
2
1 : Interrupt request
0 : No interrupt request
3 INT2 interrupt request bit
1 : Interrupt request
0
✻
0
✻
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0
✻
0
✕
4 INT3 interrupt request bit
5 INT4 interrupt request bit
6 AD conversion interrupt
0 : No interrupt request
request bit
1 : Interrupt request
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✻ “0” is set by software, but not “1.”
Fig. 2.4.4 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F 16]
Name
B
CNTR
0
interrupt
enable bit
0
1 CNTR 1 interrupt enable bit
2 Serial I/O2 interrupt enable bit
3 INT2 interrupt enable bit
4 INT3 interrupt enable bit
5 INT4 interrupt enable bit
6 AD conversion interrupt
enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
7 Fix this bit to “0.”
R W
0
0
0
0
0
0
Fig. 2.4.5 Structure of Interrupt control register 2
3806 GROUP USER’S MANUAL
2-55
APPLICATION
2.4 A-D converter
2.4.3 A-D conversion application example
Conversion of Analog input voltage
Outline : The analog input voltage input from the sensor is converted into digital values.
Figure 2.4.6 shows a connection diagram, and Figure 2.4.7 shows a setting of related registers.
Sensor
P60/AN0
3806 group
Fig. 2.4.6 Connection diagram [Conversion of Analog input voltage]
Specifications : • The analog input voltage input from the sensor is converted into digital values.
• The P6 0 /AN 0 pin is used as an analog input pin.
AD/DA control register (Address : 3416)
ADCON
0 0 0 0
Analog input pin selection bits : Select the P6 0/AN0 pin
AD conversion completion bit : Conversion in progress
A-D conversion register (Address : 3516)
AD
(read-only)
Store a result of A-D conversion ( Note)
Note: Read out a result of A-D conversion after bit 3 of the
AD/DA control register (ADCON) is set to “1.”
Fig. 2.4.7 Setting of related registers [Conversion of Analog input voltage]
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3806 GROUP USER’S MANUAL
APPLICATION
2.4 A-D converter
Control procedure : By setting the related registers as shown in Figure 2.4.7, the analog input
voltage input from the sensor are converted into digital values.
~
~
ADCON (Address : 34 16), bit0 – bit2
ADCON (Address : 34 16), bit3
• Select the P6 0/AN0 pin as an analog input pin.
• Start A-D conversion.
000 2
0
ADCON (Address : 34 16), bit3?
0
• Check the completion of A-D conversion.
1
Read out AD (Address : 35 16)
• Read out the conversion result.
~
~
Fig. 2.4.8 Control procedure [Conversion of Analog input voltage]
3806 GROUP USER’S MANUAL
2-57
APPLICATION
2.5 Processor mode
2.5 Processor mode
2.5.1 Memory map of processor mode
003B16
CPU mode register (CPUM)
Fig. 2.5.1 Memory map of processor mode related register
2.5.2 Related register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16]
Name
B
0 Processor mode bits
1
2 Stack page selection bit
Function
00 :Single-chip mode
01 :Memory expansion mode
10 :Microprocessor mode
11 :Not available
0 :0 page
1 :1 page
3 Nothing is allocated for these bits. These are write disabled bits.
4 When these bits are read out, the values are “0.”
5
6
7
✻ An initial value of bit 1 is determined by a level of the CNVSS pin.
Fig. 2.5.2 Structure of CPU mode register
2-58
3806 GROUP USER’S MANUAL
At reset
R W
0
✻
0
0
0
0
0
0
✕
✕
✕
✕
✕
APPLICATION
2.5 Processor mode
2.5.3 Processor mode application examples
____
(1) Application example of memory expansion in the case where the ONW (One-Wait)
function is not used
Outline : The external memory is accessed in the microprocessor mode.
At___
f(X IN) = 8 MHz, an available RAM is given by the following :
• OE access time : ta (OE) ≤ 50 ns
• Setup time for writing data : tsu (D) ≤ 65 ns
For example, the M5M5256BP-10 whose address access is 100 ns is available.
Figure 2.5.3 shows an expansion example of a 32K byte ROM and a 32K byte RAM.
3806 group
CNVSS
AD15
ONW
M5M27C256AK-10
2
P30, P3 1
15
–
P4
CE
S
A0–A14
A0–A14
74F04
AD14
8
M5M5256BP-10
AD0
EPROM
8
SRAM
P5
DB0
–
8
P6
8
P7
DB7
8
D0–D7
OE
DQ1–DQ8
OE
W
Memory map
0000 16 External RAM area
(M5M5256BP)
000816
SFR area
004016 Ineternal RAM area
044016 External RAM area
RD
WR
8
P8
(M5M5256BP)
8MHz
VCC = 5.0V ± 10 %
800016
External ROM area
(M5M27C256AK)
FFFF16
Fig. 2.5.3 Expansion example of ROM and RAM
3806 GROUP USER’S MANUAL
2-59
APPLICATION
2.5 Processor mode
Figure 2.5.4, Figure 2.5.5 and Figure 2.5.6 shows a standard timing at 8 MHz (No-Wait).
A0–A7
Address (low-order)
(Port P0)
A 8–A14
Address (high-order)
(Port P1)
S
(A15)
t WL(RD)
td(AH–RD)
OE
(RD of 3806)
125 ns - 10 ns (min)
125 ns - 35 ns (min)
ta(OE)
50 ns (max)
Data
DQ1–DQ 8
(Port P2)
tsu(DB–RD)
65 ns (min)
WR
“H” level
td(AH–RD)
tWL(RD)
ta(OE)
tsu(DB–RD)
:
:
:
:
RD delay time after outputting address of 3806
RD pulse width of 3806
Output enabled access time of M5M5256BP
Data bus setup time before RD of 3806
Fig. 2.5.4 Read-cycle (OE access, SRAM)
A0–A7
Address (low-order)
(Port P0)
A8–A14
Address (high-order)
(Port P1)
CE
tPHL
5.8 ns (max)
tWL(RD)
td(AH–RD)
OE
(RD of 3806)
125 ns - 10ns (min)
125 ns - 35 ns (min)
ta(OE)
50 ns (max)
D0–D7
(Port P2)
Data
tsu(DB–RD)
65 ns (min)
WR
“H” level
t PHL
td(AH–RD)
t WL(RD)
ta(OE)
tsu(DB–RD)
: Output delay time of 74F04
: RD delay time after outputting address of 3806
: RD pulse width of 3806
: Output enabled access time of M5M27C256AK
: Data bus setup time before RD of 3806
Fig. 2.5.5 Read-cycle (OE access, EPROM)
2-60
3806 GROUP USER’S MANUAL
APPLICATION
2.5 Processor mode
A0–A7
Address (low-order)
(Port P0)
A8–A14
Address (high-order)
(Port P1)
S
(A15)
tWL(WR)
125 ns - 10 ns (min)
td(AH–WR)
W
(WR of 3806)
125 ns - 35 ns (min)
td(WR–DB)
65 ns (max)
DQ1–DQ8
Data
(Port P2)
tsu(D)
35 ns (min)
OE
(RD of 3806)
“H“ level
td(AH–WR)
tWL(WR)
td(WR–DB)
tsu(D)
: WR delay time after outputting address of 3806
: WR pulse width of 3806
: Data bus delay time after WR of 3806
: Data setup time of M5M5256BP
Fig. 2.5.6 Write-cycle (W control, SRAM)
3806 GROUP USER’S MANUAL
2-61
APPLICATION
2.5 Processor mode
_____
(2) Application example of memory expansion in the case where the ONW (One-Wait)
function is
used
____
Outline : ONW function is used when the external
memory access is slow.
____
If “L” level signal is input to the P32/ ONW pin while the CPU is in the read or write status,
is extended. In the extended period,
the ___
read or___
write cycle corresponding to 1 cycle of
____
the RD or WR signal is kept at the “L” level. The ONW function operates only when data is
read from or written into addresses 0000____
16 to 0007 16 and addresses 0440 16 to FFFF 16.
Figure 2.5.7 shows an application example of the ONW function.
3806 group
CNVSS
AD15
2
74F04
M5M27C256AK-10
P30, P3 1
ONW
CE
M5M5256BP-10
S
AD14
P4
15
–
8
A0–A14
AD0
A0–A14
EPROM
DB0
P5
–
8
8
DB7
D0–D7
OE
SRAM
DQ1–DQ8
OE
W
Memory map
0000 16 External RAM area
(M5M5256BP)
8
P6
000816
SFR area
004016 Internal RAM area
RD
WR
044016 External RAM area
(M5M5256BP)
8MHz
VCC = 5.0V±10 %
800016
External ROM area
FFFF16
____
Fig. 2.5.7 Application example of the ONW function
2-62
3806 GROUP USER’S MANUAL
(M5M27C256AK)
APPLICATION
2.5 Processor mode
(3) Application example of memory expansion in the case where the High-speed version
(A-version) is used
Outline : High-speed version is used when the extarnal memory access is fast.
At___
f(X IN ) = 9 MHz, an available RAM is given by the following :
• OE access time : ta (OE) ≤ 35 ns
• Setup time for writing data : tsu (D) ≤ 50 ns
For example, the M5M5256BP-70 whose address access is 70 ns is available.
Figure 2.5.8 shows an expansion example of a 32K byte ROM and a 32K byte RAM.
3806 group (High-speed version )
CNVSS
AD15
ONW
2
P30, P3 1
P4
15
AD0
CE
S
A0–A14
A0–A14
EPROM
8
M5M5256BP-70
74F04
AD14
–
8
M5M27C256AK-85
SRAM
P5
DB0
–
8
P6
8
P7
DB7
8
D0–D7
OE
DQ1–DQ8
OE
W
Memory
0000 16 External RAM area
(M5M5256BP)
000816
SFR area
004016 Internal RAM area
044016 External RAM area
RD
WR
8
P8
(M5M5256BP)
9MHz
VCC = 5.0V±10 %
800016
External ROM area
(M5M27C256AK)
FFFF16
Fig. 2.5.8 Expansion example of ROM and RAM [High-speed version]
3806 GROUP USER’S MANUAL
2-63
APPLICATION
2.5 Processor mode
Figure 2.5.9, Figure 2.5.10 and Figure 2.5.11 shows a standard timing at 9 MHz (No-Wait).
A 0–A7
(Port P0)
Address (low-order)
A8–A14
(Port P1)
Address (high-order)
S
(A15)
t WL(RD)
td(AH–RD)
OE
(RD of 3806)
111 ns - 10ns (min)
111 ns - 35 ns (min)
ta(OE)
35 ns (max)
Data
DQ1–DQ8
(Port P2)
tsu(DB–RD)
50 ns (min)
WR
“H” level
td(AH–RD)
tWL(RD)
ta(OE)
tsu(DB–RD)
: RD delay time after outputting address of 3806
: RD pulse width of 3806
: Output enabled access time of M5M5256BP
: Data bus setup time before RD of 3806
Fig. 2.5.9 Read-cycle (OE access, SRAM) [High-speed version]
A0–A7
Adderss (low-order)
(Port P0)
A8–A14
Adderss (high-order)
(Port P1)
CE
tPHL
5.8 ns (max)
tWL(RD)
td(AH–RD)
OE
(RD of 3806)
111 ns - 10ns (min)
111 ns - 35 ns (min)
ta(OE)
45 ns (max)
D0–D7
(Port P2)
Data
tsu(DB–RD)
50 ns (min)
WR
“H” level
t PHL
td(AH–RD)
t WL(RD)
ta(OE)
tsu(DB–RD)
: Output delay time of 74F04
: RD delay time after outputting address of 3806
: RD pulse width of 3806
: Output enabled access time of M5M27C256AK
: Data bus setup time before RD of 3806
Fig. 2.5.10 Read-cycle (OE access, EPROM) [High-speed version]
2-64
3806 GROUP USER’S MANUAL
APPLICATION
2.5 Processor mode
A0–A7
Address (low-order)
(Port P0)
A8–A14
Address (high-order)
(Port P1)
S
(A15)
tWL(WR)
111 ns - 10 ns (min)
td(AH–WR)
W
(WR of 3806)
111 ns - 35 ns (min)
td(WR–DB)
30 ns (max)
DQ1–DQ8
Data
(Port P2)
tsu(D)
30 ns (min)
OE
“H” level
(RD of 3806)
td(AH–WR)
tWL(WR)
td(WR–DB)
tsu(D)
: WR delay time after outputting address of 3806
: WR pulse width of 3806
: Data bus delay time after WR of 3806
: Data setup time of M5M5256BP
Fig. 2.5.11 Write-cycle (W control, SRAM) [High-speed version]
3806 GROUP USER’S MANUAL
2-65
APPLICATION
2.6 Reset
2.6 Reset
2.6.1 Connection example of reset IC
91
1
VCC
Power source
M62022L
5
Output
35
RESET
Delay capacity
4
GND
0.1 µF
40
3
VSS
3806 group
Fig. 2.6.1 Example of Poweron reset circuit
Figure 2.6.2 shows the system example which switch to the RAM backup mode by detecting a drop of the
system power source voltage with the INT interrupt.
System power
source voltage
+5
91
+
VCC
7
VCC1
RESET
2
INT
VCC2
5
35
3
INT
40
1
V1 GND Cd
6
4
M62009L, M62009P, M62009FP
Fig. 2.6.2 RAM back-up system
2-66
3806 GROUP USER’S MANUAL
RESET
VSS
3806 group
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Mask ROM ordering method
3.7 Mark specification form
3.8 Package outline
3.9 List of instruction codes
3.10 Machine instructions
3.11 SFR memory map
3.12 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 ELECTRICAL CHARACTERISTICS
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
3-2
Parameter
Power source voltage
Input voltage P00–P07, P10–P17,
P30–P37, P40–P47,
P60–P67, P70–P77,
VREF
______
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17,
P30–P37, P40–P47,
P60–P67, P70–P77,
XOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
P20–P27,
P50–P57,
P80–P87,
All voltages are based on VSS.
Output transistors are cut off.
P20–P27,
P50–P57,
P80–P87,
Ta = 25 °C
3806 GROUP USER’S MANUAL
Ratings
–0.3 to 7.0
Unit
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to 13
V
V
–0.3 to VCC +0.3
V
500
–20 to 85
–40 to 125
mW
°C
°C
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (VCC = 3.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIL
VIL
VIL
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
f(XIN)
Parameter
Power source voltage (f(XIN) 2 MHz) (Note 1)
Power source voltage (f(XIN) = 8 MHz) (Note 1)
Power source voltage
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
Analog input voltage
AN0–AN7
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87
______
“H” input voltage
RESET, XIN, CNVSS
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87
______
“L” input voltage
RESET
“L” input voltage
XIN
“L” input voltage
CNVSS
“H” total peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 2)
“H” total peak output current
P40–P47,P50–P57, P60–P67 (Note 2)
“L” total peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 2)
“L” total peak output current
P40–P47,P50–P57, P60–P67, P70–P77 (Note 2)
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 2)
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 2)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 2)
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 2)
“H” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 3)
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)
“H” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 4)
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 4)
Internal clock oscillation frequency (VCC = 4.0 to 5.5 V)
Internal clock oscillation frequency (VCC = 3.0 to 4.0 V)
Min.
3.0
4.0
Limits
Typ.
5.0
5.0
0
2.0
3.0
Max.
5.5
5.5
Unit
V
V
VCC
VCC
0
V
AVSS
VCC
V
V
0.8 VCC
VCC
V
0.8 VCC
VCC
V
0
0.2 VCC
V
0
0
0
0.2 VCC
0.16 VCC
0.2 VCC
–80
–80
80
80
–40
–40
40
40
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
–10
mA
10
mA
–5
mA
5
mA
8
6 VCC–16
MHz
Note 1: The minimum power source voltage is X + 16 [V] (f(XIN) = XMHz) on the condition of 2 MHz < f(XIN) < 8 MHz.
6
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
3: The peak output current is the peak current flowing in each port.
4: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
3806 GROUP USER’S MANUAL
3-3
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.3 Electrical characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87 (Note 1)
VOH
“L” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47,P50–P57,
P60–P67, P70–P77, P80–P87
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
Hysteresis
“H” input current
IIH
IIH
IIH
“H” input current
“H” input current
“L” input current
IIL
IIL
IIL
VRAM
ICC
“L” input current
“L” input current
RAM hold voltage
CNTR0, CNTR1, INT0–INT4
RXD, SCLK1, SIN2, SCLK2
______
RESET
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
______
RESET, CNVSS
XIN
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
______
RESET, CNVSS
XIN
Power source current
IOH = –10 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 3.0 to 5.5 V
IOL = 10 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 3.0 to 5.5 V
Min.
Limits
Typ.
Max.
VCC–2.0
V
VCC–1.0
2.0
V
1.0
0.4
0.5
0.5
VI = VCC
VI = VCC
VI = VCC
V
V
V
5.0
µA
5.0
µA
µA
–5.0
µA
–5.0
µA
µA
V
4
VI = VSS
VI = VSS
VI = VSS
When clock stopped
f(XIN) = 8 MHz, VCC = 5 V
f(XIN) = 5 MHz, VCC = 5 V
f(XIN) = 2 MHz, VCC = 3 V
When WIT instruction is executed
with f(XIN) = 8 MHz, VCC = 5 V
When WIT instruction is executed
with f(XIN) = 5 MHz, VCC = 5 V
When WIT instruction is executed
with f(XIN) = 2 MHz, VCC = 3 V
When STP instruction
Ta = 25 °C
is executed with clock (Note 2)
stopped, output
Ta = 85 °C
transistors isolated.
(Note 2)
Unit
–4
2.0
6.4
4
0.8
5.5
13
8
2.0
1.5
mA
1
0.2
0.1
1
µA
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through V REF pin.
3.1.4 A-D converter characteristics
Table 3.1.4 A-D converter characteristics
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
—
—
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference power source input current (Note)
A-D port input current
tCONV
RLADDER
IVREF
II(AD)
Test conditions
Limits
Typ.
±1
VREF = 5.0 V
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
3-4
Min.
3806 GROUP USER’S MANUAL
50
35
150
0.5
Max.
8
±2.5
50
200
5.0
Unit
Bits
LSB
tC(φ)
kΩ
µA
µA
APPENDIX
3.1 Electrical characteristics
3.1.5 D-A converter characteristics
Table 3.1.5 D-A converter characteristics
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
—
Resolution
8
Bits
VCC = 4.0 to 5.5 V
1.0
—
Absolute accuracy
%
VCC = 3.0 to 4.0 V
2.5
tsu
Setting time
3
µs
RO
Output resistor
1
2.5
4
kΩ
IVREF
Reference power source input current (Note)
3.2
mA
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through the A-D resistance ladder.
3806 GROUP USER’S MANUAL
3-5
APPENDIX
3.1 Electrical characteristics
3.1.6 Timing requirements and Switching characteristics
Table 3.1.6 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
_____
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD–SCLK1)
tsu(SIN2–SCLK2)
th(SCLK1–RXD)
th(SCLK2–SIN2)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Min.
2
125
50
50
200
80
80
80
80
800
1000
370
400
370
400
220
200
100
200
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
Table 3.1.7 Timing requirements (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
_____
Parameter
tw(RESET)
Reset input “L” pulse width
tc(XIN)
External clock input cycle time
twH(XIN)
External clock input “H” pulse width
twL(XIN)
External clock input “L” pulse width
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD–SCLK1)
tsu(SIN2–SCLK2)
th(SCLK1–RXD)
th(SCLK2–SIN2)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Min.
2
500/
(3 VCC–8)
200/
(3 VCC–8)
200/
(3 VCC–8)
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
300
Note : When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
3-6
3806 GROUP USER’S MANUAL
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
APPENDIX
3.1 Electrical characteristics
Table 3.1.8 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Test conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Fig. 3.1.1
Min.
tc(SCLK1)/2–30
tc(SCLK1)/2–30
Limits
Typ.
Max.
140
–30
30
30
tc(SCLK2)/2–160
tc(SCLK2)/2–160
Fig. 3.1.2
200
0
10
10
Fig. 3.1.1
40
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
Table 3.1.9 Switching characteristics (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Test conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Fig. 3.1.1
Min.
tc(SCLK1)/2–50
tc(SCLK1)/2–50
Limits
Typ.
Max.
350
–30
50
50
tc(SCLK2)/2–240
tc(SCLK2)/2–240
Fig. 3.1.2
400
0
Fig. 3.1.1
20
20
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
3806 GROUP USER’S MANUAL
3-7
APPENDIX
3.1 Electrical characteristics
Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
____
tsu(ONW–φ)
____
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
____ __
tsu(ONW–RD)
____ ___
tsu(ONW–WR)
__ ____
th(RD–ONW)
___ ____
th(WR–ONW)
__
tsu(DB–RD)
__
th(RD–DB)
Parameter
Min.
–20
–20
60
0
_____
Before φ ONW input set up time
_____
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
___ _____
Before RD
___ ONW
_____ input set up time
Before WR ONW input set up time
___ _____
After RD
___ ONW
_____ input hold time
After WR ONW input hold time
___
Before RD data bus set up time
___
After RD data bus hold time
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
–20
ns
–20
ns
65
0
ns
ns
Table 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
___
___
RD and WR delay time
___
___
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
___
___
__
RD pulse width, WR pulse width
___
___
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
(When one-wait is valid)
___
__
td(AH–RD)
After AD15–AD8 ___
RD delay time
___
td(AH–WR)
After AD15–AD8 WR delay time
___
__
td(AL–RD)
After AD7–AD0 ___
RD delay time
___
td(AL–WR)
After AD7–AD0 WR delay time
___
__
tv(RD–AH)
After ___
RD AD15–AD8 valid time
___
tv(WR–AH)
After WR AD15–AD8 valid time
___
__
tv(RD–AL)
After ___
RD AD7–AD0 valid time
___
tv(WR–AL)
After WR AD7–AD0 valid time
___
___
td(WR–DB)
After WR data bus delay time
___
___
tv(WR–DB)
After WR data bus valid time
_________
___ _____
td(RESET–RESETOUT) RESETOUT output delay time (Note 1)
_________
_____
tv(φ–RESET) RESETOUT output valid time (Note 1)
Min.
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
___
td(φ–WR)
___
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
Limits
Typ.
2tc(XIN)
Max.
15
tc(XIN)–10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3tc(XIN)–10
ns
tc(XIN)–10
tc(XIN)–10
6
6
3
Fig. 3.1.1
__________
Unit
20
10
25
10
20
10
10
5
20
40
45
20
10
70
tc(XIN)–35
tc(XIN)–15
ns
tc(XIN)–40
tc(XIN)–20
ns
0
5
ns
0
5
ns
15
65
10
0
200
200
ns
ns
ns
ns
Note 1: The______
RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
3-8
3806 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
Table 3.1.12 Timing requirements in memory expansion mode and microprocessor mode (2)
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
____
tsu(ONW–φ)
____
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
____ __
tsu(ONW–RD)
____ ___
tsu(ONW–WR)
__ ____
th(RD–ONW)
___ ____
th(WR–ONW)
__
tsu(DB–RD)
__
th(RD–DB)
Parameter
Min.
–20
–20
180
0
_____
Before φ ONW input set up time
_____
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
___ _____
Before RD
___ ONW
_____ input set up time
Before WR ONW input set up time
___ _____
After RD
___ ONW
_____ input hold time
After WR ONW input hold time
___
Before RD data bus set up time
___
After RD data bus hold time
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
–20
ns
–20
ns
185
0
ns
ns
Table 3.1.13 Switching characteristics in memory expansion mode and microprocessor mode (2)
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
___
___
RD and WR delay time
___
___
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
___
___
__
RD pulse width, WR pulse width
___
___
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
(When one-wait is valid)
___
__
td(AH–RD)
After AD15–AD8 ___
RD delay time
___
td(AH–WR)
After AD15–AD8 WR delay time
___
__
td(AL–RD)
After AD7–AD0 ___
RD delay time
___
td(AL–WR)
After AD7–AD0 WR delay time
___
__
tv(RD–AH)
After ___
RD AD15–AD8 valid time
___
tv(WR–AH)
After WR AD15–AD8 valid time
___
__
tv(RD–AL)
After ___
RD AD7–AD0 valid time
___
tv(WR–AL)
After WR AD7–AD0 valid time
___
___
td(WR–DB)
After WR data bus delay time
___
___
tv(WR–DB)
After WR data bus valid time
_________
___ _____
td(RESET–RESETOUT) RESETOUT output delay time (Note 1)
_________
_____
tv(φ–RESET) RESETOUT output valid time (Note 1)
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
___
td(φ–WR)
___
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
Min.
Limits
Typ.
2tc(XIN)
Max.
15
tc(XIN)–20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3tc(XIN)–20
ns
tc(XIN)–145
ns
tc(XIN)–145
ns
tc(XIN)–20
tc(XIN)–20
150
10
15
10
15
40
20
15
7
150
3
Fig. 3.1.1
Unit
25
15
200
5
10
ns
5
10
ns
195
ns
ns
300
300
ns
ns
10
0
__________
Note1: The______
RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
3806 GROUP USER’S MANUAL
3-9
APPENDIX
3.1 Electrical characteristics
3.1.7 Absolute maximum ratings (Extended operating temperature version)
Table 3.1.14 Absolute maximum ratings (Extended operating temperature version)
Symbol
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage P00–P07, P10–P17,
P30–P37, P40–P47,
P60–P67, P70–P77,
VREF
______
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17,
P30–P37, P40–P47,
P60–P67, P70–P77,
XOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
P20–P27,
P50–P57,
P80–P87,
All voltage are based on VSS.
Output transistors are cut off.
P20–P27,
P50–P57,
P80–P87,
Ratings
–0.3 to 7.0
Unit
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to 13
V
V
–0.3 to VCC +0.3
V
500
–40 to 85
–65 to 150
mW
°C
°C
Ta = 25 °C
3.1.8 Recommended operating conditions (Extended operating temperature version)
Table 3.1.15 Recommended operating conditions (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIL
VIL
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
f(XIN)
Parameter
Power source voltage
Power source voltage
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
Analog input voltage
AN0–AN7
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87
______
“H” input voltage
RESET, XIN, CNVSS
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87
______
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
“H” total peak output current
P40–P47,P50–P57, P60–P67 (Note 1)
“L” total peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
“L” total peak output current
P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
P40–P47,P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
“H” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 3)
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)
Internal clock oscillation frequency
Min.
4.0
Limits
Typ.
5.0
0
2.0
4.0
Max.
5.5
VCC
VCC
0
Unit
V
V
V
AVSS
VCC
V
V
0.8 VCC
VCC
V
0.8 VCC
VCC
V
0
0.2 VCC
V
0
0
0.2 VCC
0.16 VCC
–80
–80
80
80
–40
–40
40
40
V
V
mA
mA
mA
mA
mA
mA
mA
mA
–10
mA
10
mA
–5
mA
5
mA
8
MHz
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
3-10
3806 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.9 Electrical characteristics (Extended operating temperature version)
Table 3.1.16 Electrical characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
VOH
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
VRAM
ICC
Parameter
Test conditions
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87 (Note 1)
“L” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47,P50–P57,
P60–P67, P70–P77, P80–P87
Hysteresis
CNTR0, CNTR1, INT0–INT4
Hysteresis
RXD, SCLK1, SIN2, SCLK2
______
Hysteresis
RESET
“H” input current P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
______
“H” input current RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
______
“L” input current
RESET, CNVSS
“L” input current
XIN
RAM hold voltage
Power source current
IOH = –10 mA
Min.
Limits
Typ.
Max.
VCC–2.0
V
IOL = 10 mA
2.0
0.4
0.5
0.5
VI = VCC
VI = VCC
VI = VCC
VI = VSS
5.0
µA
5.0
µA
µA
–5.0
µA
–5.0
µA
µA
V
–4
2.0
6.4
4
V
V
V
V
4
VI = VSS
VI = VSS
When clock stopped
f(XIN) = 8 MHz
f(XIN) = 5 MHz
When WIT instruction is executed
with f(XIN) = 8 MHz
When WIT instruction is executed
with f(XIN) = 5 MHz
When STP instruction
Ta = 25 °C
is executed with clock (Note 2)
stopped, output
Ta = 85 °C
transistors isolated.
(Note 2)
Unit
5.5
13
8
mA
1.5
1
0.1
1
µA
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through V REF pin.
3.1.10 A-D converter characteristics (Extended operating temperature version)
Table 3.1.17 A-D converter characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
—
—
tCONV
RLADDER
IVREF
II(AD)
Parameter
Test conditions
Limits
Min.
Typ.
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference power source input current (Note)
A-D port input current
±1
VREF = 5.0 V
50
35
150
0.5
Unit
Max.
8
±2.5
50
Bits
LSB
tC(φ)
200
5.0
kΩ
µA
µA
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
3806 GROUP USER’S MANUAL
3-11
APPENDIX
3.1 Electrical characteristics
3.1.11 D-A converter characteristics (Extended operating temperature version)
Table 3.1.18 D-A converter characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
—
—
tsu
RO
IVREF
Parameter
Test conditions
Resolution
Absolute accuracy
Setting time
Output resistor
Reference power source input current (Note)
Min.
1
Limits
Typ.
2.5
Max.
8
1.0
3
4
3.2
Unit
Bits
%
µs
kΩ
mA
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through the A-D resistance ladder.
3-12
3806 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version)
Table 3.1.19 Timing requirements (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
_____
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD–SCLK1)
tsu(SIN2–SCLK2)
th(SCLK1–RXD)
th(SCLK2–SIN2)
Parameter
Min.
2
125
50
50
200
80
80
80
80
800
1000
370
400
370
400
220
200
100
200
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
Table 3.1.20 Switching characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Test conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rise time
Serial I/O1 clock output fall time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output fall time
CMOS output rise time (Note 2)
CMOS output fall time (Note 2)
Fig. 3.1.1
Min.
tc(SCLK1)/2–30
tc(SCLK1)/2–30
Limits
Typ.
Max.
140
–30
30
30
tc(SCLK2)/2–160
tc(SCLK2)/2–160
Fig. 3.1.2
200
0
Fig. 3.1.1
10
10
40
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT pin and P70–77 are excluded.
3806 GROUP USER’S MANUAL
3-13
APPENDIX
3.1 Electrical characteristics
Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
____
tsu(ONW–φ)
____
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
____ __
tsu(ONW–RD)
____ ___
tsu(ONW–WR)
__ ____
th(RD–ONW)
___ ____
th(WR–ONW)
__
tsu(DB–RD)
__
th(RD–DB)
Parameter
Min.
–20
–20
60
0
_____
Before φ ONW input set up time
_____
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
___ _____
Before RD
___ ONW
_____ input set up time
Before WR ONW input set up time
___ _____
After RD
___ ONW
_____ input hold time
After WR ONW input hold time
___
Before RD data bus set up time
___
After RD data bus hold time
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
–20
ns
–20
ns
65
0
ns
ns
Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
___
___
RD and WR delay time
___
___
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
___
___
__
RD pulse width, WR pulse width
___
___
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
(When one-wait is valid)
___
__
td(AH–RD)
After AD15–AD8 ___
RD delay time
___
td(AH–WR)
After AD15–AD8 WR delay time
___
__
td(AL–RD)
After AD7–AD0 ___
RD delay time
___
td(AL–WR)
After AD7–AD0 WR delay time
___
__
tv(RD–AH)
After ___
RD AD15–AD8 valid time
___
tv(WR–AH)
After WR AD15–AD8 valid time
___
__
tv(RD–AL)
After ___
RD AD7–AD0 valid time
___
tv(WR–AL)
After WR AD7–AD0 valid time
___
___
td(WR–DB)
After WR data bus delay time
___
___
tv(WR–DB)
After WR data bus valid time
_________
___ _____
td(RESET–RESETOUT) RESETOUT output delay time (Note 1)
_________
_____
tv(φ–RESET) RESETOUT output valid time (Note 1)
Min.
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
___
td(φ–WR)
___
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
Limits
Typ.
2tc(XIN)
Max.
15
tc(XIN)–10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3tc(XIN)–10
ns
tc(XIN)–10
tc(XIN)–10
6
6
3
Fig. 3.1.1
_________
Unit
20
10
25
10
20
10
10
5
20
40
45
20
10
70
tc(XIN)–35
tc(XIN)–15
ns
tc(XIN)–40
tc(XIN)–20
ns
0
5
ns
0
5
ns
15
65
10
0
200
200
ns
ns
ns
ns
Note 1: The______
RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
3-14
3806 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.13 Absolute maximum ratings (High-speed version)
Table 3.1.23 Absolute maximum ratings (High-speed version)
Symbol
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
VREF, XIN
______
Input voltage RESET
Mask ROM version
Input voltage CNVSS
PROM version
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
XOUT
Power dissipation
Operating temperature
Storage temperature
Ratings
–0.3 to 7.0
Unit
–0.3 to VCC +0.3
V
–0.3 to 7.0
–0.3 to 7.0
–0.3 to 13
V
–0.3 to VCC +0.3
V
500
–20 to 85
–40 to 125
mW
°C
°C
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ta = 25 °C
V
V
3.1.14 Recommended operating conditions (High-speed version)
Table 3.1.24 Recommended operating conditions (High-speed version)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
VSS
VREF
AVSS
VIA
Parameter
Power source voltage (f(XIN) 4.15 MHz)
Power source voltage (f(XIN) = 10 MHz)
Power source voltage
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
Analog input voltage
AN0–AN7
Min.
2.7
4.0
Limits
Typ.
5.0
5.0
0
2.0
2.7
Max.
5.5
5.5
VCC
V
VCC
V
V
VCC
V
0.2 VCC
V
0.16 VCC
–80
–80
80
80
–40
–40
40
40
V
mA
mA
mA
mA
mA
mA
mA
mA
–10
mA
10
mA
–5
mA
5
mA
“H” input voltage
VIH
VIL
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
f(XIN)
P00–P07, P10–P17, P20–P27, P30–P37, ______
P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87, RESET, XIN, 0.8 VCC
CNVSS
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P3______
7, P40–P47,
0
P50–P57, P60–P67, P70–P77, P80–P87, RESET, CNVSS
“L” input voltage
XIN
0
“H” total peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
“H” total peak output current
P40–P47,P50–P57, P60–P67 (Note 1)
“L” total peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
“L” total peak output current
P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note 1)
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
“H” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
“H” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 3)
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)
Internal clock oscillation frequency (4.0 V VCC 5.5 V)
Internal clock oscillation frequency (2.7 V VCC 4.0 V)
V
V
VCC
0
AVSS
Unit
10
4.5VCC–8
MHz
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
3806 GROUP USER’S MANUAL
3-15
APPENDIX
3.1 Electrical characteristics
3.1.15 Electrical characteristics (High-speed version)
Table 3.1.25 Electrical characteristics (High-speed version) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87 (Note 1)
VOH
“L” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47,P50–P57,
P60–P67, P70–P77, P80–P87
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
Hysteresis
“H” input current
IIH
IIH
IIH
“H” input current
“H” input current
“L” input current
IIL
IIL
VRAM
ICC
“L” input current
RAM hold voltage
CNTR0, CNTR1, INT0–INT4
RXD, SCLK1, SIN2, SCLK2
______
RESET
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
______
RESET, CNVSS
XIN
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
______
RESET, CNVSS
XIN
Power source current
IOH = –10 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.7 to 5.5 V
IOL = 10 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 2.7 to 5.5 V
Min.
Limits
Typ.
Max.
VCC–2.0
V
VCC–1.0
2.0
V
1.0
0.4
0.5
0.5
VI = VCC
VI = VCC
VI = VCC
V
V
V
5.0
µA
5.0
µA
µA
–5.0
µA
4
VI = VSS
VI = VSS
With clock stopped
f(XIN) = 10 MHz, VCC = 5 V
f(XIN) = 4 MHz, VCC = 2.7 V
When WIT instruction is executed
with f(XIN) = 10 MHz, VCC = 5 V
When WIT instruction is executed
with f(XIN) = 4 MHz, VCC = 2.7 V
When STP instruction
Ta = 25 °C
is executed with clock (Note 2)
stopped, output
Ta = 85 °C
transistors isolated.
(Note 2)
Unit
–4
2.0
8
1.3
5.5
16
2
µA
V
mA
2
0.3
0.1
1
µA
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through V REF pin.
3.1.16 A-D converter characteristics (High-speed version)
Table 3.1.26 A-D converter characteristics (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
—
—
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference power source input current (Note)
A-D port input current
tCONV
RLADDER
IVREF
II(AD)
Test conditions
Limits
Typ.
±1
VREF = 5.0 V
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
3-16
Min.
3806 GROUP USER’S MANUAL
50
35
150
0.5
Max.
8
±2.5
50
200
5.0
Unit
Bits
LSB
tC(φ)
kΩ
µA
µA
APPENDIX
3.1 Electrical characteristics
3.1.17 D-A converter characteristics (High-speed version)
Table 3.1.27 D-A converter characteristics (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.7 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
—
—
tsu
RO
IVREF
Parameter
Test conditions
Min.
Limits
Typ.
Resolution
Absolute accuracy
VCC = 4.0 to 5.5 V
VCC = 2.7 to 5.5 V
Setting time
Output resistor
Reference power source input current (Note)
1
2.5
Max.
8
1.0
2.5
3
4
3.2
Unit
Bits
%
µs
kΩ
mA
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through the A-D resistance ladder.
3806 GROUP USER’S MANUAL
3-17
APPENDIX
3.1 Electrical characteristics
3.1.18 Timing requirements and Switching characteristics (High-speed version)
Table 3.1.28 Timing requirements (1) (High-speed version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
_____
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD–SCLK1)
tsu(SIN2–SCLK2)
th(SCLK1–RXD)
th(SCLK2–SIN2)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Min.
2
100
40
40
200
80
80
80
80
800
1000
370
400
370
400
220
200
100
200
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A 16 is “1”. Divide this value by four when f(X IN) = 8 MHz and bit 6 of address 001A 16 is “0”.
Table 3.1.29 Timing requirements (2) (High-speed version) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
_____
Parameter
tw(RESET)
Reset input “L” pulse width
tc(XIN)
External clock input cycle time
twH(XIN)
External clock input “H” pulse width
twL(XIN)
External clock input “L” pulse width
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD–SCLK1)
tsu(SIN2–SCLK2)
th(SCLK1–RXD)
th(SCLK2–SIN2)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Min.
2
1000/
(4.5 VCC–8)
400/
(4.5 VCC–8)
400/
(4.5 VCC–8)
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
300
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: When f(XIN) = 2 MHz and bit 6 of address 001A 16 is “1”. Divide this value by four when f(X IN) = 2 MHz and bit 6 of address 001A 16 is “0”.
3-18
3806 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
Table 3.1.30 Switching characteristics (1) (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
twH(SCLK1)
Serial I/O1 clock output “H” pulse width
tc(SCLK1)/2–30
ns
twL(SCLK1)
Serial I/O1 clock output “L” pulse width
tc(SCLK1)/2–30
ns
td(SCLK1–TXD)
Serial I/O1 output delay time (Note 1)
140
ns
Fig. 3.1.1
tv(SCLK1–TXD)
Serial I/O1 output valid time (Note 1)
–30
ns
tr(SCLK1)
Serial I/O1 clock output rising time
30
ns
tf(SCLK1)
Serial I/O1 clock output falling time
30
ns
twH(SCLK2)
Serial I/O2 clock output “H” pulse width
tc(SCLK2)/2–160
ns
twL(SCLK2)
Serial I/O2 clock output “L” pulse width
tc(SCLK2)/2–160
ns
td(SCLK2–SOUT2) Serial I/O2 output delay time
Fig. 3.1.2
200
ns
tv(SCLK2–SOUT2) Serial I/O2 output valid time
0
ns
tf(SCLK2)
Serial I/O2 clock output falling time
30
ns
tr(CMOS)
CMOS output rising time (Note 2)
10
30
ns
Fig. 3.1.1
tf(CMOS)
CMOS output falling time (Note 2)
10
30
ns
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
Table 3.1.31 Switching characteristics (2) (High-speed version)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Test conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Fig. 3.1.1
Min.
tc(SCLK1)/2–50
tc(SCLK1)/2–50
Limits
Typ.
Max.
350
–30
50
50
tc(SCLK2)/2–240
tc(SCLK2)/2–240
Fig. 3.1.2
400
0
Fig. 3.1.1
20
20
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
3806 GROUP USER’S MANUAL
3-19
APPENDIX
3.1 Electrical characteristics
Table 3.1.32 Timing requirements in memory expansion mode and microprocessor mode (1) (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
____
tsu(ONW–φ)
____
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
____ __
tsu(ONW–RD)
____ ___
tsu(ONW–WR)
__ ____
th(RD–ONW)
___ ____
th(WR–ONW)
__
tsu(DB–RD)
__
th(RD–DB)
Parameter
Min.
–20
–20
50
0
_____
Before φ ONW input set up time
_____
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
___ _____
Before RD
___ ONW
_____ input set up time
Before WR ONW input set up time
___ _____
After RD
___ ONW
_____ input hold time
After WR ONW input hold time
___
Before RD data bus set up time
___
After RD data bus hold time
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
25
–20
ns
–20
ns
50
0
25
ns
ns
Table 3.1.33 Switching characteristics in memory expansion mode and microprocessor mode (1) (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
After φ data bus delay time
After φ data bus valid time
___
___
__
RD pulse width, WR pulse width
___
___
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
(When one-wait is valid)
___
__
td(AH–RD)
After AD15–AD8 ___
RD delay time
___
td(AH–WR)
After AD15–AD8 WR delay time
___
__
td(AL–RD)
After AD7–AD0 ___
RD delay time
___
td(AL–WR)
After AD7–AD0 WR delay time
___
__
tv(RD–AH)
After ___
RD AD15–AD8 valid time
___
tv(WR–AH)
After WR AD15–AD8 valid time
___
__
tv(RD–AL)
After ___
RD AD7–AD0 valid time
___
tv(WR–AL)
After WR AD7–AD0 valid time
___
___
td(WR–DB)
After WR data bus delay time
___
___
tv(WR–DB)
After WR data bus valid time
_________
___ _____
td(RESET–RESETOUT) RESETOUT output delay time (Note 1)
_________
_____
tv(φ–RESET) RESETOUT output valid time (Note 1)
Min.
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–DB)
tv(φ–DB)
Limits
Typ.
2tc(XIN)
Max.
10
tc(XIN)–10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3tc(XIN)–10
ns
tc(XIN)–10
tc(XIN)–10
2
2
Fig. 3.1.1
_________
Unit
16
5
20
5
16
5
15
35
40
30
tc(XIN)–35
tc(XIN)–16
ns
tc(XIN)–40
tc(XIN)–20
ns
2
5
ns
2
5
ns
15
30
10
0
200
100
ns
ns
ns
ns
Note 1: The______
RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
3-20
3806 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
Table 3.1.34 Timing requirements in memory expansion mode and microprocessor mode (2) (High-speed version)
(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise
Limits
Symbol
Parameter
Min.
Typ.
Max.
_____
____
tsu(ONW–φ)
Before φ ONW input set up time
–20
_____
____
th(φ–ONW)
After φ ONW input hold time
–20
tsu(DB–φ)
Before φ data bus set up time
120
60
th(φ–DB)
After φ data bus hold time
0
___ _____
____ __
tsu(ONW–RD)
Before RD
___ ONW
_____ input set up time
____ ___
–20
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW)
After RD
___ ONW
_____ input hold time
___ ____
–20
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
Before RD data bus set up time
120
60
___
__
th(RD–DB)
After RD data bus hold time
0
noted)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Table 3.1.35 Switching characteristics in memory expansion mode and microprocessor mode (2) (High-speed version)
(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD15–AD8 valid time
AD7–AD0 delay time
AD7–AD0 valid time
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
___
___
__
RD pulse width, WR pulse width
___
___
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
(When one-wait is valid)
___
__
td(AH–RD)
After AD15–AD8 ___
RD delay time
___
td(AH–WR)
After AD15–AD8 WR delay time
___
__
td(AL–RD)
After AD7–AD0 ___
RD delay time
___
td(AL–WR)
After AD7–AD0 WR delay time
___
__
tv(RD–AH)
After ___
RD AD15–AD8 valid time
___
tv(WR–AH)
After WR AD15–AD8 valid time
___
__
tv(RD–AL)
After ___
RD AD7–AD0 valid time
___
tv(WR–AL)
After WR AD7–AD0 valid time
___
___
td(WR–DB)
After WR data bus delay time
___
___
tv(WR–DB)
After WR data bus valid time
_________
___ _____
td(RESET–RESETOUT) RESETOUT output delay time (Note 1)
_________
_____
tv(φ–RESET) RESETOUT output valid time (Note 1)
Min.
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–DB)
tv(φ–DB)
Limits
Typ.
2tc(XIN)
Max.
10
tc(XIN)–20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3tc(XIN)–20
ns
tc(XIN)–20
tc(XIN)–20
5
5
Fig. 3.1.1
Unit
40
10
50
10
40
10
30
100
100
80
tc(XIN)–100
tc(XIN)–40
ns
tc(XIN)–100
tc(XIN)–50
ns
5
10
ns
5
10
ns
30
80
10
300
150
0
ns
ns
ns
ns
_________
Note 1: The______
RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
Measurement output pin
1kΩ
100pF
Measurement output pin
100pF
CMOS output
N-channel open-drain output
Fig. 3.1.1 Circuit for measuring output switching
characteristics (1)
Fig. 3.1.2 Circuit for measuring output switching
characteristics (2)
3806 GROUP USER’S MANUAL
3-21
APPENDIX
3.1 Electrical characteristics
3.1.19 Timing diagram
Timing Diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8 VCC
CNTR0, CNTR1
0.2 VCC
tWL(INT)
tWH(INT)
0.8 VCC
INT0–INT4
0.2 VCC
tW(RESET)
RESET
0.8 VCC
0.2 VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8 VCC
XIN
tC(SCLK1), tC(SCLK2)
tWL(SCLK1), tWL(SCLK2)
tWH(SCLK1), tWH(SCLK2)
tr
tf
SCLK1
SCLK2
0.2 VCC
0.8 VCC
0.2 VCC
tsu(RXD-SCLK1),
tsu(SIN2-SCLK2)
RXD
SIN2
th(SCLK1-RXD),
th(SCLK2- SIN2)
0.8 VCC
0.2 VCC
td(SCLK1-TXD),td(SCLK2-SOUT2)
TX D
SOUT2
Fig. 3.1.3 Timing diagram (in single-chip mode)
3-22
3806 GROUP USER’S MANUAL
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1)
tC(φ)
tWL(φ)
tWH(φ)
φ
0.5 VCC
tv(φ-AH)
td(φ-AH)
AD15–AD8
0.5 VCC
td(φ-AL)
AD7–AD0
tv(φ-AL)
0.5 VCC
tv(φ-SYNC)
td(φ-SYNC)
SYNC
0.5 VCC
td(φ-WR)
RD,WR
tv(φ-WR)
0.5 VCC
th(φ-ONW)
tSU(ONW-φ)
0.8 VCC
0.2 VCC
ONW
tSU(DB-φ)
th(φ-DB)
0.8 VCC
0.2 VCC
DB0–DB7
(At CPU reading)
td(φ-DB)
DB0–DB7
(At CPU writing)
tv(φ-DB)
0.5 VCC
Timing Diagram in Microprocessor Mode
RESET
0.8 VCC
0.2 VCC
φ
0.5 VCC
td(RESET- RESET OUT)
RESETOUT
tv(φ- RESET OUT)
0.5 VCC
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (1)
3806 GROUP USER’S MANUAL
3-23
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2)
tWL(RD)
tWL(WR)
RD,WR
0.5 VCC
td(AH-RD)
td(AH-WR)
AD15–AD8
tv(RD-AH)
tv(WR-AH)
0.5 VCC
td(AL-RD)
td(AL-WR)
AD7–AD0
tv(RD-AL)
tv(WR-AL)
0.5 VCC
th(RD-ONW)
th(WR-ONW)
tsu(ONW-RD)
tsu(ONW-WR)
ONW
0.8 VCC
0.2 VCC
(At CPU reading)
tWL(RD)
RD
0.5 VCC
tSU(DB-RD)
DB0–DB7
(At CPU writing)
tWL(WR)
WR
0.5 VCC
tv(WR-DB)
td(WR-DB)
DB0–DB7
0.5 VCC
Fig. 3.1.5 Timing diagram (in memory expansion mode and microprocessor mode) (2)
3-24
th(RD-DB)
0.8 VCC
0.2 VCC
3806 GROUP USER’S MANUAL
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current characteristic examples
Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples.
[Measuring condition : 25 °C, A-D conversion stopped]
Rectangular waveform
Power source current
9
(mA)
Vcc = 5.5 V, Ta = 25 °C
8
7
6
Vcc = 4.0 V, Ta = 25 °C
5
4
3
2
Vcc = 2.7V, Ta = 25 °C
1
0
0
1
2
3
4
5
6
7
8
9
10
Frequency f(X IN) (MHz)
Fig. 3.2.1 Power source current characteristic example
[Measuring condition : 25 °C, A-D conversion stopped]
Rectangular waveform
Power source current
(mA) 9
8
7
6
5
4
3
2
Vcc = 5.5 V, Ta = 25 °C
Vcc = 4.0 V, Ta = 25 °C
1
0
Vcc = 2.7 V, Ta = 25 °C
0
1
2
3
4
5
6
7
8
9
10
Frequency f(X IN) (MHz)
Fig. 3.2.2 Power source current characteristic example (in wait mode)
3806 GROUP USER’S MANUAL
3-25
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristic examples
Figures 3.2.3, Figure 3.2.4, Figure 3.2.5 and Figure 3.2.6 show port standard characteristic examples.
[Port P0 0 I OH–VOH characteristic (P-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P8)
IOH
(mA)
–50
–45
–40
Vcc = 5.0 V
Ta = 85 °C
–35
–30
Vcc = 4.0 V
Ta = 85 °C
–25
–20
Vcc = 2.7 V
Ta = 85 °C
–15
–10
–5
0
0 0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOH (V)
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1)
[Port P0 0 IOH –V OH characteristic (P-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P8)
IOH
(mA)
–50
–45
Vcc = 5.0 V
Ta = 25 °C
–40
–35
Vcc = 4.0 V
Ta = 25 °C
–30
–25
Vcc = 2.7 V
Ta = 25 °C
–20
–15
–10
–5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOH (V)
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2)
3-26
3806 GROUP USER’S MANUAL
APPENDIX
3.2 Standard characteristics
[Port P00 I OL–V OL characteristic (N-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7, P8)
IOL
(mA)
50
45
Vcc = 5.0 V
Ta = 85 °C
40
35
30
Vcc = 4.0 V
Ta = 85 °C
25
20
15
Vcc = 2.7 V
Ta = 85 °C
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOL (V)
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1)
[Port P00 I OL–V OL characteristic (N-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7, P8)
IOL
(mA)
50
Vcc = 5.0 V
Ta = 25 °C
45
40
35
Vcc = 4.0 V
Ta = 25 °C
30
25
20
15
Vcc = 2.7 V
Ta = 25 °C
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V OL (V)
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2)
3806 GROUP USER’S MANUAL
3-27
APPENDIX
3.2 Standard characteristics
3.2.3 A-D conversion standard characteristics
Figure 3.2.7 shows the A-D conversion standard characteristics.
The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the
ideal value. For example, the conversion of output code from 0 to 1 occurs ideally at the point of AN0 =
10 mV, but the measured value is 0 mV. Accordingly, the measured point of conversion is represented as
“10 – 0 = 10 mV.”
The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For
example, the measured width of the input voltage for output code 13 is 22 mV, so the differential nonlinear
error is represented as “22 – 20 = 2 mV” (0.1 LSB).
A-D CONVERTER STEP WIDTH MEASUREMENT
V CC = 5.12 [ V ] , V REF = 5.12 [ V ]
XIN = 4.80 [ MH Z ] , ANALOG Port P6 0
Temp. = 25deg.
30
20
20+1LSB
10
10
0
0
– 10
Absolute precision error
–1LSB
– 20
0
8
16
24
32
40
48
56
64
STEP No.
72
80
88
96
104
112
120
128
30
30
20
20 +1LSB
10
10
0
0
– 10
–1LSB
– 20
– 30
128
1LSB WI DTH [mV]
ERROR [mV]
– 30
1LSB WI DTH [mV]
ERROR [mV]
1LSB WIDTH
30
136
144
152
160
168
176
184
192
200
STEP No.
208
216
224
232
240
248
256
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode
Fig. 3.2.7 A-D conversion standard characteristics
3-28
3806 GROUP USER’S MANUAL
APPENDIX
3.2 Standard characteristics
3.2.4 D-A conversion standard characteristics
Figure 3.2.8 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates
the absolute precision error. In this case, it represents the difference between the ideal analog output value
for an input code and the measured value.
The upper-side line on the graph indicates the change width of output analog value to a one-bit change
of input code.
D-A CONVERTER STEP WIDTH MEASUREMENT
V CC = 5.12 [ V ] , V REF = 5.12 [ V ]
X IN = 4.80 [ MH Z ] , ANALOG OUTPUT
Temp. = 25deg.
DA
30
20
20 +1LSB
10
10
0
0
– 10
Absolute precision error
–1LSB
– 20
0
8
16
24
32
40
48
56
64
STEP No.
72
80
88
96
104
112
120
128
30
30
20
20 +1LSB
10
10
0
0
– 10
–1LSB
– 20
– 30
128
1LSB WI DTH [mV]
ERROR [mV]
– 30
1LSB WI DTH [mV]
ERROR [mV]
1LSB WIDTH
30
136
144
152
160
168
176
184
192
200
STEP No.
208
216
224
232
240
248
256
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode
Fig. 3.2.8 D-A conversion standard characteristics
3806 GROUP USER’S MANUAL
3-29
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Sequence for switching an external interrupt
detection edge
When the external interrupt detection edge must be
switched, make sure the following sequence.
Reason
The interrupt circuit recognizes the switching of the
detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Bit 7 of the interrupt control register 2
Fix the bit 7 of the interrupt control register 2
(Address:003F16) to “0”.
Clear an interrupt enable bit to “0” (interrupt disabled)
Switch the detection edge
Clear an interrupt request bit to “0” (no interrupt request issued)
Set the interrupt enable bit to “1” ( interrupt enabled )
b7
0
b0
Interrupt control register 2
Address 003F16
Figure 3.3.1 shows the structure of the interrupt
control register 2.
Interrupt enable bits
Not used
Fix this bit to “0”
Fig. 3.3.1 Structure of interrupt control register 2
3.3.2 Notes on the serial I/O1
(1) Stop of data transmission
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the transmit enable bit to “0” (transmit disabled), and clear the serial I/O enable bit to “0” (serial I/O1 disabled)in
the following cases :
● when stopping data transmission during transmitting data in the clock synchronous serial I/O mode
● when stopping data transmission during transmitting data in the UART mode
● when stopping only data transmission during transmitting and receiving data in the UART mode
Reason
Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit
is cleared
to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1,
______
and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer
register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial
I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and ti may cause
an operation failure to a microcomputer.
(2) Stop of data reception
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled) in the
following case :
● when stopping data reception during receiving data in the clock synchronous serial I/O mode
Clear the receive enable bit to “0” (receive disabled) in the following cases :
● when stopping data reception during receiving data in the UART mode
● when stopping only data reception during transmitting and receiving data in the UART mode
3-30
3806 GROUP USER’S MANUAL
APPENDIX
3.3 Notes on use
(3) Stop of data transmission and reception in a clock synchronous serial I/O mode
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at the same time in the
following case:
● when stopping data transmission and reception during transmitting and receiving data in the clock synchronous
mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of
transmission and reception is disabled, a bit error occurs because transmission and reception cannot be
synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the
transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the
transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O1 disabled) (refer to (1)).
_____
(4) The SRDY pin on a receiving side _____
When signals are output from the SRDY pin on the reception_____
side by using an external clock in the clock
synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable
bit to “1” (transmit enabled).
(5) Stop of data reception in a clock synchronous
serial I/O mode
Set the serial I/O1 control register again after the
transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive
enable bit to “0.”
Clear both the transmit
enable bit (TE) and the
receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of
the serial I/O1 control
register
Set both the transmit enable
bit (TE) and the receive
enable bit (RE) to “1”
Can be set with the
LDM instruction at
the same time
(6) Control of data transmission using the transmit shift completion flag
The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When checking
the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data
transmission, note this delay.
(7) Control of data transmission using an external clock
When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1”
at “H” level of the SCLK input signal. Also, write data to the transmit buffer register at “H” level of the SCLK input
signal.
3.3.3 Notes on the A-D converter
(1) Input of signals from signal source with high impedance to an analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor
of 0.01 µF to 1 µF. Further, maek sure to check the operation of application products on the user side.
Reason
The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal
source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may
cause the A-D conversion precision to be worse.
3806 GROUP USER’S MANUAL
3-31
APPENDIX
3.3 Notes on use
(2) AVSS pin
Connect a power source for the A-D converter, AVSS pin to the VSS line of the analog circuit.
(3) A clock frequency during an A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is
too low. Thus, make sure the following during an A-D conversion.
● f(XIN) is 500 kHz or more .
(When the ONW pin is "L", f(XIN) is 1 MHz or more.)
● Do not execute the STP instruction and WIT instruction.
3.3.4 Notes on the RESET pin
When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and
the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make
sure the following :
●Make the length of the wiring which is connected to a capacitor the shortest possible.
●Make sure to check the operation of application products on the user side.
Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may
malfunction.
3.3.5 Notes on input and output pins
(1) Fix of a port input level in stand-by state
Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state, especially
for the I/O ports of the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.
When determining a resistance value, make sure the following:
●External circuit
●Variation of output levels during the ordinary operation
* stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
Reason
Even when setting as an output port with its direction register, in the following state :
●N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the
level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input and an I/O port are “undefined.” This may cause power source current.
(2) Modify of the content of I/O port latch
When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the
unspecified bit may be changed.
Reason
The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit.
Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed
to all bits of the port latch.
●As for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit
managing.
●As for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit
managing.
3-32
3806 GROUP USER’S MANUAL
APPENDIX
3.3 Notes on use
Make sure the following :
●Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
●Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction,
its value may be changed in case where content of the pin differs from a content of the port latch.
* bit managing instructions : SEB and CLB instruction
(3) The AVSS pin when not using the A-D converter
When not using the A-D converter, handle a power source pin for the A-D converter, AVSS pin as follows :
● AVSS : Connect to the VSS pin
Reason
If the AVSS pin is opened, the microcomputer may malfunction by effect of noise or others.
3.3.6 Notes on memory expansion mode and microprocessor mode
(1) Writing data to the port latch of port P3
In the memory expansion or the microprocessor mode, ports P30 and P31 can be used as the output port. Use the
LDM or STA instruction for writing data to the port latch (address 000616) of port P3.
When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write
enabled memory at address 000616.
Reason
In the memory expansion or microprocessor mode, address 000616 is allocated in the external area.
Accordingly,
● Data is read from the external memory.
● Data is written to both the port latch of the port P3 and the external memory.
Accordingly, when executing a read-modify-write instruction for address 000616, external memory data is read and
modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled
memory is not allocated at address 000616, the read data is undefined. The undefined data is modified and written
to the port latch of the port P3. The port latch data of port P3 becomes “undefined.”
(2) Overlap of an internal memory and an external memory
When the internal and the external memory are overlapped in the memory expansion mode, the internal memory
is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed :
● When reading data
Only the data in the internal memory is read into the CPU and the data in the external memory is not read into
the CPU. However, as the read signal and address are still valid, the external memory data of the
corresponding address is output to the external data bus.
● When writing data
Data is written in both the internal and the external memory.
3806 GROUP USER’S MANUAL
3-33
APPENDIX
3.3 Notes on use
3.3.7 Notes on built-in PROM
(1) Programming adapter
To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose
PROM programmer as shown in Table 3.3.1.
Table 3.3.1 Programming adapter
Microcomputer
Programming adapter
M38063E6FS
PCA4738L-80A
PROM mode
M38063E6FP
PCA4738F-80A
(one-time blank)
M38063E6GP
256K
PCA4738G-80A
(one-time blank)
M38067ECAFS
PCA4738L-80A
M38067ECFP
(one-time blank)
M38067ECDFP
PCA4738F-80A
(one-time blank)
1M
M38067ECAFP
(one-time blank)
M38067ECGP
(one-time blank)
PCA4738G-80A
M38067ECAGP
(one-time blank)
(2) Write and read
In PROM mode, operation is the same as that of the M5M27C256AK and the M5M27C101, but programming
conditions of PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as
the CNVSS pin), or the product may be permanently damaged.
● Programming voltage : 12.5 V
● Setting of programming adapter switch : refer to table 3.3.2
● Setting of PROM programmer address : refer to table 3.3.3
Table 3.3.2 Setting of programming adapter switch
Programming adapter
SW 1
SW 2
SW 3
CMOS
CMOS
OFF
PCA4738F-80A
PCA4738L-80A
PCA4738G-80A
3-34
3806 GROUP USER’S MANUAL
APPENDIX
3.3 Notes on use
Table 3.3.3 Setting of PROM programmer address
Microcomputer
PROM programmer start address
PROM programmer completion address
Address : 208016 (Note 1)
Address : 7FFD16 (Note 1)
Address : 408016 (Note 2)
Address : FFFD16 (Note 2)
M38063E6FS
M38063E6FP
M38063E6GP
M38067ECFP
M38067ECGP
M38067ECDFP
M38067ECAFS
M38067ECAFP
M38067ECAGP
Note1 : Addresses A08016 to FFFD16 in the internal PROM correspond to addresses 208016 to 7FFD16 in the
ROM programmer.
2 : Addresses 408016 to FFFD16 in the internal PROM correspond to addresses 4080 16 to FFFD16 in the
ROM programmer.
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537Angstrom . At least 15 W-sec/cm 2 are required to erase EPROM contents.
3806 GROUP USER’S MANUAL
3-35
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in
theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for the RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor
across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm).
Reason
The reset works to initialize a microcomputer.
The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having
a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state
of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset
circuit
RESET
VSS
N.G.
Reset
circuit
RESET
VSS
VSS
VSS
3806 group
O.K.
3806 group
Fig. 3.4.1 Wiring for the RESET pin
(2) Wiring for clock input/output pins
●Make the length of wiring which is connected to clock I/O pins as short as possible.
●Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an
oscillatorand the VSS pin of a microcomputer as short as possible.
●Separate the VSS pattern only for oscillation from other VSS patterns.
Reason
A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock
I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway.
Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level
of an oscillator, the correct clock will not be input in the microcomputer.
3-36
3806 GROUP USER’S MANUAL
APPENDIX
3.4 Countermeasures against noise
An example of V SS patterns on the
underside of a printed circuit board
Noise
Oscillator wiring
pattern example
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
XIN
XOUT
VSS
O.K.
Separate the V SS line for oscillation from other V SS lines
Fig. 3.4.2 Wiring for clock I/O pins
(3) Wiring for the VPP pin of the One Time PROM
version and the EPROM version
(In this microcomputer the VPP pin is also used
as the CNVSS pin)
Connect an approximately 5 kΩ resistor to theV P P
pin the shortest possible in series and also to the VSS
pin. When not connecting the resistor, make the
length of wiring between the VPP pin and the VSS pin
the shortest possible.
Approximately
5kΩ
CNVSS/VPP
VSS
Note:Even when a circuit which inclued an
approximately 5 kΩ resistor is used in the Mask ROM
version, the maicrocomputer operates correctly.
Reason
The VPP pin of the One Time PROM and the EPROM
version is the power source input pin for the built-in
PROM. When programming in the built-in PROM,
the impedance of the VPP pin is low to allow the
electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters
the VPP pin, abnormal in struction codes or data are
read from the built-in PROM, which may cause a
program runaway.
3806 group
Make it the shortest possible
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM
and the EPROM version
3.4.2 Connection of a bypass capacitor across the
Vss line and the Vcc line
Connect an approximately 0.1 µF bypass capacitor
across the VSS line and the VCC line as follows:
●Connect a bypass capacitor across the VSS pin
and the VCC pin at equal length .
●Connect a bypass capacitor across the VSS pin
and the VCC pin with the shortest possible wiring.
●Use lines with a larger diameter than other signal
lines for VSS line and VCC line.
VCC
Chip
VCC
VSS
VSS
Fig. 3.4.4 Bypass capacitor across the VSS line and
the VCC line
3806 GROUP USER’S MANUAL
3-37
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
●Connect an approximately 100 Ω to 1 kΩ resistor to an
analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to
the microcomputer as close as possible.
●Connect an approximately 1000 pF capacitor across
the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as
possible. Also, connect the capacitor across the
analog input pin and the VSS pin at equal length.
Reason
Signals which is input in an analog input pin (such as
an A-D converter input pin) are usually output signals
from sensor. The sensor which detects a change of
event is installed far from the printed circuit board
with a microcomputer, the wiring to an analog input
pin is longer necessarily. This long wiring functions
as an antenna which feeds noise into the
microcomputer, which causes noise to an analog
input pin.
3.4.4. Consideration for oscillator
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
Noise
(Note)
N.G.
3-38
O.K.
VSS
Note:The resistor is for dividing resistance
with a thermister.
Fig.3.4.5 Analog signal line and a resistor and a
capacitor
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig.3.4.6 Wiring for a large current signal line
(2) Keeping an oscillator away from signal lines
where potential levels change frequently
Install an oscillator and a connecting pattern of an
osillator away from signal lines where potential levels
change frequently. Also, do not cross such signal
lines over the clock lines or the signal lines which are
sensitive to noise.
Reason
Signal lines where potential levels change frequently
(such as the CNTR pin line) may affect other lines at
signal rising or falling edge. If such lines cross over
a clock line, clock waveforms may be deformed,
which causes a microcomputer failure or a program
runaway.
Analog
input pin
Thermistor
(1) Keeping an oscillator away from large current
signal lines
Install a microcomputer (and especially an oscillator)
as far as possible from signal lines where a current
larger than the tolerance of current value flows.
Reason
In the system using a microcomputer, there are
signal lines for controlling motors, LEDs, and thermal
heads or others. When a large current flows through
those signal lines, strong noise occurs because of
mutual inductance.
Microcomputer
Do not cross
CNTR
XIN
XOUT
VSS
Fig.3.4.7 Wiring to a signal line where potential levels
change frequently
3806 GROUP USER’S MANUAL
APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
●Connect a resistor of 100 Ω or more to an I/O port
inseries.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
<Software>
Port latch
●As for an input port, read data several times by a
program for checking whether input levels are
I/O port
pins
equal or not.
●As for an output port, since the output data may
reverse because of noise, rewrite data to its port
latch at fixed periods.
Fig. 3.4.8 Setup for I/O ports
●Rewirte data to direction registers and pull-up
control registers (only the product having it) at fixed
periods.
When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be
output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.
3.4.6 Providing of watchdog timer function by
software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
In the following example, to reset a microcomputer to
normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt
processing routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
N
(SWDT)
=N?
≤0
RTI
Return
=N
Interrupt processing
>0
Main routine
routine errors
errors
<The main routine>
●Assigns a single byte of RAM to a software watchdog
timer (SWDT) and writes the initial value N in the
SWDT once at each execution of the main routine.
Fig. 3.4.9 Watchdog timer by software
The initial value N should satisfy the following
condition:
N+1 ≥ (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N
should have a margin.
●Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of
interrupt processing count after the initial value N has been set.
●Detects that the interrupt processing routine has failed and determines to branch to the program initialization
routine for recovery processing in the following cases:
If the SWDT contents do not change after interrupt processing
3806 GROUP USER’S MANUAL
3-39
APPENDIX
3.4 Countermeasures against noise
<The interrupt processing routine>
●Decrements the SWDT contents by 1 at each interrupt processing.
●Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at
almost fixed cycles (at the fixed interrupt processing count).
●Detects that the main routine has failed and determines to branch to the program initialization routine for recovery
processing in the following case:
When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value
N.
3-40
3806 GROUP USER’S MANUAL
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016]
B
Name
0 Port Pi0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16, 1116]
B
Function
Name
At reset
R W
0 Port Pi direction register
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0
✕
1
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0
✕
0
✕
0
✕
0
✕
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
✕
0
✕
0
✕
2
3
4
5
6
7
Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
3806 GROUP USER’S MANUAL
3-41
APPENDIX
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816]
Function
B
At reset
0 A transmission data is written to or a receive data is read out
from this buffer register.
1 • At writing : a data is written to the transmit buffer register.
• At reading : a content of the receive buffer register is read out.
R W
?
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 3.5.3 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status reigster (SIO1STS) [Address : 1916]
Name
B
Transmit
buffer
empty flag
0
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE)
4 Parity error flag (PE)
5 Framing error flag (FE)
6 Summing error flag (SE)
Function
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0
R W
✕
0
✕
0
✕
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
0
✕
0
✕
0 : No error
1 : Framing error
0 : (OE) (PE) (FE) = 0
1 : (OE) (PE) (FE) = 1
0
✕
0
✕
1
✕
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is “0.”
Fig. 3.5.4 Structure of Serial I/O1 status register
3-42
3806 GROUP USER’S MANUAL
At reset
APPENDIX
3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
0
1
Name
BRG count source
selection bit (CSS)
Serial I/O1
synchronous clock
selection bit (SCS)
Function
At reset
0 : f(XIN)
1 : f(XIN)/4
0
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
0
R W
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
3
SRDY1 output enable bit
(SRDY)
Transmit interrupt
source selection bit
(TIC)
4
Transmit enable bit (TE)
5
Receive enable bit (RE)
6
Serial I/O1 mode
selection bit (SIOM)
7
Serial I/O1 enable bit
(SIOE)
2
0 : I/O port (P47)
1 : SRDY1 output pin
0 : Transmit buffer empty
1 : Transmit shift operating
completion
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : UART
1 : Clock synchronous serial I/O
0
0 : Serial I/O1 disabled
(P44–P47 : I/O port)
1 : Serial I/O1 enabled
(P44–P47 : Serial I/O function pin)
0
0
0
0
0
Fig. 3.5.5 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
Name
B
Character
length
0
selection bit (CHAS)
1 Parity enable bit
2
3
4
5
6
7
Function
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
(PARE)
Parity selection bit
(PARS)
Stop bit length selection
bit (STPS)
P45/TxD P-channel
output disable bit
(POFF)
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
At reset
R W
0
0
0
0
0
1
1
1
✕
✕
✕
Fig. 3.5.6 Structure of UART control register
3806 GROUP USER’S MANUAL
3-43
APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16]
Function
B
At reset
0 A count value of Baud rate generator is set.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 3.5.7 Structure of Baud rate generator
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 1D16]
Name
B
Internal
synchronous
0
clock selection bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8
1 : f(XIN)/16
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
0 : I/O port (P71, P72)
1 : SOUT2, SCLK2 output pin
0 : I/O port (P73)
SRDY2 output enable bit
1 : SRDY2 output pin
0 : LSB first
Transfer direction
1 : MSB first
selection bit
Serial I/O2 synchronous clock 0 : External clock
1 : Internal clock
selection bit
Nothing is allocated for this bit. This is write disabled bit. When
this bit is read out, the value is “0.”
0
0
0
4
0
6
7
Fig. 3.5.8 Structure of Serial I/O2 control register
3806 GROUP USER’S MANUAL
R W
0
3 Serial I/O2 port selection bit
5
3-44
At reset
0
0
0
✕
APPENDIX
3.5 List of registers
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
Function
B
At reset
0 A shift register for serial transmission and reception.
?
At transmitting : Set a transmission data.
● At receiving : Store a reception data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
●
Fig. 3.5.9 Structure of Serial I/O2 register
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
[Address : 2016, 2416, 2616]
B
0
1
2
Function
●
●
●
The count value of each prescaler is set.
The value set in this register is written to both the prescaler and
the prescaler latch at the same time.
When the prescaler is read out, the value (count value) of the
prescaler is read out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y
3806 GROUP USER’S MANUAL
3-45
APPENDIX
3.5 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116]
B
0
●
●
1
●
2
Function
At reset
The count value of the Timer 1 is set.
The value set in this register is written to both the Timer 1 and
the Timer 1 latch at the same time.
When the Timer 1 is read out, the value (count value) of the
Timer 1 is read out.
1
R W
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.5.11 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX), Timer Y (TY)
[Address : 2216, 2516, 2716]
B
0
Function
●
●
1
2
●
The count value of each timer is set.
The value set in this register is written to both the Timer and the
Timer latch at the same time.
When the Timer is read out, the value (count value) of the Timer
is read out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y
3-46
At reset
3806 GROUP USER’S MANUAL
R W
APPENDIX
3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 23 16]
Name
B
0 Timer X operating mode
1
2 CNTR 0 active edge switch
bit
3 Timer X count stop bit
4 Timer Y operating mode
5
6 CNTR 1 active edge switch
bit
7 Timer Y count stop bit
Function
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer X (refer to Table 3.5.1).
0 : Count start
1 : Count stop
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer Y (refer to Table 3.5.1 ).
0 : Count start
1 : Count stop
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.13 Structure of Timer XY mode register
Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit
Operating mode of
Timer X/Timer Y
Timer mode
Function of CNTR 0/CNTR 1 edge switch bit (bits 2 and 6)
“0”
“1”
Pulse output mode
“0”
“1”
Event counter mode
“0”
“1”
Pulse width measurement mode
“0”
“1”
• Generation of CNTR0/CNTR1 interrupt request : Falling
(No effect on timer count)
• Generation of CNTR 0/CNTR1 interrupt request : Rising
(No effect on timer count)
• Start of pulse output : From “H” level
• Generation of CNTR0/CNTR1 interrupt request : Falling
• Start of pulse output : From “L” level
• Generation of CNTR 0/CNTR1 interrupt request : Rising
• Timer X/Timer Y : Count of rising edge
• Generation of CNTR0/CNTR1 interrupt request : Falling
• Timer X/Timer Y : Count of falling edge
• Generation of CNTR0/CNTR1 interrupt request : Rising
• Timer X/Timer Y : Measurement of “H” level width
• Generation of CNTR0/CNTR1 interrupt request : Falling
• Timer X/Timer Y : Measurement of “L” level width
• Generation of CNTR 0/CNTR1 interrupt request : Rising
3806 GROUP USER’S MANUAL
edge
edge
edge
edge
edge
edge
edge
edge
3-47
APPENDIX
3.5 List of registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register (ADCON) [Address : 34 16]
B
0 Analog input pin selection bits
1
2
3
4
5
6
7
Function
Name
b2 b1 b0
0 0 0 : P6 0/AN0
0 0 1 : P6 1/AN1
0 1 0 : P6 2/AN2
0 1 1 : P6 3/AN3
1 0 0 : P6 4/AN4
1 0 1 : P6 5/AN5
1 1 0 : P6 6/AN6
1 1 1 : P6 7/AN7
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
0 : DA 1 output disable
DA1 output enable bit
1 : DA 1 output enable
0
: DA 2 output disabled
DA2 output enable bit
1 : DA 2 output enabled
At reset
R W
0
0
0
1
0
0
0
✕
✕
0
Fig. 3.5.14 Structure of AD/DA control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address : 3516]
B
Function
0 The read-only register which A-D conversion results are stored.
1
2
3
4
5
6
7
Fig. 3.5.15 Structure of A-D conversion register
3-48
3806 GROUP USER’S MANUAL
At reset
?
?
?
?
?
?
?
?
R W
✕
✕
✕
✕
✕
✕
✕
✕
APPENDIX
3.5 List of registers
D-A1 conversion register, D-A2 conversion register
b7 b6 b5 b4 b3 b2 b1 b0
D-A1 conversion register (DA1), D-A2 conversion register (DA2)
[Address : 36 16, 3716]
B
0
Function
At reset
An output value of each D-A converter is set.
R W
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.5.16 Structure of D-A 1 conversion, D-A 2 conversion register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name
B
0 INT0 interrupt edge
1
2
3
4
5
6
7
Function
0 : Falling edge active
1 : Rising edge active
selection bit
INT1 interrupt edge
0 : Falling edge active
1 : Rising edge active
selection bit
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
INT2 interrupt edge
0 : Falling edge active
1 : Rising edge active
selection bit
0 : Falling edge active
INT3 interrupt edge
1 : Rising edge active
selection bit
0 : Falling edge active
INT4 interrupt edge
1 : Rising edge active
selection bit
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “0.”
At reset
R W
0
0
0
✕
0
0
0
0
0
✕
✕
Fig. 3.5.17 Structure of Interrupt edge selection register
3806 GROUP USER’S MANUAL
3-49
APPENDIX
3.5 List of registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16]
Name
B
0 Processor mode bits
1
2 Stack page selection bit
3
4
5
6
7
Function
00 :Single-chip mode
01 :Memory expansion mode
10 :Microprocessor mode
11 :Not available
0 :0 page
1 :1 page
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
✻ An initial value of bit 1 is determined by a level of the CNVSS pin.
Fig. 3.5.18 Structure of CPU mode register
3-50
3806 GROUP USER’S MANUAL
At reset
R W
0
✻
0
0
0
0
0
0
✕
✕
✕
✕
✕
APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C 16]
Function
Name
B
0 INT0 interrupt request bit
1 INT 1 interrupt request bit
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit interrupt
request bit
4 Timer X interrupt request
bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
At reset
R W
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0
✻
✻ “0” is set by software, but not “1.”
Fig. 3.5.19 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D 16]
Name
B
0 CNTR 0 interrupt request bit
1 CNTR 1 interrupt request bit
2 Serial I/O2 interrupt request
bit
3 INT 2 interrupt request bit
4 INT 3 interrupt request bit
5 INT 4 interrupt request bit
6 AD conversion interrupt
request bit
Function
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
At reset
R W
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✕
✻ “0” is set by software, but not “1.”
Fig. 3.5.20 Structure of Interrupt request register 2
3806 GROUP USER’S MANUAL
3-51
APPENDIX
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
Name
B
0 INT0 interrupt enable bit
1 INT 1 interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
3 Serial I/O1 transmit interrupt
enable bit
Timer
X interrupt enable bit
4
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.21 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name
B
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
2 Serial I/O2 interrupt enable bit 0 : Interrupt disabled
0
3 INT 2 interrupt enable bit
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
4 INT 3 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
5 INT 4 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 CNTR 0 interrupt enable bit
1 CNTR 1 interrupt enable bit
6 AD conversion interrupt
enable bit
7 Fix this bit to “0.”
Fig. 3.5.22 Structure of Interrupt control register 2
3-52
At reset
3806 GROUP USER’S MANUAL
0
0
0
R W
APPENDIX
3.6 Mask ROM ordering method
3.6 Mask ROM ordering method
GZZ-SH03-63B<07B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38062M3-XXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38062M3-XXXFP
Microcomputer name :
M38062M3-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
507F16
508016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38062M3–’
data
ROM 12158 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address D08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
D07F16
D08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38062M3–’
data
ROM 12158 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38062M3–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘3’ = 3316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-53
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH03-63B<07B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38062M3-XXXFP/GP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE
‘M38062M3–’
*= $0000
.BYTE
‘M38062M3–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38062M3-XXXFP, 80P6S for M38062M3-XXXGP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-54
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-80B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38062M3DXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
507F16
508016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38062M3D’
data
ROM 12158 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address D08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
D07F16
D08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38062M3D’
data
ROM 12158 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38062M3D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘3’ = 3316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘D’ = 4416
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-55
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-80B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38062M3DXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE
‘M38062M3D’
*= $0000
.BYTE
‘M38062M3D’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38062M3DXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-56
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-26B<13B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38062M4-XXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38062M4-XXXFP
Microcomputer name :
M38062M4-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38062M4–’
data
ROM 16254 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
C07F16
C08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38062M4–’
data
ROM 16254 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38062M4–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘4’ = 3416
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-57
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-26B<13B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38062M4-XXXFP/GP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE
‘M38062M4–’
*= $0000
.BYTE
‘M38062M4–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38062M4-XXXFP, 80P6S for M38062M4-XXXGP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-58
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-81B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38062M4DXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38062M4D’
data
ROM 16254 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
C07F16
C08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38062M4D’
data
ROM 16254 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38062M4D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘4’ = 3416
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘D’ = 4416
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-59
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-81B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38062M4DXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE
‘M38062M4D’
*= $0000
.BYTE
‘M38062M4D’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38062M4DXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-60
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH03-26B<9ZC0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38063M6-XXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38063M6-XXXFP
Microcomputer name :
M38063M6-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38063M6–’
data
ROM 24446 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38063M6–’
data
ROM 24446 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38063M6–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘3’ = 3316
‘M’ = 4D16
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-61
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH03-26B<9ZC0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38063M6-XXXFP/GP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE
‘M38063M6–’
*= $0000
.BYTE
‘M38063M6–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38063M6-XXXFP, 80P6S for M38063M6-XXXGP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-62
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-64B<36B0>
Mask ROM number
SINGLE-CHIP MICROCOMPUTER M38063M6AXXXFP/GP/HP
MITSUBISHI ELECTRIC
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38063M6AXXXFP
Microcomputer name :
M38063M6AXXXGP
M38063M6AXXXHP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38063M6A’
data
ROM 24446 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38063M6A’
data
ROM 24446 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38063M6A”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘3’ = 3316
‘M’ = 4D16
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘A’ = 4116
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-63
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-64B<36B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38063M6AXXXFP/GP/HP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE
‘M38063M6A’
*= $0000
.BYTE
‘M38063M6A’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38063M6AXXXFP, 80P6S for M38063M6AXXXGP, 80P6D for M38063M6AXXXHP) and
attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-64
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-72B<15A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38063M6DXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38063M6D’
data
ROM 24446 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38063M6D’
data
ROM 24446 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38063M6D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘3’ = 3316
‘M’ = 4D16
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘D’ = 4416
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-65
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-72B<15A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38063M6DXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE
‘M38063M6D’
*= $0000
.BYTE
‘M38063M6D’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38063M6DXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-66
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-87B<17B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38067M8-XXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38067M8-XXXFP
Microcomputer name :
M38067M8-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
807F16
808016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38067M8–’
data
ROM 32638 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38067M8–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘8’ = 3816
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-67
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-87B<17B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38067M8-XXXFP/GP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier
assembler source program.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE
‘M38067M8–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38067M8-XXXFP, 80P6S for M38067M8-XXXGP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-68
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-63B<36B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38067M8AXXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38067M8AXXXFP
Microcomputer name :
M38067M8AXXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
807F16
808016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38067M8A’
data
ROM 32638 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38067M8A”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘8’ = 3816
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘A’ = 4116
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-69
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-63B<36B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38067M8AXXXFP/GP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier
assembler source program.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE
‘M38067M8A’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38067M8AXXXFP, 80P6S for M38067M8AXXXGP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-70
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-89B<17A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38067M8DXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
807F16
808016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38067M8D’
data
ROM 32638 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38067M8D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘8’ = 3816
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘D’ = 4416
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-71
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-89B<17A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38067M8DXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier
assembler source program.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE
‘M38067M8D’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38067M8DXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-72
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-53B<35A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38067MC-XXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38067MC-XXXFP
Microcomputer name :
M38067MC-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
407F16
408016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38067MC–’
data
ROM 49022 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38067MC–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16. The
ASCII codes and addresses are listed to the right in
hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-73
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-53B<35A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38067MC-XXXFP/GP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier
assembler source program.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE
‘M38067MC–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38067MC-XXXFP, 80P6S for M38067MC-XXXGP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-74
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-66B<36A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38067MCAXXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38067MCAXXXFP
Microcomputer name :
M38067MCAXXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
407F16
408016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38067MCA’
data
ROM 49022 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38067MCA”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘A’ = 4116
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-75
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-66B<36A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38067MCAXXXFP/GP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier
assembler source program.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE
‘M38067MCA’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38067MCAXXXFP, 80P6S for M38067MCAXXXGP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-76
3806 GROUP USER’S MANUAL
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-54B<35A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38067MCDXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
407F16
408016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38067MCD’
data
ROM 49022 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38067MCD”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘D’ = 4416
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-77
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-54B<35A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38067MCDXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier
assembler source program.
EPROM type
The pseudo-command
27512
*=
.BYTE
$0000
‘M38067MCD’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38067MCDXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3-78
3806 GROUP USER’S MANUAL
APPENDIX
3.7 Mark specification form
3.7 Mark specification form
3806 GROUP USER’S MANUAL
3-79
APPENDIX
3.7 Mark specification form
3-80
3806 GROUP USER’S MANUAL
APPENDIX
3.8 Package outline
3.8 Package outline
3806 GROUP USER’S MANUAL
3-81
APPENDIX
3.8 Package outline
3-82
3806 GROUP USER’S MANUAL
APPENDIX
3.9 List of instruction codes
3.9 List of instruction codes
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
ORA
JSR
IND, X ZP, IND
BBS
0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
LDM
ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
ADC
IND, X
MUL
ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
LDA
IND, Y ZP, IND
BBC
5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
SBC
IND, X
DIV
ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
—
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
ORA
ASL
CLB
ABS, X ABS, X 0, ZP
AND
ABS
ROL
ABS
SEB
1, ZP
AND
ROL
CLB
ABS, X ABS, X 1, ZP
EOR
ABS
LSR
ABS
SEB
2, ZP
EOR
LSR
CLB
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
ADC
ROR
CLB
ABS, X ABS, X 3, ZP
LDY
LDA
LDX
CLB
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
CMP
DEC
CLB
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
SBC
INC
CLB
ABS, X ABS, X 7, ZP
3-byte instruction
2-byte instruction
1-byte instruction
3806 GROUP USER’S MANUAL
3-83
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
7
ASL
C←
0
←0
IMM
# OP n
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
Adds the carry, accumulator and memory contents. The results are entered into the
accumulator.
Adds the contents of the memory in the address indicated by index register X, the
contents of the memory specified by the addressing mode and the carry. The results are
entered into the memory at the address indicated by index register X.
69 2
2
65 3
2
“AND’s” the accumulator and memory contents.
The results are entered into the accumulator.
“AND’s” the contents of the memory of the address indicated by index register X and the
contents of the memory specified by the addressing mode. The results are entered into
the memory at the address indicated by index
register X.
29 2
2
25 3
2
06 5
2
0A 2
Shifts the contents of accumulator or contents
of memory one bit to the left. The low order bit
of the accumulator or memory is cleared and
the high order bit is shifted into the carry flag.
1
#
BBC
(Note 4)
Ab or Mb = 0?
Branches when the contents of the bit specified in the accumulator or memory is “0”.
13 4
+
2i
2
17 5
+
2i
3
BBS
(Note 4)
Ab or Mb = 1?
Branches when the contents of the bit specified in the accumulator or memory is “1”.
03 4
+
2i
2
07 5
+
2i
3
BCC
(Note 4)
C = 0?
Branches when the contents of carry flag is
“0”.
BCS
(Note 4)
C = 1?
Branches when the contents of carry flag is
“1”.
BEQ
(Note 4)
Z = 1?
Branches when the contents of zero flag is “1”.
BIT
A
BMI
(Note 4)
N = 1?
Branches when the contents of negative flag is
“1”.
BNE
(Note 4)
Z = 0?
Branches when the contents of zero flag is “0”.
BPL
(Note 4)
N = 0?
Branches when the contents of negative flag is
“0”.
BRA
PC ← PC ± offset
Jumps to address specified by adding offset to
the program counter.
BRK
B←1
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
PCL ← ADL
PCH ← ADH
Executes a software interrupt.
3-84
V
M
24 3
“AND’s” the contents of accumulator and
memory. The results are not entered anywhere.
00 7
3806 GROUP USER’S MANUAL
1
2
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
75 4
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
2
6D 4
3 7D 5
3 79 5
35 4
2
2D 4
3 3D 5
3 39 5
16 6
2
0E 6
3 1E 7
3
2C 4
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
SP
# OP n
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
# OP n
# OP n
# OP n
3
61 6
2 71 6
2
N
V
•
•
•
•
Z
C
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90 2
2
•
•
•
•
•
•
•
•
B0 2
2
•
•
•
•
•
•
•
•
F0 2
2
•
•
•
•
•
•
•
•
M7 M6 •
•
•
•
Z
•
3
3806 GROUP USER’S MANUAL
#
7
30 2
2
•
•
•
•
•
•
•
•
D0 2
2
•
•
•
•
•
•
•
•
10 2
2
•
•
•
•
•
•
•
•
80 4
2
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
•
3-85
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
BVC
(Note 4)
V = 0?
Branches when the contents of overflow flag is
“0”.
BVS
(Note 4)
V = 1?
Branches when the contents of overflow flag is
“1”.
CLB
Ab or Mb ← 0
Clears the contents of the bit specified in the
accumulator or memory to “0”.
CLC
C←0
Clears the contents of the carry flag to “0”.
18 2
1
CLD
D←0
Clears the contents of decimal mode flag to
“0”.
D8 2
1
CLI
I←0
Clears the contents of interrupt disable flag to
“0”.
58 2
1
CLT
T←0
Clears the contents of index X mode flag to
“0”.
12 2
1
CLV
V←0
Clears the contents of overflow flag to “0”.
B8 2
1
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
Compares the contents of accumulator and
memory.
Compares the contents of the memory specified by the addressing mode with the contents
of the address indicated by index register X.
COM
M←M
Forms a one’s complement of the contents of
memory, and stores it into memory.
CPX
X–M
Compares the contents of index register X and
memory.
E0 2
CPY
Y–M
Compares the contents of index register Y and
memory.
C0 2
DEC
A ← A – 1 or
M←M–1
Decrements the contents of the accumulator
or memory by 1.
DEX
X←X–1
Decrements the contents of index register X CA 2
by 1.
1
DEY
Y←Y–1
Decrements the contents of index register Y
by 1.
1
DIV
A ← (M(zz + X + 1),
M(zz + X)) / A
M(S) ← 1’s complememt
of Remainder
S←S–1
Divides the 16-bit data that is the contents of
M (zz + x + 1) for high byte and the contents of
M (zz + x) for low byte by the accumulator.
Stores the quotient in the accumulator and the
1’s complement of the remainder on the stack.
EOR
(Note 1)
When T = 0
–M
A←AV
“Exclusive-ORs” the contents of accumulator
and memory. The results are stored in the accumulator.
“Exclusive-ORs” the contents of the memory
specified by the addressing mode and the
contents of the memory at the address indicated by index register X. The results are
stored into the memory at the address indicated by index register X.
A
# OP n
BIT, A
# OP n
1B 2
+
2i
C9 2
ZP
# OP n
BIT, ZP
# OP n
#
1F 5
+
2i
2
1
C5 3
2
44 5
2
2
E4 3
2
2
C4 3
2
C6 5
2
45 3
2
E6 5
2
2
__
When T = 1
–M
M(X) ← M(X) V
1A 2
88 2
49 2
INC
A ← A + 1 or
M←M+1
Increments the contents of accumulator or
memory by 1.
INX
X←X+1
Increments the contents of index register X by
1.
E8 2
1
INY
Y←Y+1
Increments the contents of index register Y by
1.
C8 2
1
3-86
2
3A 2
3806 GROUP USER’S MANUAL
1
1
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
OP n
D5 4
D6 6
ZP, Y
# OP n
2
2
ABS
# OP n
CD 4
ABS, X
# OP n
3 DD 5
ABS, Y
# OP n
3 D9 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
C1 6
IND, Y
# OP n
2 D1 6
REL
# OP n
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
50 2
2
•
•
•
•
•
•
•
•
70 2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
N
•
•
•
•
•
Z
C
N
•
•
•
•
•
Z
•
EC 4
3
N
•
•
•
•
•
Z
C
CC 4
3
N
•
•
•
•
•
Z
C
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
3
E2 16 2
55 4
2
4D 4
3 5D 5
3 59 5
F6 6
2
EE 6
3 FE 7
3
3
41 6
2 51 6
3806 GROUP USER’S MANUAL
2
3-87
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
Jumps to the specified address.
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
After storing contents of program counter in
stack, and jumps to the specified address.
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
Load accumulator with contents of memory.
LDM
M ← nn
Load memory with immediate value.
LDX
X←M
Load index register X with contents of
memory.
A2 2
LDY
Y←M
Load index register Y with contents of
memory.
A0 2
LSR
7
0→
MUL
M(S) · A ← A ✕ M(zz + X)
S←S–1
Multiplies the accumulator with the contents of
memory specified by the zero page X addressing mode and stores the high byte of the result
on the stack and the low byte in the accumulator.
NOP
PC ← PC + 1
No operation.
ORA
(Note 1)
When T = 0
A←AVM
“Logical OR’s” the contents of memory and accumulator. The result is stored in the
accumulator.
“Logical OR’s” the contents of memory indicated by index register X and contents of
memory specified by the addressing mode.
The result is stored in the memory specified by
index register X.
0
→C
When T = 1
M(X) ← M(X) V M
3-88
A9 2
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
A5 3
2
3C 4
3
2
A6 3
2
2
A4 3
2
46 5
2
05 3
2
2
Load memory indicated by index register X
with contents of memory specified by the addressing mode.
Shift the contents of accumulator or memory
to the right by one bit.
The low order bit of accumulator or memory is
stored in carry, 7th bit is cleared.
4A 2
EA 2
3806 GROUP USER’S MANUAL
1
1
09 2
2
#
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
OP n
B5 4
ZP, Y
# OP n
2
B6 4
ABS
# OP n
ABS, X
# OP n
4C 3
3
20 6
3
AD 4
3 BD 5
2 AE 4
ABS, Y
# OP n
3 B9 5
3
BE 5
IND
Processor status register
ZP, IND
IND, X
# OP n
# OP n
# OP n
6C 5
3 B2 4
2
02 7
2
3
IND, Y
# OP n
REL
# OP n
SP
# OP n
22 5
A1 6
2 B1 6
2
3
#
2
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
B4 4
2
AC 4
3 BC 5
3
N
•
•
•
•
•
Z
•
56 6
2
4E 6
3 5E 7
3
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
62 15 2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
3806 GROUP USER’S MANUAL
2
3-89
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
OP n
# OP n
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
PHA
M(S) ← A
S←S–1
Saves the contents of the accumulator in
memory at the address indicated by the stack
pointer and decrements the contents of stack
pointer by 1.
48 3
1
PHP
M(S) ← PS
S←S–1
Saves the contents of the processor status
register in memory at the address indicated by
the stack pointer and decrements the contents
of the stack pointer by 1.
08 3
1
PLA
S←S+1
A ← M(S)
Increments the contents of the stack pointer
by 1 and restores the accumulator from the
memory at the address indicated by the stack
pointer.
68 4
1
PLP
S←S+1
PS ← M(S)
Increments the contents of stack pointer by 1
and restores the processor status register
from the memory at the address indicated by
the stack pointer.
28 4
1
ROL
7
←
Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is
shifted into the carry flag and the carry flag is
shifted into the low order bit.
2A 2
1
26 5
2
Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is
shifted into the carry flag and the carry flag is
shifted into the high order bit.
6A 2
1
66 5
2
82 8
2
E5 3
2
0
←C ←
ROR
7
C→
RRF
7
→
0
→
0
→
Rotates the contents of memory to the right by
4 bits.
RTI
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
Returns from an interrupt routine to the main
routine.
40 6
1
RTS
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
Returns from a subroutine to the main routine.
60 6
1
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
Subtracts the contents of memory and
complement of carry flag from the contents of
accumulator. The results are stored into the
accumulator.
Subtracts contents of complement of carry flag
and contents of the memory indicated by the
addressing mode from the memory at the address indicated by index register X. The
results are stored into the memory of the address indicated by index register X.
When T = 1
_
M(X) ← M(X) – M – C
E9 2
SEB
Ab or Mb ← 1
Sets the specified bit in the accumulator or
memory to “1”.
SEC
C←1
Sets the contents of the carry flag to “1”.
38 2
1
SED
D←1
Sets the contents of the decimal mode flag to
“1”.
F8 2
1
SEI
I←1
Sets the contents of the interrupt disable flag
to “1”.
78 2
1
SET
T←1
Sets the contents of the index X mode flag to
“1”.
32 2
1
3-90
2
0B 2
+
2i
3806 GROUP USER’S MANUAL
1
0F 5
+
2i
#
2
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
(Value saved in stack)
F5 4
2
ED 4
3 FD 5
3 F9 5
3
E1 6
2 F1 6
3806 GROUP USER’S MANUAL
2
•
•
•
•
•
•
•
•
N
V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
3-91
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
STA
M←A
STP
IMM
# OP n
Stores the contents of accumulator in memory.
Stops the oscillator.
42 2
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
85 4
2
1
STX
M←X
Stores the contents of index register X in
memory.
86 4
2
STY
M←Y
Stores the contents of index register Y in
memory.
84 4
2
TAX
X←A
Transfers the contents of the accumulator to AA 2
index register X.
1
TAY
Y←A
Transfers the contents of the accumulator to
index register Y.
1
TST
M = 0?
Tests whether the contents of memory are “0”
or not.
64 3
2
TSX
X←S
Transfers the contents of the stack pointer to BA 2
index register X.
1
TXA
A←X
Transfers the contents of index register X to
the accumulator.
8A 2
1
TXS
S←X
Transfers the contents of index register X to
the stack pointer.
9A 2
1
TYA
A←Y
Transfers the contents of index register Y to
the accumulator.
98 2
1
Stops the internal clock.
C2 2
1
WIT
Notes 1
2
3
4
5
3-92
A8 2
: The number of cycles “n” is increased by 3 when T is 1.
: The number of cycles “n” is increased by 2 when T is 1.
: The number of cycles “n” is increased by 1 when T is 1.
: The number of cycles “n” is increased by 2 when branching has occurred.
: N, V, and Z flags are invalid in decimal operation mode.
3806 GROUP USER’S MANUAL
#
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
95 5
2
96 5
94 5
2
Symbol
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
8D 5
3 9D 6
3 99 6
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
81 7
2 91 7
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
Contents
Symbol
IMP
IMM
A
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
BIT, A
Accumulator bit relative addressing mode
ZP
BIT, ZP
Zero page addressing mode
Zero page bit relative addressing mode
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ab
Mb
OP
n
#
3806 GROUP USER’S MANUAL
Contents
Addition
Subtraction
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
1 bit of accumulator
1 bit of memory
Opcode
Number of cycles
Number of bytes
3-93
APPENDIX
3.11 SFR memory map
3.11 SFR memory map
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
3-94
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
P0
P0
P1
P1
P2
P2
P3
P3
P4
P4
P5
P5
P6
P6
P7
P7
P8
P8
(P0)
direction
(P1)
direction
(P2)
direction
(P3)
direction
(P4)
direction
(P5)
direction
(P6)
direction
(P7)
direction
(P8)
direction
register (P0D)
register (P1D)
register (P2D)
register (P3D)
register (P4D)
register (P5D)
register (P6D)
register (P7D)
register (P8D)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Serial I/O2 control register (SIO2CON)
Serial I/O2 register (SIO2)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
AD/DA control register (ADCON)
A-D conversion register (AD)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
3806 GROUP USER’S MANUAL
1
3806 GROUP USER’S MANUAL
24
21
22
23
19
20
18
17
16
15
14
13
11
12
10
9
8
74
7
73
6
5
3
4
2
P87
P86
P85
P84
P83
P82
P81
P80
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63 /AN3
P62/AN2
P61/AN1
P60/AN0
P77
P76
P75
P74
P73/SRDY2
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/INT4
P52/INT3
P51/INT2
P50
P47/SRDY1
P46/SCLK1
P45/TXD
P44/RXD
P43/INT1
64
41
42
43
45
44
47
46
48
50
49
53
52
51
54
55
56
57
58
59
60
61
62
63
P30
P31
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
APPENDIX
3.12 Pin configuration
3.12 Pin configuration
PIN CONFIGURATION (TOP VIEW)
65
40
66
39
67
38
68
37
69
36
70
35
71
72
34
M38063M6-XXXFP
33
32
75
31
30
76
29
77
28
78
27
79
80
26
25
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40
P41
RESET
CNVSS
P42/INT0
Package type : 80P6N-A
80-pin plastic-molded QFP
3-95
APPENDIX
3.12 Pin configuration
41
43
42
45
44
46
47
48
50
49
52
51
53
55
54
57
56
58
60
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
32
69
70
31
M38063M6-XXXGP
M38063M6AXXXHP
71
72
30
29
28
73
20
18
19
17
16
15
14
13
12
P60 /AN0
P77
P76
P75
P74
P73/SRDY2
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2
P56/DA1
P55/CNTR 1
P54/CNTR 0
P53/INT4
P52/INT3
P51/INT2
P50
P47/SRDY1
P46/SCLK1
P45/TXD
11
21
10
22
80
9
79
CNVSS
P42/INT0
P43/INT1
P44/RXD
8
23
7
78
6
RESET
24
4
25
77
5
76
3
26
1
27
75
Package type : 80P6S-A/80P6D-A
80-pin plastic-molded QFP
3-96
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
Vss
XOUT
XIN
P40
P41
74
2
P31
P30
P87
P86
P85
P84
P83
P82
P81
P80
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
59
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
PIN CONFIGURATION (TOP VIEW)
3806 GROUP USER’S MANUAL
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
3806Group
Mar. First Edition 1996
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1996 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
3806 Group
H-EE416-A KI-9603 Printed in Japan (ROD)
© 1996 MITSUBISHI ELECTRIC CORPORATION
New publication, effective Mar. 1996.
Specifications subject to change without notice.