Data Sheet

74AVCH1T45-Q100
Dual-supply voltage level translator/transceiver; 3-state
Rev. 3 — 6 January 2016
Product data sheet
1. General description
The 74AVCH1T45-Q100 is a single bit, dual supply transceiver that enables bidirectional
level translation. It features two 1-bit input-output ports (A and B), a direction control input
(DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied
with any voltage between 0.8 V and 3.6 V making the device suitable for translating
between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A
and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows
transmission from A to B and a LOW on DIR allows transmission from B to A.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
The 74AVCH1T45-Q100 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range:
 VCC(A): 0.8 V to 3.6 V
 VCC(B): 0.8 V to 3.6 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-12 (0.8 V to 1.3 V)
 JESD8-11 (0.9 V to 1.65 V)
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-B (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 Class 3B exceeds 8000 V
 HBM JESD22-A114E Class 3B exceeds 8000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
 Maximum data rates:
 500 Mbit/s (1.8 V to 3.3 V translation)
 320 Mbit/s (< 1.8 V to 3.3 V translation)
 320 Mbit/s (translate to 2.5 V or 1.8 V)
 280 Mbit/s (translate to 1.5 V)
 240 Mbit/s (translate to 1.2 V)
 Suspend mode
 Bus hold on data inputs
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial Power-down mode operation
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
74AVCH1T45GW-Q100 40 C to +125 C
SC-88
Description
Version
plastic surface-mounted package; 6 leads
SOT363
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AVCH1T45GW-Q100
K5
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
',5
',5
$
$
9&&$
%
%
9&&%
9&&$
DDJ
Fig 1.
Logic symbol
74AVCH1T45_Q100
Product data sheet
9&&%
DDJ
Fig 2.
Logic diagram
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74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
6. Pinning information
6.1 Pinning
$9&+74
9&&$ 9&&%
*1' ',5
$ %
DDD
Fig 3.
Pin configuration SOT363
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
VCC(A)
1
supply voltage port A and DIR
GND
2
ground (0 V)
A
3
data input or output
B
4
data input or output
DIR
5
direction control
VCC(B)
6
supply voltage port B
7. Functional description
Table 4.
Function table[1]
Supply voltage
Input
Input/output[2]
VCC(A), VCC(B)
DIR[3]
A
B
0.8 V to 3.6 V
L
A=B
input
0.8 V to 3.6 V
H
input
B=A
GND[4]
X
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2]
The input circuit of the data I/O is always active.
[3]
The DIR input circuit is referenced to VCC(A).
[4]
If at least one of VCC(A) or VCC(B) is at GND level, the device goes into Suspend mode.
74AVCH1T45_Q100
Product data sheet
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Rev. 3 — 6 January 2016
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74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC(A)
VCC(B)
IIK
input clamping current
Conditions
Min
Max
Unit
supply voltage A
0.5
+4.6
V
supply voltage B
0.5
+4.6
V
50
-
[1]
0.5
+4.6
[1][2][3]
0.5
[1]
0.5
+4.6
V
-
50
mA
VI < 0 V
VI
input voltage
IOK
output clamping current
VO < 0 V
VO
output voltage
Active mode
50
Suspend or 3-state mode
IO
output current
VO = 0 V to VCCO
ICC
supply current
ICC(A) or ICC(B)
IGND
ground current
Tstg
storage temperature
total power dissipation
Ptot
Tamb = 40 C to +125 C
[4]
-
mA
V
mA
VCCO + 0.5 V
-
100
mA
100
-
mA
65
+150
C
-
250
mW
[1]
The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
VCCO is the supply voltage associated with the output port.
[3]
VCCO + 0.5 V should not exceed 4.6 V.
[4]
For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
74AVCH1T45_Q100
Product data sheet
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Dual-supply voltage level translator/transceiver; 3-state
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC(A)
Conditions
Min
Max
Unit
supply voltage A
0.8
3.6
V
VCC(B)
supply voltage B
0.8
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
0
VCCO
V
0
3.6
V
40
+125
C
-
5
Active mode
[1]
Suspend or 3-state mode
Tamb
ambient temperature
t/V
input transition rise and fall rate
VCCI = 0.8 V to 3.6 V
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the input port.
[2]
ns/V
10. Static characteristics
Table 7.
Typical static characteristics at Tamb = 25 C[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH
HIGH-level output voltage
Conditions
Min
Typ
Max
Unit
-
0.69
-
V
0.07
-
V
VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
VOL
LOW-level output voltage
VI = VIH or VIL
II
input leakage current
DIR input; VI = 0 V or 3.6 V;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold LOW current
VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
[3]
-
26
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
-
0.025 0.25 A
-
A
IBHH
bus hold HIGH current
VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
[4]
-
24
-
A
IBHLO
bus hold LOW overdrive
current
VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V
[5]
-
28
-
A
IBHHO
bus hold HIGH overdrive
current
VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V
[6]
-
26
-
A
IOZ
OFF-state output current
A or B port; VO = 0 V or VCCO;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
[7]
-
0.5
2.5
A
IOFF
power-off leakage current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
0.1
1
A
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
-
0.1
1
A
DIR input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
-
1.0
-
pF
CI
input capacitance
74AVCH1T45_Q100
Product data sheet
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Dual-supply voltage level translator/transceiver; 3-state
Table 7.
Typical static characteristics at Tamb = 25 C[1][2] …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
CI/O
A and B port; Suspend mode;
VO = VCCO or GND; VCC(A) = VCC(B) = 3.3 V
input/output capacitance
Min
Typ
Max
-
4.0
-
Unit
pF
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the data input port.
[3]
The bus hold circuit can sink at least the minimum low sustaining current at VIL max. Measure IBHL after lowering VI to GND and then
raising it to VIL max.
[4]
The bus hold circuit can source at least the minimum high sustaining current at VIH min. Measure IBHH after raising VI to VCC and then
lowering it to VIH min.
[5]
An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6]
An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7]
For I/O ports, the parameter IOZ includes the input leakage current.
Table 8.
Static characteristics [1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
HIGH-level
input voltage
40 C to +85 C
Conditions
40 C to +125 C
Min
Max
Min
Max
Unit
data input
VCCI = 0.8 V
0.70VCCI
-
0.70VCCI
-
V
VCCI = 1.1 V to 1.95 V
0.65VCCI
-
0.65VCCI
-
V
VCCI = 2.3 V to 2.7 V
1.6
-
1.6
-
V
VCCI = 3.0 V to 3.6 V
2
-
2
-
V
VCC(A) = 0.8 V
0.70VCC(A)
-
0.70VCC(A)
-
V
VCC(A) = 1.1 V to 1.95 V
0.65VCC(A)
-
0.65VCC(A)
-
V
VCC(A) = 2.3 V to 2.7 V
1.6
-
1.6
-
V
VCC(A) = 3.0 V to 3.6 V
2
-
2
-
V
VCCI = 0.8 V
-
0.30VCCI
-
0.30VCCI
V
VCCI = 1.1 V to 1.95 V
-
0.35VCCI
-
0.35VCCI
V
VCCI = 2.3 V to 2.7 V
-
0.7
-
0.7
V
VCCI = 3.0 V to 3.6 V
-
0.9
-
0.9
V
VCC(A) = 0.8 V
-
0.30VCC(A)
-
0.30VCC(A) V
VCC(A) = 1.1 V to 1.95 V
-
0.35VCC(A)
-
0.35VCC(A) V
VCC(A) = 2.3 V to 2.7 V
-
0.7
-
0.7
V
VCC(A) = 3.0 V to 3.6 V
-
0.9
-
0.9
V
DIR input
VIL
LOW-level
input voltage
data input
DIR input
74AVCH1T45_Q100
Product data sheet
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Dual-supply voltage level translator/transceiver; 3-state
Table 8.
Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH
VOL
40 C to +85 C
Conditions
Max
Min
Max
VCCO  0.1
-
VCCO  0.1
-
V
IO = 3 mA;
VCC(A) = VCC(B) = 1.1 V
0.85
-
0.85
-
V
IO = 6 mA;
VCC(A) = VCC(B) = 1.4 V
1.05
-
1.05
-
V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
1.2
-
1.2
-
V
IO = 9 mA;
VCC(A) = VCC(B) = 2.3 V
1.75
-
1.75
-
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
2.3
-
2.3
-
V
-
0.1
-
0.1
V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
-
0.25
-
0.25
V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
-
0.35
-
0.35
V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
-
0.45
-
0.45
V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
-
0.55
-
0.55
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
-
0.7
-
0.7
V
-
1
-
1.5
A
15
-
15
-
A
VI = 0.58 V;
VCC(A) = VCC(B) = 1.65 V
25
-
25
-
A
VI = 0.70 V;
VCC(A) = VCC(B) = 2.3 V
45
-
45
-
A
VI = 0.80 V;
VCC(A) = VCC(B) = 3.0 V
100
-
90
-
A
15
-
15
-
A
VI = 1.07 V;
VCC(A) = VCC(B) = 1.65 V
25
-
25
-
A
VI = 1.60 V;
VCC(A) = VCC(B) = 2.3 V
45
-
45
-
A
VI = 2.00 V;
VCC(A) = VCC(B) = 3.0 V
100
-
100
-
A
HIGH-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
LOW-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
input leakage
current
IBHL
bus hold LOW A or B port
current
VI = 0.49 V;
VCC(A) = VCC(B) = 1.4 V
DIR input; VI = 0 V or 3.6 V;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
bus hold HIGH A or B port
current
VI = 0.91 V;
VCC(A) = VCC(B) = 1.4 V
74AVCH1T45_Q100
Product data sheet
Unit
Min
II
IBHH
40 C to +125 C
[3]
[4]
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NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
Table 8.
Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
IBHLO
40 C to +85 C
Conditions
Unit
Min
Max
Min
Max
125
-
125
-
A
200
-
200
-
A
300
-
300
-
A
500
-
500
-
A
125
-
125
-
A
200
-
200
-
A
VCC(A) = VCC(B) = 2.7 V
300
-
300
-
A
VCC(A) = VCC(B) = 3.6 V
500
-
500
-
A
-
5
-
7.5
A
bus hold LOW A or B port
overdrive
VCC(A) = VCC(B) = 1.6 V
current
VCC(A) = VCC(B) = 1.95 V
[5]
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
IBHHO
40 C to +125 C
bus hold HIGH A or B port
overdrive
VCC(A) = VCC(B) = 1.6 V
current
VCC(A) = VCC(B) = 1.95 V
[6]
[7]
IOZ
OFF-state
output current
A or B port; VO = 0 V or VCCO;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
5
-
35
A
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
-
5
-
35
A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
8
-
12
A
VCC(A) = 3.6 V; VCC(B) = 0 V
-
8
-
12
A
VCC(A) = 0 V; VCC(B) = 3.6 V
2
-
8
-
A
-
8
-
12
A
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
2
-
8
-
A
VCC(A) = 0 V; VCC(B) = 3.6 V
-
8
-
12
A
-
16
-
24
A
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI;
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the data input port.
[3]
The bus hold circuit can sink at least the minimum low sustaining current at VIL max. Measure IBHL after lowering VI to GND and then
raising it to VIL max.
[4]
The bus hold circuit can source at least the minimum high sustaining current at VIH min. Measure IBHH after raising VI to VCC and then
lowering it to VIH min.
[5]
An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6]
An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7]
For I/O ports, the parameter IOZ includes the input leakage current.
74AVCH1T45_Q100
Product data sheet
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Rev. 3 — 6 January 2016
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Dual-supply voltage level translator/transceiver; 3-state
11. Dynamic characteristics
Table 9.
Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5
Symbol Parameter
tpd
VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
propagation delay A to B
15.8
8.4
8.0
8.0
8.7
9.5
ns
B to A
15.8
12.7
12.4
12.2
12.0
11.8
ns
DIR to A
12.2
12.2
12.2
12.2
12.2
12.2
ns
tdis
disable time
ten
enable time
[1]
Conditions
DIR to B
11.7
7.9
7.6
8.2
8.7
10.2
ns
DIR to A
27.5
20.6
20.0
20.4
20.7
22.0
ns
DIR to B
28.0
20.6
20.2
20.2
20.9
21.7
ns
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5
Symbol Parameter
Conditions
tpd
propagation delay A to B
tdis
disable time
ten
[1]
enable time
VCC(A)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
15.8
12.7
12.4
12.2
12.0
11.8
ns
B to A
15.8
8.4
8.0
8.0
8.7
9.5
ns
DIR to A
12.2
4.9
3.8
3.7
2.8
3.4
ns
DIR to B
11.7
9.2
9.0
8.8
8.7
8.6
ns
DIR to A
27.5
17.6
17.0
16.8
17.4
18.1
ns
DIR to B
28.0
17.6
16.2
15.9
14.8
15.2
ns
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
CPD
[1]
power dissipation
capacitance
Conditions
VCC(A) and VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
A port: (direction A to B);
B port: (direction B to A)
1
2
2
2
2
2
pF
A port: (direction B to A);
B port: (direction A to B)
9
11
11
12
14
17
pF
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
[2]
fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL =  .
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V  0.1 V
1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V
3.3 V  0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation
delay
A to B
1.0
9.0
0.7
6.8
0.6
6.1
0.5
5.7
0.5
6.1
ns
B to A
1.0
9.0
0.8
8.0
0.7
7.7
0.6
7.2
0.5
7.1
ns
disable time
DIR to A
2.2
8.8
2.2
8.8
2.2
8.8
2.2
8.8
2.2
8.8
ns
DIR to B
2.2
8.4
1.8
6.7
2.0
6.9
1.7
6.2
2.4
7.2
ns
enable time
DIR to A
-
17.4
-
14.7
-
14.6
-
13.4
-
14.3
ns
DIR to B
-
17.8
-
15.6
-
14.9
-
14.5
-
14.9
ns
4.6
0.5
3.7
0.5
3.5
ns
VCC(A) = 1.4 V to 1.6 V
tpd
propagation
delay
A to B
1.0
8.0
0.7
5.4
0.6
B to A
1.0
6.8
0.8
5.4
0.7
5.1
0.6
4.7
0.5
4.5
ns
tdis
disable time
DIR to A
1.6
6.3
1.6
6.3
1.6
6.3
1.6
6.3
1.6
6.3
ns
DIR to B
2.0
7.6
1.8
5.9
1.6
6.0
1.2
4.8
1.7
5.5
ns
DIR to A
-
14.4
-
11.3
-
11.1
-
9.5
-
10.0
ns
DIR to B
-
14.3
-
11.7
-
10.9
-
10.0
-
9.8
ns
A to B
1.0
7.7
0.6
5.1
0.5
4.3
0.5
3.4
0.5
3.1
ns
B to A
1.0
6.1
0.7
4.6
0.5
4.4
0.5
3.9
0.5
3.7
ns
ten
enable time
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation
delay
disable time
enable time
DIR to A
1.6
5.5
1.6
5.5
1.6
5.5
1.6
5.5
1.6
5.5
ns
DIR to B
1.8
7.8
1.8
5.7
1.4
5.8
1.0
4.5
1.5
5.2
ns
DIR to A
-
13.9
-
10.3
-
10.2
-
8.4
-
8.9
ns
DIR to B
-
13.2
-
10.6
-
9.8
-
8.9
-
8.6
ns
VCC(A) = 2.3 V to 2.7 V
propagation
delay
A to B
1.0
7.2
0.5
4.7
0.5
3.9
0.5
3.0
0.5
2.6
ns
B to A
1.0
5.7
0.6
3.8
0.5
3.4
0.5
3.0
0.5
2.8
ns
tdis
disable time
DIR to A
1.5
4.2
1.5
4.2
1.5
4.2
1.5
4.2
1.5
4.2
ns
DIR to B
1.7
7.3
2.0
5.2
1.5
5.1
0.6
4.2
1.1
4.8
ns
ten
enable time
DIR to A
-
13.0
-
9.0
-
8.5
-
7.2
-
7.6
ns
DIR to B
-
11.4
-
8.9
-
8.1
-
7.2
-
6.8
ns
tpd
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
[1]
propagation
delay
A to B
1.0
7.1
0.5
4.5
0.5
3.7
0.5
2.8
0.5
2.4
ns
B to A
1.0
6.1
0.6
3.6
0.5
3.1
0.5
2.6
0.5
2.4
ns
disable time
DIR to A
1.5
4.7
1.5
4.7
1.5
4.7
1.5
4.7
1.5
4.7
ns
DIR to B
1.7
7.2
0.7
5.5
0.6
5.5
0.7
4.1
1.7
4.7
ns
DIR to A
-
13.3
-
9.1
-
8.6
-
6.7
-
7.1
ns
DIR to B
-
11.8
-
9.2
-
8.4
-
7.5
-
7.1
ns
enable time
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V  0.1 V
1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V
3.3 V  0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation
delay
A to B
1.0
9.9
0.7
7.5
0.6
6.8
0.5
6.3
0.5
6.8
ns
B to A
1.0
9.9
0.8
8.8
0.7
8.5
0.6
8.0
0.5
7.9
ns
disable time
DIR to A
2.2
9.7
2.2
9.7
2.2
9.7
2.2
9.7
2.2
9.7
ns
DIR to B
2.2
9.2
1.8
7.4
2.0
7.6
1.7
6.9
2.4
8.0
ns
enable time
DIR to A
-
19.1
-
16.2
-
16.1
-
14.9
-
15.9
ns
DIR to B
-
19.6
-
17.2
-
16.5
-
16.0
-
16.5
ns
VCC(A) = 1.4 V to 1.6 V
tpd
propagation
delay
A to B
1.0
8.8
0.7
6.0
0.6
5.1
0.5
4.1
0.5
3.9
ns
B to A
1.0
7.5
0.8
6.0
0.7
5.7
0.6
5.2
0.5
5.0
ns
tdis
disable time
DIR to A
1.6
7.0
1.6
7.0
1.6
7.0
1.6
7.0
1.6
7.0
ns
DIR to B
2.0
8.3
1.8
6.5
1.6
6.6
1.2
5.3
1.7
6.1
ns
DIR to A
-
15.8
-
12.5
-
12.3
-
10.5
-
11.1
ns
DIR to B
-
15.8
-
13.0
-
12.7
-
11.1
-
10.9
ns
A to B
1.0
8.5
0.6
5.7
0.5
4.8
0.5
3.8
0.5
3.5
ns
B to A
1.0
6.8
0.7
5.1
0.5
4.9
0.5
4.3
0.5
4.1
ns
ten
enable time
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation
delay
disable time
enable time
DIR to A
1.6
6.1
1.6
6.1
1.6
6.1
1.6
6.1
1.6
6.1
ns
DIR to B
1.8
8.6
1.8
6.3
1.4
6.4
1.0
5.0
1.5
5.8
ns
DIR to A
-
15.4
-
11.4
-
11.3
-
9.3
-
9.9
ns
DIR to B
-
14.6
-
11.8
-
10.9
-
9.9
-
9.6
ns
VCC(A) = 2.3 V to 2.7 V
propagation
delay
A to B
1.0
8.0
0.5
5.2
0.5
4.3
0.5
3.3
0.5
2.9
ns
B to A
1.0
6.3
0.6
4.2
0.5
3.8
0.5
3.3
0.5
3.1
ns
tdis
disable time
DIR to A
1.5
4.7
1.5
4.7
1.5
4.7
1.5
4.7
1.5
4.7
ns
DIR to B
1.7
8.0
2.0
5.8
1.5
5.7
0.6
4.7
1.1
5.3
ns
ten
enable time
DIR to A
-
14.3
-
10.0
-
9.5
-
8.0
-
8.4
ns
DIR to B
-
12.7
-
9.9
-
9.0
-
8.0
-
7.6
ns
tpd
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
[1]
propagation
delay
A to B
1.0
7.9
0.5
5.0
0.5
4.1
0.5
3.1
0.5
2.7
ns
B to A
1.0
6.8
0.6
4.0
0.5
3.5
0.5
2.9
0.5
2.7
ns
disable time
DIR to A
1.5
5.2
1.5
5.2
1.5
5.2
1.5
5.2
1.5
5.2
ns
DIR to B
1.7
7.9
0.7
6.0
0.6
6.1
0.7
4.6
1.7
5.2
ns
DIR to A
-
14.7
-
10.1
-
9.6
-
7.5
-
7.9
ns
DIR to B
-
13.1
-
10.2
-
9.3
-
8.3
-
7.9
ns
enable time
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
12. Waveforms
9,
90
$%LQSXW
*1'
W3+/
W3/+
92+
%$RXWSXW
90
DDH
92/
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
The data input (A, B) to output (B, A) propagation delay times
9,
',5LQSXW
90
*1'
W 3/=
RXWSXW
/2:WR2))
2))WR/2:
W 3=/
9&&2
90
9;
92/
W 3+=
92+
W 3=+
9<
RXWSXW
+,*+WR2))
2))WR+,*+
90
*1'
RXWSXWV
HQDEOHG
RXWSXWV
GLVDEOHG
RXWSXWV
HQDEOHG
DDH
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Enable and disable times
Table 14.
Measurement points
Supply voltage
Input[1]
Output[2]
VCC(A), VCC(B)
VM
VM
VX
VY
1.1 V to 1.6 V
0.5VCCI
0.5VCCO
VOL + 0.1 V
VOH  0.1 V
1.65 V to 2.7 V
0.5VCCI
0.5VCCO
VOL + 0.15 V
VOH  0.15 V
3.0 V to 3.6 V
0.5VCCI
0.5VCCO
VOL + 0.3 V
VOH  0.3 V
[1]
VCCI is the supply voltage associated with the data input port.
[2]
VCCO is the supply voltage associated with the output port.
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
12 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
W:
9,
QHJDWLYH
SXOVH
90
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
90
90
9
W:
9(;7
9&&
9,
*
5/
92
'87
57
5/
&/
DDH
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 6.
Test circuit for measuring switching times
Table 15.
Test data
Supply voltage
Input
VCC(A), VCC(B)
VI[1]
Load
t/V
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ[2]
1.1 V to 1.6 V
VCCI
1.0 ns/V
15 pF
2 k
open
GND
2VCCO
1.65 V to 2.7 V
VCCI
 1.0 ns/V
15 pF
2 k
open
GND
2VCCO
3.0 V to 3.6 V
VCCI
 1.0 ns/V
15 pF
2 k
open
GND
2VCCO
[1]
VCCI is the supply voltage associated with the data input port.
[2]
VCCO is the supply voltage associated with the output port.
74AVCH1T45_Q100
Product data sheet
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 7 is an example of the 74AVCH1T45-Q100 being used in a
unidirectional logic level-shifting application.
$9&+74
9&&
9&&
9&&$
*1'
$
V\VWHP
9&&%
',5
9&&
9&&
%
V\VWHP
DDD
Fig 7.
Unidirectional logic level-shifting application
Table 16.
74AVCH1T45_Q100
Product data sheet
Description unidirectional logic level-shifting application
Pin
Name
Function
Description
1
VCC(A)
VCC1
supply voltage of system-1 (0.8 V to 3.6 V)
2
GND
GND
device GND
3
A
OUT
output level depends on VCC1 voltage
4
B
IN
input threshold value depends on VCC2 voltage
5
DIR
DIR
the GND (LOW level) determines B port to A port direction
6
VCC(B)
VCC2
supply voltage of system-2 (0.8 V to 3.6 V)
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 8 shows the 74AVCH1T45-Q100 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable pin, the system designer
should take precautions to avoid bus contention between system-1 and system-2 when
changing directions.
$9&+74
9&&
9&&
9&&$
*1'
,2
$
9&&%
9&&
',5
9&&
,2
%
',5&75/
V\VWHP
V\VWHP
DDD
Fig 8.
Bidirectional logic level-shifting application
Table 17 provides a sequence that illustrates data transmission from system-1 to
system-2 and then from system-2 to system-1.
Table 17.
Description bidirectional logic level-shifting application[1]
State DIR CTRL I/O-1
I/O-2
Description
1
H
output
input
system-1 data to system-2
2
H
Z
Z
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
3
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 are still disabled.
The bus-line state depends on bus hold.
4
L
input
output
system-2 data to system-1
[1]
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
15 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 18.
Typical total supply current (ICC(A) + ICC(B))
VCC(A)
VCC(B)
Unit
0V
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
0.1
0.1
0.1
0.1
0.1
0.1
A
0.8 V
0.1
0.1
0.1
0.1
0.1
0.7
2.3
A
1.2 V
0.1
0.1
0.1
0.1
0.1
0.3
1.4
A
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.9
A
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.5
A
2.5 V
0.1
0.7
0.3
0.1
0.1
0.1
0.1
A
3.3 V
0.1
2.3
1.4
0.9
0.5
0.1
0.1
A
13.4 Enable times
The enable times for the 74AVCH1T45-Q100 are calculated from the following formulas:
• ten (DIR to A) = tdis (DIR to B) + tpd (B to A)
• ten (DIR to B) = tdis (DIR to A) + tpd (A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the
74AVCH1T45-Q100 is initially transmitting from A to B, then the DIR bit is switched, the B
port of the device must be disabled before presenting it with an input. After the B port has
been disabled, an input signal applied to it appears on the corresponding A port after the
specified propagation delay.
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
14. Package outline
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Package outline SOT363 (SC-88)
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
17 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
15. Abbreviations
Table 19.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
MIL
Military
16. Revision history
Table 20.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AVCH1T45_Q100 v.3
20160106
Product data sheet
-
74AVCH1T45_Q100 v.2
-
74AVCH1T45_Q100 v.1
Modifications:
74AVCH1T45_Q100 v.2
Modifications:
74AVCH1T45_Q100 v.1
74AVCH1T45_Q100
Product data sheet
•
Table 16: Labels for pins 4 and 5 corrected.
20130409
•
Product data sheet
Type number 74AVCH1T45GM-Q100 has been removed.
20120807
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
-
© NXP Semiconductors N.V. 2016. All rights reserved.
18 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AVCH1T45_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
19 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AVCH1T45_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
20 of 21
74AVCH1T45-Q100
NXP Semiconductors
Dual-supply voltage level translator/transceiver; 3-state
19. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
13.1
13.2
13.3
13.4
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 14
Unidirectional logic level-shifting application . 14
Bidirectional logic level-shifting application. . . 15
Power-up considerations . . . . . . . . . . . . . . . . 16
Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 January 2016
Document identifier: 74AVCH1T45_Q100