Data Sheet

74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
Rev. 2 — 19 January 2015
Product data sheet
1. General description
The 74HC123-Q100; 74HCT123-Q100 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC123-Q100; 74HCT123-Q100 are dual retriggerable monostable multivibrators
with output pulse width control by three methods:
1. The basic pulse is defined by the selection of the external resistor (REXT) and
capacitor (CEXT).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering.
3. An internal connection from nRD to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input nRD as shown in Table 3.
Schmitt trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 DC triggered from active HIGH or active LOW inputs
 Retriggerable for very long pulses up to 100 % duty factor
 Direct reset terminates output pulse
 Schmitt trigger action on all inputs except for the reset input
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
 Specified from 40 C to +85 C and from 40 C to +125 C
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1.
Ordering information
Type number
74HC123D-Q100
Package
Temperature range Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm
74HCT123D-Q100
74HC123PW-Q100
74HCT123PW-Q100
74HC123BQ-Q100
SOT763-1
4. Functional diagram
6
$
%
5'
4
4
5'
4
4
5'
6
%
5(;7&(;7
7
$
&(;7
4
&(;7
5(;7&(;7
4
7
4
4
5'
DDD
Fig 1.
Functional diagram
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
&;
5(;7&(;7 5(;7&(;7
4
$
4 4 4
4
%
%
5'
PQD
5
5'
Fig 2.
4 5'
&;
5&;
7
$
5
6
&(;7 &(;7
5&;
PQD
Logic symbol
Fig 3.
IEC logic symbol
Q5(;7&(;7
9&&
Q4
Q5'
5
&/
9&&
Q4
5
&/
9&&
5
&/
&/
Q$
Q%
Fig 4.
&/
5
PQD
Logic diagram
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
$
WHUPLQDO
LQGH[DUHD
+&4
+&74
5(;7&(;7
&(;7
4
5(;7&(;7
4
&(;7
4
4
4
&(;7
4
4
5(;7&(;7
&(;7
5'
5(;7&(;7
%
*1'
$
4
9&&
5'
%
%
5'
9&&
$
%
5'
*1'
$
9&&
+&4
DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5.
Pin configuration for SO16 and TSSOP16
Fig 6.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A
1
negative-edge triggered input 1
1B
2
positive-edge triggered input 1
1RD
3
direct reset LOW and positive-edge triggered input 1
1Q
4
active LOW output 1
2Q
5
active HIGH output 2
2CEXT
6
external capacitor connection 2
2REXT/CEXT
7
external resistor and capacitor connection 2
GND
8
ground (0 V)
2A
9
negative-edge triggered input 2
2B
10
positive-edge triggered input 2
2RD
11
direct reset LOW and positive-edge triggered input 2
2Q
12
active LOW output 2
1Q
13
active HIGH output 1
1CEXT
14
external capacitor connection 1
1REXT/CEXT
15
external resistor and capacitor connection 1
VCC
16
supply voltage
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
6. Functional description
Table 3.
Function table[1]
Input
Output
nRD
nA
nB
nQ
nQ
L
X
X
L
H
H[2]
H[2]
X
H
X
L[2]
X
X
L
L[2]
H
L

H

H

L
H
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH transition;  = HIGH-to-LOW transition;
= one HIGH level output pulse;
[2]
= one LOW level output pulse.
If the monostable was triggered before this condition was established, the pulse continues as programmed.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
Min
Max
Unit
0.5
+7
V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
-
20
mA
IO
output current
except for pins nREXT/CEXT;
VO = 0.5 V to (VCC + 0.5 V)
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
-
50
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
[1]
SO16 package
[1]
-
500
mW
TSSOP16 package
[2]
-
500
mW
DHVQFN16 package
[3]
-
500
mW
For SO16 packages: Ptot derates linearly with 8 mW/K above 70 C.
[2]
For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[3]
For DHVQFN16 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
VCC
supply voltage
Conditions
74HC123-Q100
74HCT123-Q100
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
t/V
input transition rise and
fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
40
+25
+125
40
+25
+125
Tamb
nRD input
ambient temperature
C
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
LOW-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
VI = VCC or GND; VCC = 6.0 V
-
-
0.1
-
1.0
-
1.0
A
-
-
8.0
-
80
-
160
A
74HC123-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
CI
25 C
Conditions
input
capacitance
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
3.5
-
-
-
-
-
pF
74HCT123-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
3.98
4.32
-
3.84
-
3.7
-
V
-
0
0.1
-
0.1
-
0.1
V
-
0.15
0.26
-
0.33
-
0.4
V
-
-
0.1
-
1.0
-
1.0
A
-
-
8.0
-
80
-
160
A
pins nA, nB
-
35
125
-
160
-
170
A
pin nRD
-
50
180
-
225
-
245
A
-
3.5
-
-
-
-
-
pF
IO = 4 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 A
IO = 4.0 mA
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
additional
per input pin; IO = 0 A;
supply current VI = VCC  2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
capacitance
74HC_HCT123_Q100
Product data sheet
VI = VCC or GND; VCC = 5.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
74HC123-Q100
tpd
propagation nRD, nA, nB to nQ or nQ;
delay
CEXT = 0 pF; REXT = 5 k;
see Figure 9
[1]
VCC = 2.0 V
-
83
255
-
320
-
385
ns
VCC = 4.5 V
-
30
51
-
64
-
77
ns
VCC = 5 V; CL = 15 pF
-
26
-
-
-
-
-
ns
VCC = 6.0 V
-
24
43
-
54
-
65
ns
VCC = 2.0 V
-
66
215
-
270
-
325
ns
VCC = 4.5 V
-
24
43
-
54
-
65
ns
VCC = 5 V; CL = 15 pF
-
20
-
-
-
-
-
ns
-
19
37
-
46
-
55
ns
nRD (reset) to nQ or nQ;
CEXT = 0 pF; REXT = 5 k;
see Figure 9
VCC = 6.0 V
tt
tW
transition
time
pulse width
[1]
see Figure 9
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC = 4.5 V
-
7
15
-
19
-
22
ns
VCC = 6.0 V
-
6
13
-
16
-
19
ns
nA LOW; see Figure 10
VCC = 2.0 V
100
8
-
125
-
150
-
ns
VCC = 4.5 V
20
3
-
25
-
30
-
ns
VCC = 6.0 V
17
2
-
21
-
26
-
ns
nB HIGH; see Figure 10
VCC = 2.0 V
100
17
-
125
-
150
-
ns
VCC = 4.5 V
20
6
-
25
-
30
-
ns
VCC = 6.0 V
17
5
-
21
-
26
-
ns
VCC = 2.0 V
100
14
-
125
-
150
-
ns
VCC = 4.5 V
20
5
-
25
-
30
-
ns
17
4
-
21
-
26
-
ns
CEXT = 100 nF; REXT = 10
k
-
450
-
-
-
-
-
s
CEXT = 0 pF; REXT = 5 k
-
75
-
-
-
-
-
ns
nRD LOW; see Figure 11
VCC = 6.0 V
nQ HIGH and nQ LOW;
VCC = 5.0 V;
see Figure 10 and Figure 11
74HC_HCT123_Q100
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
25 C
Conditions
trtrig
retrigger
time
nA, nB; CEXT = 0 pF; REXT =
5 k; VCC = 5.0 V;
see Figure 10
REXT
external
resistance
see Figure 7
[3][4]
VCC = 2.0 V
VCC = 5.0 V
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
110
-
-
-
-
-
ns
10
-
1000
-
-
-
-
k
2
-
1000
-
-
-
-
k
CEXT
external
VCC = 5.0 V; see Figure 7
capacitance
[4]
-
-
-
-
-
-
-
pF
CPD
power
per monostable; VI = GND
dissipation to VCC
capacitance
[5]
-
54
-
-
-
-
-
pF
-
30
51
-
64
-
77
ns
-
26
-
-
-
-
-
ns
VCC = 4.5 V
-
27
46
-
58
-
69
ns
VCC = 5 V; CL = 15 pF
-
23
-
-
-
-
-
ns
-
28
51
-
64
-
77
ns
-
26
-
-
-
-
-
ns
-
23
46
-
58
-
69
ns
-
23
-
-
-
-
-
ns
-
7
15
-
19
-
22
ns
nA LOW; see Figure 10
20
3
-
25
-
30
-
ns
nB HIGH; see Figure 10
20
5
-
25
-
30
-
ns
20
7
-
25
-
30
-
ns
CEXT = 100 nF; REXT = 10
k
-
450
-
-
-
-
-
s
CEXT = 0 pF; REXT = 5 k
-
75
-
-
-
-
-
ns
74HCT123-Q100
tPHL
HIGH to
nRD, nA, nB to nQ or nQ;
LOW
CEXT = 0 pF; REXT = 5 k;
propagation see Figure 9
delay
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
nRD (reset) to nQ or nQ;
CEXT = 0 pF; REXT = 5 k;
see Figure 9
tPLH
LOW to
nRD, nA, nB to nQ or nQ;
HIGH
CEXT = 0 pF; REXT = 5 k;
propagation see Figure 9
delay
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
nRD (reset) to nQ or nQ;
CEXT = 0 pF; REXT = 5 k;
see Figure 9
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
tt
transition
time
VCC = 4.5 V; see Figure 9
tW
pulse width
VCC = 4.5 V
[1]
nRD LOW; see Figure 11
nQ HIGH and nQ LOW;
VCC = 5.0 V; see Figure 10
and Figure 11
74HC_HCT123_Q100
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 23
NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
25 C
Conditions
trtrig
retrigger
time
nA, nB; CEXT = 0 pF; REXT =
5 k; VCC = 5.0 V;
see Figure 10
REXT
external
timing
resistor
VCC = 5.0 V; see Figure 7
CEXT
external
timing
capacitor
VCC = 5.0 V; see Figure 7
CPD
power
per monostable;
dissipation VI = GND to VCC  1.5 V
capacitance
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
110
-
-
-
-
-
ns
2
-
1000
-
-
-
-
k
[4]
-
-
-
-
-
-
-
pF
[5]
-
56
-
-
-
-
-
pF
[3][4]
[1]
tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH
[2]
For other REXT and CEXT combinations, see Figure 7. If CEXT > 10 nF, the following formula is valid.
tW = K  REXT  CEXT, where:
tW = typical output pulse width in ns;
REXT = external resistor in k;
CEXT = external capacitor in pF;
K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC = 2.0 V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.
[3]
The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width is only extended
when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF, the next
formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid:
trtrig = 30 + 0.19  REXT  CEXT0.9 + 13  REXT1.05, where:
trtrig = retrigger time in ns;
CEXT = external capacitor in pF; REXT = external resistor in k.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF.
[4]
When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi + (CL  VCC2  fo) + 0.75  CEXT  VCC2  fo + D  16  VCC where:
fi = input frequency in MHz;
fo = output frequency in MHz;
D = duty factor in %;
CL = output load capacitance in pF;
VCC = supply voltage in V;
CEXT = timing capacitance in pF;
(CL  VCC2  fo) sum of outputs.
74HC_HCT123_Q100
Product data sheet
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Dual retriggerable monostable multivibrator with reset
DDD
W: QV
DDD
.
IDFWRU
&(;7S)
9&&9
VCC = 5.0 V; Tamb = 25 C.
CEXT = 10 nF; REXT = 10 k to 100 k.
Tamb = 25 C.
(1) REXT = 100 k
(2) REXT = 50 k
(3) REXT = 10 k
(4) REXT = 2 k
Fig 7.
Typical output pulse width as a function of the
external capacitor value
74HC_HCT123_Q100
Product data sheet
Fig 8.
74HC123-Q100 typical ‘K’ factor as function of
VCC
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Dual retriggerable monostable multivibrator with reset
11. Waveforms
9,
90
Q%LQSXW
*1'
W:
9,
90
Q$LQSXW
*1'
W:
9,
90
Q5'LQSXW
*1'
W3/+
W3/+
W:
92+
Q4RXWSXW
9<
90
9;
92/
W7+/
W:
92/
W3/+
W:
92+
Q4RXWSXW
W3+/
UHVHW
9<
90
9;
W3+/
W3+/
W7/+
W3/+
UHVHW
W3+/
DDD
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9.
Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times
74HC_HCT123_Q100
Product data sheet
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Rev. 2 — 19 January 2015
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12 of 23
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NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Q%LQSXW
W:
Q$LQSXW
WUWULJ
W:
Q4RXWSXW
W:
W:
W:
PQD
nRD = HIGH
Fig 10. Output pulse control using retrigger pulse
Q%LQSXW
Q5'LQSXW
W:
Q4RXWSXW
W:
W:
PQD
nA = LOW
Fig 11. Output pulse control using reset input nRD
74HC_HCT123_Q100
Product data sheet
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Rev. 2 — 19 January 2015
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13 of 23
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Dual retriggerable monostable multivibrator with reset
9,
W:
QHJDWLYH
SXOVH
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
9
90
90
90
W:
9&&
9&&
*
9,
92
5/
6
RSHQ
'87
&/
57
DDG
Test data is given in Table 8.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 12. Test circuit for measuring switching times
Table 8.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
74HC123-Q100
VCC
6 ns
15 pF, 50 pF
1 k
open
74HCT123-Q100
3V
6 ns
15 pF, 50 pF
1 k
open
74HC_HCT123_Q100
Product data sheet
Load
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
S1 position
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
12. Application information
12.1 Timing component connections
The basic output pulse width is defined by the values of the external timing components
REXT and CEXT.
&(;7
5(;7
*1'
Q&(;7
Q5(;7&(;7
Q$
Q%
9&&
Q4
Q4
Q5'
DDD
(1) For minimum noise generation, ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND).
Fig 13. Timing component connections
12.2 Power-up considerations
When the monostable is powered-up, it may produce an output pulse, with a pulse width
defined by the values of REXT and CEXT. This output pulse can be eliminated using the
circuit shown in Figure 14.
&(;7
5(;7
*1'
Q&(;7
Q5(;7&(;7
Q$
Q%
9&&
Q4
Q4
Q5'
5(6(7
9&&
DDD
Fig 14. Power-up output pulse elimination circuit
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 23
NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
12.3 Power-down considerations
A large capacitor CEXT may cause problems when powering-down the monostable due to
the energy stored in this capacitor. When a system containing this device is
powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain
damage. The damage is due to the capacitor discharging through the input protection
diodes. To avoid this possibility, use a damping diode (DEXT) and connect as shown in
Figure 15. DEXT is preferably a germanium or Schottky type diode able to withstand large
current surges.
'(;7
&(;7
5(;7
*1'
Q&(;7
Q5(;7&(;7
Q$
Q%
9&&
Q4
Q4
Q5'
DDD
Fig 15. Power-down protection circuit
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74HC123-Q100; 74HCT123-Q100
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Dual retriggerable monostable multivibrator with reset
13. Package outline
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74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
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Fig 17. Package outline SOT403-1 (TSSOP16)
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
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Fig 18. Package outline SOT763-1 (DHVQFN16)
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
19 of 23
74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
14. Abbreviations
Table 9.
Abbreviations
Acronym
Abbreviation
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
Low-power Schottky Transistor-Transistor Logic
MM
Machine Model
MIL
Military
15. Revision history
Table 10.
Revision history
Document ID
Release date
74HC_HCT123_Q100 v.2 20150119
Modifications:
•
Product data sheet
Change notice
Supersedes
Product data sheet
-
74HC_HCT123_Q100 v.1
Table 7: Power dissipation capacitance condition for 74HCT123-Q100 is corrected.
74HC_HCT123_Q100 v.1 20120801
74HC_HCT123_Q100
Data sheet status
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
-
© NXP Semiconductors N.V. 2015. All rights reserved.
20 of 23
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Dual retriggerable monostable multivibrator with reset
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT123_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
21 of 23
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74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
22 of 23
NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
18. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
12.1
12.2
12.3
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 15
Timing component connections . . . . . . . . . . . 15
Power-up considerations . . . . . . . . . . . . . . . . 15
Power-down considerations . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 January 2015
Document identifier: 74HC_HCT123_Q100