5 4 3 2 1 D D EVB-LAN9352 Page No Schematic Page C 1 Title 2 Block Diagram 3 Power Supply & RST 4 LAN9352 (part1) 5 Copper Mode Interface 6 SFP Interface 7 STRAP,GPIO,I2C & FXLOS 8 LAN9352 (part2) C B B A A Chennai India Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 5 4 3 2 Page: TITLE Board Name: EVB-LAN9352-REV-A Sheet 1 1 Rev of A 9 5 4 3 2 1 JUTLAND EVB LAN9352 D D C C B B A A Chennai India Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 5 4 3 2 Page: Block Diagram Board Name: EVB-LAN9352-REV-A Sheet 2 1 Rev of A 9 5 4 3 2 1 D D FB1 2 2 EN12_1 2A/0.05DCR BLM18EG221SN1D Switch, SPDT, Slide P/N:1101M2S3CQE2 J1 2 1 5V_SW 3 R1 0E C2 10uF 25V VIN ENABLE VOUT TRIM 3_Amp GND C3 4 5 C1 3 OKR-T/3-W12-C 0.1uF R2 1K VOUT_3V3 R3 3.30K 1% R4 470E 1% (Ra) (Rb) R4A 33E 1% C4 C5 10uF 0.1uF 4.7uF DNP 1 1 A 5V_EXT 3 3V3 3V3 C D1 GRN C SW1 1 TP2 ORANGE 3 V REGULATOR, 3A ( 3V3 fixed when Rb=470E) U1 5V 2 TP1 RED "3V3 Present" POWER SUPPLY C 3V3 3V3 3V3 2 RESET# RESET NDS355AN_NMOS 1 D RST# Q1 3 R8 1K 1 G 5 MR# 2 3V3 VDD 4 5 U2 2 1/10W 1% 3 sw_pb_2P B 1 R7 100 GND SW2 R5 4.75K 1% 0.1uF 2 1 C6 R6 10.0K 1/10W 1% B RED U3 S 2 4 1 R9 TPS3125 2.2K 74LVC1G14 A C D2 "Reset" 1 3 SOT23_5 Threshold = 2.64V Delay = 180ms 2 Reset Generator A A TP3 BLACK TP4 BLACK Chennai India Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 5 4 3 2 Page: Power Supply & RST Board Name: EVB-LAN9352-REV-A Sheet 3 1 Rev of A 9 5 4 2 1 Power Supply Filtering VDD33TXRX1 3V3 2A/0.05DCR 0.1uF C24 C20 C21 C22 0.1uF 0.1uF 1uF 470pF C18 0.1uF C16 C17 0.1uF 0.1uF 0.1uF C14 C15 0.1uF C13 C12 DNP C11 FB5 2A/0.05DCR 18pF REG_EN R10 12.1K 1% RBIAS RST# 11 IRQ 49 ATEST/FXLOSEN B 7 65 8 46 I2C2_SCL I2C2_SDA 48 47 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 53 51 50 38 22 21 13 12 RBIAS IRQ ATEST/FXLOSEN 64 67 VDD12TX1 VDD12TX2 6 28 43 VDDCR_1 VDDCR_2 VDDCR_3 16 24 36 42 52 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDD33BIAS VDD33 REG_EN RST# C FXSDENA/FXSDA/FXLOSA INT PORT0 C27 OSCVDD12 OSCI OSCO OSCVSS TESTMODE EESCL/TCK EESDA/TMS TXNA TXPA RXNA RXPA INT PORT1 1 3V3 3 1 2 4 OSC OSCI OSCO I2C 25.000MHz 25ppm Y1 OTHER SIGNALS 18pF 2 C26 POWER Note: OSCVSS need to connect to Chip gnd. VDD33TXRX1 VDD33TXRX2 59 72 U4-1 C 66 5 VDD12TX1 VDD12TX2 0.1uF 0.1uF BLM18EG221SN1D C25 C23 1.0uF DNP TP5 SMT VDDCR 1.0uF 2A/0.05DCR 3V3 2A/0.05DCR 0.1uF 3V3 FB4 C9 3V3 0.1uF VDD33TXRX2 0.1uF FB3 C8 C10 C7 1.0uF DNP D VDDCR VDD12TX1 VDD12TX2 DNP 1.0uF FB2 VDD33TXRX1 VDD33TXRX2 D Low ESR C19 3V3 3 TXNB TXPB RXNB RXPB FXSDA/FXLOSA 60 61 62 63 TXNA TXPA RXNA RXPA 71 70 69 68 TXNB TXPB RXNB RXPB 10 FXSDB/FXLOSB GND B 73 58 57 54 LAN9352_QFN72 NC_3 NC_2 NC_1 FXSDENB/FXSDB/FXLOSB GPIO0/LED0/TDO/LEDPOL0/MNGT0 GPIO1/LED1/TDI/LEDPOL1/MNGT1 GPIO2/LED2/LEDPOL2/E2PSIZE GPIO3/LED3/LEDPOL3/EEEEN GPIO4/LED4/LEDPOL4/1588EN GPIO5/LED5/LEDPOL5/PHYADD GPIO6 GPIO7 9 A A Chennai India Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 5 4 3 2 Page: LAN9352 (Part1) Board Name: EVB-LAN9352-REV-A Sheet 4 1 Rev of A 9 5 4 3 2 R61 LINK/ACT TXPA DNP R16 R17 0E 0E TXNA DNP R18 R19 0E 0E FX_SFP-TXPA R12 49.9 1/10W 1% R13 49.9 1/10W 1% R14 49.9 1/10W 1% C R11 49.9 1/10W 1% R15 0E GRN 1 COP-TXPA 4 FX_SFP-TXNA 9 10 T1 Pulse J0011D01BNL BLM18EG221SN1D D LED2_ANODE 2A/0.05DCR 2 COP-TXNA A FB6 PORT1 330E LED2_CATHODE VDD33TXRX1 1 RJ45 D XMIT TD+ 75 75 1 TXCT 4&5 TD- 2 Default assembly LED1 (Green) = LINK/ACT DNP C30 10pF 50V 5% DNP C31 10pF 50V 5% C32 0.022uF 7 8 50V 10% 7&8 RD- 6 1000 pF NC 2 kV CHS GND Note: Capacitors C28 through C31 are optional for EMI purposes and are not populated on the LAN9252 evaluation board. These capacitors are required for operation in an EMI constrained environment. 14 13 C YEL C A1 DNP C29 10pF 50V 5% RXCT GND DNP C28 10pF 50V 5% 3 12 6 COP-RXNA 75 C1 FX_SFP-RXNA LED2 (Yellow) = SPEED 75 11 5 0E 0E RCV RD+ MTG1 3 COP-RXPA MTG FX_SFP-RXPA 16 DNP R22 R23 0E 0E 15 RXNA DNP R20 R21 GND1 RXPA R62 R24 330E LED0_CATHODE 0E LED0_ANODE SPEED RES1210 R63 LINK/ACT 10 T2 Pulse J0011D01BNL TXPB TXNB R25 49.9 1/10W 1% DNP R30 R31 0E 0E FX_SFP-TXPB DNP R32 R33 0E 0E FX_SFP-TXNB DNP R34 R35 0E 0E FX_SFP-RXPB R26 49.9 1/10W 1% R27 49.9 1/10W 1% R28 49.9 1/10W 1% C BLM18EG221SN1D B LED5_ANODE 2A/0.05DCR R29 0E GRN 1 COP-TXPB 4 2 COP-TXNB 9 FB7 A PORT2 330E LED5_CATHODE VDD33TXRX2 RJ45 B XMIT TD+ 75 75 1 TXCT 4&5 TD- 2 LED1 (Green) = LINK/ACT 8 6 1000 pF NC A Note: Capacitors C33 through C36 are optional for EMI purposes and are not populated on the LAN9252 evaluation board. These capacitors are required for operation in an EMI constrained environment. 2 kV CHS GND YEL A A1 50V 10% 7 12 C37 0.022uF C1 DNP C36 10pF 50V 5% 11 DNP C35 10pF 50V 5% MTG1 DNP C34 10pF 50V 5% RD- GND DNP C33 10pF 50V 5% 3 7&8 RXCT MTG 6 COP-RXNB 75 16 FX_SFP-RXNB 15 5 0E 0E 75 GND1 DNP R36 R37 LED2 (Yellow) = SPEED RD+ 14 RXNB 3 COP-RXPB RCV 13 RXPB R64 R38 0E Chennai India 330E LED3_CATHODE LED3_ANODE SPEED Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 RES1210 5 4 3 2 Page: Copper Mode Interface Board Name: EVB-LAN9352-REV-A Sheet 5 1 Rev of A 9 5 4 3V3 R39 82 R40 82 R41 49.9 R42 49.9 Note:Place capacitors, and resistors close to FOT C38 D 0.1uF 3 2 3V3 Fiber Port 0 :SFP Interface R43 82 R44 82 R45 49.9 R46 49.9 1 Note:Place capacitors, and resistors close to FOT Assemble 0E at C38,C40,C42,C44 FX_SFP-RXNA C39 0.1uF C41 0.1uF C43 0.1uF Fiber Port 1 :SFP Interface Assemble 0E at C39,C41,C43,C45 D FX_SFP-RXNB C40 0.1uF C42 0.1uF FX_SFP-RXPA FX_SFP-RXPB FX_SFP-TXPA FX_SFP-TXPB DNP R47 100 C44 SFP_VCCT 0.1uF L2 SFP_VCCR FX_SFP-TXNA DNP R48 100 3V3 1uH C45 0.1uF C48 + 10uF 16V 0.1uF L4 C49 0.1uF R51 130 R52 130 1uH R54 4.7K R55 4.7K C52 + 10uF 16V 0.1uF L3 C53 0.1uF 1uH C C55 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 C54 + 10uF 16V Note:Place resistors close to ASIC 0.1uF J3 FTLF1217P2 VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 31 30 29 28 27 26 25 24 23 22 21 31 30 29 28 27 26 25 24 23 22 21 31 30 29 28 27 26 25 24 23 22 21 C56 + 10uF 16V C57 0.1uF SFP_VCCT2 1 2 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 SFP_VCCT C51 20 19 18 17 16 15 14 13 12 11 1uH 20 19 18 17 16 15 14 13 12 11 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 J2 FTLF1217P2 VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 Note:Place resistors close to ASIC DNP C50 + 10uF 16V SFP_RD2+ SFP_RD2- C47 SFP_TD2SFP_TD2+ SFP_RD+ SFP_RD- SFP_TDSFP_TD+ R50 130 DNP C46 + 10uF 16V C R53 4.7K L1 SFP_VCCR2 FX_SFP-TXNB R49 130 B 3V3 SFP_VCCT2 R57 4.7K R56 4.7K FXSDA/FXLOSA R58 4.7K R59 4.7K B R60 4.7K FXSDB/FXLOSB A A Chennai India Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 5 4 3 2 Page: SFP Interface Board Name: EVB-LAN9352-REV-A Sheet 6 1 Rev of A 9 3 2 GPIO [0:2] & LED_POL_Strap GPIO0 SCL 2 R86 0E GPIO3 5 I2C2_SDA 6 I2C2_SCL Note: U5: IC DIP Socket. Different sizes can be mounted I2C EEPROM Lower size Below 16K(2K X 8) 3 1 3 J15 1 3 1 J13 GPIO4 D I2C EEPROM Higher size Above 16K(2K X 8) [Default-512KBIT) 2 2 2 2 GPIO1 3 J14 1 3 GPIO2 R85 0E R84 1K J8 1 3 J9 1 J7 C R74 1K 2 2 R73 0E SDA WP R68 R67 A0 A1 A2 24FC512 R72 0E 2K VCC 2 7 2 2 1 2 3 0.1uF 8 3 1 3 1 2 0E R83 10.0K LED3_CATHODE LED5_CATHODE 2 2 R66 LED3_ANODE LED5_ANODE R82 10.0K LED1_CATHODE LED4_CATHODE 2 LED0_CATHODE LED2_CATHODE R81 10.0K U5 J12 2 R71 10.0K GPIO5 GND R70 10.0K 3 1 3 1 LED1_ANODE LED4_ANODE 1 1 1 LED0_ANODE LED2_ANODE R69 10.0K J10 3V3 C58 GPIO3 J11 3V3 3V3 GPIO4 2 J5 2 J6 2 J4 3V3 GPIO1 3 1 GPIO2 3 1 GPIO0 D 3V3 1 3V3 I2C EEPROM 1 3V3 1 3V3 1 2K 4 4 5 GPIO5 FX_Los_Strap_1 & 2 C 3V3 3V3 LED0_ANODE LED0_ANODE LED0_CATHODE LED0_CATHODE LED1_ANODE LED1_CATHODE LED2_ANODE LED2_ANODE LED2_CATHODE LED2_CATHODE DNP D3 1 GRN A PORT1 SPEED 2 LED3_ANODE C LED3_CATHODE D4 1 GRN A FULL DUPLEX 2 C PORT1 DNP LINK/ACT 2 D5 1 C GRN A LED3_ANODE LED3_CATHODE LED4_ANODE LED4_CATHODE LED5_ANODE LED5_CATHODE LED5_ANODE LED5_CATHODE DNP D6 1 GRN A PORT2 SPEED 1 2 2 GPIO6 R87 C Poupulate DNP Poupulate Poupulate FULL DUPLEX 2 C PORT2 DNP LINK/ACT 2 D8 1 C GRN A R79 Ref.Voltage Function 3V3 Above 2 V selects FX-LOS for ports 0 and 1 1V5 Level of 1.5 V selects FX-LOS for port 0 and FX-SD/copper twisted pair for port 1 further determined by FXSDB 3 10K J16 OPEN D7 1 GRN A R77 3V3 DNP Poupulate (Default) (Default) 1 R88 ATEST/FXLOSEN Level of 0V Selects FX-SD / copper twisted pair for ports A and B further determined by FXSDA and FXSDB. 0V (Default) 2 GPIO7 R77 10K DNP R79 10K 3 10K J17 OPEN 3V3 MNGT2 B Signal Name Logic 0 LEDPOL0/ MNGT0 LEDPOL1/ MNGT1 LEDPOL2 E2ESIZE LEDPOL3 EEEEN A LEDPOL4 1588EN LEDPOL5 PHYADD 1 Connector J4,J7 (2&3) J4,J7 (1&2) R89 FX_Mode_Strap_1 & 2 3 10K 3V3 J23 The LED is set as active high/ Serial Management Mode Stratp:1=I2C The LED is set as active low/ Serial Management Mode Stratp:0=SMI FXSDA/FXLOSA 3V3 MNGT3 0 J5,J8 (2&3) The LED is set as active high. 1 J5,J8 (1&2) The LED is set as active low, 0 J6,J9 (2&3) The LED is set as active high. EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8) 1 J6,J9 (1&2) The LED is set as active low, EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only) 0 J10,J13 (2&3) The LED is set as active high. EEE Disable 1 J10,J13 (1&2) The LED is set as active low, EEE Enable 0 J11,J14 (2&3) The LED is set as active high. 1588 Disable 1 J11,J14 (1&2) The LED is set as active low, 1588 Enable 0 J12,J15 (2&3) 1 J12,J15 (1&2) 5 B 2 A3 LED Polarity Strap 1 R90 3 10K PORT 3V3 Management Strap Selection MNGT1 MNGT0 MNGT3 MNGT2 1 2 3 4 5 6 7 8 J18 HEADER 8 4 10K 1 J5 & J8 J4 & J7 The LED is set as active low, PHYADD =1,2,3 R76 PORT0 J24 The LED is set as active high. PHYADD=0,1,2 DNP 10K 2 A4 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 R75 3 J24 FXSDB/FXLOSB R78 DNP 10K R80 10K PORT1 MODE Poupulate Copper R76 (Default) Fiber R75 Copper (Default) Fiber DNP R75 R76 R80 R78 R78 R80 HOST MODE J23 0 0 X X SPI 0 1 0 0 HBI Multiplexed 1 Phase 8-bit 0 1 0 1 HBI Multiplexed 1 Phase 16-bit (Default) 0 1 1 0 HBI Multiplexed 2 Phase 8-bit 0 1 1 1 HBI Multiplexed 2 Phase 16-bit 1 0 X X HBI Indexed 8-bit 1 1 X X HBI Indexed 16-bit A Chennai India Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 2 Page: STRAP,GPIO,I2C & FXLOS Board Rev Name: EVB-LAN9352-REV-A A of 9 Sheet 7 1 5 4 A0 A1 A2 SW DIP-4/SM R96 RD_RDWR 35 WR_ENB 34 CS 32 PME_LATCH1 20 FIFOSEL_LATCH0 39 RD/RD_WR A0/D15/AD15 D14/AD14 D13/AD13 D12/AD12 D11/AD11 D10/AD10 D9/AD9/SCK D8/AD8 D7/AD7 D6/AD6 D5/AD5/SCS# D4/AD4 D3/AD3/SIO3 D2/AD2/SIO2 D1/AD1/SO/SIO1 D0/AD0/SI/SIO0 I2C1_SDA 6 WR/ENB I2C1_SCL I2C EEPROM Only for Host SOC 4 24FC512 R95 5 SDA SCL WP 2K 8 4.7K 4.7K 1 2 3 I2C3_1 I2C3_2 I2C3_3 I2C3_7 7 CS PME FIFOSEL P8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 AD7 AD3 GPMC_OEN_REN GPMC_WEN AD12 AD10 AD14 C AD5 AD1 CS PME_LATCH1 FIFOSEL_LATCH0 A3_SOC A1_SOC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 U4-2 AD6 AD2 ALELO GPMC_BE0N_CLE AD13 AD9 AD15 AD11 AD8 AD4 AD0 SIO1 SCK SCS# J20 R100 R101 1 3 5 7 9 0 0 A4_SOC A2_SOC A0_SOC 10 ON 9 8 7 6 1 2 3 4 5 A4 A3 A2 A1 A0 SYS_RESETN GPMC_DIR I2C1_SDA I2C2_SDA J25 2 SIO3 SCS# SIO1 A IRQ 1 D AD15 2 A0 3 ALELO 2 A1 3 ALEHI 2 A2 3 SW4 *(1-2) 1 A0_AD15 C JS102011CQN SW5 1 0 SIO0 3 4 1 2 Default :J27 Open VDD3V3EXP VDD_5V C60 DNP 1 2 2 5V power to SOC board from EVB Board Default Short 0.1uF I2C1_SCL 2 J22 1 J27 1 J19 2 RST_GPIO *(1-2) ALELO_A1 JS102011CQN SW6 *(1-2) ALEHI_A2 JS102011CQN SW7 *(2-3) 1 SYS_RESETN 1 D9 J20 - SPI AARDVAR HEADER J20+J21 - SPI STROM HEADER 2 3 RST# JS102011CQN DIODE Short 1 -2 = To Reset ASIC from SoC-GPIO Short 2-3 = To Reset SoC from ASIC HBI or SPI selection B SW8 5V AD3 AD3_SIO3 SIO3 1 2 3 4 5 6 AD2 AD2_SIO2 SIO2 GPMC_OEN_REN 2 SW11 1 GPMC_DIR 3 GPMC_WEN 2 GPMC_BE0N_CLE 3 RD_RDWR JS102011CQN SW9 AD0 AD0_SIO0 SIO0 1 2 3 I2C2_SCL ALEHI 4 5 6 AD1 AD1_SIO1 SIO1 SW12 1 WR_ENB JS102011CQN SW10 AD9 AD9_SCK SCK SIO2 SIO0 SCK 1 2 3 4 5 6 AD5 AD5_SCS# SCS# SW8,SW9 & SW10 = HBI or SPI selection HBI or SPI+GPIO Config selection Short 1-2 & 4-5 for HBI Config (2-3 & 5-6 open):Default RST_GPIO A Short 2-3 & 5-6 for SPI+GPIO Config (1-2 & 4-5 open) HEADER 23x2 Chennai India Part Number: EVB-LAN9352 Project Size: B Name: LAN9352 Date: Thursday, August 13, 2015 Board to Board Connectors for SoC 5 A0_AD15 AD14 AD13 AD12 AD11 AD10 AD9_SCK AD8 AD7 AD6 AD5_SCS# AD4 AD3_SIO3 AD2_SIO2 AD1_SIO1 AD0_SIO0 J21 SIO2 SIO3 3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 37 17 18 25 26 27 23 45 44 41 56 55 40 14 15 19 A4 A3 1 Note: PIC32 MX SoC INDEXED MODE:SW15-ON position TI SOC INDEXED MODE: SW15-OFF position (Default) P9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 R102 A4 A3 ALEHI_A2 ALELO_A1 SW15 A4_SOC A3_SOC A2_SOC A1_SOC A0_SOC B VDD3V3EXP VDD_5V 2 4 6 8 10 31 30 33 29 LAN9352_QFN72 Aardvark / SPI Storm- Connector I2C2_SCL I2C2_SDA 219-5MS HEADER 23x2 1 A4/MNGT3 A3/MNGT2 A2/ALEHI A1/ALELO U6 VCC 1 2 3 4 2K C59 0.1uF GND 8 7 6 5 4.7K 4.7K SW3 D 2 3V3 R94 R93 R92 Host SOC EEPROM R91 3V3 3 4 3 2 Page: LAN9352 (Part2) Board Name: EVB-LAN9352-REV-A Sheet 8 1 Rev of A 9